CD22301 CD22301E 1-888-INTERSIL FN1368 75VRMS IN4152

CT RO DU NT LETE P EPLACEME at O BS O DE D R ter EN rt Cen /tsc COMM S upp o NO RE r Technical .intersil.com ww t ou contac

CD22301 CD22301 CT RO DU NT LETE P EPLACEME at O BS O DE D R ter EN rt Cen /tsc COMM S upp o NO RE r Technical .intersil.com ww t ou contac TERSIL or w 8-IN 1-88 ® November 2002 Monolithic PCM Repeater Features Description · Automatic Line Buildout The CD22301 CD22301 monolithic PCM repeater circuit is designed for T1 carrier systems operating with a bipolar pulse train of 1.544Mbits/s. It can also be used in the T148 carrier system operating with a ternary pulse train of 2.37Mbits/s. The circuit operates from a 5.1V ±5% externally regulated supply. · Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1V · Buffered Output Applications · Bipolar Carrier System . . . . . . . . . . . . . T1 1.544Mbits/s · Ternary Carrier System . . . . . . . . . . . . T148 2.37Mbits/s The CD22301 CD22301 provides active circuitry to perform all functions of signal equalization and amplification, automatic line buildout (ALBO), threshold detection, clock extraction, pulse timing and buffered output formation. Part Number Information PART NUMBER TEMP. RANGE (oC) CD22301E CD22301E -40 to 85 Pinout PACKAGE 18 Ld PDIP CD22301 CD22301 (PDIP) TOP VIEW PKG. NO. E18.3 ALBO GROUND 1 18 SUBSTRATE ALBO 1 OUTPUT 2 17 ALBO BIAS ALBO 2 OUTPUT 3 16 OSC BIAS ALBO 3 OUTPUT 4 15 LC TANK INPUT PREAMP INPUT + 5 14 VCC PREAMP INPUT - 6 13 CLOCK LIMITER OUTPUT PREAMP OUTPUT + 7 12 TIMING PULSE INPUT PREAMP OUTPUT - 8 11 OUTPUT PULSE 1 VEE 9 10 OUTPUT PULSE 2 Functional Diagram ALBO OUTPUT CIRCUIT ALBO GND ALBO BIAS 1 17 VCC 1K 15K 100 100 AO1 3 AO3 100 2 AO2 50K 18K FROM ALBO PEAK DETECTOR 4 VEE 100 100 100 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 All other trademarks mentioned are the property of their respective owners. FN1368 FN1368.4 CD22301 CD22301 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Input Current (Into Pin 9 or 10). . . . . . . . . . . . . . . . . . . . . . . . . 25mA Peak Current (Into Pin 9 or 10). . . . . . . . . . . . . . . . . . . . . . . . 100mA Input Surge Voltage (Between Pins 5 and 6, t = 10ms) . . . . . . . 50V Output Surge Voltage (Between Pins 10 and 11, t = 1ms). . . . . 50V Power Dissipation For TA = -40oC to 60oC. . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW For TA = 60oC to 85oC . . . . Derate Linearly 12mW/oC to 200mW Device Dissipation per Output Transistor For TA = Full Package Temperature Range (All Types) . . . . 100mW Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . -65oC TA 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40oC TA 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = 25oC, VCC = 5.1V ±5% (See Figure 4) Electrical Specifications PARAMETER MIN TYP MAX UNITS - 0 0.1 V 2.4 2.9 3.4 V - 5.1 - V 3.1 3.6 4.1 V ICC - 22 30 mA Output Pulse 1, 2 (Pins 10 and 11) - 0 100 µA MIN TYP MAX UNITS STATIC DC VOLTAGES ALBO Pins (Pins 2, 3, 4 and 17) Pre Amp Inputs and Outputs (Pins 5, 6, 7 and 8) Output Pulse 1, 2 (Pins 10 and 11) Oscillator/Clock (Pins 12, 13, 15 and 16) STATIC DC CURRENTS Electrical Specifications PARAMETER TA = 25oC, VCC = 5.1V ±5% SYMBOL FIGURE NOTE ZIN 7 20 - - k ZOUT 7 - - 2 k AO 7 47 50 - dB Preamplifier Output Offset Voltage VOUT 7 1 -50 0 50 mV Clock Limiter Input Impedance ZIN(CL) 5 2 10 - - k ALBO Off Impedance ZALBO(off) 5 3 20 - - k ALBO On Impedance ZALBO(on) 5 4 - - 10 DATA Threshold Voltage VTH(D) 6 5, 8 0.62 0.7 0.78 V CLOCK Threshold Voltage VTH(CL) 6 6, 8 0.92 1.1 1.28 V ALBO Threshold VTH(AL) 6 7, 8 1.4 1.5 1.6 V VTH(D) as % of VTH(AL) 44 47 49 % VTH(CL) as % of VTH(AL) 66 73 80 % DYNAMIC SPECIFICATIONS Preamplifier Input Impedance Preamplifier Output Impedance Preamplifier Gain at 2.37MHz Buffer Gate Voltage (low) Differential Buffer Gate Voltage Output Pulse Rise Time VOL 4 9 0.65 0.8 0.95 V VOL 4 9 -0.15 0 0.15 V tR 4, 8 9, 10 - - 40 ns 2 CD22301 CD22301 Electrical Specifications TA = 25oC, VCC = 5.1V ±5% (Continued) PARAMETER SYMBOL FIGURE NOTE MIN TYP MAX UNITS Output Pulse Fall Time tF 4, 8 9, 10 - - 40 ns Output Pulse Width tW 4, 8 9, 10 290 324 340 ns Pulse Width Differential tW 4, 8 9, 10 -10 0 10 ns Clock Drive Current ICL - 2 - mA NOTES: 1. No signal input. Measure voltage between pins 7 and 8. 2. Measure clock limiter input impedance at pin 15. See Figure 5. 3. Adjust potentiometer for 0V (See Figure 5). Measure ALBO off impedances from pins 2, 3 and 4 to pin 1. 4. Increase potentiometer until voltage at pin 17 = 2V (See Figure 5). Measure ALBO on impedances from pins 2, 3 and 4 to pin 1. 5. Adjust potentiometer for V = 0V (See Figure 6). Then slowly increase V in the positive direction until pulses are observed at the DATA terminal. 6. Continue increasing V until the DC level at the clock terminal drops to 4V (See Figure 6). 7. Continue increasing V until the ALBO terminal rises to 1V (See Figure 6). 8. Turn potentiometer in the opposite direction and measure negative threshold voltages by repeating tests outlined in notes 5, 6 and 7. 9. Set eIN = 2.75mVRMS at f 1.185MHz. Adjust frequency until maximum amplitude is obtained at pin 15. Observe output pulses at pins 10 and 11. 10. Adjust input signal amplitude until pulses just appear in outputs. Increase input amplitude by 3dB. 600 - 800pF + ALBO GND 1 SUBSTRATE AO1 2 AO2 3 4 AO3 0.1µF 2200pF 470µH 1500pF 1.8K PULSE INPUT 430 0.1µF ALBO OUTPUT CIRCUIT SEE FIG. 1 120K 17µH 0.1 µF PEAK DETECTOR BIAS LC TANK 16 15 INPUT CLOCK CIRCUIT SEE FIG. 2 510 82pF 5 2.7K 8.2K 1µF ALBO 18 BIAS 17 PREAMPLIFIER CLOCK THRESHOLD COMPARATOR LIMITER 13 TIMING PULSE AMPLIFIER 12 33pF 6 130 4.53K 100 µH PHASE SHIFT NETWORK 3.83K 150pF 15µH 1.33K 14 VCC DATA THRESHOLD COMPARATOR 6.19K GATE 7 GATE 8 FF 11 PULSE OUTPUT FF 10 0.1µF 9 VEE FIGURE 1. TYPICAL 1.544MHz T1 REPEATER SYSTEM 3 VCC CD22301 CD22301 16 15 VCC VCC VCC FROM LIMITER 12 TO AMPLIFIER 5.1K TO TIMING PULSE AMPLIFIER 13 5.1K 12K 5.5K VEE VEE VEE FROM CLOCK THRESHOLD DETECTOR FIGURE 2. CLOCK INTERFACE CIRCUIT FIGURE 3. PHASE-SHIFT INTERFACE CIRCUITS 1 18 2 17 3 16 1µF 0.68µF L1 (NOTE) 4 eIN 0.001 µF 8.2k 8.2k 15 5 0.1µF 14 6 100µH 13 7 12 130 8 11 9 20 pF 10 130 PULSE OUTPUT FIGURE 4. DC AND OUTPUT PULSE TEST CIRCUIT 1 18 2 17 3 16 4 15 5 14 0.1µF 5K VCC = 5.1V 0.01µF 6 13 7 12 8 11 9 10 FIGURE 5. TEST CIRCUIT FOR IMPEDANCE MEASUREMENT 4 RESONATE AT 1.272MHz 91k VCC = 5.1V 3.83k 0.1 µF C1 (NOTE) NOTE: C1 AND L1 0.1µF CD22301 CD22301 1 18 2 17 3 16 4 15 1µF 1µF CLOCK 1µF 5 0.1 µF - 3V + 8.2k 14 6 13 7 12 8 11 9 8.2k VCC = 5.1V 1µF 0.1 µF 8.2 k 2k 10 0.1µF 75 0.1 µF 8.2k 0.1 µF 2.75VRMS 75VRMS at 1.185MHz IN4152 IN4152 130 5k V DATA FIGURE 6. TEST CIRCUIT FOR THRESHOLD VOLTAGE MEASUREMENT 1 18 2 17 3 16 4 15 5 14 NC NC 1.0µF ein VCC = 5.1V 0.1µF 6 13 7 12 8 11 9 50 200 k 10 200k 1.0 µF NC FIGURE 7. PREAMPLIFIER GAIN AND IMPEDANCE MEASUREMENT CIRCUIT 100% 90% tW 50% 0% 10% tF tR FIGURE 8. OUTPUT PULSE WAVEFORM 5