CC2550 SWRS039B CFR47 STDT66 J-STD-020D CC2550EM CC2500EM AT-41CD2 C51/C71 - Datasheet Archive

 

CC2550 Low-Cost Low-Power 2.4 GHz RF Transmitter Applications · 2400-2483.5 MHz ISM/SRD band systems · Consumer

 

CC2550 CC2550 CC2550 CC2550 Low-Cost Low-Power 2.4 GHz RF Transmitter Applications · 2400-2483.5 MHz ISM/SRD band systems · Consumer electronics · Wireless game controllers · Wireless audio · RF enabled remote controls Product Description The CC2550 CC2550 is a low-cost 2.4 GHz transmitter designed for very low-power wireless applications. The circuit is intended for the 24002483.5 MHz ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency band. The main operating parameters and the 64byte transmit FIFO of CC2550 CC2550 can be controlled via an SPI interface. In a typical system, the CC2550 CC2550 will be used together with a microcontroller and a few passive components. The RF transmitter is integrated with a highly configurable baseband modulator. The modulator supports various modulation formats and has a configurable data rate up to 500 kBaud. The CC2550 CC2550 provides extensive hardware support for packet handling, data buffering and burst transmissions. Key Features RF Performance Low-Power Features · · · · · Programmable output power up to +1 dBm Programmable data rate from 1.2 to 500 kBaud Frequency range: 2400 ­ 2483.5 MHz · 200 nA SLEEP mode current consumption Fast startup time: 240 us from SLEEP to TX mode (measured on EM design [3]) 64-byte TX data FIFO (enables burst mode data transmission) Analog Features · · · OOK, 2-FSK, GFSK, and MSK supported Suitable for frequency hopping and multichannel systems due to a fast settling frequency synthesizer with 90 us settling time Integrated analog temperature sensor Digital Features · · · Flexible support for packet oriented systems: On-chip support for sync word insertion, flexible packet length, and automatic CRC handling Efficient SPI interface: All registers can be programmed with one "burst" transfer Optional automatic whitening of data General · · · · · SWRS039B SWRS039B Few external components: Complete onchip frequency synthesizer, no external filters needed Green package: RoHS compliant and no antimony or bromine Small size (QLP 4x4 mm package, 16 pins) Suited for systems compliant with EN 300 328 and EN 300 440 class 2 (Europe), FCC CFR47 CFR47 Part 15 (US), and ARIB STDT66 STDT66 (Japan) Support for asynchronous and synchronous serial transmit mode for backwards compatibility with existing radio communication protocols Page 1 of 58 CC2550 CC2550 Table of Contents APPLICATIONS .1 PRODUCT DESCRIPTION.1 KEY FEATURES .1 RF PERFORMANCE .1 ANALOG FEATURES .1 DIGITAL FEATURES.1 LOW-POWER FEATURES.1 GENERAL .1 TABLE OF CONTENTS .2 ABBREVIATIONS.4 1 ABSOLUTE MAXIMUM RATINGS .4 2 OPERATING CONDITIONS .5 3 GENERAL CHARACTERISTICS.5 4 ELECTRICAL SPECIFICATIONS .5 4.1 CURRENT CONSUMPTION .5 4.2 RF TRANSMIT SECTION .6 4.3 CRYSTAL OSCILLATOR .7 4.4 FREQUENCY SYNTHESIZER CHARACTERISTICS .7 4.5 ANALOG TEMPERATURE SENSOR .8 4.6 DC CHARACTERISTICS .8 4.7 POWER-ON RESET .8 5 PIN CONFIGURATION.9 6 CIRCUIT DESCRIPTION .10 7 APPLICATION CIRCUIT .10 8 CONFIGURATION OVERVIEW .13 9 CONFIGURATION SOFTWARE.14 10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE .14 10.1 CHIP STATUS BYTE .15 10.2 REGISTERS ACCESS .16 10.3 SPI READ .16 10.4 COMMAND STROBES .17 10.5 FIFO ACCESS .17 10.6 PATABLE ACCESS .17 11 11.1 11.2 12 13 13.1 13.2 13.3 13.4 14 14.1 14.2 14.3 15 15.1 15.2 16 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION .18 CONFIGURATION INTERFACE .18 GENERAL CONTROL AND STATUS PINS .18 DATA RATE PROGRAMMING.19 PACKET HANDLING HARDWARE SUPPORT .19 DATA WHITENING .19 PACKET FORMAT .20 PACKET HANDLING IN TRANSMIT MODE .22 PACKET HANDLING IN FIRMWARE .22 MODULATION FORMATS .22 FREQUENCY SHIFT KEYING .23 MINIMUM SHIFT KEYING.23 AMPLITUDE MODULATION .23 FORWARD ERROR CORRECTION WITH INTERLEAVING .23 FORWARD ERROR CORRECTION (FEC).23 INTERLEAVING .24 RADIO CONTROL.25 SWRS039B SWRS039B Page 2 of 58 CC2550 CC2550 16.1 16.2 16.3 16.4 16.5 17 18 19 19.1 20 21 22 22.1 23 24 25 26 26.1 26.2 27 27.1 27.2 27.3 27.4 27.5 27.6 27.7 27.8 27.9 28 28.1 28.2 29 29.1 29.2 29.3 29.4 29.5 30 31 32 32.1 32.2 33 34 POWER-ON START-UP SEQUENCE .25 CRYSTAL CONTROL .26 VOLTAGE REGULATOR CONTROL.26 TX MODE .27 TIMING .27 TX FIFO .27 FREQUENCY PROGRAMMING.28 VCO .29 VCO AND PLL SELF-CALIBRATION .29 VOLTAGE REGULATORS .29 OUTPUT POWER PROGRAMMING .30 CRYSTAL OSCILLATOR.32 REFERENCE SIGNAL .32 EXTERNAL RF MATCH .32 PCB LAYOUT RECOMMENDATIONS.33 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS .33 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION .34 ASYNCHRONOUS OPERATION .34 SYNCHRONOUS SERIAL OPERATION .35 SYSTEM CONSIDERATIONS AND GUIDELINES .35 SRD REGULATIONS .35 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS .35 WIDEBAND MODULATION NOT USING SPREAD SPECTRUM .36 DATA BURST TRANSMISSIONS.36 CONTINUOUS TRANSMISSIONS .36 SPECTRUM EFFICIENT MODULATION .36 LOW COST SYSTEMS .36 BATTERY OPERATED SYSTEMS .36 INCREASING OUTPUT POWER .37 CONFIGURATION REGISTERS.37 CONFIGURATION REGISTER DETAILS .41 STATUS REGISTER DETAILS.49 PACKAGE DESCRIPTION (QLP 16).52 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 16) .53 PACKAGE THERMAL PROPERTIES .53 SOLDERING INFORMATION .53 TRAY SPECIFICATION .54 CARRIER TAPE AND REEL SPECIFICATION .54 ORDERING INFORMATION.54 REFERENCES .54 GENERAL INFORMATION.55 DOCUMENT HISTORY .55 PRODUCT STATUS DEFINITIONS .56 ADDRESS INFORMATION .57 TI WORLDWIDE TECHNICAL SUPPORT.57 SWRS039B SWRS039B Page 3 of 58 CC2550 CC2550 Abbreviations Abbreviations used in this data sheet are described below. ACP Adjacent Channel Power NA Not Applicable ADC Analog to Digital Converter NRZ Non Return to Zero (coding) AGC Automatic Gain Control LO Local Oscillator AMR Automatic Meter Reading OBW Occupied Bandwidth ARIB Association of Radio Industries and Businesses OOK On Off Keying ASK Amplitude Shift Keying PA Power Amplifier BER Bit Error Rate PCB Printed Circuit Board BT Bandwidth-Time product PD Power Down CFR Code of Federal Regulations PER Packet Error Rate CRC Cyclic Redundancy Check PLL Phase Locked Loop DC Direct Current POR Power-on Reset ESR Equivalent Series Resistance QPSK Quadrature Phase Shift Keying FCC Federal Communications Commission QLP Quad Leadless Package FEC Forward Error Correction RF Radio Frequency FHSS FIFO 2-FSK Frequency Hopping Spread Spectrum First-In-First-Out Frequency Shift Keying RX SMD SNR Receive, Receive Mode Surface Mount Device Signal to Noise Ratio GFSK Gaussian shaped Frequency Shift Keying SPI Serial Peripheral Interface I/Q In-Phase/Quadrature SRD Short Range Device ISM Industrial, Scientific and Medical TX Transmit, Transmit Mode LC Inductor-Capacitor VCO Voltage Controlled Oscillator LO Local Oscillator WLAN Wireless Local Area Networks MCU Microcontroller Unit XOSC Crystal Oscillator MSB Most Significant Bit XTAL Crystal MSK Minimum Shift Keying 1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Parameter Min Max Units Condition/Note Supply voltage ­0.3 3.9 V Voltage on any digital pin ­0.3 VDD+0.3, max 3.9 V Voltage on the pins RF_P, RF_N and DCOUPL ­0.3 2.0 V Storage temperature range ­50 150 °C Solder reflow temperature 260 °C According to IPC/JEDEC J-STD-020D J-STD-020D ESD 255 Reprogramming the packet automation control register, PCKCTRL0, during TX mode opens the possibility to transmit packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode (PCKCTRL0.LENGTH_CONFIG=2) must be active. The PKTLEN register is set to mod(length, 256). When less than 256 bytes remains of the packet the MCU disables infinite packet length mode and activates fixed packet length mode. When the internal byte counter reaches the PKTLEN value, the transmission ends the radio enters the state determined by TXOFF_MODE). Automatic CRC appending can be used (by setting PKTCTRL0.CRC_EN=1). When for example a 600-byte packet is to be transmitted, the MCU should do the following (see also Figure 11): · Set PKTCTRL0.LENGTH_CONFIG=2. · Pre-program the PKTLEN mod(600,256)=88. · Transmit at least 345 bytes (600 ­ 255), for example by filling the 64-byte TX FIFO six times (384 bytes transmitted). · Set PKTCTRL0.LENGTH_CONFIG=0. · The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted. register Figure 11: Packet Length > 255 SWRS039B SWRS039B Page 21 of 58 to CC2550 CC2550 13.3 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written to the TX FIFO is interpreted as the destination address, if this feature is enabled in the device that receives the packet. The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO and the result is sent as two extra bytes at the end of the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart TX mode. If whitening is enabled, everything following the sync words will be whitened. This is done before the optional FEC/Interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1. the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be written to TX FIFO. There are two possible solutions to get the necessary status information: a) Interrupt driven solution It is possible to use one of the GDO pins to give an interrupt when a sync word has been transmitted and/or when a complete packet has been transmitted (IOCFGx=0x06). In addition, there are 2 configurations for the IOCFGx register that are associated with the TX FIFO (IOCFGx=0x02 and IOCFG=0x03) that can be used as interrupt sources to provide information on how many bytes are in the TX FIFO. See Table 22. b) SPI polling The PKTSTATUS register can be polled at a given rate to get information about the current GDO0 value. The TXBYTES register can be polled at a given rate to get information about the number of bytes in the TX FIFO. Alternatively, the number of bytes in the TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus. This only valid when R/W = 0. If FEC/Interleaving is enabled, everything following the sync words will be scrambled by the interleaver, and FEC encoded before being modulated. FEC is enabled by setting MDMCFG.FEC_EN=1. As explained in Section 10.3 and the CC2550 CC2550 Errata Notes [1], when using SPI polling there is a small, but finite, probability that a single read from registers PKTSTATUS and TXBYTES is being corrupt. The same is the case when reading the chip status byte. It is therefore recommended to employ an interrupt driven solution. 13.4 Refer to the TI website for SW examples ([5] and [6]). Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been transmitted. Additionally, for packets longer than 64 bytes 14 Modulation Formats CC2550 CC2550 supports amplitude, frequency and phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register. Manchester encoding is not supported at the same time as using the FEC/Interleaver option. Optionally, the data stream can be Manchester coded by the modulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. SWRS039B SWRS039B Page 22 of 58 CC2550 CC2550 14.1 Frequency Shift Keying 14.2 Minimum Shift Keying 2-FSK can optionally be shaped by a Gaussian filter with BT=1, producing a GFSK modulated signal. When using MSK1, the complete transmission (preamble, sync word and payload) will be MSK modulated. The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by: Phase shifts are performed with a constant transition time. f dev = f xosc (8 + DEVIATION _ M ) 2 DEVIATION _ E 17 2 The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol. The MSK modulation format implemented in CC2550 CC2550 inverts the sync word and data compared to e.g. signal generators. The symbol encoding is shown in Table 17. Format Symbol Coding 14.3 Amplitude Modulation 2-FSK\GFSK `0' ­ Deviation `1' + Deviation The supported amplitude modulation On-Off Keying (OOK) simply turns on or off the PA to modulate 1 and 0 respectively. Table 17: Symbol Encoding for 2-FSK/GFSK Modulation 1 Identical to offset QPSK with half-sine shaping (data coding may differ) 15 Forward Error Correction with Interleaving 15.1 Forward Error Correction (FEC) CC2550 CC2550 has built in support for Forward Error Correction (FEC) that can be used with CC2500 CC2500 [9] at the receiver end. To enable this option, set MDMCFG1.FEC_EN=1. FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data in such a way that the CC2500 CC2500 [9] can restore the original data in the presence of some bit errors. The use of FEC allows correct reception at a lower SNR, thus extending communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate (PER) is related to BER by: PER = 1 - (1 - BER) packet _ length a lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, SWRS039B SWRS039B transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors). The FEC scheme adopted for CC2550 CC2550 is convolutional coding, in which n bits are generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the m-bit window). The convolutional coder is a rate 1/2 code with a constraint length of m=4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. I.e. to transmit at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate. I.e. to transmit at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate. This will require a higher CC2500 CC2500 [9] receiver bandwidth, and thus reduced sensitivity. In other words, the improved reception by using FEC and the degraded Page 23 of 58 CC2550 CC2550 sensitivity from a higher receiver bandwidth will be counteracting factors. into the rows of the matrix, whereas the data passed onto the convolutional decoder is read from the columns of the matrix. 15.2 Interleaving When FEC and interleaving is used at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO in a CC2500 CC2500 [9]. Data received through radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving on the receiver side, a continuous span of errors in the received stream will become single errors spread apart. CC2550 CC2550 employs matrix interleaving, which is illustrated in Figure 12. The on-chip interleaving buffer is a 4 x 4 matrix. The data bits from the rate ½ convolutional coder are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix. Conversely, in a CC2500 CC2500 [9] receiver, the received symbols are written Interleaver Write buffer Packet Engine FEC Encoder When FEC and interleaving is used the minimum data payload is 2 bytes. Note that for the CC2500 CC2500 [9] transceiver FEC is only supported in fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). Interleaver Read buffer Modulator Figure 12: General Principle of Matrix Interleaving SWRS039B SWRS039B Page 24 of 58 CC2550 CC2550 16 Radio Control SIDLE SLEEP 0 SPWD CAL_COMPLETE MANCAL 3,4,5 CSn = 0 IDLE 1 SXOFF SCAL CSn = 0 XOFF 2 STX | SFSTXON FS_WAKEUP 6,7 FS_AUTOCAL = 01 & STX | SFSTXON FS_AUTOCAL = 00 | 10 | 11 & STX | SFSTXON SETTLING 9,10,11 SFSTXON FSTXON 18 CALIBRATE 8 CAL_COMPLETE STX STX TXOFF_MODE = 01 TXOFF_MODE = 10 TX 19,20 TXFIFO_UNDERFLOW TXOFF_MODE = 00 & FS_AUTOCAL = 10 | 11 CALIBRATE 12 TXOFF_MODE = 00 & FS_AUTOCAL = 00 | 01 TX_UNDERFLOW 22 SFTX IDLE 1 Figure 13: Complete Radio Control State Diagram CC2550 CC2550 has a built-in state machine that is used to switch between different operation states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. A simplified state diagram, together with typical usage and current consumption, is shown in Figure 4 on page 13. The complete radio control state diagram is shown in Figure SWRS039B SWRS039B 13. The numbers refer to the state number readable in the MARCSTATE status register. This register is primarily for test purposes. 16.1 Power-On Start-Up Sequence When the power supply is turned on, the system must be reset. One of the following two Page 25 of 58 CC2550 CC2550 sequences must be followed: Automatic power-on reset (POR) or manual reset. 16.1.1 Automatic POR A power-on reset circuit is included in the CC2550 CC2550. The minimum requirements stated in Section 4.7 must be followed for the power-on reset to function properly. The internal powerup sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section 10.1 for more details on CHIP_RDYn. When the CC2550 CC2550 reset is completed the chip will be in the IDLE state and the crystal oscillator will be running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed the SO pin will first go high, indicating that the crystal oscillator is not stabilized, before going low as shown in Figure 14. Figure 14: Power-On Reset 16.1.2 Manual Reset The other global reset possibility on CC2550 CC2550 is the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual powerup sequence is as follows (see Figure 15): · Strobe CSn low / high. · Hold CSn high for at least 40 µs relative to pulling CSn low · Pull CSn low and wait for SO to go low (CHIP_RDYn). · Issue the SRES strobe on the SI line. · When SO goes low again, reset is complete and the chip is in the IDLE state. XOSC and voltage regulator switched on 40 us CSn SO XOSC Stable SI SRES Figure 15: Power-On Reset with SRES Note that the above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC2550 CC2550 after this, it is only necessary to issue an SRES command strobe. 16.2 Crystal Control The crystal oscillator is automatically turned on when CSn goes low. It will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be used; as described in Section 10.1 on page 15. Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in Section 4.3 on page 7. 16.3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state, which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is now in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state. All CC2550 CC2550 register values (with the exception of the MCSM0.PO_TIMEOUT field) are lost in SWRS039B SWRS039B Page 26 of 58 CC2550 CC2550 the SLEEP state. After the chip gets back to the IDLE state, the registers will have default (reset) contents and must be reprogrammed over the SPI interface. 16.4 TX Mode Transmit mode is activated by the MCU by using the STX command strobe. The frequency synthesizer must be calibrated regularly. CC2550 CC2550 has one manual calibration option (using the SCAL strobe), and three automatic calibration options, controlled by the MCSM0.FS_AUTOCAL setting: · Calibrate when going from IDLE to TX (or FSTXON) · Calibrate when going from TX to IDLE automatically · Calibrate every fourth time when going from TX to IDLE automatically If the radio goes from TX to IDLE by issuing an SIDLE strobe, calibration will not be performed. The calibration takes a constant number of XOSC cycles (see Table 18 for timing details). FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX. · TX: Start sending preambles The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. 16.5 Timing The radio controller controls most timing in CC2550 CC2550, such as synthesizer calibration and PLL lock time. Timing from IDLE to TX is constant, dependent on the auto calibration setting. The calibration time is constant 18739 clock periods. Table 18 shows timing in crystal clock cycles for key state transitions. Power on time and XOSC start-up times are variable, but within the limits stated in Table 6. Note that in a frequency hopping spread spectrum or a multi-channel protocol the calibration time can be reduced from 721 µs to approximately 150 µs. This is explained in Section 27.2. IDLE Description XOSC Periods 26 MHz Crystal Idle to TX/FSTXON, no calibration 2298 88.4 µs Idle to TX/FSTXON, with calibration ~21037 809 µs TX to IDLE, no calibration 2 0.1 µs TX to IDLE, including calibration ~18739 721 µs Manual calibration After activating TX mode, the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are: · · ~18739 721 µs Table 18: State Transition Timing 17 TX FIFO The CC2550 CC2550 contains a 64 byte FIFO for data to be transmitted. The SPI interface is used for writing to the TX FIFO. Section 10.5 contains details on the SPI FIFO access. The FIFO controller will detect underflow in the TX FIFO. When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflow will result in an error in the TX FIFO content. The chip status byte that is available on the SO pin while transferring the SPI address contains the fill grade of the TX FIFO if the R/W bit in SWRS039B SWRS039B the header byte is 0. Section 10.1 on page 15 contains more details on this. The number of bytes in the TX FIFO can also be read from the TXBYTES.NUM_TXBYTES status register. The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the FIFO. Table 19 lists the 16 FIFO_THR settings and the corresponding thresholds for the TX FIFO. A signal will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. The signal can be Page 27 of 58 CC2550 CC2550 viewed on the GDO pins (see Section 25 on page 33). Figure 17 shows the number of bytes in the TX FIFO when the threshold flag toggles, in the case of FIFO_THR=13. Figure 16 shows the signal as the FIFO is filled above the threshold, and then drained below. FIFO_THR 29 9 (1001) 25 10 (1010) 21 11 (1011) 17 12 (1100) 13 13 (1101) 9 14 (1110) 5 15 (1111) 1 Figure 16: FIFO_THR=13 vs. Number of Bytes in FIFO (GDOx_CFG=0x02) 33 8 (1000) GDO 37 7 (0111) 6 41 6 (0110) 7 45 5 (0101) 8 49 4 (0100) 9 10 9 53 3 (0011) 8 57 2 (0010) 7 61 1 (0001) 6 Bytes in TX FIFO 0 (0000) NUM_TXBYTES FIFO_THR=13 Underflow margin 8 bytes TXFIFO Figure 17: Example of FIFO at Threshold Table 19: FIFO_THR Settings and the Corresponding FIFO Thresholds 18 Frequency Programming The frequency programming in CC2550 CC2550 is designed to minimize the programming needed in a channel-oriented system. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. f carrier = ( ( The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1 and FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be used. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by: f XOSC FREQ + CHAN (256 + CHANSPC _ M ) 2 CHANSPC _ E -2 216 SWRS039B SWRS039B ) Page 28 of 58 CC2550 CC2550 With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get e.g. 1 MHz channel spacing one solution is to use 333 kHz channel spacing and select each third channel in CHANNR.CHAN. 19 VCO The VCO is completely integrated on-chip. calibration is initiated when the SCAL command strobe is activated in the IDLE mode. 19.1 VCO and PLL Self-Calibration The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation, CC2550 CC2550 includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 18 on page 27. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the 20 If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state. The calibration values are not maintained in sleep mode. Therefore, the CC2550 CC2550 must be recalibrated after reprogramming the configuration registers when the chip has been in the SLEEP state. To check that the PLL is in lock the user can program register IOCFGx.GDOx_CFG to 0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0 or 1). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC2550 CC2550 Errata Notes [1]. For more robust operation the source code could include a check so that the PLL is recalibrated until PLL lock is achieved if the PLL does not lock the first time. Voltage Regulators CC2550 CC2550 contains several on-chip linear voltage regulators, which generate the supply voltage needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and required pin voltages in Table 1 and Table 11 are not exceeded. The voltage regulator for the digital core requires one external decoupling capacitor. If the chip is programmed to enter power-down mode, (SPWD strobe issued), the power will be turned off after CSn goes high. The power and crystal oscillator will be turned on again when CSn goes low. The voltage regulator output should only be used for driving the CC2550 CC2550. Setting the CSn pin low turns on the voltage regulator to the digital core and starts the crystal oscillator. The SO pin on the SPI interface must go low before the first positive edge of SCLK (setup time is given in Table 14). SWRS039B SWRS039B Page 29 of 58 CC2550 CC2550 21 Output Power Programming The RF output power level from the device has two levels of programmability, as illustrated in Figure 18. The RF output power level from the device is programmed through the PATABLE register. · · If 2-FSK, GFSK or MSK modulation is used the desired output power is programmed to index 0 in the PATABLE register (PATABLE(0)[7:0]). The 3-bit FREND0.PA_POWER value shall be set to 0 (reset default value). If OOK modulation is used the desired output power for the logic 0 and logic 1 power levels are programmed to index 0 and index 1 in the PATABLE register respectively (PATABLE(0)[7:0] and PATABLE(1)[7:0]). The 3-bit FREND0.PA_POWER value shall be set to 1. Table 20 contains recommended PATABLE settings for various output levels and frequency bands. See Section 10.6 on page 17 for PATABLE programming details. The SmartRF® Studio software [4] should be used to obtain optimum PATABLE settings for various output powers. PATABLE must be programmed in burst mode if writing to other entries than PATABLE(0) (OOK modulation). Note that all content of the PATABLE is lost when entering the SLEEP state. Figure 18: PA_POWER and PATABLE SWRS039B SWRS039B Page 30 of 58 CC2550 CC2550 PATABLE(7)[7:0] The PA uses this setting. PATABLE(6)[7:0] PATABLE(5)[7:0] PATABLE(4)[7:0] Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for OOK modulation. PATABLE(3)[7:0] PATABLE(2)[7:0] PATABLE(1)[7:0] PATABLE(0)[7:0] Index into PATABLE(7:0) e.g 6 PA_POWER[2:0] in FREND0 register The SmartRF® Studio software should be used to obtain optimum PATABLE settings for various output powers. Figure 19: PA_POWER and PATABLE Output Power, Typical, o +25 C, 3.0 V [dBm] PATABLE Value Current Consumption, Typical [mA] (­55 or less) 0x00 8.0 ­30 0x44 9.3 ­28 0x41 9.2 ­26 0x43 9.7 ­24 0x84 9.8 ­22 0x82 9.7 ­20 0x47 10.0 ­18 0xC8 11.6 ­16 0x85 10.2 ­14 0x59 11.6 ­12 0xC6 11.2 ­10 0x97 12.0 ­8 0xD6 12.9 ­6 0x7F 14.7 ­4 0xA9 16.2 ­2 0xBF 18.1 0 0xEE 19.4 1 0xFF 21.3 Table 20: Optimum PATABLE Settings for Various Output Power Levels SWRS039B SWRS039B Page 31 of 58 CC2550 CC2550 22 Crystal Oscillator A crystal in the frequency range 26-27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C51 and C71) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency. CL = 1 1 1 + C 51 C 71 The crystal oscillator circuit is shown in Figure 20. Typical component values for different values of CL are given in Table 21. The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see Section 4.3 on page 7). + C parasitic XOSC_Q1 XTAL The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 2.5 pF. Component XOSC_Q2 C51 C71 Figure 20: Crystal Oscillator Circuit CL= 10 pF CL=13 pF CL=16 pF C51 15 pF 22 pF 27 pF C71 15 pF 22 pF 27 pF Table 21: Crystal Oscillator Component Values 22.1 Reference Signal The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This input clock can either be a fullswing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak-peak amplitude. The reference signal must be connected to the 23 XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal this capacitor can be omitted. The XOSC_Q2 line must be left un-connected. C51 and C71 can be omitted when using a reference signal External RF Match The balanced RF output of CC2550 CC2550 is designed for a simple, low-cost matching and balun network on the printed circuit board. A few passive external components ensure proper matching. Although CC2550 CC2550 has a balanced RF output, the chip can be connected to a single-ended antenna with few external low cost capacitors and inductors. differential impedance as seen from the RFport (RF_P and RF_N) towards the antenna: Zout = 80 + j74 To ensure optimal matching of the CC2550 CC2550 differential output it is highly recommended to follow the CC2550EM CC2550EM reference design [3] as closely as possible. Gerber files for the reference designs are available for download from the TI website. The passive matching/filtering network connected to CC2550 CC2550 should have the following SWRS039B SWRS039B Page 32 of 58 CC2550 CC2550 24 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias. The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias for good thermal performance and sufficiently low inductance to ground. In the CC2550EM CC2550EM reference designs [3] 5 vias are placed inside the exposed die attached pad. These vias should be "tented" (covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process. The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using "tented" vias reduces the solder paste coverage below 100%. See Figure 21 for top solder resist and top paste masks. See Figure 24 for recommended PCB layout for QLP 16 package. Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line by separate vias. The best routing is from the power line to the decoupling capacitor and then to the CC2550 CC2550 supply pin. Supply power filtering is very important. Each decoupling capacitor ground pad should be connected to the ground plane using a separate via. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Please note that components smaller than those specified may have differing characteristics. Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry. A CC2500/2550DK CC2500/2550DK Development Kit with a fully assembled CC2550EM CC2550EM Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance. The schematic, BOM and layout Gerber files are all available from the TI website [3]. Figure 21: Left: Top Paste Mask. Right: Top Solder Resist Mask (negative). Circles are Vias. 25 General Purpose / Test Output Control Pins The two digital output pins GDO0 and GDO1 are general control pins configured with IOCFG0.GDO0_CFG and IOCFG1.GDO1_CFG respectively. Table 22 shows the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the MCU. GDO1 is the same pin as the SO pin on the SPI interface, SWRS039B SWRS039B thus the output programmed on this pin will only be valid when CSn is high. The default value for GDO1 is 3-stated, which is useful when the SPI interface is shared with other devices. The default value for GDO0 is a 135-141 kHz clock output (XOSC frequency divided by 192). Since the XOSC is turned on at power-onPage 33 of 58 CC2550 CC2550 reset, this can be used to clock the MCU in systems with only one crystal. When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG. IOCFG0.GDO0_CFG register. The voltage on the GDO0 pin is then proportional to temperature. See Section 4.5 on page 8 for temperature sensor specifications. An on-chip analog temperature sensor is enabled by writing the value 128 (0x80) to the In SLEEP mode, GDO1 will be hardwired to 1 and GDO0 will be high impedance. GDOx_CFG[5:0] 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) to 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) to 40 (0x28) 41 (0x29) 42 (0x2A) 43 (0x2B) 44 (0x2C) 45 (0x2D) 46 (0x2E) 47 (0x2F) 48 (0x30) 49 (0x31) 50 (0x32) 51 (0x33) 52 (0x34) 53 (0x35) 54 (0x36) 55 (0x37) 56 (0x38) 57 (0x39) 58 (0x3A) 59 (0x3B) 60 (0x3C) 61 (0x3D) 62 (0x3E) 63 (0x3F) Description Reserved ­ defined in the transceiver version. Reserved ­ defined in the transceiver version. Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX FIFO is below the same threshold. Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below theTX FIFO threshold. Reserved ­ defined in the transceiver version. Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed. Asserts when sync word has been sent, and de-asserts at the end of the packet. The pin will also de-assert if the TX FIFO underflows. Reserved Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU. Serial Clock. Synchronous to the data in synchronous serial mode. In TX mode, data is sampled by CC2550 CC2550 on the rising edge of the serial clock when GDOx_INV=0. Reserved ­ used for test. CHIP_RDY Reserved ­ used for test. XOSC_STABLE Reserved ­ used for test. GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data). High impedance (3-state) HW to 0 (HW1 achieved with _INV signal). Can be used to control an external PA CLK_XOSC/1 CLK_XOSC/1.5 CLK_XOSC/2 CLK_XOSC/3 CLK_XOSC/4 CLK_XOSC/6 CLK_XOSC/8 Note: There are 2 GDO pins, but only one CLK_XOSC/n can be selected as an output at any CLK_XOSC/12 XOSC/12 time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other GDO pin must be CLK_XOSC/16 XOSC/16 configured to a value less than 0x30. The GDO0 default value is CLK_XOSC/192 XOSC/192. CLK_XOSC/24 XOSC/24 CLK_XOSC/32 XOSC/32 CLK_XOSC/48 XOSC/48 CLK_XOSC/64 XOSC/64 CLK_XOSC/96 XOSC/96 CLK_XOSC/128 XOSC/128 CLK_XOSC/192 XOSC/192 Table 22: GDOx Signal Selection (x = 0 or 1) 26 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC2550 CC2550 to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, SWRS039B SWRS039B significantly offload the microcontroller and simplify software development. 26.1 Asynchronous Operation For backward compatibility with systems already using the asynchronous data transfer from other Chipcon products, asynchronous Page 34 of 58 CC2550 CC2550 transfer is also included in CC2550 CC2550. When asynchronous transfer is enabled, several of the support mechanisms for the MCU that are included in CC2550 CC2550 will be disabled, such as packet handling hardware, buffering in the FIFO and so on. The asynchronous transfer mode does not allow the use of the data whitener, interleaver and FEC, and it is not possible to use Manchester encoding. Note that MSK is asynchronous transfer. not supported Setting PKTCTRL0.PKT_FORMAT enables asynchronous serial mode. to for 3 The GDO0 pin is used for data input (TX data). The CC2550 CC2550 modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate. the synchronous mode, data is transferred on a two wire serial interface. The CC2550 CC2550 provides a clock that is used to set up new data on the data input line. Data input (TX data) is the GDO0 pin. This pin will automatically be configured as an input when TX is active. Preamble and sync word insertion may or may not be active, dependent on the sync mode set by the MDMCFG3.SYNC_MODE. If preamble and sync word is disabled, all other packet handler features and FEC should also be disabled. The MCU must then handle preamble and sync word insertion in software. If preamble and sync word insertion is left on, all packet handling features and FEC can be used. When using the packet handling features in synchronous serial mode, the CC2550 CC2550 will insert the preamble and sync word and the MCU will only provide the data payload. This is equivalent to the recommended FIFO operation mode. 26.2 Synchronous Serial Operation Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial operation mode. In 27 System considerations and Guidelines 27.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. The most important regulations for the 2.4 Ghz band are EN 300 440 and EN 300 328 (Europe), FCC CFR47 CFR47 part 15.247 and 15.249 (USA), and ARIB STD-T66 STD-T66 (Japan). A summary of the most important aspects of these regulations can be found in Application Note AN032 AN032 [2]. Please note that compliance with regulations is dependent on complete system performance. It is the customer's responsibility to ensure that the system complies with regulations. 27.2 Frequency Hopping Channel Systems and Multi- The 2.400 ­ 2.4835 GHz band is shared by many systems both in industrial, office and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multi-channel protocol because the frequency diversity SWRS039B SWRS039B makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading. CC2550 CC2550 is highly suited for FHSS or multichannel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller. Charge pump current, VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC2550 CC2550. There are 3 ways of obtaining the calibration data from the chip: 1) Frequency hopping with calibration for each hop. The PLL calibration time is approximately 720 µs. The blanking interval between each frequency hop is then approximately 810 us. 2) Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting Page 35 of 58 CC2550 CC2550 FSCAL3, FSCAL2 and FSCAL1 register values in MCU memory. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. The PLL turn on time is approximately 90 µs. The blanking interval between each frequency hop is then approximately 90 us. The VCO current calibration result is available in FSCAL2 and is not dependent on the RF frequency. Neither is the charge pump current calibration result available in FSCAL3. The same value can therefore be used for all frequencies. 3) Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4] strobe STX with MCSM0.FS_AUTOCAL=1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from approximately 720 µs to approximately 150 µs. The blanking interval between each frequency hop is then approximately 240 us There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. Solution 3) gives approximately 570 µs smaller blanking interval than solution 1). 27.4 Data Burst Transmissions The high maximum data rate of CC2550 CC2550 opens up for burst transmissions. A low average data rate link (e.g. 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kBaud) will reduce the time in TX mode, and hence also reduce the average current consumption significantly. Reducing the time in TX mode will reduce the likelihood of collisions with other systems, e.g. WLAN. 27.5 Continuous Transmissions In data streaming applications the CC2550 CC2550 opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate.) 27.6 Spectrum Efficient Modulation CC2500 CC2500 also has the possibility to use Gaussian shaped 2-FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In `true' 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift `softer', the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK. 27.7 Low Cost Systems 27.3 Wideband Modulation Spread Spectrum not Using Digital modulation systems under FCC part 15.247 includes 2-FSK and GFSK modulation. A maximum peak output power of 1 W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band. Operating at high data rates and high frequency separation, the CC2550 CC2550 is suited for systems targeting compliance with digital modulation systems as defined by FCC part 15.247. An external power amplifier is needed to increase the output above +1 dBm. A differential antenna will eliminate the need for a balun, and the DC biasing can be achieved in the antenna topology, see Figure 3. The CC25XX CC25XX Folded Dipole reference design [7] contains schematics and layout files for a CC2500EM CC2500EM with a folded dipole PCB antenna. This design note can also be used with the CC2550 CC2550. Please see DN004 DN004 [8] for more details on this design. A HC-49 HC-49 type SMD crystal is used in the CC2550EM CC2550EM reference design. Note that the crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used. 27.8 Battery Operated Systems In low power applications, the SLEEP state should be used when the CC2550 CC2550 is not active. SWRS039B SWRS039B Page 36 of 58 CC2550 CC2550 27.9 Increasing Output Power In some applications it may be necessary to extend the link range by adding an external power amplifier. The power amplifier should be inserted between the antenna and the balun as shown in Figure 22. Figure 22: Block Diagram of CC2550 CC2550 Usage with External Power Amplifier 28 Configuration Registers The configuration of CC2550 CC2550 is done by programming 8-bit registers. The optimum configuration data based on selected system parameters are most easily found by using the SmartRF® Studio software [4]. Complete descriptions of the registers are given in the following tables. After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface. There are 9 command strobe registers, listed in Table 23. Accessing these registers will initiate the change of an internal state or mode. There are 29 normal 8-bit configuration registers, listed in Table 24. Some of these registers are for test purposes only, and need not be written for normal operation of CC2550 CC2550. There are also 6 status registers, which are listed in Table 25. These registers, which are read-only, contain information about the status of CC2550 CC2550. SWRS039B SWRS039B The TX FIFO is accessed through one 8-bit register. Only write operations are allowed to the TX FIFO. During the header byte transfer and while writing data to a register or the TX FIFO, a status byte is returned on the SO line. This status byte is described in Table 15 on page 16. Table 26 summarizes the SPI address space. Registers that are only defined in the CC2500 CC2500 transceiver are also listed. CC2500 CC2500 and CC2550 CC2550 are register compatible, but registers and fields only implemented in the transceiver always contain 0 in CC255 CC255