CC1101 CC1100 SWRS061E J-STD-020C C101C CC1101EM DN010 AN050 DN013 SMAFF-433 - Datasheet Archive

 

Low-Power Sub-1 GHz RF Transceiver (Enhanced CC1100 ) Applications · Ultra low-power wireless applications operating in

 

CC1101 CC1101 Low-Power Sub-1 GHz RF Transceiver (Enhanced CC1100 CC1100 ) Applications · Ultra low-power wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands · Wireless alarm and security systems · Industrial monitoring and control · · · · Wireless sensor networks AMR ­ Automatic Meter Reading Home and building automation Wireless MBUS Product Description The CC1101 CC1101 is a low-cost sub-1 GHz transceiver designed for very low-power wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868, and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-348 MHz, 387-464 MHz and 779-928 MHz bands. The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 500 kBaud. CC1101 CC1101 is an improved and code compatible version of the CC1100 CC1100 RF transceiver. The main improvements on the CC1101 CC1101 include [1]: The main operating parameters and the 64byte transmit/receive FIFOs of CC1101 CC1101 can be controlled via an SPI interface. In a typical system, the CC1101 CC1101 will be used together with a microcontroller and a few additional passive components. Higher input saturation level · Improved output power ramping · Extended frequency bands of operation, i.e. CC1100 CC1100: 400-464 MHz and 800-928 MHz CC1101 CC1101: 387-464 MHz and 779-928 MHz 16 · 17 Better close-in phase noise thus improved Adjacent Channel Power (ACP) performance 18 · 19 Improved spurious response for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio. 20 · CC1101 CC1101 provides extensive hardware support 1 2 3 15 CC1101 CC1101 14 13 10 9 8 11 7 12 5 6 4 This product shall not be used in any of the following products or systems without prior express written permission from Texas Instruments: (i) (ii) (iii) implantable cardiac rhythm management systems, including without limitation pacemakers, defibrillators and cardiac resynchronization devices, external cardiac rhythm management systems that communicate directly with one or more implantable medical devices; or other devices used to monitor or treat cardiac function, including without limitation pressure sensors, biochemical sensors and neurostimulators. Please contact lpw-medical-approval@list.ti.com if your application might fall within the category described above. SWRS061E SWRS061E Page 1 of 97 CC1101 CC1101 Key Features · RF Performance · · · · · · High sensitivity (­112 dBm at 1.2 kBaud, 868 MHz, 1% packet error rate) Low current consumption (14.7 mA in RX, 1.2 kBaud, 868 MHz) Programmable output power up to +12 dBm for all supported frequencies Excellent receiver selectivity and blocking performance Programmable data rate from 1.2 to 500 kBaud Frequency bands: 300-348 MHz, 387-464 MHz and 779-928 MHz · · · Low-Power Features · · Analog Features · · · · 2-FSK, GFSK, and MSK supported as well as OOK and flexible ASK shaping Suitable for frequency hopping systems due to a fast settling frequency synthesizer; 90 µs settling time Automatic Frequency Compensation (AFC) can be used to align the frequency synthesizer to the received signal centre frequency Integrated analog temperature sensor Digital Features · · · · · · · SWRS061E SWRS061E 200 nA sleep mode current consumption Fast startup time; 240 µs from sleep to RX or TX mode (measured on EM reference design [2] and [3]) Wake-on-radio functionality for automatic low-power RX polling Separate 64-byte RX and TX data FIFOs (enables burst mode data transmission) General · · · Flexible support for packet oriented systems; On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling Efficient SPI interface; All registers can be programmed with one "burst" transfer Digital RSSI output Programmable channel filter bandwidth Programmable Carrier Sense (CS) indicator Programmable Preamble Quality Indicator (PQI) for improved protection against false sync word detection in random noise Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) Support for per-package Link Quality Indication (LQI) Optional automatic whitening and dewhitening of data · · · Few external components; Completely onchip frequency synthesizer, no external filters or RF switch needed Green package: RoHS compliant and no antimony or bromine Small size (QLP 4x4 mm package, 20 pins) Suited for systems targeting compliance with EN 300 220 (Europe) and FCC CFR Part 15 (US) Suited for systems targeting compliance with the Wireless MBUS standard EN 13757-4:2005 Support for asynchronous and synchronous serial receive/transmit mode for backwards compatibility with existing radio communication protocols Page 2 of 97 CC1101 CC1101 Abbreviations Abbreviations used in this data sheet are described below. ACP Adjacent Channel Power MSK ADC Analog to Digital Converter N/A Minimum Shift Keying Not Applicable AFC Automatic Frequency Compensation NRZ Non Return to Zero (Coding) AGC AMR ASK Automatic Gain Control Automatic Meter Reading Amplitude Shift Keying OOK PA PCB On-Off Keying Power Amplifier Printed Circuit Board BER Bit Error Rate PD Power Down BT Bandwidth-Time product PER Packet Error Rate CCA Clear Channel Assessment PLL Phase Locked Loop CFR Code of Federal Regulations POR Power-On Reset CRC Cyclic Redundancy Check PQI Preamble Quality Indicator CS Carrier Sense PQT Preamble Quality Threshold CW Continuous Wave (Unmodulated Carrier) PTAT Proportional To Absolute Temperature DC Direct Current QLP Quad Leadless Package DVGA Digital Variable Gain Amplifier QPSK Quadrature Phase Shift Keying ESR Equivalent Series Resistance RC Resistor-Capacitor FCC Federal Communications Commission RF Radio Frequency FEC Forward Error Correction RSSI Received Signal Strength Indicator FIFO First-In-First-Out RX Receive, Receive Mode FHSS Frequency Hopping Spread Spectrum SAW Surface Aqustic Wave 2-FSK Binary Frequency Shift Keying SMD Surface Mount Device GFSK Gaussian shaped Frequency Shift Keying SNR Signal to Noise Ratio IF Intermediate Frequency SPI Serial Peripheral Interface I/Q In-Phase/Quadrature SRD Short Range Devices ISM Industrial, Scientific, Medical TBD To Be Defined LC Inductor-Capacitor T/R Transmit/Receive LNA Low Noise Amplifier TX Transmit, Transmit Mode LO Local Oscillator UHF Ultra High frequency LSB Least Significant Bit VCO Voltage Controlled Oscillator LQI Link Quality Indicator WOR Wake on Radio, Low power polling MCU Microcontroller Unit XOSC Crystal Oscillator MSB Most Significant Bit XTAL Crystal SWRS061E SWRS061E Page 3 of 97 CC1101 CC1101 Table Of Contents APPLICATIONS . 1 PRODUCT DESCRIPTION. 1 KEY FEATURES . 1 KEY FEATURES . 2 RF PERFORMANCE . 2 ANALOG FEATURES . 2 DIGITAL FEATURES. 2 LOW-POWER FEATURES. 2 GENERAL . 2 ABBREVIATIONS. 3 TABLE OF CONTENTS . 4 1 ABSOLUTE MAXIMUM RATINGS . 7 2 OPERATING CONDITIONS . 7 3 GENERAL CHARACTERISTICS. 7 4 ELECTRICAL SPECIFICATIONS . 8 4.1 CURRENT CONSUMPTION . 8 4.2 RF RECEIVE SECTION . 11 4.3 RF TRANSMIT SECTION . 15 4.4 CRYSTAL OSCILLATOR . 17 4.5 LOW POWER RC OSCILLATOR . 17 4.6 FREQUENCY SYNTHESIZER CHARACTERISTICS . 18 4.7 ANALOG TEMPERATURE SENSOR . 18 4.8 DC CHARACTERISTICS . 19 4.9 POWER-ON RESET . 19 5 PIN CONFIGURATION. 20 6 CIRCUIT DESCRIPTION . 22 7 APPLICATION CIRCUIT . 22 7.1 BIAS RESISTOR . 22 7.2 BALUN AND RF MATCHING . 23 7.3 CRYSTAL . 23 7.4 REFERENCE SIGNAL . 23 7.5 ADDITIONAL FILTERING . 23 7.6 POWER SUPPLY DECOUPLING . 24 7.7 ANTENNA CONSIDERATIONS . 24 7.8 PCB LAYOUT RECOMMENDATIONS . 26 8 CONFIGURATION OVERVIEW . 27 9 CONFIGURATION SOFTWARE. 29 10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE . 29 10.1 CHIP STATUS BYTE . 31 10.2 REGISTER ACCESS . 31 10.3 SPI READ . 32 10.4 COMMAND STROBES . 32 10.5 FIFO ACCESS . 32 10.6 PATABLE ACCESS . 33 11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION . 34 11.1 CONFIGURATION INTERFACE . 34 11.2 GENERAL CONTROL AND STATUS PINS . 34 11.3 OPTIONAL RADIO CONTROL FEATURE . 34 12 DATA RATE PROGRAMMING. 35 13 RECEIVER CHANNEL FILTER BANDWIDTH . 35 SWRS061E SWRS061E Page 4 of 97 CC1101 CC1101 14 14.1 14.2 14.3 15 15.1 15.2 15.3 15.4 15.5 15.6 16 16.1 16.2 16.3 17 17.1 17.2 17.3 17.4 17.5 17.6 18 18.1 18.2 19 19.1 19.2 19.3 19.4 19.5 19.6 19.7 20 21 22 22.1 23 24 25 26 27 27.1 27.2 28 28.1 28.2 28.3 28.4 28.5 28.6 28.7 28.8 28.9 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION. 36 FREQUENCY OFFSET COMPENSATION. 36 BIT SYNCHRONIZATION . 36 BYTE SYNCHRONIZATION . 36 PACKET HANDLING HARDWARE SUPPORT . 37 DATA WHITENING . 37 PACKET FORMAT . 38 PACKET FILTERING IN RECEIVE MODE . 40 PACKET HANDLING IN TRANSMIT MODE . 40 PACKET HANDLING IN RECEIVE MODE . 41 PACKET HANDLING IN FIRMWARE . 41 MODULATION FORMATS . 42 FREQUENCY SHIFT KEYING . 42 MINIMUM SHIFT KEYING. 42 AMPLITUDE MODULATION . 43 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION . 43 SYNC WORD QUALIFIER . 43 PREAMBLE QUALITY THRESHOLD (PQT) . 43 RSSI. 44 CARRIER SENSE (CS). 45 CLEAR CHANNEL ASSESSMENT (CCA) . 47 LINK QUALITY INDICATOR (LQI) . 47 FORWARD ERROR CORRECTION WITH INTERLEAVING . 47 FORWARD ERROR CORRECTION (FEC). 47 INTERLEAVING . 48 RADIO CONTROL. 49 POWER-ON START-UP SEQUENCE . 49 CRYSTAL CONTROL . 50 VOLTAGE REGULATOR CONTROL. 51 ACTIVE MODES . 51 WAKE ON RADIO (WOR). 52 TIMING . 53 RX TERMINATION TIMER . 53 DATA FIFO . 54 FREQUENCY PROGRAMMING. 55 VCO . 56 VCO AND PLL SELF-CALIBRATION . 56 VOLTAGE REGULATORS . 56 OUTPUT POWER PROGRAMMING . 56 SHAPING AND PA RAMPING. 58 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS . 59 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION . 61 ASYNCHRONOUS SERIAL OPERATION . 61 SYNCHRONOUS SERIAL OPERATION . 61 SYSTEM CONSIDERATIONS AND GUIDELINES . 62 SRD REGULATIONS . 62 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS . 62 WIDEBAND MODULATION WHEN NOT USING SPREAD SPECTRUM . 63 WIRELESS MBUS. 63 DATA BURST TRANSMISSIONS. 63 CONTINUOUS TRANSMISSIONS . 63 LOW COST SYSTEMS . 63 BATTERY OPERATED SYSTEMS . 64 INCREASING OUTPUT POWER . 64 SWRS061E SWRS061E Page 5 of 97 CC1101 CC1101 29 29.1 29.2 29.3 30 30.1 30.2 31 32 33 33.1 CONFIGURATION REGISTERS. 64 CONFIGURATION REGISTER DETAILS ­ REGISTERS WITH PRESERVED VALUES IN SLEEP STATE . 69 CONFIGURATION REGISTER DETAILS ­ REGISTERS THAT LOOSE PROGRAMMING IN SLEEP STATE . 89 STATUS REGISTER DETAILS. 90 PACKAGE DESCRIPTION (QFN 20). 93 RECOMMENDED PCB LAYOUT FOR PACKAGE (QFN 20). 93 SOLDERING INFORMATION . 93 ORDERING INFORMATION. 94 REFERENCES . 95 GENERAL INFORMATION. 96 DOCUMENT HISTORY . 96 SWRS061E SWRS061E Page 6 of 97 CC1101 CC1101 1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Min Max Units Supply voltage ­0.3 3.9 V Voltage on any digital pin ­0.3 VDD + 0.3, max 3.9 V Voltage on the pins RF_P, RF_N, DCOUPL, RBIAS ­0.3 2.0 V Voltage ramp-up rate 120 kV/µs Input RF level +10 dBm 150 °C Solder reflow temperature 260 °C According to IPC/JEDEC J-STD-020C J-STD-020C ESD 750 V According to JEDEC STD 22, method A114, Human Body Model (HBM) ESD 400 V According to JEDEC STD 22, C101C C101C, Charged Device Model (CDM) Storage temperature range ­50 Condition All supply pins must have the same voltage Table 1: Absolute Maximum Ratings Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. 2 Operating Conditions The operating conditions for CC1101 CC1101 are listed Table 2 in below. Parameter Min Max Unit Operating temperature -40 85 °C Operating supply voltage 1.8 3.6 V Condition All supply pins must have the same voltage Table 2: Operating Conditions 3 General Characteristics Parameter Min Frequency range Typ Max Unit 300 348 MHz 387 464 MHz Condition/Note If using a 27 MHz crystal, the lower frequency limit for this band is 392 MHz 779 Data rate 928 MHz 1.2 500 kBaud 2-FSK 1.2 250 kBaud GFSK, OOK, and ASK 26 500 kBaud (Shaped) MSK (also known as differential offset QPSK) Optional Manchester encoding (the data rate in kbps will be half the baud rate) Table 3: General Characteristics SWRS061E SWRS061E Page 7 of 97 CC1101 CC1101 4 Electrical Specifications 4.1 Current Consumption TA = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM CC1101EM reference designs ([2] and [3]). Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Table 7 for additional details on current consumption and sensitivity. Parameter Min Typ Max 0.2 1 Unit Condition µA Voltage regulator to digital part off, register values retained, lowpower RC oscillator running (SLEEP state with WOR enabled) µA Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set) 165 µA Voltage regulator to digital part on, all other modules in power down (XOFF state) 9.8 µA Automatic RX polling once each second, using low-power RC oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate, th PLL calibration every 4 wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1) 34.2 µA Same as above, but with signal in channel above carrier sense level, 1.95 ms RX timeout, and no preamble/sync word found 1.5 µA Automatic RX polling every 15 second, using low-power RC oscillator, with 460kHz filter bandwidth and 250 kBaud data rate, th PLL calibration every 4 wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1) 39.3 µA Same as above, but with signal in channel above carrier sense level, 29.3 ms RX timeout, and no preamble/sync word found 1.7 mA Only voltage regulator to digital part and crystal oscillator running (IDLE state) 8.4 Current consumption, 315 MHz Voltage regulator to digital part off, register values retained (SLEEP state). All GDO pins programmed to 0x2F (HW to 0) 100 Current consumption µA 0.5 Current consumption in power down modes mA Only the frequency synthesizer is running (FSTXON state). This currents consumption is also representative for the other intermediate states when going from IDLE to RX or TX, including the calibration state 15.4 mA Receive mode, 1.2 kBaud, reduced current, input at sensitivity limit 14.4 mA Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit 15.2 mA Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit 14.3 mA Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit 16.5 mA Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit 15.1 mA Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit 27.4 mA Transmit mode, +10 dBm output power 15.0 mA Transmit mode, 0 dBm output power 12.3 mA Transmit mode, ­6 dBm output power th SWRS061E SWRS061E Page 8 of 97 CC1101 CC1101 Parameter Condition 16.0 mA Receive mode, 1.2 kBaud, register settings optimized for reduced current, input at sensitivity limit mA Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit 15.7 mA Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit 15.0 mA Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit 17.1 mA Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit 15.7 mA Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit 29.2 mA Transmit mode, +10 dBm output power 16.0 mA Transmit mode, 0 dBm output power 13.1 Current consumption, 868/915 MHz Unit 15.0 Current consumption, 433 MHz Min Typ Max mA Transmit mode, ­6 dBm output power 15.7 mA Receive mode, 1.2 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 1 for current consumption with register settings optimized for sensitivity. 14.7 mA Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 1 for current consumption with register settings optimized for sensitivity. 15.6 mA Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 1 for current consumption with register settings optimized for sensitivity. 14.6 mA Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 1 for current consumption with register settings optimized for sensitivity. 16.9 mA Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 1 for current consumption with register settings optimized for sensitivity. 15.6 mA Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 1 for current consumption with register settings optimized for sensitivity. 34.2 mA Transmit mode, +12 dBm output power, 868 MHz 30.0 mA Transmit mode, +10 dBm output power, 868 MHz 16.8 mA Transmit mode, 0 dBm output power, 868 MHz 16.4 mA Transmit mode, ­6 dBm output power, 868 MHz. 33.4 mA Transmit mode, +11 dBm output power, 915 MHz 30.7 mA Transmit mode, +10 dBm output power, 915 MHz 17.2 mA Transmit mode, 0 dBm output power, 915 MHz 17.0 mA Transmit mode, ­6 dBm output power, 915 MHz Table 4: Current Consumption SWRS061E SWRS061E Page 9 of 97 CC1101 CC1101 Temperature [°C] Current [mA], PATABLE=0xC0, +12 dBm Current [mA], PATABLE=0xC5, +10 dBm Current [mA], PATABLE=0x50, 0 dBm Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.0 V -40 25 85 Supply Voltage VDD = 3.6 V -40 25 85 32.7 31.5 30.5 35.3 34.2 33.3 35.5 34.4 33.5 30.1 29.2 28.3 30.9 30.0 29.4 31.1 30.3 29.6 16.4 16.0 15.6 17.3 16.8 16.4 17.6 17.1 16.7 Table 5: Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz Temperature [°C] Current [mA], PATABLE=0xC0, +11 dBm Current [mA], PATABLE=0xC3, +10 dBm Current [mA], PATABLE=0x8E, 0 dBm Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.0 V -40 25 85 Supply Voltage VDD = 3.6 V -40 25 85 31.9 30.7 29.8 34.6 33.4 32.5 34.8 33.6 32.7 30.9 29.8 28.9 31.7 30.7 30.0 31.9 31.0 30.2 17.2 16.8 16.4 17.6 17.2 16.9 17.8 17.4 17.1 Table 6: Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz 17,8 19,5 19 17,4 17,2 17 -40C 16,8 +85C +25C 16,6 Current [mA] Current [mA] 17,6 18,5 -40C 18 +25C 17,5 +85C 17 16,4 16,2 -110 -90 -70 -50 -30 16,5 -100 -10 -80 -60 Input Power Level [dBm] 1.2 kBaud GFSK -20 250 kBaud GFSK 19,5 17,8 17,6 19,0 17,4 17,2 17,0 -40C 16,8 +85C +25C 16,6 16,4 16,2 -100 Current [mA] Current [mA] -40 Input Power Level [dBm] -40C 18,5 +25C 18,0 +85C 17,5 17,0 -80 -60 -40 -20 -90 Input Power Level [dBm] -70 -50 -30 -10 Input Power Level [dBm] 38.4 kBaud GFSK 500 kBaud MSK Figure 1: Typical RX Current Consumption over Temperature and Input Power Level, 868/915 MHz, Sensitivity Optimized Setting SWRS061E SWRS061E Page 10 of 97 CC1101 CC1101 4.2 RF Receive Section TA = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM CC1101EM reference designs ([2] and [3]). Parameter Spurious emissions Max Unit Condition/Note 812 kHz User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal) -68 ­57 dBm 25 MHz ­ 1 GHz (Maximum figure is the ETSI EN 300 220 limit) -66 Digital channel filter bandwidth Min Typ ­47 dBm Above 1 GHz (Maximum figure is the ETSI EN 300 220 limit) 58 Typical radiated spurious emission is -49 dBm measured at the VCO frequency RX latency 9 bit Serial operation. Time from start of reception until data is available on the receiver data output pin is equal to 9 bit 315 MHz 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity -111 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.2 mA to 15.4 mA at the sensitivity limit. The sensitivity is typically reduced to -109 dBm 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity -88 dBm MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud 433 MHz 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity -112 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.0 mA to 16.0 mA at the sensitivity limit. The sensitivity is typically reduced to -110 dBm 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity ­104 dBm 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) Receiver sensitivity -95 dBm 868/915 MHz 868 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity ­112 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.7 mA at sensitivity limit. The sensitivity is typically reduced to -109 dBm Saturation ­14 dBm FIFOTHR.CLOSE_IN_RX=0. See more in DN010 DN010 [11] Adjacent channel rejection ±100 kHz offset Image channel rejection Blocking ±2 MHz offset ±10 MHz offset 37 dB 31 dB -50 -40 dBm dBm Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing See Figure 2 for selectivity performance at other offset frequencies IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit Desired channel 3 dB above the sensitivity limit See Figure 2 for blocking performance at other offset frequencies SWRS061E SWRS061E Page 11 of 97 CC1101 CC1101 Parameter Min Typ Max Unit Condition/holde Note 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity ­104 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.6 mA at the sensitivity limit. The sensitivity is typically reduced to -102 dBm Saturation ­16 dBm FIFOTHR.CLOSE_IN_RX=0. See more in DN010 DN010 [11] Adjacent channel rejection -200 kHz offset +200 kHz offset 12 25 dB dB Image channel rejection 23 dB Blocking ±2 MHz offset ±10 MHz offset -50 -40 dBm dBm Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing See Figure 3 for blocking performance at other offset frequencies IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit Desired channel 3 dB above the sensitivity limit See Figure 3 for blocking performance at other offset frequencies 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) Receiver sensitivity ­95 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.9 mA to 16.9 mA at the sensitivity limit. The sensitivity is typically reduced to -91 dBm Saturation ­17 dBm FIFOTHR.CLOSE_IN_RX=0. See more in DN010 DN010 [11] Adjacent channel rejection 25 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing See Figure 4 for blocking performance at other offset frequencies Image channel rejection 14 dB IF frequency 304 kHz Desired channel 3 dB above the sensitivity limit Blocking ±2 MHz offset ±10 MHz offset -50 -40 dBm dBm Desired channel 3 dB above the sensitivity limit See Figure 4 for blocking performance at other offset frequencies 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity Image channel rejection Blocking ±2 MHz offset ±10 MHz offset ­90 dBm 1 dB -50 -40 dBm dBm MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud IF frequency 355 kHz Desired channel 3 dB above the sensitivity limit Desired channel 3 dB above the sensitivity limit See Figure 5 for blocking performance at other offset frequencies Table 7: RF Receive Section SWRS061E SWRS061E Page 12 of 97 CC1101 CC1101 Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.6 V -40 25 85 -113 -112 -110 -113 -112 -110 -113 -112 -110 -105 -104 -102 -105 -104 -102 -105 -104 -102 -97 -96 -92 -97 -95 -92 -97 -94 -92 -91 Temperature [°C] Sensitivity [dBm] 1.2 kBaud Sensitivity [dBm] 38.4 kBaud Sensitivity [dBm] 250 kBaud Sensitivity [dBm] 500 kBaud Supply Voltage VDD = 3.0 V -40 25 85 -90 -86 -91 -90 -86 -91 -90 -86 Table 8: Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized Setting Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.6 V -40 25 85 -113 -112 -110 -113 -112 -110 -113 -112 -110 -105 -104 -102 -104 -104 -102 -105 -104 -102 -97 -94 -92 -97 -95 -92 -97 -95 -92 -91 Temperature [°C] Sensitivity [dBm] 1.2 kBaud Sensitivity [dBm] 38.4 kBaud Sensitivity [dBm] 250 kBaud Sensitivity [dBm] 500 kBaud Supply Voltage VDD = 3.0 V -40 25 85 -89 -86 -91 -90 -86 -91 -89 -86 Table 9: Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized Setting 80 60 70 50 60 40 50 Selectivity [dB] Blocking [dB] 40 30 20 10 30 20 10 0 -40 -30 -20 -10 0 10 20 30 40 0 -10 -1 -20 -0,9 -0,8 -0,7 -0,6 -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 -10 Offset [MHz] Offset [MHz] Figure 2: Typical Selectivity at 1.2 kBaud Data Rate, 868.3 MHz, GFSK, 5.2 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 58 kHz SWRS061E SWRS061E Page 13 of 97 1 CC1101 CC1101 50 70 60 40 50 30 Selectivity [dB] Blocking [dB] 40 30 20 20 10 10 0 -1 0 -40 -30 -20 -10 0 10 20 30 -0,9 -0,8 -0,7 -0,6 -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 40 -10 -10 -20 -20 Offset [MHz] Offset [MHz] Figure 3: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, GFSK, 20 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 100 kHz 60 50 50 40 40 30 Selectivity [dB] Blocking [dB] 30 20 10 20 10 0 0 -40 -30 -20 -10 0 10 20 30 -2 40 -1,5 -1 -0,5 0 0,5 1 1,5 2 -10 -10 -20 -20 Offset [MHz] Offset [MHz] Figure 4: Typical Selectivity at 250 kBaud Data Rate, 868 MHz, GFSK, IF Frequency is 304 kHz and the Digital Channel Filter Bandwidth is 540 kHz 60 40 50 30 40 20 Selectivity [dB] Blocking [dB] 30 20 10 0 10 0 -40 -30 -20 -10 0 10 20 30 40 -2 -1,5 -1 -0,5 0 0,5 1 1,5 -10 -10 -20 -30 -20 Offset [MHz] Offset [MHz] Figure 5: Typical Selectivity at 500 kBaud Data Rate, 868 MHz, GFSK, IF Frequency is 355 kHz and the Digital Channel Filter Bandwidth is 812 kHz SWRS061E SWRS061E Page 14 of 97 2 CC1101 CC1101 4.3 RF Transmit Section TA = 25°C, VDD = 3.0 V, +10dBm if nothing else stated. All measurement results are obtained using the CC1101EM CC1101EM reference designs ([2] and [3]). Parameter Min Typ Max Unit Differential load impedance 122 + j31 433 MHz 116 + j41 86.5 + j43 Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1101EM CC1101EM reference designs ([2] and [3]) available from theTI website 868/915 MHz Condition/Note 315 MHz Output power, highest setting 315 MHz +10 dBm 433 MHz +10 dBm 868 MHz +12 dBm 915 MHz +11 dBm Output power, lowest setting -30 dBm Output power is programmable, and full range is available in all frequency bands. Output power may be restricted by regulatory limits. See also Application Note AN050 AN050 [6] and Design Note DN013 DN013 [18], which gives the output power and harmonics when using multi-layer inductors. The output power is then typically +10 dBm when operating at 868/915 MHz. Delivered to a 50 single-ended load via CC1101EM CC1101EM reference designs ([2] and [3]) RF matching network Output power is programmable, and full range is available in all frequency bands Delivered to a 50 single-ended load via CC1101EM CC1101EM reference designs ([2] and [3]) RF matching network Harmonics, radiated Measured on CC1101EM CC1101EM reference designs ([2] and [3]) with CW, maximum output power nd -49 -40 dBm dBm nd -47 -55 dBm dBm nd -50 -54 dBm dBm Note: All harmonics are below -41.2 dBm when operating in the 902 ­ 928 MHz band 315 MHz < -35 < -53 dBm dBm Measured with +10 dBm CW at 315 MHz and 433 MHz Frequencies below 960 MHz Frequencies above 960 MHz 433 MHz -43 < -45 dBm dBm Frequencies below 1 GHz Frequencies above 1 GHz -36 < -46 dBm dBm Measured with +12 dBm CW at 868 MHz -34 dBm Measured with +11 dBm CW at 915 MHz (requirement is -20 dBc under FCC 15.247) < -50 dBm 2 Harm, 433 MHz rd 3 Harm, 433 MHz 2 Harm, 868 MHz rd 3 Harm, 868 MHz 2 Harm, 915 MHz rd 3 Harm, 915 MHz The antennas used during the radiated measurements (SMAFF-433 SMAFF-433 from R.W.Badland and Nearson S331 868/915) play a part in attenuating the harmonics Harmonics, conducted 868 MHz nd 2 Harm other harmonics 915 MHz nd 2 Harm other harmonics SWRS061E SWRS061E Page 15 of 97 CC1101 CC1101 Parameter Min Typ Max Unit Condition/Note Spurious emissions conducted, harmonics not included 315 MHz < -58 < -53 dBm dBm Measured with +10 dBm CW at 315 MHz and 433 MHz Frequencies below 960 MHz Frequencies above 960 MHz 433 MHz < -50 < -54 < -56 dBm dBm dBm Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz 868 MHz < -50 < -52 < -53 dBm dBm dBm Measured with +12 dBm CW at 868 MHz Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz All radiated spurious emissions are within the limits of ETSI. The peak conducted spurious emission is -53 dBm at 699 MHz, which is in a frequency band limited to -54 dBm by EN 300 220. An alternative filter can be used to reduce the emission at 699 MHz below -54 dBm, for conducted measurements, and is shown in Figure 1. See more information in DN017 DN017 [12] 915 MHz TX latency < -51 < -54 dBm dBm 8 bit Measured with +11 dBm CW at 915 MHz Frequencies below 960 MHz Frequencies above 960 MHz Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports Table 10: RF Transmit Section Temperature [°C] Output Power [dBm], PATABLE=0xC0, +12 dBm Output Power [dBm], PATABLE=0xC5, +10 dBm Output Power [dBm], PATABLE=0x50, 0 dBm Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.0 V -40 25 85 Supply Voltage VDD = 3.6 V -40 25 85 12 11 10 12 12 11 12 12 11 11 10 9 11 10 10 11 10 10 1 0 -1 2 1 0 2 1 0 Table 11: Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz Temperature [°C] Output Power [dBm], PATABLE=0xC0, +11 dBm Output Power [dBm], PATABLE=0x8E, +0 dBm Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.0 V -40 25 85 Supply Voltage VDD = 3.6 V -40 25 85 11 10 10 12 11 11 12 11 11 2 1 0 2 1 0 2 1 0 Table 12: Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz SWRS061E SWRS061E Page 16 of 97 CC1101 CC1101 4.4 Crystal Oscillator TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM CC1101EM reference designs ([2] and [3]). Parameter Crystal frequency Min Typ Max Unit 26 26 27 MHz Tolerance Load capacitance ±40 10 ppm 13 20 100 ESR Start-up time pF Condition/Note This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. 150 µs Simulated over operating conditions This parameter is to a large degree crystal dependent. Measured on the CC1101EM CC1101EM reference designs ([2] and [3]) using crystal AT-41CD2 AT-41CD2 from NDK Table 13: Crystal Oscillator Parameters 4.5 Low Power RC Oscillator TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM CC1101EM reference designs ([2] and [3]). Parameter Min Typ Max Calibrated frequency 34.7 34.7 36 kHz ±1 % Frequency accuracy after calibration Temperature coefficient Supply voltage coefficient Initial calibration time Unit Condition/Note Calibrated RC Oscillator frequency is XTAL frequency divided by 750 +0.5 % / °C Frequency drift when temperature changes after calibration +3 %/V Frequency drift when supply voltage changes after calibration 2 ms When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running Table 14: RC Oscillator Parameters SWRS061E SWRS061E Page 17 of 97 CC1101 CC1101 4.6 Frequency Synthesizer Characteristics TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1101EM CC1101EM reference designs ([2] and [3]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal. Parameter Programmed frequency resolution Min Typ 397 Max Unit 412 FXOSC/ 16 2 Condition/Note Hz 26-27 MHz crystal. The resolution (in Hz) is equal for all frequency bands Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing Synthesizer frequency tolerance ±40 ppm RF carrier phase noise ­92 dBc/Hz @ 50 kHz offset from carrier RF carrier phase noise ­92 dBc/Hz @ 100 kHz offset from carrier RF carrier phase noise ­92 dBc/Hz @ 200 kHz offset from carrier RF carrier phase noise ­98 dBc/Hz @ 500 kHz offset from carrier RF carrier phase noise ­107 dBc/Hz @ 1 MHz offset from carrier RF carrier phase noise ­113 dBc/Hz @ 2 MHz offset from carrier RF carrier phase noise ­119 dBc/Hz @ 5 MHz offset from carrier RF carrier phase noise ­129 dBc/Hz @ 10 MHz offset from carrier PLL turn-on / hop time 85.1 88.4 88.4 µs Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running PLL RX/TX settling time 9.3 9.6 9.6 µs Settling time for the 1·IF frequency step from RX to TX PLL TX/RX settling time 20.7 21.5 21.5 µs Settling time for the 1·IF frequency step from TX to RX PLL calibration time 694 721 721 µs Calibration can be initiated manually or automatically before entering or after leaving RX/TX Table 15: Frequency Synthesizer Parameters 4.7 Analog Temperature Sensor TA = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM CC1101EM reference designs ([2] and [3]). Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Parameter Min Typ Max Unit Output voltage at ­40°C 0.651 V Output voltage at 0°C 0.747 V Output voltage at +40°C 0.847 V Output voltage at +80°C 0.945 Condition/Note V Temperature coefficient Error in calculated temperature, calibrated 2.47 -2 * 0 mV/°C 2 * °C Fitted from ­20 °C to +80 °C From ­20 °C to +80 °C when using 2.47 mV / °C, after 1-point calibration at room temperature * The indicated minimum and maximum error with 1point calibration is based on simulated values for typical process parameters Current consumption increase when enabled 0.3 mA Table 16: Analog Temperature Sensor Parameters SWRS061E SWRS061E Page 18 of 97 CC1101 CC1101 4.8 DC Characteristics TA = 25°C if nothing else stated. Digital Inputs/Outputs Min Max Unit Logic "0" input voltage 0 0.7 Logic "1" input voltage Condition V VDD-0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 mA output current Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current Logic "0" input current N/A ­50 nA Input equals 0V Logic "1" input current N/A 50 nA Input equals VDD Table 17: DC Characteristics 4.9 Power-On Reset For proper Power-On-Reset functionality the power supply should comply with the requirements in Table 18 below. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section on page 49 for further details. Parameter Min Power-up ramp-up time Power off time Typ Max 5 1 Unit Condition/Note ms From 0V until reaching 1.8V ms Minimum time between power-on and power-off Table 18: Power-On Reset Requirements SWRS061E SWRS061E Page 19 of 97 CC1101 CC1101 5 Pin Configuration GND RBIAS DGUARD GND SI The CC1101 CC1101 pin-out is shown in Figure 6 and Table 19. See Section 26 for details on the I/O configuration. 20 19 18 17 16 SCLK 1 15 AVDD SO (GDO1) 2 14 AVDD GDO2 3 13 RF_N DVDD 4 12 RF_P DCOUPL 5 11 AVDD 7 8 9 10 GDO0 (ATEST) CSn XOSC_Q1 AVDD XOSC_Q2 6 GND Exposed die attach pad Figure 6: Pinout Top View . Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip Pin # Pin Name Pin type Description 1 SCLK Digital Input Serial configuration interface, clock input 2 SO (GDO1) Digital Output Serial configuration interface, data output Optional general output pin when CSn is high 3 GDO2 Digital Output Digital output pin for general use: · Test signals · FIFO status signals · Clear channel indicator · Clock output, down-divided from XOSC · Serial output RX data 4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O's and for the digital core voltage regulator 5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling NOTE: This pin is intended for use with the CC1101 CC1101 only. It can not be used to provide supply voltage to other devices SWRS061E SWRS061E Page 20 of 97 CC1101 CC1101 Pin # Pin Name Pin type Description 6 GDO0 Digital I/O Digital output pin for general use: · Test signals (ATEST) · FIFO status signals · Clear channel indicator · Clock output, down-divided from XOSC · Serial output RX data · Serial input TX data Also used as analog test I/O for prototype/production testing 7 CSn Digital Input Serial configuration interface, chip select 8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input 9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 10 XOSC_Q2 Analog I/O Crystal oscillator pin 2 11 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 12 RF_P RF I/O Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode 13 RF_N RF I/O Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode 14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 16 GND Ground (Analog) Analog ground connection 17 RBIAS Analog I/O External bias resistor for reference current 18 DGUARD Power (Digital) Power supply connection for digital noise isolation 19 GND Ground (Digital) Ground connection for digital noise isolation 20 SI Digital Input Serial configuration interface, data input Table 19: Pinout Overview SWRS061E SWRS061E Page 21 of 97 CC1101 CC1101 6 Circuit Description FREQ SYNTH 90 PA RC OSC BIAS RBIAS XOSC XOSC_Q1 RXFIFO DIGITAL INTERFACE TO MCU 0 RF_N MODULATOR RF_P TXFIFO ADC PACKET HANDLER LNA FEC / INTERLEAVER ADC DEMODULATOR RADIO CONTROL SCLK SO (GDO1) SI CSn GDO0 (ATEST) GDO2 XOSC_Q2 Figure 7: CC1101 CC1101 Simplified Block Diagram A simplified block diagram of CC1101 CC1101 is shown in Figure 7. CC1101 CC1101 features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering and demodulation bit/packet synchronization are performed digitally. The transmitter part of CC1101 CC1101 is based on direct synthesis of the RF frequency. The 7 frequency synthesizer includes a completely on-chip LC VCO and a 90 degree phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode. A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband includes support for channel configuration, packet handling, and data buffering. Application Circuit Only a few external components are required for using the CC1101 CC1101. The recommended application circuits for CC1101 CC1101 are shown in Figure 8 and Figure 9. The external components are described in Table 20, and typical values are given in Table 21. wound inductors as this give better output power, sensitivity, and attenuation of harmonics compared to using multi-layer inductors. See also Design Note DN013 DN013 [18], which gives the output power and harmonics when using multi-layer inductors. The output power is then typically +10 dBm when operating at 868/915 MHz. The 315 MHz and 433 MHz CC1101EM CC1101EM reference design [2] use inexpensive multilayer inductors. The 868 MHz and 915 MHz CC1101EM CC1101EM reference design [3] use wire7.1 Bias Resistor The bias resistor R171 is used to set an accurate bias current. SWRS061E SWRS061E Page 22 of 97 CC1101 CC1101 7.2 Balun and RF Matching The balanced RF input and output of CC1101 CC1101 share two common pins and are designed for a simple, low-cost matching and balun network on the printed circuit board. The receive- and transmit switching at the CC1101 CC1101 front-end is controlled by a dedicated on-chip function, eliminating the need for an external RX/TXswitch. A few external passive components combined with the internal RX/TX switch/termination circuitry ensures match in both RX and TX mode. The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C121, L121 and L131 for the 315/433 MHz reference design [2], and L121, L131, C121, L122, C131, C122 and L132 for the 868/915 MHz reference design [3]) form a balun that converts the differential RF signal on CC1101 CC1101 to 7.3 a single-ended RF signal. C124 is needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50 load. C125 provides DC blocking and is only needed if there is a DC path in the antenna. For the 868/915 MHz reference design, this component may also be used for additional filtering, see section 7.5 below. Suggested values for 315 MHz, 433 MHz, and 868/915 MHz are listed in Table 21. The balun and LC filter component values and their placement are important to keep the performance optimized. It is highly recommended to follow the CC1101EM CC1101EM reference design ([2] and [3]). Gerber files and schematics for the reference designs are available for download from the TI website. Crystal A crystal in the frequency range 26-27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C81 and C101) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency. CL = 1 1 1 + C81 C101 + C parasitic The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see Section 4.4 on page 17). The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application. The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 2.5 pF. 7.4 Reference Signal The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This input clock can either be a fullswing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak-peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be 7.5 connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal, this capacitor can be omitted. The XOSC_Q2 line must be left un-connected. C81 and C101 can be omitted when using a reference signal. Additional Filtering In the 868/915 MHz reference design, C126 and L125 together with C125 build an optional SWRS061E SWRS061E filter to reduce emission at 699 MHz. This filter is necessary for applications with an external Page 23 of 97 CC1101 CC1101 antenna connector that seek compliance with ETSI EN 300-220. For more information, see DN017 DN017 [12]. If this filtering is not necessary, C125 will work as a DC block (only necessary if there is a DC path in the antenna). C126 and L125 should in that case be left unmounted. 7.6 Power Supply Decoupling The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the 7.7 Additional external components (e.g. an RF SAW filter) may be used in order to improve the performance in specific applications. Replacing the multilayer inductors in the balun, match and filter part of the application circuit with wire-wound inductors also improves the RF performance. For more information, see DN017 DN017 [12]. decoupling capacitors are very important to achieve the optimum performance. The CC1101EM CC1101EM reference designs ([2] and [3]) should be followed closely. Antenna Considerations The reference design ([2] and [3]) contains a SMA connector and is matched for a 50 load. The SMA connector makes it easy to connect evaluation modules and prototypes to different test equipment for example a Component C51 spectrum analyzer. The SMA connector can also be replaced by an antenna suitable for the desired application. Please refer to the antenna selection guide [16] for further details regarding antenna solutions provided by TI. Description Decoupling capacitor for on-chip voltage regulator to digital part C81/C101 C81/C101 Crystal loading capacitors C121/C131 C121/C131 RF balun/matching capacitors C122 RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz). C123 RF LC filter/matching capacitor C124 RF balun DC blocking capacitor C125 RF LC filter DC blocking capacitor and part of optional RF LC filter (868/915 MHz) C126 Part of optional RF LC filter and DC-block (868/915 MHz) L121/L131 L121/L131 RF balun/matching inductors (inexpensive multi-layer type) L122 RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz). (inexpensive multi-layer type) L123 RF LC filter/matching filter inductor (inexpensive multi-layer type) L124 RF LC filter/matching filter inductor (inexpensive multi-layer type) L125 Optional RF LC filter/matching filter inductor (inexpensive multi-layer type) (868/915 MHz) L132 RF balun/matching inductor. (inexpensive multi-layer type) R171 Resistor for internal bias current reference XTAL 26MHz - 27MHz crystal Table 20: Overview of External Components (excluding supply decoupling capacitors) SWRS061E SWRS061E Page 24 of 97 CC1101 CC1101 1.8V-3.6V power supply R171 1 SCLK GND 16 RBIAS 17 DGUARD 18 SI 20 SO (GDO1) GDO2 (optional) 3 GDO2 AVDD 14 C131 L131 C125 RF_N 13 DIE ATTACH PAD: 10 XOSC_Q2 7 CSn 5 DCOUPL 9 AVDD RF_P 12 8 XOSC_Q1 4 DVDD C51 Antenna (50 Ohm) AVDD 15 CC1101 CC1101 2 SO (GDO1) 6 GDO0 Digital Inteface SCLK GND 19 SI AVDD 11 C121 L121 L122 L123 C122 C123 C124 GDO0 (optional) CSn XTAL C81 C101 Figure 8: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply decoupling capacitors) Figure 9: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply decoupling capacitors) SWRS061E SWRS061E Page 25 of 97 CC1101 CC1101 Component Value at 315MHz C51 Value at 433MHz Value at 868/915MHz 100 nF ± 10%, 0402 X5R Manufacturer Murata GRM1555C GRM1555C series C81 27 pF ± 5%, 0402 NP0 Murata GRM1555C GRM1555C series C101 27 pF ± 5%, 0402 NP0 Murata GRM1555C GRM1555C series C121 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.0 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C GRM1555C series C122 12 pF ± 5%, 0402 NP0 8.2 pF ± 0.5 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C GRM1555C series C123 6.8 pF ± 0.5 pF, 0402 NP0 5.6 pF ± 0.5 pF, 0402 NP0 3.3 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C GRM1555C series C124 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0 Murata GRM1555C GRM1555C series C125 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 12 pF ± 5%, 0402 NP0 Murata GRM1555C GRM1555C series 47 pF ± 5%, 0402 NP0 Murata GRM1555C GRM1555C series C126 C131 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C GRM1555C series L121 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic Murata LQG15HS LQG15HS series (315/433 MHz) Murata LQW15xx series (868/915 MHz) L122 18 nH ± 5%, 0402 monolithic 22 nH ± 5%, 0402 monolithic 18 nH ± 5%, 0402 monolithic Murata LQG15HS LQG15HS series (315/433 MHz) Murata LQW15xx series (868/915 MHz) L123 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic Murata LQG15HS LQG15HS series (315/433 MHz) Murata LQW15xx series (868/915 MHz) L124 12 nH ± 5%, 0402 monolithic Murata LQG15HS LQG15HS series (315/433 MHz) Murata LQW15xx series (868/915 MHz) L125 3.3 nH ± 5%, 0402 monolithic Murata LQG15HS LQG15HS series (315/433 MHz) Murata LQW15xx series (868/915 MHz) 12 nH ± 5%, 0402 monolithic Murata LQG15HS LQG15HS series (315/433 MHz) Murata LQW15xx series (868/915 MHz) 18 nH ± 5%, 0402 monolithic Murata LQG15HS LQG15HS series (315/433 MHz) Murata LQW15xx series (868/915 MHz) L131 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic L132 R171 XTAL 56 k ± 1%, 0402 Koa RK73 series 26.0 MHz surface mount crystal NDK, AT-41CD2 AT-41CD2 Table 21: Bill Of Materials for the Application Circuit 7.8 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias. (covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process. The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias for good thermal performance and sufficiently low inductance to ground. The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using "tented" vias reduces the solder paste coverage below 100%. See Figure 10 for top solder resist and top paste masks. In the CC1101EM CC1101EM reference designs ([2] and [3]), 5 vias are placed inside the exposed die attached pad. These vias should be "tented" SWRS061E SWRS061E Page 26 of 97 CC1101 CC1101 Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC1101 CC1101 supply pin. Supply power filtering is very important. Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. Routing in the ground plane underneath the chip or the balun/RF matching circuit, or between the chip's ground vias and the decoupling capacitor's ground vias should be avoided. This improves the grounding and ensures the shortest possible current return path. The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Please note that components with different sizes than those specified may have differing characteristics. Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry. A CC1101DK CC1101DK Development Kit with a fully assembled CC1101EM CC1101EM Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance. The schematic, BOM and layout Gerber files are all available from the TI website ([2] and [3]). Figure 10: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias 8 Configuration Overview CC1101 CC1101 can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. See Section 10 below for more description of the SPI interface. The following key parameters can be programmed: · · · · · · · · · Power-down / power up mode Crystal oscillator power-up / power-down Receive / transmit mode RF channel selection Data rate Modulation format RX channel filter bandwidth RF output power Data buffering with separate 64-byte receive and transmit FIFOs SWRS061E SWRS061E · · · · Packet radio hardware support Forward Error Correction (FEC) interleaving Data whitening Wake-On-Radio (WOR) with Details of each configuration register can be found in Section 29, starting on page 64. Figure 11 shows a simplified state diagram that explains the main CC1101 CC1101 states together with typical usage and current consumption. For detailed information on controlling the CC1101 CC1101 state machine, and a complete state diagram, see Section 19, starting on page 49. Page 27 of 97 CC1101 CC1101 Figure 11: Simplified State Diagram, with Typical Current Consumption at 1.2 kBaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized). Frequency Band = 868 MHz SWRS061E SWRS061E Page 28 of 97 CC1101 CC1101 9 Configuration Software CC1101 CC1101 can be configured using the SmartRF® Studio software [8]. The SmartRF® Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF® Studio user interface for CC1101 CC1101 is shown in Figure 12. After chip reset, all the registers have default values as shown in the tables in Section 29. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface. Figure 12: SmartRF® Studio [8] User Interface 10 4-wire Serial Configuration and Data Interface CC1101 CC1101 is configured via a simple 4-wire SPIcompatible interface (SI, SO, SCLK and CSn) where CC1101 CC1101 is the slave. This interface is also used to read and write buffered data. All transfers on the SPI interface are done most significant bit first. All transactions on the SPI interface start with a header byte containing a R/W bit, a burst ¯ access bit (B), and a 6-bit address (A5 ­ A0). SWRS061E SWRS061E The CSn pin must be kept low during transfers on the SPI bus. If CSn goes high during the transfer of a header byte or during read/write from/to a register, the transfer will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 13 with reference to Table 22. When CSn is pulled low, the MCU must wait until CC1101 CC1101 SO pin goes low before starting to Page 29 of 97 CC1101 CC1101 transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low. Figure 13: Configuration Registers Write and Read Operations Parameter Description Min Max Units fSCLK SCLK frequency - 10 MHz - 9 - 6.5 100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access). SCLK frequency, single access No delay between address and data byte SCLK frequency, burst access No delay between address and data byte, or between data bytes tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 - µs tsp CSn low to positive edge on SCLK, in active mode 20 - ns tch Clock high 50 - ns tcl Clock low 50 - ns trise Clock rise time - 5 ns tfall Clock fall time - 5 ns tsd Setup data (negative SCLK edge) to positive edge on SCLK Single access 55 - ns Burst access 76 - (tsd applies between address and data bytes, and between data bytes) thd Hold data after positive edge on SCLK 20 - ns tns Negative edge on SCLK to CSn high. 20 - ns Table 22: SPI Interface Timing Requirements Note: The minimum tsp,pd figure in Table 22 can be used in cases where the user does not read the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from powerdown depends on the start-up time of the crystal being used. The 150 µs in Table 22 is the crystal oscillator start-up time measured on CC1101EM CC1101EM reference designs ([2] and [3]) using crystal AT-41CD2 AT-41CD2 from NDK. SWRS061E SWRS061E Page 30 of 97 CC1101 CC1101 10.1 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC1101 CC1101 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running. Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core are on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The RX state will be active Bits when the chip is in receive mode. Likewise, TX is active when the chip is transmitting. The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations (the R/W bit in the header byte is ¯ set to 1), the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations (the R/W bit in the header byte is ¯ set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are available/free. Table 23 gives a status byte summary. Name Description 7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using the SPI interface. 6:4 STATE[2:0] Indicates the current main state machine mode Value State 000 Description IDLE IDLE state (Also reported for some transitional states instead of SETTLING or CALIBRATE) 001 TX Transmit mode 011 FSTXON Fast TX ready 100 CALIBRATE Frequency synthesizer calibration is running 101 SETTLING PLL is settling 110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any useful data, then flush the FIFO with SFRX 111 FIFO_BYTES_AVAILABLE[3:0] Receive mode 010 3:0 RX TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with SFTX The number of bytes available in the RX FIFO or free bytes in the TX FIFO Table 23: Status Byte Summary 10.2 Register Access The configuration registers on the CC1101 CC1101 are located on SPI addresses from 0x00 to 0x2E. Table 42 on page 66 lists all configuration registers. It is highly recommended to use SmartRF® Studio [8] to generate optimum register settings. The detailed description of each register is found in Section 29.1 and 29.2, starting on page 69. All configuration registers can be both written to and read. The R/W bit controls if the register should be ¯ written to or read. When writing to registers, SWRS061E SWRS061E the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin. Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A5 ­ A0) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 Page 31 of 97 CC1101 CC1101 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high. For register addresses in the range 0x300x3D, the burst bit is used to select between status registers when burst bit is one, and between command strobes when burst bit is zero. See more in Section 10.3 below. Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only be read. 10.3 SPI Read When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC1101 CC1101 Errata Notes [4] for more details. 10.4 Command Strobes Command Strobes may be viewed as single byte instructions to CC1101 CC1101. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 13 command strobes are listed in Table 41 on page 65. Note: An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This means that if for example an SIDLE strobe is issued while the radio is in RX state, any other command strobes issued before the radio reaches IDLE state will be ignored. address bits (in the range 0x30 through 0x3D) are written. The R/W bit can be either one or ¯ zero and will determine how the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted. When writing command strobes, the status byte is sent on the SO pin. A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES strobe is being issued, one will have to wait for SO to go low again before the next header byte can be issued as shown in Figure 14. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high. The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, ¯ the burst access bit (set to 0), and the six Figure 14: SRES Command Strobe 10.5 FIFO Access The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W bit is zero, the TX FIFO is ¯ accessed, and the RX FIFO is accessed when the R/W bit is one. ¯ SWRS061E SWRS061E The TX FIFO is write-only, while the RX FIFO is read-only. The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method Page 32 of 97 CC1101 CC1101 expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that one byte is free in the TX FIFO. The following header bytes access the FIFOs: The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERFLOW, or RXFIFO_OVERFLOW states. Both FIFOs are flushed when going to the SLEEP state. · 0x3F: Single byte access to TX FIFO · 0x7F: Burst access to TX FIFO · 0xBF: Single byte access to RX FIFO · 0xFF: Burst access to RX FIFO When writing to the TX FIFO, the status byte (see Section 10.1) is output on SO for each new data byte as shown in Figure 13. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Figure 15 gives a brief overview of different register access types possible. 10.6 PATABLE Access The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for reduced bandwidth. See SmartRF® Studio [8] for recommended shaping / PA ramping sequences. See also Section 24 on page 56 for details on output power programming. The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CSn is high. When the highest value is reached the counter restarts at zero. The access to the PATABLE is either single byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The R/W bit controls whether the ¯ access is a read or a write access. If one byte is written to the PATABLE and this value is to be read out, CSn must be set high before the read access in order to set the index counter back to zero. Note that the content of the PATABLE is lost when entering the SLEEP state, except for the first byte (index 0). For more information, see Design Note DN501 DN501 [21]. Figure 15: Register Access Types SWRS061E SWRS061E Page 33 of 97 CC1101 CC1101 11 Microcontroller Interface and Pin Configuration In a typical system, CC1101 CC1101 will interface to a microcontroller. This microcontroller must be able to: · Program CC1101 CC1101 into different modes · Read and write buffered data · Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn) 11.1 Configuration Interface The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in Section 10 on page 29. 11.2 General Control and Status Pins The CC1101 CC1101 has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 26 page 59 for more details on the signals that can be programmed. GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin. In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode. The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature sensor are found in Section 4.7 on page 18. With default PTEST register setting (0x7F), the temperature sensor output is only available if the frequency synthesizer is enabled (e.g. the MANCAL, FSTXON, RX, and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F). 11.3 Optional Radio Control Feature The CC1101 CC1101 has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE, RX, and TX. This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit. SCLK are set to RX and CSn toggles. When CSn is low the SI and SCLK has normal SPI functionality. All pin control command strobes are executed immediately except the SPWD strobe. The SPWD strobe is delayed until CSn goes high. State changes are commanded as follows: CSn SCLK SI Function · If CSn is high, the SI and SCLK are set to the desired state according to Table 24. 1 X X Chip unaffected by SCLK/SI 0 0 Generates SPWD strobe · If CSn goes low, the state of SI and SCLK is latched and a command strobe is generated internally according to the pin configuration. 0 1 Generates STX strobe 1 0 Generates SIDLE strobe 1 1 Generates SRX strobe It is only possible to change state with the latter functionality. That means that for instance RX will not be restarted if SI and 0 SPI mode SPI mode SPI mode (wakes up into IDLE if in SLEEP/XOFF) SWRS061E SWRS061E Table 24: Optional Pin Control Coding Page 34 of 97 CC1101 CC1101 12 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency. If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M = 0. The data rate can be set from 0.8 kBaud to 500 kBaud with the minimum step size according to Table 25 below. (256 + DRATE _ M ) 2 DRATE _ E f 2 28 DRATE _ M = 1.2 / 2.4 3.17 0.0062 4.8 6.35 0.0124 6.35 9.6 12.7 0.0248 12.7 19.6 25.4 0.0496 38.4 50.8 0.0992 76.8 101.6 0.1984 153.6 203.1 0.3967 203.1 250 406.3 0.7935 406.3 R DATA 2 28 - 256 f XOSC 2 DRATE _ E 0.8 101.6 R 2 20 DRATE _ E = log 2 DATA f XOSC Data rate Step Size [kBaud] 50.8 The following approach can be used to find suitable values for a given data rate: Max Data Rate [kBaud] 25.4 XOSC Typical Data Rate [kBaud] 3.17 RDATA = Min Data Rate [kBaud] 500 500 1.5869 Table 25: Data Rate Step Size 13 Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. The following formula gives the relation between the register settings and the channel filter bandwidth: BWchannel f XOSC = 8 (4 + CHANBW _ M )·2CHANBW _ E Table 26 lists the channel filter bandwidths supported by the CC1101 CC1101. For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel centre tolerance due to crystal inaccuracy should also be subtracted from the channel filter bandwidth. The following example illustrates this: With the channel filter bandwidth set to 500 kHz, the signal should stay within 80% of SWRS061E SWRS061E 500 kHz, which is 400 kHz. Assuming 915 MHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 915MHz, which is ±37 kHz. If the whole transmitted signal bandwidth is to be received within 400 kHz, the transmitted signal bandwidth should be maximum 400 kHz ­ 2·37 kHz, which is 326 kHz. By compensating for a frequency offset between the transmitter and the receiver, the filter bandwidth can be reduced and the sensitivity can be improved, see more in DN005 DN005 [20] and in Section 14.1. MDMCFG4.CHANBW_E MDMCFG4. CHANBW_M 00 01 10 11 00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58 Table 26: Channel Filter Bandwidths [kHz] (assuming a 26 MHz crystal) Page 35 of 97 CC1101 CC1101 14 Demodulator, Symbol Synchronizer, and Data Decision CC1101 CC1101 contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 0 for more information), the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 14.1 Frequency Offset Compensation The CC1101 CC1101 has a very fine frequency resolution (see Table 15). This feature can be used to compensate for frequency offset and drift. When using 2-FSK, GFSK, or MSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency within certain limits, by estimating the centre of the received data. The frequency offset compensation configuration is controlled from the FOCCFG register. By compensating for a large frequency offset between the transmitter and the receiver, the sensitivity can be improved, see DN005 DN005 [20]. The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMIT configuration register. If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm may drift to the boundaries when trying to track noise. The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after the sync word has been found. Note: Frequency offset compensation is not supported for ASK or OOK modulation. The estimated frequency offset value is available in the FREQEST status register. This can be used for permanent frequency offset compensation. By writing the value from FREQEST into FSCTRL0.FREQOFF, the frequency synthesizer will automatically be adjusted according to the estimated frequency offset. More details regarding this permanent frequency compensation algorithm can be found in DN015 DN015 [13]. 14.2 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 12 on page 35. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate. 14.3 Byte Synchronization Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet by the modulator in transmit mode. The MSB in the sync word is sent first. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 17.1). The sync word detector correlates against the user-configured 16 or 32 bit sync word. The SWRS061E SWRS061E correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is configured through the SYNC1 and SYNC0 registers. In order to make false detections of sync words less likely, a mechanism called preamble quality indication (PQI) can be used to qualify the sync word. A threshold value for the preamble quality must be exceeded in order for a detected sync word to be accepted. See Section 17.2 on page 43 for more details. Page 36 of 97 CC1101 CC1101 15 Packet Handling Hardware Support The CC1101 CC1101 has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO: · · · A programmable number of preamble bytes A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word A CRC checksum computed over the data field. The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate where the recommended preamble length is 8 bytes. In addition, the following can be implemented on the data field and the optional 2-byte CRC checksum: · · Whitening of the data with a PN9 sequence Forward Error Correction (FEC) by the use of interleaving and coding of the data (convolutional coding) In receive mode, the packet handling support will de-construct the data packet by implementing the following (if enabled): · · · · · Preamble detection Sync word detection CRC computation and CRC check One byte address check Packet length check (length byte checked against a programmable maximum length) De-whitening De-interleaving and decoding · · Optionally, two status bytes (see Table 27 and Table 28) with RSSI value, Link Quality Indication, and CRC status can be appended in the RX FIFO. Bit Field Name Description 7:0 RSSI RSSI value Table 27: Received Packet Status Byte 1 (first byte appended after the data) Bit Field Name Description 7 CRC_OK 1: CRC for received data OK (or CRC disabled) 0: CRC error in received data 6:0 LQI Indicating the link quality Table 28: Received Packet Status Byte 2 (second byte appended after the data) Note: Register fields that control the packet handling features should only be altered when CC1101 CC1101 is in the IDLE state. 15.1 Data Whitening From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies). Real data often contain long sequences of zeros and ones. In these cases, performance can be improved by whitening the data before transmitting, and de-whitening the data in the receiver. SWRS061E SWRS061E With CC1101 CC1101, this can be done automatically. By setting PKTCTRL0.WHITE_DATA=1, all data, except the preamble and the sync word will be XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted. This is shown in Figure 16. At the receiver end, the data are XOR-ed with the same pseudorandom sequence. In this way, the whitening is reversed, and the original data appear in the receiver. The PN9 sequence is initialized to all 1's. Page 37 of 97 CC1101 CC1101 Figure 16: Data Whitening in TX Mode 15.2 Packet Format The format of the data packet can be configured and consists of the following items (see Figure 17): · · Preamble Synchronization word · · · · Optional length byte Optional address byte Payload Optional 2 byte CRC Data field 16/32 bits 8 bits 8 bits 8 x n bits Legend: Inserted automatically in TX, processed and removed in RX. CRC-16 CRC-16 Address field 8 x n bits Length field Preamble bits (1010.1010) Sync word Optional data whitening Optionally FEC encoded/decoded Optional CRC-16 CRC-16 calculation Optional user-provided fields processed in TX, processed but not removed in RX. Unprocessed user data (apart from FEC and/or whitening) 16 bits Figure 17: Packet Format The preamble pattern is an alternat