CC1010 CFR47 SWRS047A TQFP-64 CC1010EM XOSC32 X32CON 28-2F 38-3F 98-9F 08-0F - Datasheet Archive

 

CC1010 Single Chip Very Low Power RF Transceiver with 8051-Compatible Microcontroller Applications · Very low power UHF

 

CC1010 CC1010 CC1010 CC1010 Single Chip Very Low Power RF Transceiver with 8051-Compatible Microcontroller Applications · Very low power UHF wireless data transmitters and receivers · 315 / 433 / 868 and 915 MHz ISM/SRD band systems · Home automation and security · AMR ­ Automatic Meter Reading · RKE ­ Remote Keyless Entry with acknowledgement · Low power telemetry · Toys Product Description The CC1010 CC1010 is a true single-chip UHF transceiver with an integrated high performance 8051 microcontroller with 32 kB of Flash program memory. The RF transceiver can be programmed for operation in the 300 ­ 1000 MHz range, and is designed for very low power wireless applications. The CC1010 CC1010 together with a few external passive components constitutes a powerful embedded system with wireless communication capabilities. CC1010 CC1010 is based on Chipcon's SmartRF®02 technology in 0.35 µm CMOS. Key Features · 300-1000 MHz RF Transceiver · Very low current consumption (9.1 mA in RX) · High sensitivity (typically -107 dBm) · Programmable output power up to +10 dBm · Data rate up to 76.8 kbps · Very few external components · Fast PLL settling allowing frequency hopping protocols · RSSI · EN 300 220 and FCC CFR47 CFR47 part 15 compliant · 8051-Compatible Microcontroller · Typically 2.5 times the performance of a standard 8051 · 32 kB Flash, 2048 + 128 Byte SRAM · 3 channel 10 bit ADC, 4 timers / 2 PWMs, 2 UARTs, RTC, Watchdog, SPI, DES encryption, 26 general I/O pins · In-circuit interactive debugging is supported for the Keil µVision2 IDE through a simple serial interface. · 2.7 - 3.6 V supply voltage · 64-lead TQFP SWRS047A SWRS047A Page 1 of 146 CC1010 CC1010 Table Of Contents 1. FEATURES. 4 2. ABSOLUTE MAXIMUM RATINGS . 5 3. RECOMMENDED OPERATING CONDITIONS. 5 4. DC CHARACTERISTICS . 6 5. ELECTRICAL SPECIFICATIONS. 7 6. ADC . 8 7. RF SECTION, GENERAL . 8 8. RF TRANSMIT SECTION . 9 9. RF RECEIVE SECTION . 10 10. IF SECTION. 11 11. FREQUENCY SYNTHESIZER SECTION. 12 12. PIN CONFIGURATION . 13 13. PIN DESCRIPTION . 15 14. BLOCK DIAGRAM. 18 15. 8051 CORE . 19 15.1 GENERAL DESCRIPTION . 19 15.2 RESET. 19 15.3 MEMORY MAP . 20 15.4 CPU REGISTERS . 23 15.5 INSTRUCTION SET SUMMARY . 24 15.6 INTERRUPTS . 28 15.7 EXTERNAL INTERRUPTS . 32 15.8 MAIN CRYSTAL OSCILLATOR. 32 15.9 POWER AND CLOCK MODES . 34 15.10 FLASH PROGRAM MEMORY . 37 15.11 SPI FLASH PROGRAMMING. 37 15.12 SERIAL PROGRAMMING ALGORITHM . 37 15.13 8051 FLASH PROGRAMMING . 42 15.14 FLASH POWER CONTROL . 43 15.15 IN CIRCUIT DEBUGGING. 44 15.16 CHIP VERSION / REVISION . 45 16. 8051 PERIPHERALS . 47 16.1 GENERAL PURPOSE I/O . 47 16.2 TIMER 0 / TIMER 1. 52 16.3 TIMER 2 / 3 WITH PWM . 59 16.4 POWER ON RESET (BROWN-OUT DETECTION) . 62 16.5 WATCHDOG TIMER. 63 16.6 REAL-TIME CLOCK . 65 16.7 SERIAL PORT 0 AND 1 . 66 16.8 SPI MASTER . 71 16.9 DES ENCRYPTION / DECRYPTION . 75 16.10 RANDOM BIT GENERATION . 78 16.11 ADC . 79 17. RF TRANSCEIVER . 83 17.1 GENERAL DESCRIPTION . 83 17.2 RF TRANSCEIVER BLOCK DIAGRAM . 83 17.3 RF APPLICATION CIRCUIT . 85 17.4 TRANSCEIVER CONFIGURATION OVERVIEW . 88 17.5 RF TRANSCEIVER RX/TX CONTROL AND POWER MANAGEMENT . 89 17.6 DATA MODEM AND DATA MODES . 91 17.7 BAUD RATES . 94 17.8 TRANSMITTING AND RECEIVING DATA . 95 SWRS047A SWRS047A Page 2 of 146 CC1010 CC1010 17.9 DEMODULATION AND DATA DECISION . 97 17.10 SYNCHRONIZATION AND PREAMBLE DETECTION . 102 17.11 RECEIVER SENSITIVITY VERSUS DATA RATE AND FREQUENCY SEPARATION . 105 17.12 FREQUENCY PROGRAMMING . 107 17.13 LOCK INDICATION . 110 17.14 RECOMMENDED SETTINGS FOR ISM FREQUENCIES . 111 17.15 VCO . 113 17.16 VCO AND PLL SELF-CALIBRATION . 113 17.17 VCO, LNA AND BUFFER CURRENT CONTROL . 118 17.18 INPUT / OUTPUT MATCHING . 120 17.19 OUTPUT POWER PROGRAMMING . 123 17.20 RSSI OUTPUT . 126 17.21 IF OUTPUT . 127 17.22 OPTIONAL LC FILTER . 128 18. RESERVED REGISTERS AND TEST REGISTERS . 129 19. SYSTEM CONSIDERATIONS AND GUIDELINES . 131 19.1 SRD REGULATIONS. 131 19.2 LOW COST SYSTEMS . 131 19.3 BATTERY OPERATED SYSTEMS. 131 19.4 NARROW-BAND SYSTEMS . 131 19.5 HIGH RELIABILITY SYSTEMS . 131 19.6 FREQUENCY HOPPING SPREAD SPECTRUM SYSTEMS. 132 19.7 SOFTWARE . 132 19.8 DEVELOPMENT TOOLS . 132 19.9 PA "SPLATTERING". 132 19.10 PCB LAYOUT RECOMMENDATIONS . 133 19.11 ANTENNA CONSIDERATIONS . 133 20. PACKAGE DESCRIPTION (TQFP-64 TQFP-64). 134 21. SOLDERING INFORMATION . 134 22. TRAY SPECIFICATION . 134 23. LIST OF ABBREVIATIONS . 137 24. SFR SUMMARY . 138 25. ALPHABETIC REGISTER INDEX . 142 26. ORDERING INFORMATION . 145 27. GENERAL INFORMATION. 146 27.1 DOCUMENT HISTORY . 146 SWRS047A SWRS047A Page 3 of 146 CC1010 CC1010 1. Features Fully Integrated UHF RF Transceiver · Programmable frequency in the range 300 ­ 1000 MHz · High sensitivity (typically -107 dBm at 2.4 kBaud) · Programmable output power ­20 to +10 dBm · Very low current consumption (RX: 9.1 mA) · Very few external components required and no external RF switch or IF filter required · Single port antenna connection · Fast PLL settling allows frequency hopping protocols · FSK modulation with a data rate of up to 76.8 kBaud · Manchester or NRZ coding and decoding of data performed in hardware. Byte delineation of data can be performed in hardware to lessen the processor burden · RSSI output which can be sampled by on-chip ADC · Complies with EN 300 220 and FCC CFR47 CFR47 part 15 High-Performance and Low-Power 8051-Compatible Microcontroller · Optimised 8051-core which typically gives 2.5x the performance of a standard 8051 · Dual data pointers · Idle and sleep modes · In-circuit interactive debugging is supported for the Keil µVision IDE through a simple serial interface Data and Non-volatile Program Memory · 32 kB of non-volatile Flash memory in-system programmable through a simple SPI interface or by the 8051 core. · Typical Flash memory endurance: 20 000 write/erase cycles · Programmable read and write lock of portions of Flash memory for software security · 2048 + 128 Byte of internal SRAM Hardware DES Encryption / Decryption · DES supported in hardware · Output Feedback Mode or Cipher Feedback Mode DES to avoid the requirement that data length must be a multiple of eight bytes Peripheral Features · Power On Reset / Brown-Out Detection · Three channel, max 23 kSample/s, 10 bit ADC · Programmable watchdog timer. · Real time clock with 32 kHz crystal oscillator · Two timers / pulse counters and two timers / pulse width modulators · Two programmable serial UARTs. · Master SPI interface · 26 configurable general-purpose I/O-pins · Random bit generator in hardware Low Power · 8051 core and peripherals can use the RTC's 32 kHz clock · Idle and sleep modes for reduced power consumption. System can wake up on interrupt or when ADC input exceeds a set threshold · Low-power fully static CMOS design Operating Conditions · 2.7 - 3.6 V supply voltage · -40 - 85 °C operational temperature · 3 - 24 MHz crystal (up to 50 ppm) for the main crystal oscillator Packaging · 64-lead TQFP SWRS047A SWRS047A Page 4 of 146 CC1010 CC1010 2. Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Supply voltage, VDD Voltage on any pin Min. -0.3 -0.3 Input RF level Storage temperature range Storage temperature range -50 -40 Units V V 260 Lead temperature Max. 5.0 VDD+0.3, max 5.0 10 150 125 °C dBm °C °C Condition Un-programmed device Programmed device, data retention > 0.49 years at 125°C T = 10 s Table 1. Absolute Maximum Ratings Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. 3. Recommended Operating Conditions Tc = -40 to 85°C, VDD = 2.7 to 3.6 V if nothing else stated Parameter Min Typ Max Unit Condition Supply voltage, DVDD, AVDD 2.7 3.3 3.6 V Supply voltage during normal operation Supply voltage, DVDD, AVDD 2.7 3.6 V Supply voltage during program/erase Flash memory Operating temperature, free-air -40 85 °C Main oscillator frequency 3 24 MHz RTC oscillator frequency 32768 Hz Table 2. Recommended Operating Conditions SWRS047A SWRS047A Page 5 of 146 CC1010 CC1010 4. DC Characteristics The DC Characteristics of CC1010 CC1010 are listed in Table 3 below. Tc = 25°C, VDD = 3.3 V if nothing else stated Digital Inputs/Outputs Min Max Unit Condition Logic "0" input voltage 0 0.3*VDD V Logic "1" input voltage 0.7*VDD VDD V Logic "0" output voltage 0 0.4 V Logic "1" output voltage 2.5 VDD V Logic "0" output voltage 0 0.4 V Logic "1" output voltage 2.5 VDD V Logic "0" input current NA -1 µA Output current -2.0 mA, ports P0.3-P0.0, P1.7P1.0, P2.7-P2.4, P2.2P2.0 Output current 2.0mA, ports P0.3-P0.0, P1.7P1.0, P2.7-P2.4, P2.2P2.0 Output current -8.0 mA, port P2.3 Output current 8.0mA, port P2.3 Input signal equals GND Logic "1" input current NA 1 µA Input signal equals VDD Table 3. DC Characteristics Supply current [mA] 25 20 15 10 5 0 0 4 8 12 16 20 24 Frequency [MHz] Figure 1. Typical CPU core supply current vs. clock frequency SWRS047A SWRS047A Page 6 of 146 CC1010 CC1010 5. Electrical Specifications Tc = 25°C, VDD = 3.3 V if nothing else stated All electrical specifications are measured on Chipcon's CC1010EM CC1010EM reference design. Parameter Min. Typ. Max. Unit Condition Power on reset (POR) voltage 2.7 2.9 3.1 V Tc = -40 to 85°C Brown out voltage 2.7 2.9 3.1 V Tc = -40 to 85°C RTC start-up time 160 ms Current consumption MCU, Active mode 14.8 1.3 mA mA 14.7456 MHz, main oscillator 32 kHz, RTC oscillator See page 33 for explanation of modes. See Figure 1 page 6 for supply current vs. clock frequency Current consumption MCU, Idle mode 12.8 29.4 mA µA 14.7456 MHz, main oscillator 32 kHz, RTC oscillator Current consumption, Power Down mode Current consumption, Poweron reset circuit (when enabled) Current consumption Main crystal oscillator Current consumption RF Transceiver, Receive mode, 433/868 MHz 0.2 1 µA 34 uA 67 µA 14.7456 MHz crystal 9.1/ 11.9 mA Current for RF transceiver alone Current consumption RF Transceiver, Transmit mode, 433/868 MHz P=0.01 mW (-20 dBm) 5.3/8.6 mA P=0.3 mW (-5 dBm) 8.9/13.8 mA P=1 mW (0 dBm) 10.4/17 mA P=2.5 mW (4 dBm) 24.8/ 23.5 mA P=10 mW (10 dBm) 26.6/NA mA 32 kHz oscillator crystal load capacitance 12 The output power is delivered to a single-ended 50 load, see also page 123. Current is for RF transceiver alone pF Table 4. Electrical specifications SWRS047A SWRS047A Page 7 of 146 CC1010 CC1010 6. ADC Parameter Min. Typ. Max. Unit Condition Number of bits 10 bits Differential Nonlinearity (DNL) +/-0.2 LSB VDD is reference voltage Integral Nonlinearity (INL) +/-1.3 LSB VDD is reference voltage Offset 3 LSB 7 Hz test tone Total Harmonic Distortion (THD) 59 dB 7 Hz test tone SINAD 54 9 dB bits 7 Hz test tone Internal reference tolerance ± 10 % Conversion time 44 Clock frequency 32 µs Input voltage 250 kHz 1.3 External reference voltage 250 2.7 V Vref When ADC is operated at 250 kHz 250 kHz recommended for full 10-bit performance External reference voltage should never exceed 2.7 V. It is recommended to use a reference voltage close to 1.3 V to have the best possible linearity. V 0 Table 5. ADC characteristics 7. RF section, general Parameter Min. RF Frequency Range Data rate Typ. Max. Unit Condition 300 1000 MHz Programmable in steps of < 250 Hz 0.6 76.8 kBaud NRZ or Manchester encoding. 76.8 kBaud equals 76.8 kbps using NRZ coding. See page 94 Table 6 General RF characteristics SWRS047A SWRS047A Page 8 of 146 CC1010 CC1010 8. RF transmit section Parameter Min. Typ. Max. Unit Condition Binary FSK frequency separation 0 64 65 kHz The frequency corresponding to the digital "0" is denoted f0, while f1 corresponds to a digital "1". The frequency separation is f1-f0. The RF carrier frequency, fc, is then given by fc=(f0+f1)/2. (The frequency deviation is given by fd=+/-(f1-f0)/2 ) The frequency separation is programmable in 250 Hz steps. Separations up to 65 kHz are guaranteed at 1 MHz reference frequency. Larger separations can be achieved at higher reference frequencies Output power 433 / 868 MHz -20 0 10/4 dBm Delivered to single-ended 50 load. The output power is programmable, see page 123 Transmit mode, optimum load impedance. For matching details see "Input/ output matching" p.120 RF output impedance 433 / 868 MHz 140/80 Harmonics 2nd harmonic, 433 / 868 MHz rd 3 harmonic, 433 / 868 MHz -7/-15 -27/-29 dBm Conducted measur at maximum output power. An external LC filter should be used to reduce harmonics emission to comply with SRD requirements. See p.128 Table 7. RF transmit characteristics SWRS047A SWRS047A Page 9 of 146 CC1010 CC1010 9. RF receive section Parameter Min. Receiver Sensitivity, 433 / 868 MHz Typ. Max. Condition dBm -107/ -106 Unit 2.4 kBaud, Manchester coded data, 64 kHz frequency separation, BER = 10-3 See Table 33 and Table 34page 105 for typical sensitivity figures at other data rates. System noise bandwidth 30 kHz Cascaded noise figure 433/868 MHz 12/13 dB Saturation (maximum input level) 10 2.4 kBaud, Manchester coded data dBm 2.4 kBaud, Manchester coded data, BER = 10-3 Input IP3 -1 -26 dBm dBm 76.8 kBaud NRZ, BER = 10-3 From LNA to IF output Blocking 40 dBc At +/- 1 MHz LO leakage -57 dBm Input impedance 90-j13 68-j24 36-j11 36-j13 Receive mode, series equivalent at 315 MHz at 433 MHz at 868 MHz at 915 MHz For matching details see "Input/ output matching" p. 120. Turn on time 11 128 Baud The demodulator settling time, which is programmable, determines the turn-on time. See page 97 for details. Table 8. RF receive characteristics SWRS047A SWRS047A Page 10 of 146 CC1010 CC1010 10. IF section Parameter Min. Intermediate frequency (IF) 433/868 MHz Typ. Max. 10.7 IF bandwidth (noise bandwidth) RSSI dynamic range 175 -105 Condition kHz 150/ 130 Unit Internal IF filter MHz External IF filter kHz -60 dBm RSSI 3-dB bandwidth RSSI accuracy 260 ±6 kHz dB RSSI linearity ±2 868 MHz CW, -70 dBm See p. 126 for details dB Table 9 IF characteristics SWRS047A SWRS047A Page 11 of 146 CC1010 CC1010 11. Frequency synthesizer section Parameter Min. Crystal Oscillator Frequency Typ. 3 Condition MHz Crystal frequency can be 3-4, 6-8 or 9-24 MHz. Recommended frequencies are 3.6864, 7.3728, 11.0592, 14.7456, 18.4320 and 22.1184 MHz. See page 32 for details ppm 433 MHz 868 MHz The crystal frequency accuracy and drift (ageing and temperature dependency) will determine the frequency accuracy of the transmitted signal. ± 50 ± 25 Crystal operation Unit 24 Crystal frequency accuracy requirement Max. Parallel Crystal load capacitance 12 12 12 12 20 16 16 12 C171 and C181 are loading capacitors 30 30 16 16 pF pF pF pF 3-4 MHz, 20 pF recommended 6-8 MHz, 16 pF recommended 9-16 MHz, 16 pF recommended 16-24 MHz, 12 pF recommended Crystal oscillator start-up time 5 1.5 2 ms ms ms 3.6864 MHz, 16 pF load 7.3728 MHz, 16 pF load 16 MHz, 16 pF load Output signal phase noise -85 dBc/Hz At 100 kHz offset from carrier PLL lock time (RX / TX turn time) 200 µs PLL turn-on time 250 µs Table 10. Frequency synthesizer characteristics SWRS047A SWRS047A Page 12 of 146 CC1010 CC1010 DGND DVDD P0.2 (MISO) P0.3 P1.5 P1.6 P1.7 P2.6 P2.7 PROG RESET DVDD AD0 (Top view) AD1 AD2 (RSSI/IF) AGND 12. Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P3.0 (RXD0) AVDD 2 47 P3.1 (TXD0) AGND 3 46 P3.2 (INT0) RF_IN 4 45 P2.5 RF_OUT 5 44 P2.4 CC1010 CC1010 AVDD 1 AVDD 6 AGND 7 AGND 8 AGND 9 L1 10 L2 11 AVDD 12 43 DVDD 42 P2.3 41 DGND 40 DVDD 39 P2.2 38 P1.4 37 P1.3 CHP_OUT 13 36 P1.2 R_BIAS 14 35 P1.1 AVDD 15 34 P0.1 (MOSI) AGND 16 33 P0.0 (SCK) Pin # 1 2 3 4 Pin name DGND (INT1) P3.3 (PWM2) P3.4 (PWM3) P3.5 (TXD1) P2.1 (RXD1) P2.0 P1.0 POR_E DGND AGND DGND XOSC32 XOSC32_Q1 XOSC32 XOSC32_Q2 XOSC_Q2 XOSC_Q1 AGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin type Description AVDD AVDD AGND RF_IN Alternate function - Power (A) Power (A) Power (A) RF input 5 6 7 8 9 10 RF_OUT AVDD AGND AGND AGND L1 - RF output Power (A) Power (A) Power (A) Power (A) Analog 11 L2 - Analog 12 AVDD - Power (A) Power supply ADC Power supply Mixer and IF Ground connection Mixer and IF RF signal input from antenna (external ACcoupling) RF signal output to antenna Power supply LNA and PA Ground connection LNA and PA Ground connection PA Ground connection VCO and prescaler Connection #1 for external VCO tank inductor Connection #2 for external VCO tank inductor Power supply VCO and prescaler SWRS047A SWRS047A Page 13 of 146 CC1010 CC1010 Pin # 13 Pin name Pin type Description CHP_OUT Alternate function - Analog output 14 R_BIAS - Analog 15 16 17 18 AVDD AGND AGND XOSC_Q1 - Power (A) Power (A) Power (A) Analog input 19 20 - Analog output Analog output - Analog input 32 kHz crystal pin1 or external clock input 22 23 24 25 XOSC_Q2 XOSC32 XOSC32_Q 2 XOSC32 XOSC32_Q 1 AGND DGND DGND POR_E Charge pump current output when external loop filter is used Connection for external precision bias resistor (82 k, ± 1%) Power supply misc. analog modules Ground connection misc. analog modules Analog ground connection 3-24 MHz crystal, pin 1 or external clock input 3-24 MHz crystal, pin 2 32 kHz crystal pin2 - Power (A) Power (D) Power (D) Digital input 26 27 28 29 P1.0 P2.0 P2.1 P3.5 Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O 30 P3.4 RXD1 (I) TXD1 (O) PWM3 (O) T1 (I) PWM2 (O) T0 (I) 31 P3.3 INT1 (I) Digital high-Z I/O 32 33 DGND P0.0 SCK (O) SCK (I) Power (D) Digital high-Z I/O 34 P0.1 MO (O) SI (I) Digital high-Z I/O 35 36 37 38 39 P1.1 P1.2 P1.3 P1.4 P2.2 - 40 41 42 DVDD DGND P2.3 - 43 44 45 46 DVDD P2.4 P2.5 P3.2 - Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O (Schmitt trigger input) Power (D) Power (D) Digital high-Z I/O (8 mA) Power (D) Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Analog ground connection Digital ground connection Digital ground connection Power-on reset enable. 0: Disable internal power-on reset module 1: Enable internal power-on reset module 8051 port 1, bit 0 8051 port 2, bit 0 or RX of serial port 1 8051 port 2, bit 1 or TX of serial port 1 8051 port 3, bit 5 or pulse width modulator 3's output or Timer / Counter 1 external input 8051 port 3, bit 4 or pulse width modulator 2's output or Timer / Counter 0 external input 8051 port 3, bit 3 or interrupt 1 input configurable as level or edge sensitive Ground connection digital part 8051 port 0, bit 0 or SPI master interface serial clock output or Flash programming SPI slave clock input. 8051 port 0, bit 1 or SPI interface master output or Flash programming SPI slave serial data input 8051 port 1, bit 1 8051 port 1, bit 2 8051 port 1, bit 3 8051 port 1, bit 4 8051 port 2, bit 2 47 48 49 50 P3.1 P3.0 DGND DVDD TXD0 (O) RXD0 (I) - 21 INT0 (I) Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Power (D) Power (D) Digital power supply Ground connection digital part 8051 port 2, bit 3 Digital power supply 8051 port 2, bit 4 8051 port 2, bit 5 8051 port 3, bit 2 or interrupt 0 input configurable as level or edge sensitive 8051 port 3, bit 1 or TX of serial port 0 8051 port 3, bit 0 or RX of serial port 1 Digital ground connection Digital power supply SWRS047A SWRS047A Page 14 of 146 CC1010 CC1010 Pin # 51 Pin name 52 53 54 55 56 57 58 P0.3 P1.5 P1.6 P1.7 P2.6 P2.7 59 Alternate function MI (I) SO (O) Pin type Description Digital high-Z I/O PROG - Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital input 8051 port 0, bit 2 or SPI interface master input or Flash programming SPI slave serial data output 8051 port 0, bit 3 8051 port 1, bit 5 8051 port 1, bit 6 8051 port 1, bit 7 8051 port 2, bit 6 8051 port 2, bit 7 Flash program enable pad, active low RESET - Digital input (pull-up) System reset pin, active low P0.2 60 61 62 63 DVDD AD0 AD1 AD2 RSSI (O), IF (O) Power (D) Analog input Analog input Analog input/output 64 AGND - Power (A) Digital power supply ADC input channel 0 ADC input channel 1 ADC input channel 2, RSSI (Receiver signal strength indicator) output, or IF output when using external demodulator Analog ground connection ADC A = Analog, D = Digital, I = input, O= Output 13. Pin description AVDD, DVDD Supply voltages for analog and digital modules respectively. All supply pins should be decoupled by capacitors. In particular, the digital and analog supply domains should be properly decoupled from each other (a ferrite bead can be used to prevent high-frequency noise from coupling from one supply domain to another). The placement and size of decoupling capacitors and supply filtering are critical with respect to LO leakage and sensitivity. Chipcon's reference layout designs should be used (available from Chipcon's website). See also page 133 for layout recommendations. AGND, DGND Ground for analog and digital modules respectively. Normally one common ground plane is recommended. If two separate analog and digital grounds are used they should be interconnected in one place, and one place only. RFIN This is the RF input, internally connected to the low noise amplifier (LNA). The signal source (antenna) should be matched to the input impedance. A DC ground is needed for LNA biasing. RFOUT This is the RF output, internally connected to the power amplifier (PA). The external load (antenna) should be matched to the output impedance (optimum load impedance). This pin must be DC coupled to AVDD for PA biasing (open drain output). L1, L2 Connection to internal voltage controlled oscillator (VCO). An inductor should be connected between these pins. The inductor value will determine the VCO tuning range. The inductor should be place very close to the pins in order to minimize paracitic inductance. CHP_OUT Charge Pump output. If the RF transceiver is configured for external loop filter this is the current output from the charge pump. Normally the internal loop filter should be used and this pin should be left open (not connected). SWRS047A SWRS047A Page 15 of 146 CC1010 CC1010 RBIAS Current output from internal band gap cell bias generator. A precision resistor (82 k, ±1%) should be connected between this pin and ground to set the correct bias current level. XOSC_Q1, XOSC_Q2 These are the main oscillator connection pins. An external crystal should be connected between these pins, and load capacitors should be connected between each pin and ground. If an external oscillator is used, the clock signal should be connected to the XOSC_Q1 pin, and XOSC_Q2 should be left open (not connected). XOSC32 XOSC32_Q1, XOSC32 XOSC32_Q2 These are the real time clock (RTC) oscillator connection pins. An external crystal should be connected between these pins, and load capacitors should be connected between each pin and ground. If an external oscillator is used, the clock signal should be connected to the XOSC32 XOSC32_Q1 pin, and XOSC32 XOSC32_Q2 should be left open (not connected). POR_E Enable signal for the on-chip power-on reset module. The power-on reset is enabled when POR_E is connected to DVDD and disabled when connected to DGND. PROG Active low Flash programming enable pin. When this signal is active (driven to DGND) a Flash programmer can be connected to the SPI interface. Under normal operation it must be driven to DVDD. RESET Active low asynchronous system reset. It has an internal pull-up resistor and can be left unconnected during normal operation. AD0, AD1 Analog inputs to A/D converter channels 0 and 1 respectively. When not used these pins can be left open (not connected). AD2 (RSSI/IF) Analog input to A/D converter channel 2. This pin can also be configured to be RSSI output or IF output. The pin is configured by the FREND register. When not used this pin can be left open (not connected). PORT 0 Port 0 is a 4-bit (P0.3-P0.0) bi-directional CMOS I/O port with 2 mA drivers. A direction register (P0DIR) controls whether each pin is an output or input and the register P0 is used to read the input or control the logical value of the output. Pins P0.0 - P0.2 can be configured to become a master SPI interface in register SPCR and will then override P0(2:0), P0DIR(2) and P0DIR(1). Used as SPI interface, P0.0 is SCK, P0.1 is MOSI, and P0.2 is MISO. PORT 1 Port 1 is an 8-bit (P1.7-P1.0) bidirectional CMOS I/O port with 2 mA drivers. A direction register (P1DIR) controls whether each pin is an output or input and the register P1 is used to read the input or control the logical value of the output. PORT 2 Port 2 is an 8-bit (P2.7-P2.0) bidirectional CMOS I/O port with 2 mA drivers, except for P2.3 that has an 8 mA output buffer. A direction register (P2DIR) controls whether each pin is an output or input and the register P2 is used to read the input or control the logical value of the output. Pins P2.0 and P2.1 can be configured to become the RXD1 and TXD1 pin, respectively, of UART 1. Pin P2.2 has a Schmitt-trigger input stage. Note that while this pin does have hysteresis, it will draw a large input current (~0.5 mA) if the input voltage is close to VDD/2. PORT 3 Port 3 is a 6-bit (P3.5-P3.0) bi-directional CMOS I/O port with 2 mA drivers. A direction register (P3DIR) controls whether each pin is an output or input. The register P3 is used to read the input or control the logical value of the output. SWRS047A SWRS047A Page 16 of 146 CC1010 CC1010 Pins P3.0 and P3.1 can be configured to become the RXD0 and TXD0 pin, respectively, of UART 0. Pins P3.2 and P3.3 are connected to the external interrupt inputs INT0 and INT1 , respectively, and can cause interrupts if the corresponding interrupt enable flags are set in register IE. The interrupts inputs can be configured to be either levelsensitive or edge-sensitive. Pins P3.4 and P3.5 can be configured to become the pulse width modulator (PWM) outputs of Timer/PWM 2 and Timer/PWM 3, respectively. When pulse width modulation is enabled the corresponding bits in P3DIR and P3 are overridden. SWRS047A SWRS047A Page 17 of 146 CC1010 CC1010 14. Block Diagram The CC1010 CC1010 Block Diagram is shown in Figure 2 below. Programmable I/O (General purpose or alternate function) Port 0 Port 2 POR_E Power-on reset RAM Arbiter DES Module FLASH Programming DMA Port 1 32 kB FLASH Port 3 Timers/ PWMs 128 byte SRAM 8051 core Timers/ Counters Interrupt Controller Watchdog Timer Reset Generation RESET 2048 byte SRAM General purpose I/O PROG UARTs UARTs SPI Realtime Clock Special Function Registers (SFRs) AD0 AD1 AD2 (RSSI/IF) 32 kHz crystal ADC System clock MUX Clock Multiplexer RF Transceiver IF MIXER RF_IN RSSI IF stage LNA MODEM CODEC, Bit synchronizer, Serializer/Deserializer :N.n Bias Bias resistor RF_OUT PA LPF VCO CHP PD :R Main Crystal Oscillator 3-24 MHz crystal L1 L2 CHP_OUT VCO inductor Figure 2. CC1010 CC1010 Block Diagram SWRS047A SWRS047A Page 18 of 146 CC1010 CC1010 15. 8051 Core 15.1 General description The CC1010 CC1010 microcontroller core is based on the industry-standard 8051 architecture. The MCU core is 8-bit, with program and data memory located in separate memory spaces (Harvard architecture). The internal registers are organised as four banks of 8 registers each. The instruction set supports direct, indirect and register addressing modes. Program memory can be addressed using indexed addressing. The core registers are comprised of an accumulator, a stack pointer and dual data pointer registers in addition to the general registers. The various peripherals are controlled through Special Function Registers (SFRs) located in the internal RAM space. Data memory is split into internal and external RAM. The name "external RAM" is in fact misleading since in the case of the CC1010 CC1010 all the RAM is internal to the chip. The difference between external and internal is that external RAM can only be accessed by a few instructions. Therefore, frequently-accessed variables as well as the stack should be kept in internal RAM. Peripheral units, including general purpose I/O, 2 standard 8051 timers, 2 extra timers with PWM functionality, a watchdog timer, a real-time clock, an SPI master interface, hardware DES encryption, a true random bit generator and ADC are all described from page 47 and out. Dual data pointers are available for faster data transfer. The 8051 core is instruction set compatible with the industry standard 8051. It also has one additional instruction, TRAP, to enable advanced in-circuitdebugging features. This is described on page 44. The instruction cycle time is 4 clock cycles, which typically gives a 2.5X average reduction in instruction execution time over the original Intel 8051. 15.2 Reset CC1010 CC1010 must be reset at start-up. There are several sources for reset in CC1010 CC1010 : · External reset pin, RESET . Applying a low signal to this pin at any time will reset almost all registers in CC1010 CC1010. Exceptions can be found in Table 40 on page 141. The input is asynchronous and is synchronised internally, so that the reset can be released independent of the timing of the active clock signal. If the main crystal oscillator is inactive, the reset input should be held long enough for the oscillator to start up and stabilize. See Electrical Specifications page 7 for oscillator start-up timing. · voltage may require an external POR module, as described in the Power On Reset (Brown-Out Detection) section at page 62. Power On Reset (POR). The internal POR module can generate reset upon power-up. Special requirements for power consumption or power supply · Brown-out detection reset. The POR will also detect low supply voltage and generate a reset. · Watchdog timer reset. The watchdog timer can generate a reset, as described in the section on page 63. · ADC reset. The ADC module can be programmed to generate a reset signal if its inputs exceed a programmed threshold. See the ADC section on page 79 for details. The POR and ADC reset signals will be held for 1024 clock periods after the signal is released. This will ensure a safe clock start-up if the crystal oscillator is currently not running. SWRS047A SWRS047A Page 19 of 146 CC1010 CC1010 15.3 Memory Map The CC1010 CC1010 memory map is shown in Figure 3. from (to) the address pointed to by the currently selected data pointer. CC1010 CC1010 has 2 blocks of RAM on chip. This The instructions MOVX A, @Ri and MOVX @Ri, A moves data to (from) the accumulator, from (to) the address given by the memory page address register MPAGE and the register Ri (R0 or R1). MPAGE gives the 8 most significant address bits, while the register Ri gives the 8 least significant bits. In many 8051 implementations, this type of external RAM access is performed using P2 to give the most significant address bits. Existing software may therefore have to be adapted to make use of MPAGE instead of P2. includes the 128 bytes Internal RAM and the 2048 bytes External RAM. (The 2048byte RAM will be referred to as External RAM, although it is on-chip. Direct access to off-chip RAM is not implemented.) Access to the internal RAM is performed using the MOV instruction. MOV A, @Ri, MOV @Ri, A and MOV @Ri, #data use indirect addressing. MOV A, direct, MOV Rn, direct, MOV direct, A, MOV direct, Rn, MOV direct, direct and MOV direct, #data use direct addressing. MOV @Ri, direct uses indirect and direct addressing. All direct addressing instructions can also be used to access the SFRs. CC1010 CC1010 also implements the option to access SFRs indirectly, as described in the In Circuit Debugging section on page 44. CC1010 CC1010 has dual data pointers to external RAM, provided in the 16 bit registers DPTR0 and DPTR1 (SFRs DPH0, DPL0, DPH1 and DPL1). If a high-level language compilator is used, it should be set up to make use of both pointers for better performance. The data pointer is selected through DPS.SEL. Access to the external RAM is performed using the MOVX instruction and indirect addressing using either the 16 bit data pointers or the 8 bit registers R0 or R1 together with MPAGE. MOVX A, @DPTR and MOVX @DPTR, A moves data to (from) the accumulator, The program memory can be read using the MOVC A, @A+DPTR and MOVC A, @A+PC instructions, which moves a byte from the program memory address given by A+DPTR or A+PC respectively. The program memory can not be written using MOV commands, but uses the method described in the 8051 Flash Programming section on page 42. CC1010 CC1010 also provides a possibility to stretch the access cycle to external RAM, through CKCON.MD(2:0) (see page 55). The default value for CKCON.MD is "001". It is recommended to set CKCON.MD to "000" for faster RAM access. SWRS047A SWRS047A Page 20 of 146 CC1010 CC1010 Flash Program Memory 0x7FFF External RAM 0x7FF Internal RAM / SFR 0xFF Accesible through indirect addressing Accesible through indirect addressing Special Function Registers (SFR), accessible through Direct Addressing 0x7F Internal RAM Accessible through Direct and Indirect Addressing 0x00 0x00 0x00 Figure 3. Memory Map DPL0 (0x82) - Data Pointer 0, low byte Bit 7:0 Name DPL0(7:0) R/W R/W Reset value 0x00 Description Data Pointer 0, low byte DPH0 (0x83) - Data Pointer 0, high byte Bit 0 Name DPH0(7:0) R/W R/W Reset value 0x00 Description Data Pointer 0, high byte DPL1 (0x84) - Data Pointer 1, low byte Bit 7:0 Name DPL1(7:0) R/W R/W Reset value 0x00 Description Data Pointer 1, low byte DPH1 (0x85) - Data Pointer 1, high byte Bit 7:0 Name DPH1(7:0) R/W R/W Reset value 0x00 Description Data Pointer 1, high byte SWRS047A SWRS047A Page 21 of 146 CC1010 CC1010 DPS (0x86) - Data Pointer Select Bit 7:1 0 Name R/W R0 R/W SEL Reset value 0x00 0x00 Description Reserved, read as 0 Data Pointer Select for external RAM access 0 : DPH0 and DPL0 are used 1 : DPH1 and DPL1 are used MPAGE (0x92) - Memory Page Select Register Bit 7:0 Name MPAGE(7:0) R/W R/W Reset value 0x00 Description Memory Page A total of 119 Special Function Registers (SFRs) are accessible from the microcontroller core. The names and addresses of all SFRs are listed in Table 11. All standard 8051 registers are available, in addition to SFRs which are CC1010 CC1010 specific, controlling modules such as the RF Transceiver, DES encryption, ADC and Real-Time Clock. 0/8 0xF8 0xF0 0xE8 0xE0 0xD8 0xD0 0xC8 0xC0 0xB8 0xB0 0xA8 0xA0 0x98 0x90 0x88 0x80 EIP B EIE ACC EICON PSW RFMAIN SCON1 IP P3 IE P2 SCON0 P1 TCON P0 1/9 TEST0 FSHAPE7 FSDELAY CURRENT MODEM2 X32CON X32CON RFBUF SBUF1 RDATA TCON2 SPCR SBUF0 EXIF TMOD SP 2/A TEST1 FSHAPE6 FSEP0 PA_POW MODEM1 WDT FREQ_0A RFCON RADRL T2PRE SPDR MPAGE TL0 DPL0 3/B TEST2 FSHAPE5 FSEP1 PLL MODEM0 PDET FREQ_1A CRPCON RADRH T3PRE SPSR ADCON TL1 DPH0 All SFRs will be described in the following sections. A more detailed overview is provided in Table 40 on page 141, which also includes all reset values. SFRs with addresses ending with 0 or 8 (leftmost column of Table 11) are bit adressable. 4/C 5/D TEST3 FSHAPE4 FSCTRL LOCK MATCH BSYNC FREQ_2A CRPKEY CRPINI4 CRPINI0 T2 P0DIR ADDATL TH0 DPL1 TEST4 FSHAPE3 RTCON CAL FLTIM FREQ_0B CRPDAT CRPINI5 CRPINI1 T3 P1DIR ADDATH TH1 DPH1 6/E 7/F TEST5 FSHAPE2 FREND PRESCALER FREQ_1B CRPCNT CRPINI6 CRPINI2 FLADR P2DIR ADCON2 CKCON DPS TEST6 FSHAPE1 TESTMUX RESERVED FREQ_2B RANCON CRPINI7 CRPINI3 FLCON P3DIR CHVER ADTRH PCON Table 11 CC1010 CC1010 SFR Overview SWRS047A SWRS047A Page 22 of 146 CC1010 CC1010 15.4 CPU Registers CC1010 CC1010 provides 4 register banks of 8 registers each. These register banks are mapped in the the internal data memory (see the Memory section on page 33) at addresses 0x00 - 0x07, 0x08 - 0x0F, 0x10 - 0x17 and 0x18 - 0x1F. Each register bank contains the 8 8-bit registers R0 through R7. The different register banks are selected through the Program Status Word PSW.RS(1:0) as shown below. PSW also contains carry, overflow and parity flags that reflect the current CPU state. In addition, the CPU uses the accumulator register A (accessed via the SFR space as ACC), B (for multiplication and division) and the stack pointer SP. These registers are shown below. Note that the hardware stack pointer SP is increased when pushing and decreased when popping data, unlike many other microcontroller architectures. PSW (0xD0) - Program Status Word Bit 7 Name CY R/W R/W Reset value 0 6 AC R/W 0 5 4 3 F0 RS1 RS0 R/W R/W R/W 0 0 0 2 OV R/W 0 1 0 F1 P R/W R/W 0 0 Description Carry Flag, set to 1 when the last arithmetic operation resulted in a carry (during addition) or borrow (during subtraction), otherwise cleared to 0 by all arithmetic operations. CY is also used for rotation instructions. Auxiliary carry flag. Set to 1 when the last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high order nibble, otherwise cleared to 0 by all arithmetic operations. Flag 0 (Available to the user for general purpose) Register bank select. RS1 RS0 Working register bank and address 0 0 Bank0 0x00-0x07 0 1 Bank1 0x08-0x0F 1 0 Bank2 0x10-0x17 1 1 Bank3 0x18-0x1F Overflow flag. Set to 1 when the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise, the bit cleared to 0 by all arithmetic operations. Flag 1 (Available to the user for general purpose) Parity flag. Set to 1 when the modulo-2 sum of the 8 bits in the accumulator is 1 (odd parity), cleared to 0 on even parity. ACC (0xE0) - Accumulator Register Bit 7:0 Name ACC(7:0) R/W R/W Reset value 0x00 Description Accumulator R/W R/W Reset value 0x00 Description B is used for multiplication and division B (0xF0) - B Register Bit 7:0 Name B(7:0) SWRS047A SWRS047A Page 23 of 146 CC1010 CC1010 SP (0x81) - Stack Pointer Bit 7:0 Name SP(7:0) R/W R/W Reset value 0x07 Description Stack Pointer, used for pushing and poping data to and from the stack. Note that the reset value for SP is 0x07 15.5 Instruction Set Summary The 8051 instruction set is summarised in Table 12 below. All mnemonics are Copyright © Intel Corporation 1980. One non-standard 8051 instruction, TRAP, with opcode 0xA5 is included to enable setting of breakpoints. This instruction is described in the In Circuit Debugging section at page 44. Symbols used in the table are: · A - Accumulator · AB - Register pair A and B · B - Multiplication register · C - Carry flag · DPTR - Data pointer · Rn - Register R0 - R7 · PC - Program counter · direct - 8-bit data address (Internal RAM 0x00 - 0x7F, SFRs 0x80-0xFF) · · rel - Two's complement offset byte used by SJMP and conditional jumps · bit - Direct bit address · #data - 8-bit constant · #data 16 - 16-bit constant · addr 16 - 16-bit destination address · addr 11 - 11-bit destination address, used by ACALL and AJMP. The branch will be within the same 2 kB block of program memory of the first byte of the following instruction. @Ri - Internal register pointed to by R0 or R1 (except MOVX) CY AC OV P SUBB A, direct Arithmetic Add register to A Add direct byte to A Add data memory to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add data memory to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Hex Opcode ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn Instr. Cycles Description Bytes Mnemonic The `Bytes' column shows the number of bytes of Flash memory used. Further, the number of instruction cycles is shown. Each instruction cycle requires four clock cycles. The 4 rightmost columns shows which flags in the program status word PSW (see page 23) are affected by the instructions. 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 28-2F 28-2F 25 26-27 24 38-3F 38-3F 35 36-37 34 98-9F 98-9F x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 2 2 95 x x x x SWRS047A SWRS047A Page 24 of 146 CC1010 CC1010 A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data CLR A CPL A SWAP A RL A RLC A RR A RRC A P ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL OV Move direct byte to A INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A AC MOV A, direct SUBB A, #data CY MOV A, Rn Subtract data memory from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment data memory Decrement A Decrement register Decrement direct byte Decrement data memory Increment data pointer Multiply A by B Divide A by B Decimal adjust A Logical AND register to A AND direct byte to A AND data memory to A AND immediate to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR data memory to A OR immediate to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR data memory to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Swap nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry Data Transfer Move register to A Hex Opcode SUBB A, @Ri Instr. Cycles Description Bytes Mnemonic 1 1 96-97 x x x x 2 2 94 x x x x 1 1 2 1 1 1 2 1 1 1 1 1 1 1 2 1 1 1 2 1 3 5 5 1 04 08-0F 08-0F 05 06-07 14 18-1F 18-1F 15 16-17 A3 A4 84 D4 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 58-5F 58-5F 55 56-57 54 52 53 48-4F 48-4F 45 46-47 44 42 43 68-6F 68-6F 65 66-67 64 62 63 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 E4 F4 C4 23 33 03 13 x x 1 1 2 2 E8EF E5 SWRS047A SWRS047A x x x x x x x x x x x x x x x x x x x x x x x x Page 25 of 146 1 1 MOV A, #data MOV Rn, A MOV Rn, direct Move immediate to A Move A to register Move direct byte to register 2 1 2 2 1 2 MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte 2 2 2 3 2 2 2 3 E6E7 74 F8-FF A8AF 78-7F 78-7F F5 88-8F 88-8F 85 Move data memory to direct byte Move immediate to direct byte MOV A to data memory Move direct byte to data memory 2 3 1 2 2 3 1 2 MOV @Ri, #data MOV DPTR, #data MOVC A, @A+DPTR 2 3 1 2 3 3 MOVC A, @A+PC MOVX A, @Ri Move immediate to data memory Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external data (A8) to A 1 1 3 2-9 MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn Move external data (A16) to A Move A to external data (A8) Move A to external data (A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register 1 1 1 2 2 1 2-9 2-9 2-9 2 2 1 XCH A, direct XCH A, @Ri Exchange A and direct byte Exchange A and data memory 2 1 2 1 XCHD A, @Ri Exchange A and data memory nibble Boolean Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND direct bit inverse to carry OR direct bit to carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit 1 1 1 2 1 2 1 2 2 2 2 2 2 2 1 2 1 2 1 2 2 2 2 2 2 2 CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C SWRS047A SWRS047A x x 86-87 75 F6-F7 A6A7 76-77 90 93 x 83 E2E3 E0 F2-F3 F0 C0 D0 C8CF C5 C6C7 D6D7 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 P Hex Opcode Move data memory to A OV Instr. Cycles MOV A, @Ri AC Description CY Mnemonic Bytes CC1010 CC1010 x x x x x x x x x x x x x x x Page 26 of 146 CC1010 CC1010 CJNE @Ri, #d, rel DJNZ Rn, rel DJNZ direct, rel NOP TRAP 11-F1 11-F1 12 22 32 01-E1 01-E1 02 80 40 50 20 30 10 73 60 70 B5 x 3 4 B4 x 3 4 x 3 4 2 3 3 4 B8BF B6B7 D8DF D5 1 1 1 3 00 A5 x Table 12. Instruction Set Summary SWRS047A SWRS047A Page 27 of 146 P 3 4 4 4 3 4 3 3 3 4 4 4 3 3 3 4 OV 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 AC CY CJNE Rn, #d, rel Branching Absolute call to subroutine Long call to subroutine Return from subroutine Return from interrupt Absolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Jump indirect relative DPTR Jump on accumulator = 0 Jump on accumulator /= 0 Compare A and direct, jump relative if not equal Compare A and immediate, jump relative if not equal Compare reg and immediate, jump relative if not equal Compare ind and immediate, jump relative if not equal Decrement register, jump relative if not zero Decrement direct byte, jump relative if not zero Misc. No operation Set EICON.FDIF = 1, used for breakpoints Hex Opcode ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #d, rel Instr. Cycles Description Bytes Mnemonic CC1010 CC1010 15.6 Interrupts In CC1010 CC1010 there are a total of 15 interrupt sources, which share 12 interrupt lines. These are all shown in Table 13. Each interrupt's natural priority, interrupt vector, Interrupt interrupt enable and interrupt flag, is also shown in the table, and will be described below. Natural Priority 0 IP.PX0 IP.PT0 IP.PX1 IP.PT1 IP.PS0 6 7 8 9 External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Port 0 Transmit Interrupt Serial Port 0 Receive Interrupt Serial Port 1 Transmit Interrupt Serial Port 1 Receive Interrupt RF Transmit / Receive Interrupt Timer 2 Interrupt ADC Interrupt - Interrupt Vector 0x33 1 2 3 4 5 Flash / Debug interrupt Priority Control Interrupt Enable Interrupt Flag 0x03 0x0B 0x13 0x1B 0x23 EICON. FDIE IE.EX0 IE.ET0 IE.EX1 IE.ET1 IE.ES0 IP.PS1 0x3B IE.ES1 EIP.PRF EIP.PT2 EIP.PAD 0x43 0x4B 0x53 EIE.RFIE EIE.ET2 EIE.ADIE and ADCON2. ADCIE EICON. FDIF TCON.IE0 (*) TCON.TF0 (*) TCON.IE1 (*) TCON.TF1 (*) SCON0.TI_0 SCON0.RI_0 SCON1.TI_1 SCON1.TI_1 EXIF.RFIF EXIF.TF2 EXIF.ADIF and EIE.ADIE and DES Encryption / Decryption Interrupt Timer 3 Interrupt Realtime Clock Interrupt 10 11 EIP.PT3 EIP.PRTC (*) - Interrupt flag is cleared by hardware. 0x5B 0x63 ADCON2. ADCIF EXIF.ADIF and CRPCON. CRPIE EIE.ET3 EIE.RTCIE CRPCON. CRPIF EXIF.TF3 EICON.RTCIF Table 13. CC1010 CC1010 Interrupt overview 15.6.1 Interrupt Masking IE.EA is the global interrupt enable for all interrupts, except the Flash / Debug interrupt. When IE.EA is set, each interrupt is masked by the interrupt enable bits listed in Table 13. When IE.EA is cleared, all interrupts are masked, except the Flash / Debug interrupt, which has its own interrupt mask bit, EICON.FDIE. 15.6.2 Interrupt Processing When an enabled interrupt occurs, the CPU jumps to the address of the interrupt service routine (ISR) associated with that interrupt, as shown in Table 13. Most interrupts can also be initiated by setting the associated interrupt flag from software. CC1010 CC1010 executes the ISR to completion unless another interrupt set at a higher interrupt level occurs. Each ISR ends with a RETI (return from interrupt) instruction. After executing the RETI, CC1010 CC1010 returns to the next instruction that would have been executed if the interrupt had not occurred. CC1010 CC1010 always completes the instruction in progress before servicing an interrupt. If the instruction in progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, CC1010 CC1010 completes one additional instruction before servicing the interrupt. SWRS047A SWRS047A Page 28 of 146 CC1010 CC1010 IE (0xA8) - Interrupt Enable Register Bit 7 Name EA R/W R/W Reset value 0 6 ES1 R/W 0 5 4 ES0 R/W R/W 0 0 3 ET1 R/W 0 2 EX1 R/W 0 1 ET0 R/W 0 0 EX0 R/W 0 Description Global Interrupt enable / disable 0 : All interrupts except the Flash / debug interrupt are disabled 1 : Each interrupt is enabled by its individual masking bit Serial Port 1 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Reserved for future use Serial Port 0 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 1 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set External interrupt 1 (from P3.3) enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 0 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set External interrupt 0 (from P3.2) enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set EIE (0xE8) - Extended Interrupt Enable Register Bit 7 6 5 4 Name RTCIE R/W R1 R1 R1 R/W Reset value 1 1 1 0 3 ET3 R/W 0 2 ADIE R/W 0 1 ET2 R/W 0 0 RFIE R/W 0 Description Reserved, read as 1 Reserved, read as 1 Reserved, read as 1 Realtime Clock interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 3 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set ADC / DES interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 2 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set RF Interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set SWRS047A SWRS047A Page 29 of 146 CC1010 CC1010 EICON (0xD8) - Extended Interrupt Control Bit 7 Name SMOD1 R/W R/W Reset value 0 6 5 FDIE R1 R/W 1 0 4 FDIF R/W 0 3 RTCIF R/W 0 2 1 0 - R0 R0 R0 0 0 0 Description Serial Port 1 baud rate doubler enable / disable 0 : Serial Port 1 baud rate is normal 1 : Serial Port 1 baud rate is doubled Reserved, read as 1 Flash / Debug interrupt enable 0 : Interrupt is disabled 1 : Interrupt is enabled (independent of IE.EA) Flash / Debug interrupt flag FDIF is set by hardware when an 8051-initiated write to Flash program memory is completed or a TRAP instruction is executed. FDIF may also be set by software. FDIF must be cleared by software before exiting the ISR. Real-time clock interrupt flag RTCIF is set by hardware when an interrupt request is generated from the real-time clock. RTCIF may also be set by software. RTCIF must be cleared by software before exiting the ISR. Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 EXIF (0x91) - Extended Interrupt Flag Bit 7 Name TF3 R/W R/W Reset value 0 6 ADIF R/W 0 5 TF2 R/W 0 4 RFIF R/W 0 3 2 1 0 - R1 R0 R0 R0 1 0 0 0 Description Timer 3 interrupt flag. TF3 is set by hardware when an interrupt request is generated from Timer 3. TF3 may also be set by software. TF3 must be cleared by software before exiting the ISR. ADC / DES Interrupt flag. ADIF is set by hardware when an interrupt request is generated from the ADC block (ADCON2.ADCIF) or by the DES Encryption / Decryption block (CRPCON.CRPIF). These interrupts must also be enabled by setting ADCON2.ADCIE and CRPCON.CRPIE. ADIF may also be set by software. ADIF must be cleared by software before exiting the ISR Timer 2 interrupt flag. TF2 is set by hardware when an interrupt request is generated from Timer 2. TF2 may also be set by software. TF2 must be cleared by software before exiting the ISR RF Transmit / receive interrupt flag. RFIF is set by hardware when an interrupt request is generated from the RF transceiver block. RFIF may also be set by software. RFIF must be cleared by software before exiting the ISR. Reserved, read as 1 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 SWRS047A SWRS047A Page 30 of 146 CC1010 CC1010 15.6.3 Interrupt Priority Interrupts are prioritised in two stages: Interrupt level and natural priority. The interrupt level (low, high or highest) takes precedence over the natural priority. The Flash / Debug Interrupt, if enabled, always has the highest priority and is the only interrupt that can have the highest priority. All other interrupts can be assigned either low or high priority, set by the registers IP and EIP listed below. Two interrupts with the same interrupt priority that occur simultaneously are resolved through their natural priority. The natural priority is shown in Table 13. The interrupt having the lowest natural priority will be serviced first. Once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced. IP (0xB8) - Interrupt Priority Register Bit 7 6 Name PS1 R/W R1 R/W Reset value 1 0 5 4 PS0 R/W R/W 0 0 3 PT1 R/W 0 2 PX1 R/W 0 1 PT0 R/W 0 0 PX0 R/W 0 Description Reserved, read as 1 Serial Port 1 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Reserved for future use Serial Port 0 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 1 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority External Interrupt 1 (from P3.3) interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 0 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority External Interrupt 0 (from P3.2) interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority EIP (0xF8) - Extended Interrupt Priority Register Bit 7 6 5 4 Name PRTC R/W R1 R1 R1 R/W Reset value 1 1 1 0 3 PT3 R/W 0 2 PAD R/W 0 1 PT2 R/W 0 0 PRF R/W 0 Description Reserved, read as 1 Reserved, read as 1 Reserved, read as 1 Realtime Clock interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 3 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority ADC / DES interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 2 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority 0 : Interrupt has low priority 1 : Interrupt has high priority SWRS047A SWRS047A Page 31 of 146 CC1010 CC1010 15.7 External interrupts Two external interrupt pins are available in the CC1010 CC1010. They are located on pins P3.2 and P3.3, and can be set up to be either level- or edge sensitive by setting the IT1 and IT2 bits in the TCON register (see page 54 for more information). When the external interrupts are activated in the IE register, any pulse longer than 8 clock cycles will always generate an interrupt. The CC1010 CC1010 will wake up from Idle mode when an external interrupt pin is activated, but the external interrupt pins cannot wake the CC1010 CC1010 from Power-Down mode. 15.8 Main Crystal Oscillator An external clock signal or the main crystal oscillator can be used as main frequency reference and microcontroller clock signal. An external clock signal should be connected to XOSC_Q1, while XOSC_Q2 should be left open. The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Typically the total parasitic capacitance is 3-5pF. A trimming capacitor may be placed across C171 for initial tuning if necessary. The microcontroller core and main oscillator will operate at any frequency in the range 3 - 24 MHz. However, the crystal frequency should be in the range 34, 6-8 or 9-24 MHz because the crystal frequency is used as reference for the data rate in the RF transceiver part (as well as other internal functions). The following frequencies are recommended as they will provide "standard" data rates: 3.6864, 7.3728, 11.0592, 14.7456, 18.4320 and 22.1184 MHz. The selected crystal frequency range must be set in MODEM0.XOSC_FREQ(2:0) in order to get the correct data rate (see page 93). The crystal oscillator is of an advanced amplitude-regulated type. A high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain a 600 mVpp amplitude. This ensures a fast startup, keeps the current consumption and the drive level to a minimum and makes the oscillator insensitive to ESR variations. As long as you follow the crystal loading capacitance requirements, do not worry about ESR or drive levels (a typical drive level is 4 µW for 3 MHz). Using the main crystal oscillator, the crystal must be connected between the pins XOSC_Q1 and XOSC_Q2. The oscillator is designed for parallel mode operation of the crystal. In addition loading capacitors (C171 and C181) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency. CL = 1 1 1 + C171 C181 + C parasitic The main crystal oscillator circuit is shown in Figure 4. Typical component values for different values of CL are given in Table 14. Recommended load capacitance versus frequency is given in Table 10 on page 12. The initial tolerance, temperature drift, ageing and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application. By specifying the total expected frequency accuracy in SmartRF® Studio together with data rate and frequency separation, the software will calculate the total bandwidth and compare to the available IF bandwidth. Any contradictions will be reported by the software and a more accurate crystal will be recommended if required. SWRS047A SWRS047A Page 32 of 146 CC1010 CC1010 XOSC_Q1 XOSC_Q2 XTAL C181 C171 Figure 4. Crystal oscillator circuit Item C171 C181 CL= 12 pF 15 pF 15 pF CL= 20 pF 30 pF 30 pF Table 14. Crystal oscillator component values SWRS047A SWRS047A Page 33 of 146 CC1010 CC1010 15.9 Power and Clock Modes Several power modes are defined to save power when running CC1010 CC1010. The modes are described below. See also Table 15. 15.9.1 Active Mode In active mode the 8051 is running normally, executing instructions from the Flash program memory. The clock used in this mode could either be the main crystal oscillator, or it could be the 32 kHz oscillator. The current consumption depends on the actual frequency used. 15.9.2 Idle Mode After completing the instruction that sets the PCON.IDLE bit, Idle Mode is entered. In Idle Mode, the 8051 processing is stopped and internal registers maintain their current data, but all peripherals are still running. 15.9.3 Power-Down Mode After completing the instruction that sets the PCON.STOP bit, the controller core and the peripherals are stopped. In PowerDown Mode, the clock trees of the 8051 and peripherals are disabled. Only the ADC clock tree is running. This enables the ADC to generate reset as will be described in the ADC section. Note that the PCON.STOP bit does not affect the clock oscillators; these will still be running if they are switched on when entering Power-Down Mode. To ensure minimum power-consumption, the ADC should be switched off and Power-down mode should be entered by switching off the oscillators instead of using the PCON.STOP bit. There are 3 ways to exit Idle Mode: There are 2 ways to exit Power Down Mode: · · Activate any reset condition. All registers are then reset, and program execution will resume when the reset condition is cleared. Program execution will then resume from address 0x0000. · Turn the power off and on. The Power On Reset module should then be enabled, or an external reset signal should be applied during power up. · · Activate any enabled interrupt. This clears the IDLE bit, terminating Idle Mode, and executes the ISR associated with the received interrupt. The RETI instruction at the end of the ISR causes the 8051 to return to the instruction following the one that enabled Idle Mode. Activate any reset condition. All registers are then reset, and program execution will resume from address 0x0000 when the reset condition is cleared. Turn the power off and on. The Power On Reset module should then be enabled, or an external reset signal should be applied during power up. More information about minimising the power consumption of the CC1010 CC1010 can be found in Application Note AN017 AN017 Low Power Systems Using The CC1010 CC1010. SWRS047A SWRS047A Page 34 of 146 CC1010 CC1010 Mode Core Main osc. RTC osc. (32 kHz) Main osc. Stopped Idle Main osc. RTC osc. (32 kHz) Stopped Active Peripherals RTC osc. (32 kHz) ADC Off ADC On (32 kHz) Stopped Typical current consumption1 14.8 mA at 14.7456 MHz 1.3 mA Writing SFR 12.8 mA at 14.7456 MHz 29.4 uA Interrupt Reset Power off/on 200 uA ADC value exceeds threshold Reset Power off/on Reset Power off/on Power-Down Stopped Stopped 0.2 uA Exit condition Writing SFR Note 1: Flash duty-cycle reduction is used for all modes Table 15. Operating modes summary 15.9.4 Clock Modes The 8051 and its peripherals can be run on both the main crystal oscillator (Clock Mode 0) and the 32.768 kHz oscillator (Clock Mode 1). The clock mode is set in X32CON X32CON.CMODE. 15.9.5 Entering Clock Mode 1 from Clock Mode 0 After reset, the 8051 and its peripherals are running on the main crystal oscillator, and the 32.768 kHz oscillator is in power down. To enter Clock Mode 1, the 32.768 kHz oscillator must first be powered up. This requires clearing X32CON X32CON.X32_PD and then waiting at least 160 ms, after which X32CON X32CON.CMODE can be set to enter Clock Mode 1. If an external 32.768 kHz clock source is already available in the system, this clock can be applied to the XOSC32 XOSC32_Q1 pin after setting the X32CON X32CON.X32_BYPASS bit. After 2 to 3 clock periods on the 32.768 kHz oscillator, a glitch free transition has been made from the main crystal oscillator to the 32.768 kHz oscillator. If desired, the main crystal oscillator can then be set in power down to save more power by setting RFMAIN.CORE_PD and RFMAIN.BIAS_PD. This has the disadvantage that a later transition from Clock Mode 1 to Clock Mode 0 will require the main crystal oscillator to be powered up again. Since the Flash program memory draws a static current, Idle Mode together with Flash Power Control (see page 43) should be applied for maximum power saving in Clock Mode 1. The RF receiver cannot be activated in Clock Mode 1. 15.9.6 Entering Clock Mode 0 from Clock Mode 1 To enter Clock Mode 0 from Clock Mode 1, the main crystal oscillator must first be set in power up (if powered down). This requires clearing RFMAIN.CORE_PD and RFMAIN.BIAS_PD and then waiting at least 5 ms (depend on main oscillator frequency, see Electrical Specifications page 7). If the oscillator is already powered up, no waiting is required. Clearing X32CON X32CON.CMODE will then cause a glitch free transition from Clock Mode 1 to Clock Mode 0 after 2 to 3 clock periods on the main crystal oscillator. 15.9.7 Flash Power Control The Flash program memory current consumption can be controlled as described in the Flash Power Control section on page 43. SWRS047A SWRS047A Page 35 of 146 CC1010 CC1010 PCON (0x87) - Power Control Register Bit 7 Name SMOD0 R/W R/W Reset value 0 6 5 4 3 GF1 R/W R1 R1 R/W 0 1 1 0 2 GF0 R/W 0 1 STOP R/W 0 0 IDLE R/W 0 Description Serial Port 0 baud rate doubler enable. 0 : Serial Port 0 baud rate is not doubled 1 : Serial Port 0 baud rate is doubled Reserved Reserved, read as 1 Reserved, read as 1 General purpose flag 1. Bit-addressable, general purpose flag for software control. General purpose flag 0. Bit-addressable, general purpose flag for software control. Power Down (Stop) mode select. Setting the STOP bit places CC1010 CC1010 core and peripherals in Stop Mode. Idle mode select. Setting the IDLE bit places CC1010 CC1010 in Idle Mode (core is stopped but peripherals are running). X32CON X32CON (0xD1) - 32.768 kHz Crystal Oscillator Control Register Bit 7 6 5 4 3 2 Name X32_BYPASS R/W R0 R0 R0 R0 R0 R/W Reset value 0 0 0 0 0 0 1 X32_PD R/W 1 0 CMODE R/W 0 Description Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 32.768 kHz oscillator bypass control signal 0 : The internal 32.768 kHz oscillator is used to generate the 32.768kHz clock 1 : The internal 32.768 kHz oscillator is bypassed, and an external clock signal can be applied to the XOSC32 XOSC32_Q1 pin. 32.768 kHz oscillator power down signal 0 : The oscillator is powered up 1 : The oscillator is powered down (default after reset) Select different Clock Modes for the 8051 and its peripherals. 0 : Clock Mode 0 is selected (default after reset) 1 : Clock Mode 1 is selected SWRS047A SWRS047A Page 36 of 146 CC1010 CC1010 15.10 Flash Program Memory CC1010 CC1010 has 32 kBytes of on-chip Flash program memory. It is divided into 256 pages of 128 bytes each. It can be programmed / erased through a serial SPI interface or page-by-page from the 8051 as described in the following sections. others. It can also prevent parts of the Flash memory from being modified by software, such as a boot loader that should remain unchanged. Other parts of the Flash may still be updated by the boot loader. The endurance for the Flash program memory is typically 20.000 erase / write cycles. For the security of the Flash protection, please refer to the disclaimer at the end of this document. The Flash program memory can be locked for further reading / writing by setting appropriate lock bits through the serial interface. Chip erase must be performed to unlock the memory. This provides a way to prevent software from being copied by Erasing a Flash page takes 10-20 ms depending on the FLTIM register. Writing to a Flash page takes 5-10 ms. 15.11 SPI Flash Programming The on-chip Flash program memory can be programmed using the SPI Flash programming protocol described in this section. SPI Flash programming is enabled when the pin PROG is held low. This enables the SPI slave, using the pins SCK (P0.0) as the clock input, SI (P0.1) as the serial data input and SO (P0.2) as the serial data output. A Windows based Flash programmer is also available free of charge at the Chipcon web site. 15.12 Serial Programming Algorithm When writing serial data to the SPI interface, data is clocked at the rising edge of SCK. When reading data from the SPI interface, data is clocked at the falling edge of SCK, see Figure 5. 1. Apply power between VDD and DGND while SCK is set to `0'. If a crystal is not connected between XOSC_Q1 and XOSC_Q2 apply a clock signal to the XOSC_Q1 pin. 2. Give RESET a negative pulse of at least one XOSC period. 3. Set PROG low. 4. Send the Programming Enable command. Check that the slave is synchronised by verifying that the second byte of the instruction is echoed back when issuing the third byte. If the second byte did not echo, issue a positive pulse on SCK and try again. In the worst case it will take 32 attempts to synchronise. 5. Send the Set Write Cycle Time command according to the device clock oscillator frequency. c*16*clock period must be between 20-40us for safe flash programming. 6. If a chip erase is performed wait 450ms after the instruction before issuing Write. 7. Flash memory is programmed one page at a time. Each page consists of 128 bytes. Load all bytes of the page that is to be programmed with the Load Program Memory Page instruction. 8. When all bytes of a page has been loaded issue Write Program Memory Page with the page address. The write operation finishes within 5.4ms. Reading an address while writing will return 0xFF. This can be used for polling SWRS047A SWRS047A Page 37 of 146 CC1010 CC1010 to determine when a page write is finished. When a read instruction returns anything other than $FF all flash write operations have finished. Instruction Byte 1 Byte 2 15.12.1 SPI Flash Programming Instructions 9 instructions are defined to perform the serial Flash programming. These are shown in Table 16. Byte 3 Byte 4 Operation xxxx xxxx Enable serial programming after Programming Enable 1010 1100 Set Flash Timing 1010 1100 0101 1101 xxxx xxxx xxii iiii Set the Flash timing register Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase. Clears all pages, including the lock bits. Load Program Memory Page 0100 H000 xxxx xxxx bbbb bbxx iiii iiii Load data i to Programming Buffer at address b:H Write Program Memory Page 0100 1100 aaaa aaaa xxxx xxxx xxxx xxxx Write the loaded page at address a. Read Program Memory 0010 H000 aaaa aaaa bbbb bbxx oooo oooo Read data o at address a:b:H 0101 0011 xxxx xxxx PROG is set low Write Lock Bits 1010 1100 111x xxxx xxxx xxxx iiii iiii Write Lock Bits. Bits written will be ANDed together with the existing lock bits. Read Lock Bits 0101 1000 xxxx xxxx xxxx xxxx oooo oooo Read lock bits. Read Signature Byte 0011 0000 xxxx xxxx xxxx xsss oooo oooo Read signature byte o at address s a: Page address b: Even byte address H: Odd or even (high or low) byte c: Clock timing bits s: Signature byte address i: Input data o: Output data x: Don't care Table 16. SPI Flash Programming Instructions Each instruction is sent in the order bytes 1 to 4, most significant bits first. All 4 bytes must be sent, even if the last bits are 'x'. The timing for the SPI interface is shown in Figure 5. All timing parameters are listed in Table 17. SWRS047A SWRS047A Page 38 of 146 CC1010 CC1010 Tsck, high Tsck, low Tsck, rise Tsck, fall SCK (P0.0) 7 SI (P0.1) 6 7 SO (P0.2) 5 6 Tsi, setup 4 5 3 4 Tsi, hold 2 3 1 2 0 1 0 Tso, delay Figure 5. SPI Flash Programming Timing Symbol Fsck Tsck, high Tsck, low Tsck, rise Tsck, fall Tsi, setup Min 4 TXOSC 4 TXOSC TXOSC Max fXOSC / 8 TXOSC /2 TXOSC /2 - Tsi, hold TXOSC - Tso, delay - TXOSC Units ns ns Conditions The minimum time SCK must be held high The minimum time SCK must be held low The maximum rise time on SCK The maximum fall time on SCK The minimum setup time for SI before the positive edge on SCK The minimum hold time for SI after the positive edge on SCK The delay from the negative edge on SCK to valid data on SO Table 17. SPI Flash Programming Timing Parameters 15.12.2 Programming Enable Programming Enable is always the first instruction to be sent. It must be sent to synchronise the data flow and enable CC1010 CC1010 to receive further instructions. Synchronisation is achieved when byte 2 of the instruction (0x53) is echoed back from the SPI interface as byte 3. If synchronisation is not achieved, byte 3 will return all zeros. In this case, an extra clock pulse should be inserted on SCK, and the Programming Enable instruction should be resent. If synchronisation is not successful within 32 attempts, Programming Enable is unsuccessful and further debugging is needed. f XOSC f FLTIM XOSC 0.8MHz 0.4 MHz It is recommended to set FLTIM to the smallest number satisfying the equation above, to reduce the time needed for Flash programming. For a 3.6864 MHz crystal, FLTIM should be set to 5. 15.12.4 Chip Erase The Chip Erase instruction erases all data in the Flash memory, including the lock bits. All bits will be set high. Wait 450 ms (depending on Set Flash Timing) after sending the Chip Erase instruction before issuing a new instruction. 15.12.3 Set Flash Timing The Set Flash Timing instruction is needed to generate internal timing for the Flash module. FLTIM must be set in instruction byte 4 so that: 15.12.5 Load Program Memory Page The Load Program Memory Page instruction is used to load the 128 bytes of data in a page to a buffer in RAM. Each instruction writes one byte to the 7 bit address specified in the instruction. SWRS047A SWRS047A Page 39 of 146 CC1010 CC1010 15.12.6 Write Program Memory Page The Write Program Memory Page instruction writes the 128 bytes buffered through the Load Program Memory Page instructions to Flash memory. After issuing this command, wait 5.4 ms for it to complete. It is also possible to use the Read Program Memory instruction to poll when the program memory has been written. When writing is in progress, all read instructions will return 0xFF. Reading an address containing data different from 0xFF can then be used to check when the write is completed. Bit 7:3 4 Name BBLOCK 3:1 LSIZE[2:0] 0 SPIRE 15.12.7 Read Program Memory The Flash program memory can be read back byte by byte using the Read Program Memory instruction. The data is returned in byte 4 of the instruction. Wait at least 9 TXOSC between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data. 15.12.8 Write Lock Bits The reading (through SPI) and writing to the Flash program memory can be disabled by setting the lock bits as described in this section. This should be used for software protection. The lock bits are set using the Write Lock Bits instruction. A block of programmable size at the top of the Flash program memory can be locked for writing using the LSIZE bits. Page 0 can be independently locked for writing by using the BBLOCK bit. Reading data through the SPI interface can be disabled using the SPIRE bit. Function Reserved, write as '0' Boot Block Lock 0 : Page 0 is write protected 1 : Page 0 is writeable, unless LSIZE is 000 Lock Size, sets the size of the upper Flash area which is write protected. Byte sizes and page numbers are listed below: 000 : 32768 (All pages) 001 : 16384 (page 128255) 010 : 8192 (page 192-255) 011 : 4096 (page 224-255) 100 : 2048 (page 240-255) 101 : 1024 (page 248-255) 110 : 512 (page 252-255) 111 : 0 (no pages) SPI Read Flash Enable / Disable 0 : SPI Interface returns all zeros on the Read Program Memory instruction 1 : SPI Interface returns valid Flash data on the Read Program Memory instruction Table 18. Flash Lock Bits Lock bits can only be erased (set high) by issuing the Chip Erase instruction. If multiple Write Lock Bits instructions are issued without chip erase in between, each lock bit will be AND-ed together with the previously written lock bits. In effect, this means that it is not possible to unlock the Flash program memory without also erasing it. The effect of the different lock size bits are illustrated in Figure 6. The detailed description of all lock bits is given in Table 18. SWRS047A SWRS047A Page 40 of 146 0x4000 0x0000 130 129 128 127 126 2 1 0 LSIZE = 111 LSIZE = 101 LSIZE = 100 LSIZE = 110 LOCKED LOCKED LOCKED LSIZE = 011 UNLOCKED UNLOCKED UNLOCKED LSIZE = 010 LOCKED LOCKED LSIZE = 000 LSIZE = 001 Signature byte address 000 001 010 011 100 Value 0x7F 0x7F 0x7F 0x9E 0x95 101 UNLOCKED 0x6000 194 193 192 191 190 signature byte address is issued, and the value is then returned as byte 4. 0x00 Meaing JEDEC manufacturer ID, identifies Chipcon AS as the manufacturer. Identifies 32 kBytes of Flash memory Identifies CC1010 CC1010 Table 19. Signature Bytes UNLOCKED 0x7000 226 225 224 223 222 UNLOCKED 0x7800 242 241 240 239 238 LOCKED 0x7C00 LOCKED 0x7E00 255 254 253 252 251 250 249 248 247 246 UNLOCKED 0x7FFF Page number Address CC1010 CC1010 Page 0 is locked when BBLOCK is cleared Figure 6. Flash Lock Bits illustration Wait at least 9 TXOSC between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data, as with the Read Program Memory instruction. 15.12.11 SPI Flash Programming Initialisation CC1010 CC1010 must be set into the Flash programming mode to allow SPI Flash operations. This is done as follows: · Apply power between all DVDD and DGND pins. · Hold PROG low. · If a crystal is connected between XOSC_Q1 and XOSC_Q2, hold RESET 15.12.9 Read Lock Bits low and wait for the oscillator to start up. Crystal oscillator start-up times are given in Table 10. Release RESET The lock bits described in the previous section can be read through the SPI interface by using the Read Lock Bits instruction. The instruction will return the 8 lock bits in byte 4 of the instruction. Wait at least 9 TXOSC between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data, as with the Read Program Memory instruction. The lock bits can only be read through the SPI interface, and not from the 8051 core. 15.12.10 Read Signature Byte A 6 byte chip signature can be read through the SPI interface using the Read Signature Byte instruction. The 3 bit and wait at least 4 crystal oscillator periods. · If a crystal is not connected between XOSC_Q1 and XOSC_Q2, hold RESET low and apply a clock signal to XOSC_Q1. Release RESET after at least 3 clock periods, and then wait at least 4 clock periods. · Execute the Programming Enable instruction to complete the SPI Flash programming Initialisation. CC1010 CC1010 is now ready to be programmed, as described in the next section. SWRS047A SWRS047A Page 41 of 146 CC1010 CC1010 15.12.12 Programming the Flash Memory · After the initialisation is completed, SPI programming can be performed as follows: Repeat the loading and writing of each new page. · Programming can be verified using the Read Program Memory instruction. · Set the lock bits using the Write Lock Bits instruction. · Lock bits can be verified by using the Read Lock Bits instruction. · Disable all interrupts except the Flash / Debug interrupt, which must be enabled (through EICON.FDIE). · Store the 128 bytes of data to be written in the external data memory. The address of the first byte in the buffer must be a multiple of 128. · Write the 4 most significant bits of the RAM buffer address to FLCON.RMADR(3:0). Also set the bit FLCON.WRFLASH. · Set the 8051 in Idle Mode by setting PCON.IDLE. The Flash page is then automatically erased and programmed. · Device identity can be verified using the Read Signature Byte instruction. · Perform Chip Erase. · Load one page into the buffer using the Load Program Memory Page instruction. · Write the buffer to Flash by using the Write Program Memory Page instruction. 15.13 8051 Flash Programming Each of the 256 pages (128 bytes each) in Flash program memory can be programmed individually from the 8051. The 8051 must be set in Idle Mode while programming the Flash, since it has no access to the program memory while the writing is in progress. The step for writing a page to Flash is described as follows: · Set the correct write cycle time, according to the current crystal oscillator frequency, in the FLTIM SFR. This number is used to generate the timing to the on-chip Flash interface, as was also done with SPI Flash programming. It must be set so that: f XOSC f FLTIM XOSC 0.8MHz 0.4 MHz · The time used for programming a Flash page is strongly dependent on the setting in FLTIM. It is therefore recommended to set FLTIM as low as possible, as with the SPI Flash programming. · The sequence of the above steps is not important. Flash programming is started whenever entering Idle Mode while FLCON.WRFLASH is set. Write the desired Flash page number to the FLADR register. A Flash / Debug interrupt will be generated when the page write operation is completed, which will get the 8051 out of Idle Mode. An ISR must be present to service the Flash / Debug interrupt. SWRS047A SWRS047A Page 42 of 146 CC1010 CC1010 FLADR (0xAE) - Flash Write Address Register Bit 7:0 Name FLADR(7:0) R/W R/W Reset value 0x00 Description The number of of the Flash page to be written (8 MSB of the byte address) FLCON (0xAF) - Flash Write Control Register Bit 7 6:5 Name R/W R0 R/W Reset value 0 00 4 WRFLASH R/W 0 3:0 RMADR(3:0) R/W 0x0 FLASH_LP (1:0) Description Reserved, read as 0 Flash Low Power control bits 00 : The Flash module is always active. 01 : The Flash module enters standby mode when the 8051 is put in Idle mode or Stop mode 10 : The Flash module enters standby mode between instruction fetches and when the 8051 is put in Idle Mode or Stop Mode. 11 : Reserved for future use. Write Flash Start bit Starting a Flash page programming is done by first setting this bit and then setting the 8051 in Idle Mode. If the WRFLASH bit is cleared before Idle Mode is entered, no programming is performed. RAM Buffer address RMADR(3:0) contains the 4 most significant bits of the RAM address where the data is buffered before writing to Flash FLTIM (0xDD) - Flash Write Timing Register Bit 7:0 Name FLTIM(7:0) R/W R/W Reset value 0x0A If an attempt is made to write data to a Flash page which is locked (see the previous section), a Flash / Debug interrupt will be generated immediately after Idle Mode is entered. No data will be written. It is not possible to read or write the Flash lock bits from the 8051. FLTIM=0x05; /* FLADR=0x01; /* EICON|=0x20; /* IE&= ~0x80; /* FLCON=0x10 | (0x100 /* PCON|=0x01; /* Description Flash Write Timing control FLTIM must be set as described in this section prior to using the 8051 Flash programming. 15.13.1 Example Code Example C code writing data buffered at address 0x100-0x17F in external RAM to the second page in Flash (address 0x0800x0FF) is shown below. The system clock frequency is assumed to be 3.6864 MHz. An interrupt service routine must be present at address 0x33, which clears the interrupt flag EICON.FDIF and returns from the interrupt (RETI). Set Flash timing for 3.6864 MHz clock frequency */ Write data to the second page in Flash */ Enable Flash interrupt */ Disable other interrupts */ >> 7); Enable Flash writing, RAM buffer from addr. 0x100 */ Enter Idle Mode to start Flash writing. 15.14 Flash Power Control SWRS047A SWRS047A Page 43 of 146 CC1010 CC1010 The Flash module can be set into different power modes using the control bits FLCON.FLASH_LP(1:0) introduced in the previous section. After reset, the Flash module is always active, drawing a static current of approximately 2.5 mA (at nominal operating conditions). However, to save power the Flash module can be set in a power-down mode between instructions in Active mode, and always in Idle or PowerDown mode. This will save approximately 1.5 mA of the Flash current consumption during operation in Active mode, and 2.5 mA during Idle or Power-Down mode. 15.15 In Circuit Debugging In order to facilitate a software monitor for in-circuit debugging/emulation capabilities a number of hardware support features have been implemented: A breakpoint instruction has been added to the 8051's instruction set. The instruction, given the mnemonic TRAP, is a single byte instruction with the opcode 0xA5. In the original 8051 the 0xA5 opcode is executed as a NOP instruction (opcode 0x00.) In the modified core this instruction raises a highest-level interrupt (Flash / Debug) by setting the corresponding interrupt flag EICON.FDIF and waiting a sufficient number of instruction cycles to allow the interrupt to take effect before the next instruction. Since the Flash memory can only withstand 20000 (typical) erase/writecycles a simple instruction replacement mechanism has been implemented. This feature allows the surveillance of an address in the instruction memory space as defined in registers RADRL and RADRH. When this address is encountered on the Flash program memory address bus, the data returned on the data bus is replaced by the contents of register RDATA. Setting RADRH=RADRL=0 disables the replacement mechanism. This instruction replacement mechanism can be used in different ways: · A simple way of setting a single soft (not stored in FLASH) breakpoint, by setting RDATA to 0xA5 (the TRAP instruction) and RADR to the breakpoint address. · A simple way of restoring the original opcode byte of an instruction which has been subjected to a hard (stored in Flash) breakpoint, so that it can be executed (in single-step mode). · A second serial port has been added to enable debugging communication with a host PC without disrupting applications that use the main serial port for other purposes. SFRs (hardware registers) can normally only be addressed directly (i.e. by hardwiring the specific address into the corresponding MOV instruction.) This would make code in a debug monitor, which returns the value of SFRs to a PC rather bloated. Using the instruction replacement mechanism on the operand byte of the move instruction instead of the opcode byte, allows indirect addressing of SFRs. Setting breakpoints and executing the instructions which have a breakpoint attached involves writing new data to the Flash instruction memory several times. Chipcon provides software for in-circuit debugging, which may be downloaded from the Chipcon homepage. This software uses the RESERVED register, The TRAP instruction can thus be written over the first byte (opcode) of any other instruction, the execution of which then will result in a branch to a software debugging monitor in the highest priority interrupt service routine. Single-stepping through instructions is supported since exactly one instruction is executed if an interrupt condition exists when returning from an interrupt service routine. Thus, single-stepping can be accomplished simply by not clearing the corresponding interrupt flag in the interrupt service routine associated with the software monitor. SWRS047A SWRS047A Page 44 of 146 CC1010 CC1010 which can then not be used for other purposes. If in-circuit debugging is not required, the RESERVED register shown below may be used for any purpose. Writing to it will have no effect on the operation of CC1010 CC1010. Great caution should be used when the RADR is written. Since the address consists of two bytes (RADRL and RADRH), there will be a short interval where the address is not valid as only one of the bytes are written at a time. If this intermediate address point to the very same location as of the code modifying the RADR, a malfunction will occur. One possible work-around is to first write RADRH to a value pointing to a memory loca