NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| C8051F301 | Cygnal Technologies | 8KB Flash, 256 RAM, 11-Pin MCU |
2 pages, |
Original | |
| C8051F301 | Silicon Laboratories, Inc. | Microcontroller, 8KB Flash, 256 RAM, MCU |
2 pages, |
Original | |
| C8051F301 | Silicon Laboratories, Inc. | Mixed Signal ISP Flash MCU Family |
174 pages, |
Original | |
| C8051F301-GM | Silicon Laboratories, Inc. | Mixed Signal ISP Flash MCU Family |
174 pages, |
Original | |
| C8051F301-GM | Silicon Laboratories, Inc. | 25 MIPS, 8 kB Flash, 11-Pin Mixed-Signal MCU |
2 pages, |
Original | |
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Lead and Lead-free packages) Ordering Part Numbers - VDD Lead-free package: C8051F301-GM Standard package: C8051F301 Analog/Digital Power GND C2D Debug HW Reset RST/C2CK POR , C8051F301 25 MIPS, 8 kB Flash, 11-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 uC Core - Comparator - Programmable hysteresis and response time Configurable to generate , /C2D + - 4.8.2005 C8051F301 25 MIPS, 8 kB Flash, 11-Pin Mixed-Signal MCU Selected ... | Original |
2 pages, |
C8051F301-GM C8051F300DK C8051F301 C8051F301 abstract |
| Abstract: C8051F301 8KB Flash, 256 RAM, 11-Pin MCU PRELIMINARY HIGH SPEED 8051 uC Core COMPARATOR - Programmable Hysteresis and Response Time Configurable as Wake-up or Reset Source Low Current (0.4uA) - Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks Up to 25MIPS 25MIPS Throughput with 25MHz Clock Expanded Interrupt Handler ON-CHIP DEBUG - - , 10.15.2001 C8051F301 8KB Flash, 256 RAM, 11-Pin MCU PRELIMINARY SELECTED ELECTRICAL SPECIFICATIONS ... | Original |
2 pages, |
C8051F301 C8051F300DK C8051F301 abstract |
| Abstract: C8051F301 8KB Flash, 256 RAM, 11-Pin MCU PRELIMINARY COMPARATOR - Programmable Hysteresis and Response Time Configurable as Wake-up or Reset Source Low Current (0.4uA) ON-CHIP DEBUG - On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive In-System Debug (No Emulator Required!) Provides Breakpoints, Single Stepping, Watchpoints Inspect/Modify Memory, Registers, and Stack , P0.4/TX SMBus P0.5/RX P0.6/CNVS P0.7/C2D C2D CP0 + - 10.15.2001 C8051F301 8KB ... | Original |
2 pages, |
C8051F301 C8051F300DK C8051F301 abstract |
| Abstract: Rating 3 1 Example Part Number C8051F005 C8051F005 C8051F301 Lead-free QFP 1 Lead-free QFN-11 QFN-11 1 Lead-free QFN-24 QFN-24 Lead-free QFN-20/28 QFN-20/28 1 260 260 260 260 3 1 3 1 C8051F005-GQ C8051F005-GQ C8051F301-GM ... | Original |
3 pages, |
paste profile qfn 28 land pattern C8051F301 C8051F005-GQ C8051F005 APR-5000 QFN-24 reflow smt pcb ipc standard J-STD-20C C8051F311 hermetic packages PCB land all ic datasheet in one pdf file QFN-24 IPC-SM-782 IPC-SM-782 abstract |
| Abstract: 0xFF. For more information, see " Appendix: JumpStart Program Using the C8051F301". 4.6. , of the page. 4. Example Using the C8051F30 C8051F30 A Silicon Labs C8051F301 (F301) MCU (3 x 3 mm) and an , frequencies of 25 MHz with 3.3 V CMOS on CLK0 and 125 MHz using 3.3 V LVDS on CLK1. C8051F301 I2C , : JUMPSTART PROGRAM USING THE C8051F301 , ) // all other port pins unused // // // Target: C8051F301 // Tool chain: Keil 7.20 ... | Original |
40 pages, |
Si5368 F301 Si5326 AN136 Si5338-EVB Si5338s Si5356 C8051F301 Si5338 AN428 AN428 abstract |
| Abstract: CYGNAL Application Note Pin Sharing Techniques for the C2 Interface Relevant Devices This application note applies to the following devices: C8051F300 C8051F300, C8051F301, C8051F302 C8051F302, and C8051F303 C8051F303. Introduction About the C2 Pins C8051F30x devices include an on-chip Cygnal 2-Wire (C2) Interface for in-system programming, debugging, and boundary scan testing. Two signals are associated with the C2 Interface: C2 Clock (C2CK) and C2 Data (C2D). To preserve package pins, the C2CK and C2D pins also ... | Original |
4 pages, |
communication techniques inc C8051F303 C8051F302 C8051F301 C8051F300 B-100 AN024 C8051F300 abstract |
| Abstract: MCU such as the C8051F301 from Silicon Labs. The C8051F301 is 3x3 mm and contains sufficient Flash memory for this implementation. A strobe input on the C8051F301 is used to cycle through the list of , after the power is cycled. The full reference design has been implemented using the C8051F301, and test , downloaded to the C8051F301 Flash memory space. "AN198 AN198: Integrating SDCC 8051 Tools into the Silicon Labs , development environment. 3. C8051F301 Specifics Since I2C communication is required, the code calls out ... | Original |
44 pages, |
Si599 AN104 AN141 AN198 AN334 C8051F301 Si598 155.520000 Si570 Si571 Si570/Si571/Si598/Si599 AN334 abstract |
| Abstract: C8051F236 C8051F236 25 8KB 1280 C8051F300 C8051F300 25 8KB 256 C8051F301 25 8KB 256 C8051F302 C8051F302 25 8KB 256 ... | Original |
1 pages, |
C8051F015 C8051F001 C8051F002 C8051F005 C8051F006 C8051F007 C8051F010 C8051F011 C8051F012 C8051F000 C8051F016 C8051F017 C8051F018 C8051F019 C8051F000 abstract |
| Abstract: AN124 AN124 P I N S H A R I N G TE C H N I Q U E S F O R T H E C2 I N T E R F A C E Relevant Devices About the C2 Pins When C2 communication is idle, the C2 pins C8051F300 C8051F300, C8051F301, C8051F302 C8051F302, and (C2CK and C2D) function as user pins /RST and C8051F303 C8051F303. P0.7, respectively. The interface master initiates C2 communication by generating an active-low strobe on the C2CK pin. Following this strobe, the interIntroduction face master may safely `borrow' the C2 pins withC8051F30x devices include an on-chip Silicon out ... | Original |
6 pages, |
C8051F303 C8051F302 C8051F301 C8051F300 AN124 AN124 abstract |
| Abstract: Target:C8051F301 to indicate the IDE is connected to the MCU on the Stepper Motor Reference Design ... | Original |
10 pages, |
AN155 AC/ DC adapter universal motor speed control Stepper DC AC Motor speed and soft start soft start ac motor control diagram Stepper "Stepper Motor" Stepper Motors circuit stepper motor application STEPPER MOTOR wiring circuit diagram of stepper datasheet abstract |