C161CS-32R/-L C161JC-32R/-L C161JI-32R/-L D-81541 C161CS/JC/JI C161CS-32RF - Datasheet Archive

 

C161CS-32R/-L C161JC-32R/-L C161JI-32R/-L 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g .

 

U s e r ' s M a n u a l , V 3. 0 , F e b . 2 00 1 C161CS-32R/-L C161CS-32R/-L C161JC-32R/-L C161JC-32R/-L C161JI-32R/-L C161JI-32R/-L 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2001-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. U s er ' s M a n u a l , V 3. 0 , F e b . 2 00 1 C161CS-32R/-L C161CS-32R/-L C161JC-32R/-L C161JC-32R/-L C161JI-32R/-L C161JI-32R/-L 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . C161CS/JC/JI C161CS/JC/JI Revision History: Previous Version: V3.0, 2001-02 2001-01 V2.0 (intermediate version) 1999-05 V1.0 Page Subjects (major changes since last revision)1) all Converted to new company layout, figures have been redrawn 1-2 List of derivatives enhanced 2-21 List of protected bits enhanced 3-4 XBUS areas corrected 4-2 Sleep mode added 5-29 Interrupt source control enhanced 6-9 Frequency table adapted 6-10 Description of PLL base frequency improved 7-2 Bit P4LIN added 7-8 Description of temperature compensation removed 7-14 Description of PORT0 control corrected 7-31 Description of BHE during bus hold corrected 7-33 ODP4 enhanced 7-34 Description of alternate Port 4 functions corrected 7-48 CAN/SDLM interface functions added 9-6 Note reworked 9-22, 9-23 Bits BSWCx and EWENx added to register BUSCONx 9-28 Note corrected 9-31, 9-32 Description of bus arbitration improved 9-33 Description of BHE during bus hold corrected 9-35, 9-36 Section "Connecting Bus Masters" improved 9-37ff XBUS interface description improved 10-6, 10-27 Table enhanced 10-16, 10-33 Figure corrected 10-30 Description of T5M corrected 10-36 CT3 function added to figure 11-13, 11-14 Tables enhanced 13-5 Description of transmission timing improved 13-13 Baudrate tables improved 14-2 Clock path in figure corrected 14-5, 14-6 Time range table and reset source table improved 16-2, 16-3 Description of BSL entry improved 16-7 Baudrate table added C161CS/JC/JI C161CS/JC/JI Revision History: Previous Version: V3.0, 2001-02 (cont'd) 2001-01 V2.0 (intermediate version) 1999-05 V1.0 Page Subjects (major changes since last revision)1) 17-7 Frequency table enhanced 17-14 Description improved (2nd paragraph) 18-4 Sample time control added 19-1 Port 7 added 19-11 Bit timing section rearranged 20-5, 20-9 Description improved 20-10 Description of TXINCE corrected 20-12 Description improved (lower half) 20-25ff Several bit-descriptions improved 20-43 Location of RXCNTB corrected 21-1 Port 9 added 21-3 Clock count n and BRP value corrected 21-4 Figure improved 22-13 Figure corrected 22-18 Software configuration introduced (see notes) 22-19 Table enhanced for 33 MHz 22-22 Code example corrected 22-23 Address space for RSTCON corrected 23-2 SYSCON1 added (3rd paragraph) 23-21 Frequency range table improved 23-22ff Description of security mechanism and SW examples reworked 24-5 Linear stack size corrected 25-3 Offset of RH7 corrected 25-4ff P5DIDIS, RSTCON added, SDLM registers added 1) These changes refer to version V1.0, 1999-05. Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com C161CS/JC/JI C161CS/JC/JI Derivatives Table of Contents Page 1 1.1 1.2 1.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.1.1 2.1.2 2.2 2.3 2.4 2.5 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 High Instruction Bandwidth/Fast Execution . . . . . . . . . . . . . . . . . . . . . 2-3 Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . . . 2-7 The On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 The On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 3 3.1 3.2 3.3 3.4 3.5 3.6 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Internal ROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 The On-Chip XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Protection of the On-Chip Mask ROM . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 4 4.1 4.2 4.3 4.4 4.5 The Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 5 5.1 5.1.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . 5-16 Saving the Status During Interrupt Service . . . . . . . . . . . . . . . . . . . . . . 5-18 Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 6 6.1 6.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 User's Manual I-1 1-1 1-3 1-5 1-8 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Table of Contents Page 6.3 6.4 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Input Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50 8 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.8.1 9.8.2 The External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Single Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 READY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 The XBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 Accessing the On-chip XBUS Peripherals . . . . . . . . . . . . . . . . . . . . . 9-38 External Accesses to XBUS Peripherals . . . . . . . . . . . . . . . . . . . . . . 9-39 10 10.1 10.1.1 10.1.2 10.1.3 10.2 10.2.1 10.2.2 10.2.3 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 GPT1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 GPT1 Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 GPT2 Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 GPT2 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . . . 10-38 11 11.1 11.2 The Asynchronous/Synchronous Serial Interface . . . . . . . . . . . . . . 11-1 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 User's Manual I-2 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Table of Contents Page 11.3 11.4 11.5 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . . . 11-10 ASC0 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 ASC0 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 12 12.1 12.2 12.3 12.4 12.5 12.6 The Async./Synchronous Serial Interface ASC1 . . . . . . . . . . . . . . . Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . ASC1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASC1 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASC1 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 The High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . 13-1 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 SSC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 14 14.1 14.2 The Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Operation of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Reset Source Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 15 The Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 16 16.1 16.2 16.3 16.4 The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering the Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exiting Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Choosing the Baudrate for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17.1 17.2 17.3 17.4 17.5 17.6 The Capture/Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 The CAPCOM Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 CAPCOM Unit Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 Capture/Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 Compare Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 Capture/Compare Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 18 18.1 18.2 18.3 The Analog/Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Mode Selection and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 Conversion Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 A/D Converter Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 User's Manual I-3 12-1 12-5 12-5 12-6 12-6 12-6 12-7 16-1 16-2 16-5 16-5 16-6 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Table of Contents Page 19 19.1 19.2 19.2.1 19.2.2 19.2.3 19.3 19.4 19.5 19.6 19.7 The On-Chip CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Functional Blocks of the CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 General Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 CAN Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 Configuration of the Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 The Message Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 Controlling the CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30 Configuration Examples for Message Objects . . . . . . . . . . . . . . . . . . . 19-34 The Second CAN Module CAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36 The CAN Application Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37 20 20.1 20.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.4 20.5 20.6 20.7 20.8 The Serial Data Link Module (SDLM) . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Frame Format Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 The Structure of the SDLM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 Message Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 In-Frame Response (IFR) Operation . . . . . . . . . . . . . . . . . . . . . . . . 20-11 Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23 SDLM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25 Interrupt Node Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-48 21 21.1 21.2 21.3 21.3.1 21.3.2 21.3.3 21.4 21.5 The IIC Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 IIC Bus Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 The Physical IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 Operating the IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 Operation in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 Operation in Multimaster Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 Operation in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 IIC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 22 22.1 22.2 22.3 22.4 22.4.1 22.4.2 22.5 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 Status After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 Application-Specific Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . 22-9 System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 System Startup Configuration upon an External Reset . . . . . . . . . . 22-13 System Startup Configuration upon a Single-Chip Mode Reset . . . 22-20 System Configuration via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 User's Manual I-4 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Table of Contents Page 23 23.1 23.2 23.3 23.3.1 23.4 23.5 23.6 23.7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 Status of Output Pins During Power Reduction Modes . . . . . . . . . . . 23-8 Slow Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 Programmable Frequency Output Signal . . . . . . . . . . . . . . . . . . . . . . 23-17 Security Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 24 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 24.10 24.11 System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 Procedure Call Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 Table Searching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 Floating Point Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 Peripheral Control and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 Trap/Interrupt Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 Unseparable Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Overriding the DPP Addressing Mechanism . . . . . . . . . . . . . . . . . . . . 24-14 Handling the Internal Code Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 Pits, Traps and Mines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18 25 25.1 25.2 25.3 25.4 25.5 The Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 CPU General Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . 25-2 Special Function Registers Ordered by Name . . . . . . . . . . . . . . . . . . . 25-4 Special Function Registers Ordered by Address . . . . . . . . . . . . . . . . . 25-14 Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24 26 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 27 Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 28 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 User's Manual I-5 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction 1 Introduction The rapidly growing area of embedded control applications is representing one of the most time-critical operating environments for today's microcontrollers. Complex control algorithms have to be processed based on a large number of digital as well as analog input signals, and the appropriate output signals must be generated within a defined maximum response time. Embedded control applications also are often sensitive to board space, power consumption, and overall system cost. Embedded control applications therefore require microcontrollers, which: · · · · offer a high level of system integration eliminate the need for additional peripheral devices and the associated software overhead provide system security and fail-safe mechanisms provide effective means to control (and reduce) the device's power consumption. With the increasing complexity of embedded control applications, a significant increase in CPU performance and peripheral functionality over conventional 8-bit controllers is required from microcontrollers for high-end embedded control systems. In order to achieve this high performance goal Infineon has decided to develop its family of 16-bit CMOS microcontrollers without the constraints of backward compatibility. Of course the architecture of the 16-bit microcontroller family pursues successful hardware and software concepts, which have been established in Infineon's popular 8-bit controller families. User's Manual 1-1 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction About this Manual This manual describes the functionality of a number of 16-bit microcontrollers of the Infineon C166 Family. As these microcontrollers provide a great extent of identical functionality it makes sense to describe a superset of the provided features. For this reason some sections of this manual do not refer to all the C161 derivatives that are offered (e.g. devices without onchip program memory). These sections contain respective notes wherever possible. The descriptions in this manual refer to the following C161 derivatives: · · · · · · C161CS-32RF C161CS-32RF C161CS-LF C161CS-LF C161JC-32RF C161JC-32RF C161JC-LF C161JC-LF C161JI-32RF C161JI-32RF C161JI-LF C161JI-LF 256 KByte ROM, 2 CAN modules No program memory, 2 CAN modules 256 KByte ROM, 1 CAN module, SDLM module (J1850 J1850) No program memory, 1 CAN module, SDLM module (J1850 J1850) 256 KByte ROM, SDLM module (J1850 J1850) No program memory, SDLM module (J1850 J1850) This manual is valid for the versions with on-chip ROM of the mentioned derivatives as well as for the ROMless versions. Of course it refers to all devices of the different available temperature ranges and packages. For simplicity all these various versions are referred to by the term C161CS/JC/JI C161CS/JC/JI throughout this manual. The complete pro-electron conforming designations are listed in the respective data sheets. User's Manual 1-2 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction 1.1 The Members of the 16-bit Microcontroller Family The microcontrollers of the Infineon 16-bit family have been designed to meet the high performance requirements of real-time embedded control applications. The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli (interrupts). Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent. This also minimizes the need for communication via the external bus interface. The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive, industrial control, or data communications. The core of the 16-bit family has been developed with a modular family concept in mind. All family members execute an efficient control-optimized instruction set (additional instructions for members of the second generation). This allows an easy and quick implementation of new family members with different internal memory sizes and technologies, different sets of on-chip peripherals and/or different numbers of IO pins. The XBUS concept opens a straight forward path for the integration of application specific peripheral modules in addition to the standard on-chip peripherals in order to build application specific derivatives. As programs for embedded control applications become larger, high level languages are favored by programmers, because high level language programs are easier to write, to debug and to maintain. The 80C166-type microcontrollers were the first generation of the 16-bit controller family. These devices have established the C166 architecture. The C165-type and C167-type devices are members of the second generation of this family. This second generation is even more powerful due to additional instructions for HLL support, an increased address space, increased internal RAM and highly efficient management of various resources on the external bus. Enhanced derivatives of this second generation provide additional features like additional internal high-speed RAM, an integrated CAN-Module, an on-chip PLL, etc. Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance, while minimizing the part count. These efforts are supported by the so-called XBUS, defined for the Infineon 16-bit microcontrollers (second generation). This XBUS is an internal representation of the external bus interface that opens and simplifies the integration of peripherals by standardizing the required interface. One representative taking advantage of this technology is the integrated CAN module. The C165-type devices are reduced versions of the C167 which provide a smaller package and reduced power consumption at the expense of the A/D converter, the CAPCOM units and the PWM module. User's Manual 1-3 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction The C164-type devices, the C167CS C167CS derivatives, and some of the C161-type devices are further enhanced by a flexible power management and form the third generation of the 16-bit controller family. This power management mechanism provides effective means to control the power that is consumed in a certain state of the controller and thus allows the minimization of the overall power consumption with respect to a given application. A variety of different versions is provided which offer various kinds of on-chip program memory: · · · · Mask-programmable ROM Flash memory OTP memory ROMless with no non-volatile memory at all. Also there are devices with specific functional units. The devices may be offered in different packages, temperature ranges and speed classes. More standard and application-specific derivatives are planned and in development. Note: Not all derivatives will be offered in any temperature range, speed class, package or program memory variation. Information about specific versions and derivatives will be made available with the devices themselves. Contact your Infineon representative for up-to-date material. Note: As the architecture and the basic features (i.e. CPU core and built in peripherals) are identical for most of the currently offered versions of the C161CS/JC/JI C161CS/JC/JI, the descriptions within this manual that refer to the "C161CS/JC/JI C161CS/JC/JI" also apply to the other variations, unless otherwise noted. User's Manual 1-4 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction 1.2 Summary of Basic Features The C161CS/JC/JI C161CS/JC/JI is an improved representative of the Infineon family of full featured 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5/16.5 million instructions per second) with high peripheral functionality and means for power reduction. Several key features contribute to the high performance of the C161CS/JC/JI C161CS/JC/JI (the indicated timings refer to a CPU clock of 25/33 MHz). High Performance 16-bit CPU with Four-Stage Pipeline · · · · · · · 80/60 ns minimum instruction cycle time, with most instructions executed in 1 cycle 400/300 ns multiplication (16-bit × 16-bit), 800/600 ns division (32-bit / 16-bit) Multiple high bandwidth internal data buses Register based design with multiple variable register banks Single cycle context switching support 16 MBytes linear address space for code and data (Von Neumann architecture) System stack cache support with automatic stack overflow/underflow detection Control Oriented Instruction Set with High Efficiency · Bit, byte, and word data types · Flexible and efficient addressing modes for high code density · Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags · Hardware traps to identify exception conditions during runtime · HLL support for semaphore operations and efficient data access Integrated On-Chip Memory · 2 KByte internal RAM for variables, register banks, system stack and code · 8 KByte on-chip high-speed XRAM for variables, user stack and code · 256 KByte on-chip Program ROM (not for ROMless devices) External Bus Interface · · · · Multiplexed or demultiplexed bus configurations Segmentation capability and chip select signal generation 8-bit or 16-bit data bus Bus cycle characteristics selectable for five programmable address areas User's Manual 1-5 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction 16-Priority-Level Interrupt System · 59 interrupt nodes with separate interrupt vectors · 240/180 ns typical interrupt latency (400/300 ns maximum) in case of internal program execution · Fast external interrupts 8-Channel Peripheral Event Controller (PEC) · Interrupt driven single cycle data transfer · Transfer count option (std. CPU interrupt after programmable number of PEC transfers) · Eliminates overhead of saving and restoring system state for interrupt requests Intelligent On-Chip Peripheral Subsystems · 12-channel 10-bit A/D Converter with programmable conversion time (7.76 µs minimum), auto scan modes, channel injection mode · Two 16-channel Capture/Compare Units with 2 independent time bases each, very flexible PWM unit/event recording unit with different operating modes, includes four 16-bit timers/counters, maximum resolution fCPU/8 · Two Multifunctional General Purpose Timer Units GPT1: Three 16-bit timers/counters, maximum resolution fCPU/8 GPT2: Two 16-bit timers/counters, maximum resolution fCPU/4 · Two Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection · High Speed Synchronous Serial Channel programmable data length and shift direction · IIC Bus module with 10-bit addressing and 400 kbit/s · One or two on-chip CAN Bus Modules, Rev. 2.0B active · Serial Data Link Module (SDLM), compliant with J1850 J1850, supporting Class 2 · Real Time Clock · Watchdog Timer with programmable time intervals · Bootstrap Loader for flexible system initialization 93 IO Lines with Individual Bit Addressability · · · · Tri-stated in input mode Selectable input thresholds (not on all pins) Push/pull or open drain output mode Programmable port driver control Different Temperature Ranges · 0 to +70 °C, -40 to +85 °C, -40 to +125 °C User's Manual 1-6 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction Infineon CMOS Process · Low power CMOS technology including power saving Idle and Power Down modes. 128-Pin Plastic Thin Quad Flat Pack (TQFP) Package · P-TQFP, 20 × 20 mm body, 0.5 mm (19.7 mil) lead spacing, surface mount technology Complete Development Support For the development tool support of its microcontrollers, Infineon follows a clear third party concept. Currently around 120 tool suppliers world-wide, ranging from local niche manufacturers to multinational companies with broad product portfolios, offer powerful development tools for the Infineon C500 and C166 microcontroller families, guaranteeing a remarkable variety of price-performance classes as well as early availability of high quality key tools such as compilers, assemblers, simulators, debuggers or in-circuit emulators. Infineon incorporates its strategic tool partners very early into the product development process, making sure embedded system developers get reliable, well-tuned tool solutions, which help them unleash the power of Infineon microcontrollers in the most effective way and with the shortest possible learning curve. The tool environment for the Infineon 16-bit microcontrollers includes the following tools: · · · · · · · · · · · · · · Compilers (C, MODULA2, FORTH) Macro-assemblers, linkers, locators, library managers, format-converters Architectural simulators HLL debuggers Real-time operating systems VHDL chip models In-circuit emulators (based on bondout or standard chips) Plug-in emulators Emulation and clip-over adapters, production sockets Logic analyzer disassemblers Starter kits Evaluation boards with monitor programs Industrial boards (also for CAN, FUZZY, PROFIBUS, FORTH applications) Network driver software (CAN, PROFIBUS) User's Manual 1-7 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Introduction 1.3 Abbreviations The following acronyms and terms are used within this document: ADC Analog Digital Converter ALE Address Latch Enable ALU Arithmetic and Logic Unit ASC Asynchronous/synchronous Serial Controller CAN Controller Area Network (License Bosch) CAPCOM CAPture and COMpare unit CISC Complex Instruction Set Computing CMOS Complementary Metal Oxide Silicon CPU Central Processing Unit EBC External Bus Controller ESFR Extended Special Function Register Flash Non-volatile memory that may be electrically erased GPR General Purpose Register GPT General Purpose Timer unit HLL High Level Language IIC Inter Integrated Circuit (Bus) IO Input/Output OTP One Time Programmable memory PEC Peripheral Event Controller PLA Programmable Logic Array PLL Phase Locked Loop PWM Pulse Width Modulation RAM Random Access Memory RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real Time Clock SDD Slow Down Divider SFR Special Function Register SSC Synchronous Serial Controller XBUS Internal representation of the External Bus XRAM On-chip extension RAM User's Manual 1-8 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview 2 Architectural Overview The architecture of the C161CS/JC/JI C161CS/JC/JI combines the advantages of both RISC and CISC processors in a very well-balanced way. The sum of the features which are combined result in a high performance microcontroller, which is the right choice not only for today's applications, but also for future engineering challenges. The C161CS/JC/JI C161CS/JC/JI not only integrates a powerful CPU core and a set of peripheral units into one chip, but also connects the units in a very efficient way. One of the four buses used concurrently on the C161CS/JC/JI C161CS/JC/JI is the XBUS, an internal representation of the external bus interface. This bus provides a standardized method of integrating application-specific peripherals to produce derivatives of the standard C161CS/JC/JI C161CS/JC/JI. C166-Core 16 Data ROM 256 KByte 32 16 CPU Instr. / Data Data 16 PEC Interrupt Controller 16-Level Priority ASC1 RTC 2.0B act. / Cl.B ADC SSC (USART) (SPI) GPT CCOM2 CCOM1 T2 T7 T0 T3 T8 T1 T4 XBUS Control External Bus Control 16 ASC0 10-Bit 12 Channels EBC Port 0 Peripheral Data Bus 16 Port 2 CAN/SDLM Interrupt Bus On-Chip XBUS (16-Bit Demux) IIC 400 KBd, 2 Ch. Port 4 WDT 16 (USART) Port 6 XTAL External Instr. / Data 8 KByte 8 Internal RAM 2 KByte Osc / PLL XRAM 8 IRAM Dual Port ProgMem T5 BRGen Port 1 16 Port 5 T6 BRGen Port 3 12 15 Port 7 4 8 Port 9 6 MCB04323 MCB04323_1CSR Figure 2-1 User's Manual C161CS/JC/JI C161CS/JC/JI Functional Block Diagram 2-1 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview 2.1 Basic CPU Concepts and Optimizations The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware is provided for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. CPU 16 Internal RAM SP STKOV STKUN MDH MDL R15 Exec. Unit Instr. Ptr. Instr. Reg. Mul/Div-HW Bit-Mask Gen General ROM Purpose ALU 32 4-Stage Pipeline R15 (16-bit) Barrel - Shifter Registers R0 PSW SYSCON Context Ptr. BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Data Page Ptr. Code Seg. Ptr. R0 16 MCB02147 MCB02147 Figure 2-2 CPU Block Diagram To meet the demand for greater performance and flexibility, a number of areas has been optimized in the processor core. Functional blocks in the CPU core are controlled by signals from the instruction decode logic. These are summarized below, and described in detail in the following sections: 1. High Instruction Bandwidth/Fast Execution 2. High Function 8-bit and 16-bit Arithmetic and Logic Unit 3. Extended Bit Processing and Peripheral Control 4. High Performance Branch-, Call-, and Loop Processing 5. Consistent and Optimized Instruction Formats 6. Programmable Multiple Priority Interrupt Structure User's Manual 2-2 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview 2.1.1 High Instruction Bandwidth/Fast Execution Based on the hardware provisions, most of the C161CS/JC/JI C161CS/JC/JI's instructions can be executed in just one machine cycle, which requires 2 CPU clock cycles (2 × 1 / fCPU = 4 TCL). For example, shift and rotate instructions are always processed within one machine cycle, independent of the number of bits to be shifted. Branch-, multiply- and divide instructions normally take more than one machine cycle. These instructions, however, have also been optimized. For example, branch instructions only require an additional machine cycle, when a branch is taken, and most branches taken in loops require no additional machine cycles at all, due to the so-called `Jump Cache'. A 32-bit/16-bit division takes 20 CPU clock cycles, a 16-bit × 16-bit multiplication takes 10 CPU clock cycles. The instruction cycle time has been dramatically reduced through the use of instruction pipelining. This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel. The following four stage pipeline provides the optimum balancing for the CPU core: FETCH: In this stage, an instruction is fetched from the internal ROM or RAM or from the external memory, based on the current IP value. DECODE: In this stage, the previously fetched instruction is decoded and the required operands are fetched. EXECUTE: In this stage, the specified operation is performed on the previously fetched operands. WRITE BACK: In this stage, the result is written to the specified location. If this technique were not used, each instruction would require four machine cycles. This increased performance allows a greater number of tasks and interrupts to be processed. Instruction Decoder Instruction decoding is primarily generated from PLA outputs based on the selected opcode. No microcode is used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs. Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers. Multiple-cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals. User's Manual 2-3 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview High Function 8-bit and 16-bit Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition, for byte operations, signals are provided from bits six and seven of the ALU result to correctly set the condition flags. Multiple precision arithmetic is provided through a `CARRY-IN' signal to the ALU from previously calculated portions of the desired operation. Most internal execution blocks have been optimized to perform operations on either 8-bit or 16-bit quantities. Once the pipeline has been filled, one instruction is completed per machine cycle, except for multiply and divide. An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle. Thus, these operations use two coupled 16-bit registers, MDL and MDH, and require four and nine machine cycles, respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one machine cycle to setup and adjust the operands and the result. Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response. Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations. The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements. A set of consistent flags is automatically updated in the PSW after each arithmetic, logical, shift, or movement operation. These flags allow branching on specific conditions. Support for both signed and unsigned arithmetic is provided through user-specifiable branch tests. These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine. All targets for branch calculations are also computed in the central ALU. A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic shifts are also supported. Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing. These instructions provide efficient control and testing of peripherals while enhancing data manipulation. Unlike other microcontrollers, these instructions provide direct access to two operands in the bit-addressable space without requiring to move them into temporary flags. The same logical instructions available for words and bytes are also supported for bits. This allows the user to compare and modify a control bit for a peripheral in one instruction. Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations. These are also performed in a single machine cycle. In addition, bit field instructions have been provided, which allow the modification of multiple bits from one operand in a single instruction. User's Manual 2-4 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview High Performance Branch-, Call-, and Loop Processing Due to the high percentage of branching in controller applications, branch instructions have been optimized to require one extra machine cycle only when a branch is taken. This is implemented by precalculating the target address while decoding the instruction. To decrease loop execution overhead, three enhancements have been provided: · The first solution provides single cycle branch execution after the first iteration of a loop. Thus, only one machine cycle is lost during the execution of the entire loop. In loops which fall through upon completion, no machine cycles are lost when exiting the loop. No special instructions are required to perform loops, and loops are automatically detected during execution of branch instructions. · The second loop enhancement allows the detection of the end of a table and avoids the use of two compare instructions embedded in loops. One simply places the lowest negative number at the end of the specific table, and specifies branching if neither this value nor the compared value have been found. Otherwise the loop is terminated if either condition has been met. The terminating condition can then be tested. · The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers. Through the use of Compare and Increment or Decrement instructions, the user can make comparisons to any value. This allows loop counters to cover any range. This is particularly advantageous in table searching. Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines. Call instructions push the value of the IP on the system stack, and require the same execution time as branch instructions. Instructions have also been provided to support indirect branch and call instructions. This supports implementation of multiple CASE statement branching in assembler macros and high level languages. User's Manual 2-5 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design, an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing (RISC). These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds. These concepts, however, do not preclude the use of complex instructions, which are required by microcontroller users. The following goals were used to design the instruction set: 1. Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used. Avoid transfer into and out of temporary registers such as accumulators and carry bits. Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines. 2. Avoid complex encoding schemes by placing operands in consistent fields for each instruction. Also avoid complex addressing modes which are not frequently used. This decreases the instruction decode time while also simplifying the development of compilers and assemblers. 3. Provide most frequently used instructions with one-word instruction formats. All other instructions are placed into two-word formats. This allows all instructions to be placed on word boundaries, which alleviates the need for complex alignment hardware. It also has the benefit of increasing the range for relative branching instructions. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional C161CS/JC/JI C161CS/JC/JI instruction set which includes the following instruction classes: · · · · · · · · · · · · Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions Possible operand types are bits, bytes and words. Specific instruction support the conversion (extension) of bytes to words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. User's Manual 2-6 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview 2.1.2 Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a large number of interrupt sources: 1. Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap routines by performing single-cycle interrupt-driven byte or word data transfers between any two locations in segment 0 with an optional increment of either the PEC source or the destination pointer. Just one cycle is `stolen' from the current CPU activity to perform a PEC service. 2. Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at any specified priority. Interrupts may also be grouped, which provides the user with the ability to prevent similar priority tasks from interrupting each other. For each of the possible interrupt sources there is a separate control register, which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. 3. Multiple Register Banks: This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM. A single one-machine-cycle instruction allows to switch register banks from one task to another. 4. Interruptable Multiple Cycle Instructions: Reduced interrupt latency is provided by allowing multiple-cycle instructions (multiply, divide) to be interruptable. With an interrupt response time within a range from just 5 to 10 CPU clock cycles (in case of internal program execution), the C161CS/JC/JI C161CS/JC/JI is capable of reacting very fast on nondeterministic events. Its fast external interrupt inputs are sampled every CPU clock cycle and allow to recognize even very short external signals. The C161CS/JC/JI C161CS/JC/JI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so called `Hardware Traps'. Hardware traps cause an immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except for another higher prioritized trap service being in progress, a hardware trap will interrupt any current program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. User's Manual 2-7 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview 2.2 The On-Chip System Resources The C161CS/JC/JI C161CS/JC/JI controllers provide a number of powerful system resources designed around the CPU. The combination of CPU and these resources results in the high performance of the members of this controller family. Peripheral Event Controller (PEC) and Interrupt Control The Peripheral Event Controller allows to respond to an interrupt request with a single data transfer (word or byte) which only consumes one instruction cycle and does not require to save and restore the machine status. Each interrupt source is prioritized every machine cycle in the interrupt control block. If PEC service is selected, a PEC transfer is started. If CPU interrupt service is requested, the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced. When an interrupt is acknowledged, the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral. The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels. In addition, the PEC uses a dedicated area of RAM which contains the source and destination addresses. The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel. An individual PEC transfer counter is implicitly decremented for each PEC service except forming in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the vector location related to the corresponding source. PEC services are very well suited, for example, to move register contents to/from a memory table. The C161CS/JC/JI C161CS/JC/JI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. Memory Areas The memory space of the C161CS/JC/JI C161CS/JC/JI is configured in a Von Neumann architecture which means that code memory, data memory, registers and IO ports are organized within the same linear address space which covers up to 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. A 2 KByte 16-bit wide internal RAM (IRAM) provides fast access to General Purpose Registers (GPRs), user data (variables) and system stack. The internal RAM may also be used for code. A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data. User's Manual 2-8 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview The CPU has an actual register context consisting of up to 16 wordwide and/or bytewide GPRs at its disposal, which are physically located within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is also located within the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions. An 8 KByte 16-bit wide on-chip XRAM provides fast access to user data (variables), user stacks and code. The on-chip XRAM is realized as an X-Peripheral and appears to the software as an external RAM. Therefore it cannot store register banks and is not bitaddressable. The XRAM allows 16-bit accesses with maximum speed. For Special Function Registers 1024 Bytes of the address space are reserved. The standard Special Function Register area (SFR) uses 512 Bytes, while the Extended Special Function Register area (ESFR) uses the other 512 Bytes. (E)SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused (E)SFR addresses are reserved for future members of the C166 Family with enhanced functionality. An optional on-chip ROM memory (256 KByte) provides for both code and constant data storage. This memory area is connected to the CPU via a 32-bit-wide bus. Thus, an entire double-word instruction can be fetched in just one machine cycle. Program execution from on-chip program memory is the fastest of all possible alternatives. The type of the on-chip program memory depends on the chosen derivative. User's Manual 2-9 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller via its external bus interface. The integrated External Bus Controller (EBC) allows to access external memory and/or peripheral resources in a very flexible way. For up to five address areas the bus mode (multiplexed/demultiplexed), the data bus width (8-bit/16-bit) and even the length of a bus cycle (waitstates, signal delays) can be selected independently. This allows to access a variety of memory and peripheral components directly and with maximum efficiency. If the device does not run in Single Chip Mode, where no external memory is required, the EBC can control external accesses in one of the following external access modes: · · · · 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed The demultiplexed bus modes use PORT1 for addresses and PORT0 for data input/ output. The multiplexed bus modes use PORT0 for both addresses and data input/ output. Port 4 is used for the upper address lines (A16 .) if selected. Important timing characteristics of the external bus interface (waitstates, ALE length and Read/Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and/or peripherals. Access to very slow memories or peripherals is supported via a particular `Ready' function. For applications which require less than 64 KBytes of address space, a non-segmented memory model can be selected, where all locations can be addressed by 16-bits, and thus Port 4 is not needed as an output for the upper address bits (Axx . A16), as is the case when using the segmented memory model. The on-chip XBUS is an internal representation of the external bus and allows to access integrated application-specific peripherals/modules in the same way as external components. It provides a defined interface for these customized peripherals. The on-chip XRAM and the on-chip CAN-Modules are examples for these X-Peripherals. User's Manual 2-10 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview 2.3 The On-Chip Peripheral Blocks The C166 Family clearly separates peripherals from the core. This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core. Each functional block processes data independently and communicates information over common buses. Peripherals are controlled by data written to the respective Special Function Registers (SFRs). These SFRs are located either within the standard SFR area (00'FE00H FE00H . 00'FFFFH) or within the extended ESFR area (00'F000H F000H . 00'F1FFH). These built in peripherals either allow the CPU to interface with the external world, or provide functions on-chip that otherwise were to be added externally in the respective system. The C161CS/JC/JI C161CS/JC/JI generic peripherals are: · · · · · · · Two General Purpose Timer Blocks (GPT1 and GPT2) Two Serial Interfaces (ASC0 and SSC) A Watchdog Timer Two 16-channel Capture/Compare units (CAPCOM1 and CAPCOM2) A 10-bit Analog/Digital Converter A Real Time Clock Nine IO ports with a total of 93 IO lines Each peripheral also contains a set of Special Function Registers (SFRs), which control the functionality of the peripheral and temporarily store intermediate data results. Each peripheral has an associated set of status flags. Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock. Peripheral Interfaces The on-chip peripherals generally have two different types of interfaces, an interface to the CPU and an interface to external hardware. Communication between CPU and peripherals is performed through Special Function Registers (SFRs) and interrupts. The SFRs serve as control/status and data registers for the peripherals. Interrupt requests are generated by the peripherals based on specific events which occur during their operation (e.g. operation complete, error, etc.). For interfacing with external hardware, specific pins of the parallel ports are used, when an input or output function has been selected for a peripheral. During this time, the port pins are controlled by the peripheral (when used as outputs) or by the external hardware which controls the peripheral (when used as inputs). This is called the `alternate (input or output) function' of a port pin, in contrast to its function as a general purpose IO pin. User's Manual 2-11 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock (fCPU). The on-chip oscillator derives the CPU clock from the crystal or from the external clock signal. The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU. During Idle mode the CPU's clock is stopped while the peripherals continue their operation. Peripheral SFRs may be accessed by the CPU once per state. When an SFR is written to by software in the same state where it is also to be modified by the peripheral, the software write operation has priority. Further details on peripheral timing are included in the specific sections about each peripheral. Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space. The following addressing mechanisms allow to access the SFRs: · Indirect or direct addressing with 16-bit (mem) addresses must guarantee that the used data page pointer (DPP0 . DPP3) selects data page 3. · Accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx pointers instead of the data page pointers. · Short 8-bit (reg) addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area. · Short 8-bit (reg) addresses to the extended ESFR area require switching to the 512 Byte extended SFR area. This is done via the EXTension instructions EXTR, EXTP(R), EXTS(R). Byte write operations to word wide SFRs via indirect or direct 16-bit (mem) addressing or byte transfers via the PEC force zeros in the non-addressed byte. Byte write operations via short 8-bit (reg) addressing can only access the low byte of an SFR and force zeros in the high byte. It is therefore recommended, to use the bit field instructions (BFLDL and BFLDH) to write to any number of bits in either byte of an SFR without disturbing the non-addressed byte and the unselected bits. Reserved Bits Some of the bits which are contained in the C161CS/JC/JI C161CS/JC/JI's SFRs are marked as `Reserved'. User software should never write `1's to reserved bits. These bits are currently not implemented and may be used in future products to invoke new functions. In this case, the active state for these functions will be `1', and the inactive state will be `0'. Therefore writing only `0's to reserved locations provides portability of the current software to future devices. After read accesses reserved bits should be ignored or masked out. User's Manual 2-12 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by three serial interfaces with different functionality, two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families. It supports full-duplex asynchronous communication at up to 780/1030 kBaud and half-duplex synchronous communication at up to 3.1/4.1 MBaud @ 25/33 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The ASC1 is another USART which is functionally identical with the ASC0. The ASC1 is accessed via the XBUS (no bit handling) and supports 3 interrupt vectors. The port line handling is slightly different from that of the ASC0. The SSC supports full-duplex synchronous communication at up to 6.25/8.25 Mbaud @ 25/33 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2 . 16-bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data. User's Manual 2-13 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview The On-Chip CAN Modules The integrated CAN Modules (CAN1, CAN2) handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The modules provide Full CAN functionality on up to 15 message objects (up to 30 objects if both modules are connected to the same physical bus). Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 Bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. Each CAN Module uses two pins (configurable, both modules may use the same pair of pins) to interface to a bus transceiver. Note: The C161JC C161JC provides one CAN module, the C161CS C161CS provides two CAN modules. The On-chip IIC Bus Module The integrated IIC Module handles the transmission and reception of frames over the two-line IIC bus in accordance with the IIC Bus specification. The on-chip IIC Module can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or in multi-master mode. Several physical interfaces (port pins) can be established under software control. Data can be transferred at speeds up to 400 kbit/s. Two interrupt nodes dedicated to the IIC module allow efficient interrupt service and also support operation via PEC transfers. Note: The port pins associated with the IIC interfaces feature open drain drivers only, as required by the IIC specification. User's Manual 2-14 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview Serial Data Link Module (SDLM) The Serial Data Link Module (SDLM) provides serial communication via a J1850 J1850 type multiplexed serial bus via an external J1850 J1850 bus transceiver. The module conforms to the SAE Class B J1850 J1850 specification for variable pulse width modulation (VPW). The SDLM is integrated as an on-chip peripheral and is connected to the CPU via the XBUS. General SDLM Features: · Compliant to the SAE Class B J1850 J1850 specification (VPW), Class 2 protocol fully supported · Variable Pulse Width (VPW) operation at 10.4 kBaud, High Speed 4X operation at 41.6 kBaud · Programmable Normalization Bit, programmable delay for transceiver interface · Digital Noise Filter · Power Down mode with automatic wakeup support upon bus activity · Single Byte Header and Consolidated Header supported · CRC generation and checking · Receive and transmit Block Mode Data Link Operation Features: · 11 Byte Transmit Buffer and double buffered 11 Byte receive buffer (optional overwrite enable) · Support for In Frame Response (IFR) types 1, 2 and 3 · Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode · Advanced Interrupt Handling with 8 separately enabled sources · Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers · User configurable clock divider · Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress) User's Manual 2-15 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview Parallel Ports The C161CS/JC/JI C161CS/JC/JI provides up to 93 IO lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17 A23/19/17 . A16 in systems where segmentation is used to access more than 64 KBytes of memory. Port 6 provides the optional bus arbitration signals (BREQ, HLDA, HOLD) and the chip select signals CS4 . CS0. Port 2 accepts the fast external interrupt inputs and provides inputs/outputs for the CAPCOM1 unit. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE, and the system clock output (CLKOUT/ FOUT). Port 5 is used for timer control signals and for the analog inputs to the A/D Converter. Port 7 provides inputs/outputs for the CAPCOM2 unit (more on P1H). Port 9 provides the IIC Bus lines. Four pins of PORT1 may also be used as inputs/outputs for the CAPCOM2 unit. All port lines that are not used for these alternate functions may be used as general purpose IO lines. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset. The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided by 2, 4, 128, or 256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 21 µs and 671 ms can be monitored @ 25 MHz (16 µs and 335 ms @ 33 MHz). The default Watchdog Timer interval after reset is 5.2/4.0 ms (@ 25/33 MHz). User's Manual 2-16 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview A/D Converter For analog signal measurement, a 10-bit A/D converter with 12 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less analog input channels, the remaining channel inputs can be used as digital input (or IO) port pins. The A/D converter of the C161CS/JC/JI C161CS/JC/JI supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. Real Time Clock The C161CS/JC/JI C161CS/JC/JI contains a real time clock (RTC) which serves for different purposes: · System clock to determine the current time and date, even during idle mode and power down mode (optionally) · Cyclic time based interrupt, e.g. to provide a system time tick independent of the CPU frequency without loading the general purpose timers, or to wake up regularly from idle mode. · 48-bit timer for long term measurements, the maximum usable timespan is more than 100 years. The RTC module consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers RTCH and RTCL). Both timers count up. User's Manual 2-17 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview General Purpose Timer (GPT) Unit The GPT units represent a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The five 16-bit timers are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each timer can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter Mode and Incremental Interface Mode (GPT1 timers). In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events (via TxIN). Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the `gate' level on its external input pin TxIN. In Incremental Interface Mode the GPT1 timers can be directly connected to the incremental position sensor signals A and B via the respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal (TxEUD) to facilitate e.g. position tracking. The core timers T3 and T6 have output toggle latches (TxOTL) which change their state on each timer over-flow/underflow. The state of these latches may be output on port pins (TxOUT) or may be used internally to concatenate the core timers with the respective auxiliary timers resulting in 32/33-bit timers/counters for measuring long time periods with high resolution. Various reload or capture functions can be selected to reload timers or capture a timer's contents triggered by an external signal or a selectable transition of toggle latch TxOTL. The maximum resolution of the timers in module GPT1 is 8 CPU clock cycles (= 16 TCL). With their maximum resolution of 4 CPU clock cycles (= 8 TCL) the GPT2 timers provide precise event control and time measurement. User's Manual 2-18 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview Capture/Compare (CAPCOM) Units The two CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 8 CPU clock cycles. The CAPCOM units are typically used to handle high speed IO tasks such as pulse and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal CPU clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/ compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Eight register of each unit have one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. 2.4 Power Management Features The known basic power reduction modes (Idle and Power Down) are enhanced by a number of additional power management features (see below). These features can be combined to reduce the controller's power consumption to the respective application's possible minimum. · Flexible clock generation · Flexible peripheral management (peripherals can be enabled/disabled separately or in groups) · Periodic wakeup from Idle mode via RTC timer User's Manual 2-19 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview The listed features provide effective means to realize standby conditions for the system with an optimum balance between power reduction (i.e. standby time) and peripheral operation (i.e. system functionality). Flexible Clock Generation The flexible clock generation system combines a variety of improved mechanisms (partly user controllable) to provide the C161CS/JC/JI C161CS/JC/JI modules with clock signals. This is especially important in power sensitive modes like standby operation. The power optimized oscillator generally reduces the amount of power which is consumed in order to generate the clock signal within the C161CS/JC/JI C161CS/JC/JI. The clock system efficiently controls the amount of power which is consumed in order to distribute the clock signal within the C161CS/JC/JI C161CS/JC/JI. Slowdown operation is achieved by dividing the oscillator clock by a programmable factor (1 . 32) resulting in a low frequency device operation which significantly reduces the overall power consumption. Flexible Peripheral Management The flexible peripheral management provides a mechanism to enable and disable each peripheral module separately. In each situation (e.g. several system operating modes, standby, etc.) only those peripherals may be kept running which are required for the respective functionality. All others can be switched off. It also allows the operation control of whole groups of peripherals including the power required for generating and distributing their clock input signal. Other peripherals may remain active, e.g. in order to maintain communication channels. The registers of separately disabled peripherals (not within a disabled group) can still be accessed. Periodic Wakeup from Idle Mode Periodic wakeup from Idle mode combines the drastically reduced power consumption in Idle mode (in conjunction with the additional power management features) with a high level of system availability. External signals and events can be scanned (at a lower rate) by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time. This greatly reduces the system's average power consumption. User's Manual 2-20 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview 2.5 Protected Bits The C161CS/JC/JI C161CS/JC/JI provides a special mechanism to protect bits which can be modified by the on-chip hardware from being changed unintentionally by software accesses to related bits (see also Chapter 4). The following bits are protected. Table 2-1 C161CS/JC/JI C161CS/JC/JI Protected Bits Register Bit Name Notes T2IC, T3IC, T4IC T2IR, T3IR, T4IR GPT1 timer interrupt request flags T5IC, T6IC T5IR, T6IR GPT2 timer interrupt request flags CRIC CRIR GPT2 CAPREL interrupt request flag T3CON, T6CON T3OTL, T6OTL GPTx timer output toggle latches T0IC, T1IC T0IR, T1IR CAPCOM1 timer interrupt request flags T7IC, T8IC T7IR, T8IR CAPCOM2 timer interrupt request flags S0TIC, S0TBIC S0TIR, S0TBIR ASC0 transmit(buffer) interrupt request flags S0RIC, S0EIC S0RIR, S0EIR ASC0 receive/error interrupt request flags S0CON S0REN ASC0 receiver enable flag SSCTIC, SSCRIC SSCTIR, SSCRIR SSC transmit/receive interrupt request flags SSCEIC SSCEIR SSC error interrupt request flag SSCCON SSCBSY SSC busy flag SSCCON SSCBE, SSCPE SSC error flags SSCCON SSCRE, SSCTE SSC error flags ADCIC, ADEIC ADCIR, ADEIR ADC end-of-conv./overrun intr. request flag ADCON ADST, ADCRQ ADC start flag/injection request flag CC31IC CC31IC . CC16IC CC16IC CC31IR CC31IR . CC16IR CC16IR CAPCOM2 interrupt request flags CC15IC CC15IC . CC0IC CC15IR CC15IR . CC0IR CAPCOM1 interrupt request flags TFR TFR.15,14,13 Class A trap flags TFR TFR.7,3,2,1,0 Class B trap flags P2 P2.15 . P2.8 All bits of Port 2 P7 P7.7 . P7.4 All bits of Port 7 XP7IC . XP0IC XP7IR . XP0IC X-Peripheral interrupt request flags User's Manual 2-21 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Architectural Overview Table 2-1 C161CS/JC/JI C161CS/JC/JI Protected Bits (cont'd) Register Bit Name Notes ISNC RTCIR, PLLIR Interrupt node sharing request flags FOCON FOTL, FOCNT.5 . 0 Frequency output toggle latch and counter = 98 protected bits. User's Manual 2-22 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Memory Organization 3 Memory Organization The memory space of the C161CS/JC/JI C161CS/JC/JI is configured in a "Von Neumann" architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal ROM/Flash/OTP (where integrated), internal RAM, the internal Special Function Register Areas (SFRs and ESFRs), the address areas for integrated XBUS peripherals and external memory are mapped into one common address space. The C161CS/JC/JI C161CS/JC/JI provides a total addressable memory space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each, and each segment is again subdivided into four data pages of 16 KBytes each (see Figure 3-1). FF'FFFF 255 H 255.2 254.129 128 01'FFFF 80'0000 127 H Begin of Prog. Memory above 32 KB 62.12 H 0A'FFFF 11 H 10 01'8000 8 01'0000 08'0000 7 5 4 2 02'FFFF 01'FFFF 1 0 00'0000 H Data Page 3 H 6 3 H Alternate ROM Area 9 Segment 0 16 MByte External Addressing Capability 40'0000 63 Segment 1 126.65 64 H Data Page 2 Internal ROM Area H H 00'0000 H Total Address Space 16 MByte, Segments 255.0 H Segments 1 and 0 64 + 64 Kbyte MCA04325 MCA04325 Figure 3-1 User's Manual Address Space Overview 3-1 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Memory Organization Most internal memory areas are mapped into segment 0, the system segment. The upper 4 KByte of segment 0 (00'F000H F000H . 00'FFFFH) hold the Internal RAM and Special Function Register Areas (SFR and ESFR). The lower 32 KByte of segment 0 (00'0000H 0000H . 00'7FFFH) may be occupied by a part of the on-chip ROM/Flash/OTP memory and is called the Internal ROM area. This ROM area can be remapped to segment 1 (01'0000H 0000H . 01'7FFFH), to enable external memory access in the lower half of segment 0, or the internal ROM may be disabled at all. Code and data may be stored in any part of the internal memory areas, except for the SFR blocks, which may be used for control/data, but not for instructions. Note: Accesses to the internal ROM area on ROMless devices will produce unpredictable results. Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address. Double words (code only) are stored in ascending memory locations as two subsequent words. Single bits are always stored in the specified bit position at a word address. Bit position 0 is the least significant bit of the byte at an even byte address, and bit position 15 is the most significant bit of the byte at the next odd byte address. Bit addressing is supported for a part of the Special Function Registers, a part of the internal RAM and for the General Purpose Registers. xxxx6 H 15 14 Bits 8 xxxx5 H 7 6 Bits 0 xxxx4 H Byte xxxx3 H Byte xxxx2 H Word (High Byte) xxxx1 H Word (Low Byte) xxxx0 H xxxxF H MCD01996 MCD01996 Figure 3-2 Storage of Words, Bytes, and Bits in a Byte Organized Memory Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area. User's Manual 3-2 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Memory Organization 3.1 Internal ROM Area The C161CS/JC/JI C161CS/JC/JI may reserve an address area of variable size (depending on the version) for on-chip mask-programmable ROM/Flash/OTP memory (organized as X × 32). The lower 32 KByte of this on-chip memory block are referred to as "Internal ROM Area". Internal ROM accesses are globally enabled or disabled via bit ROMEN in register SYSCON. This bit is set during reset according to the level on pin EA, or may be altered via software. If enabled, the internal ROM area occupies the lower 32 KByte of either segment 0 or segment 1 (alternate ROM area). This mapping is controlled by bit ROMS1 in register SYSCON. Note: The size of the internal ROM area is independent of the size of the actual implemented Program Memory. Also devices with less than 32 KByte of Program Memory or with no Program Memory at all will have this 32 KByte area occupied, if the Program Memory is enabled. Devices with a larger Program Memory provide the mapping option only for the internal ROM area. Devices with a Program Memory size above 32 KByte expand the ROM area from the middle of segment 1, i.e. starting at address 01'8000H 8000H. The internal Program Memory can be used for both code (instructions) and data (constants, tables, etc.) storage. Code fetches are always made on even byte addresses. The highest possible code storage location in the internal Program Memory is either xx'xxFEH for single word instructions, or xx'xxFCH for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossing from internal Program Memory to external memory is not supported and causes erroneous results. Any word and byte data read accesses may use the indirect or long 16-bit addressing modes. There is no short addressing mode for internal ROM operands. Any word data access is made to an even byte address. The highest possible word data storage location in the internal ROM is xx'xxFEH. For PEC data transfers the internal Program Memory can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The internal Program Memory is not provided for single bit storage, and therefore it is not bit addressable. Note: The `x' in the locations above depend on the available Program Memory and on the mapping. The internal ROM may be enabled, disabled or mapped into segment 0 or segment 1 under software control. Chapter 24 shows how to do this and reminds of the precautions that must be taken in order to prevent the system from crashing. User's Manual 3-3 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Memory Organization 3.2 Internal RAM and SFR Area The RAM/SFR area is located within data page 3 and provides access to the internal RAM (IRAM, organized as X × 16) and to two 512 Byte blocks of Special Function Registers (SFRs). The C161CS/JC/JI C161CS/JC/JI provides 2 KByte of IRAM. 00'FFFF 00'FFFF H SFR Area IRAM/SFR Data Page 3 00'F000 H H X-Peripherals IRAM 00'E000 H 00'F600 H Reserved XRAM 00'F200 H ESFR Area Data Page 2 00'C000 H CAN1 Reserved IIC/ASC1 Reserved SDLM 00'F000 H 00'EF00 H 00'EE00 H 00'ED00 H 00'EC00 H 00'EB00 H Ext. Memory Reserved 00'8000 00'E000 H H Note: New XBUS peripherals will be preferably placed into the reserved areas, which now access external memory (bus cycles executed). MCA04823 MCA04823 Figure 3-3 User's Manual System Memory Map 3-4 V3.0, 2001-02 C161CS/JC/JI C161CS/JC/JI Derivatives Memory Organization Note: The upper 256 Bytes of SFR area, ESFR area and internal RAM are bitaddressable (see shaded blocks in Figure 3-3). Code accesses are always made on even byte addresses. The highest possible code storage location in the internal RAM is either 00'FDFEH for single word instructions or 00'FDFCH for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossing from internal RAM to the SFR area is not supported and causes erroneous results. Any word and byte data in the internal RAM can be accessed via indirect or long 16-bit addressing modes, if the selected DPP register points to data page 3. Any word data access is made on an even byte address. The highest possible word data storage location in the internal RAM is 00'FDFEH. For PEC data transfers, the internal RAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The upper 256 Byte of the internal RAM (00'FD00H FD00H through 00'FDFFH) and the GPRs of the current bank are provided for single bit storage, and thus they are bitaddressable. System Stack The system stack may be defined within the internal RAM. The size of the system stack is controlled by bitfield STKSZ in register SYSCON (see Table 3-1). Table 3-1 System Stack Size Encoding Stack Size (words) Internal RAM Addresses (words) 000B 256 00'FBFEH . 00'FA00H FA00H (Default after Reset) 001B 128 00'FBFEH . 00'FB00H FB00H 010B 64 00'FBFEH . 00'FB80H FB80H 011B 32