GR-1248 1-800-2-BT-APPS L823001 CRC-10 74ABT16245 74ABT16244 - Datasheet Archive

 

This document contains information on new a product.The parametric information, although not fully characterized, is the result

 

Preliminary Information This document contains information on new a product.The parametric information, although not fully characterized, is the result of testing initial devices. Bt8230 L O C A L B U S ATM Segmentation and Reassembly Controller-ATM SAR The highly integrated CMOS Bt8230 ATM Segmentation and Reassembly Controller Chip (SRC) combines unique features making it a state-of-the-art ATM controller. At introduction, the Bt8230 will support all requirements contained in ATM Forum UNI 3.1 and the related ANSI and ITU standards. The device's architecture allows the new traffic management algorithms for Available Bit Rate (ABR) service, to be defined in UNI 4.0, to be supported in a future pin-compatible version. The Bt8230 combines a PCI bus interface, segmentation and reassembly controllers, local memory controller, DMA coprocessor, and an automatic scheduling algorithm that controls and transmits each segmentation channel to achieve an independent bit rate of up to 200 Mbit/s per channel. The Bt8230 is especially suited for today's terminal adapters, routers/hubs, and other Wide Area Network (WAN) applications. The device supports thousands of open connections simultaneously with robust Operation and Maintenance (OAM), signaling, and Interim Local Management Interface (ILMI) features. Other key features include support for random Virtual Path Indicator/Virtual Channel Indicator (VPI/VCI) assignment, interleaved AAL5, AAL3/4 support, and termination of signaling and ILMI into local memory to maintain management connections independent of the host. The Bt8230 architecture allows for several different implementation options. Through these options, users can balance the needs of their systems between cost, function. In stand-alone mode, the Bt8230 is capable of full line rate performance. The host driver software increases in local processor mode, the host performance can be increased by performing more control functions locally. In UTOPIA slave mode, the Bt8230 can be connected directly to an ATM backplane for applications exceeding 155 Mbit/s. An evaluation system for the Bt8230 is available. It provides a working reference design, an example software driver, and facilities for generating and terminating ATM traffic. Distinguishing Features Functional Block Diagram · 32 Timer Counters 32 PCI Bus P C I D M A Reassembler Brooktree ® Control/ Status Cell FIFO Segmenter Scheduler · · · · · · · · · · · · · · Local Processor Bus Memory Arbiter · · · · · Bt8230 Simultaneous ATM and SMDS SAR ATM Forum UNI 3.1 compliant Upgradable to UNI 4.0 AAL0, AAL3/4, and AAL5 SAR Formats AAL3/4 and AAL5 CPCS fields and performs all checks Performance monitoring per GR-1248 GR-1248 and ITU I.610 Supports 16384 active Virtual Circuit Channels (VCCs) Robust per-VCC statistics supports SNMP MIB requirements 200 Mbit/s duplex throughput UTOPIA master, UTOPIA slave, or Bt8222-compatible ATM PHY interface PCI host interface (master and slave mode), Revision 2.0 Automatic scheduling algorithm operates individually on each channel Host or local segmentation and reassembly VBR, UBR traffic types Scatter/gather DMA to host memory Optional local processor for signaling, OAM, and ILMI management functions Zero- or one-wait-state local memory Boundary scan to facilitate boardlevel testing Low-power CMOS process in a 208-pin PQFP Complete working reference design, software, and documentation package available Applications UTOPIA or Bt8222 ATM Interface Rx/Tx · · · · ATM interface for routers and hubs ATM/PCI interface cards Test and WAN equipment Service Access Multiplexors Brooktree Corporation · 9868 Scranton Road · San Diego, CA 92121-3707 · 619-452-7580 1-800-2-BT-APPS 1-800-2-BT-APPS · FAX: 619-452-1249 · Internet: apps@brooktree.com · L823001 L823001 Rev. D Ordering Information Model Number Package Ambient Temperature Bt8230KPF 208-Pin Plastic Quad Flat Pack (PQFP) 0°C to 70° C Copyright © 1995 Brooktree Corporation. All rights reserved. Print date: 08/18/95 Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Brooktree Corporation. Brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Brooktree product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from such improper use or sale. Brooktree is a registered trademark of Brooktree Corporation. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. Specifications are subject to change without notice. PRINTED IN THE UNITED STATES OF AMERICA Table of Contents 1.0 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 DMA Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Segmentation Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 Reassembly Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.5 Local Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.6 Local Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.7 ATM Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 3 3 4 4 4 1.2 Logic Diagram and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 DMA Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 DMA Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 DMA Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 Misaligned Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Memory Bank Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Local Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Interface Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Bus Cycle Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3.1 Single Read Cycle, Zero Wait State Example . . . . . . . . . . . . . . . . . . . . . 2.4.3.2 Single Read Cycle, Wait States Inserted By Memory Arbitration . . . . . . 2.4.3.3 Double Read Burst With Processor Wait States . . . . . . . . . . . . . . . . . . 2.4.3.4 Single Write With One-Wait-State Memory . . . . . . . . . . . . . . . . . . . . . . 2.4.3.5 Quad Write Burst, No Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 i80960CA/CF Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.5 i80960Jx Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.6 Stand-Alone Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.7 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.8 Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.9 Bt8230 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brooktree ® 19 20 21 22 23 24 25 26 27 28 28 32 32 32 iii Table of Contents Bt8230 2.5 Segmentation Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5.1 Memory Set Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Initialization of Buffer Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Initializing Segmentation VCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Segmentation Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.5 Adding Segmentation Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.6 Descriptor Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.7 Rate-Controlled Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.8 Available Bit-Rate Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.9 Segmentation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.10 OAM, ILMI, and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.11 Idle Cell Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.12 ATM Header Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.13 AAL3/4 SAR-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.14 AAL5 SAR-PDU Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.15 AAL0 SAR-PDU Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.16 CRC-10 CRC-10 Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.17 Transmit Cell FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 38 40 42 42 44 45 47 47 47 48 49 49 50 51 51 51 2.6 Reassembly Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.6.1 Local Memory Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Hash Table/Bucket Format and Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3 Reassembly VCC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4 Scatter Method to Host Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.1 Linked Cell Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.2 Host Free Buffer Queue, HFR_BUFF_QUE . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.3 Status Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.5 Structure Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.6 Cell Buffer and Status Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7 Status Queue Full Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.8 Cell Buffer Queue Empty Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.9 Firewall Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.10 Scatter Method to Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.11 AAL5 CPCS Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.12 AAL3/4 CPCS Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.13 AAL0 Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.14 OAM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.14.1 PM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.15 Message Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.16 Credit Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.17 52-Octet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.18 Receive Cell FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 58 62 63 63 64 65 67 68 68 69 69 69 70 71 73 74 74 74 75 75 75 2.7 ATM Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.7.1 ATM Physical Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.7.2 ATM Physical I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.7.3 Bt8222 Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 iv Brooktree ® Bt8230 Table of Contents 2.7.4 UTOPIA Mode Cell Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.5 UTOPIA Mode Octet Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.6 Slave UTOPIA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.7 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.8 Receive Cell Synchronization Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.9 Transmit Cell Synchronization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 82 83 84 85 85 2.8 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.8.1 Unsupported PCI Bus Interface Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 PCI Bus Master Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.3 Burst FIFO Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.4 PCI Bus Slave Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.5 PCI Host Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.6 PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 87 89 89 89 89 3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.3.1 0x00-Real Time Clock Register (CLOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.3.2 0x04-Alarm Register 1 (ALARM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.3.3 0x0C-System Status Register (SYS_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.3.4 0x14-Configuration Register 0 (CONFIG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.4.1 0x20-Segmentation Control Register (SEG_CTRL) . . . . . . . . . . . . . . . . . . . . . . . 96 3.4.2 0x24-Segmentation Status Queue Base Register (SEG_SBASE) . . . . . . . . . . . . . 97 3.4.3 0x28-Segmentation Virtual Connection Base Register (SEG_VBASE) . . . . . . . . . 98 3.4.4 0x2C-Segmentation Status Position Register (SEG_ST) . . . . . . . . . . . . . . . . . . . 98 3.4.5 0x30-Segmentation Available Bit Rate Register (SEG_ABR) . . . . . . . . . . . . . . . . 99 3.4.6 0x34-Segmentation Free Buffer Descriptor Register (SEG_FR_BD) . . . . . . . . . . . 99 3.4.7 0x38-Segmentation Host Transmit Base Register (SEG_HRBASE) . . . . . . . . . . . 99 3.4.8 0x3C-Segmentation Local Transmit Base Register (SEG_LRBASE) . . . . . . . . . . 100 3.4.9 0x40-Segmentation Host Transmit Register (SEG_HXMIT) . . . . . . . . . . . . . . . . 100 3.4.10 0x44-Segmentation Local Transmit Register (SEG_LXMIT) . . . . . . . . . . . . . . . 101 3.5.1 0x70-Reassembly Control Register (RSM_CTRL) . . . . . . . . . . . . . . . . . . . . . . . 101 3.5.2 0x74-Reassembly Status Queue Base Register (RSM_SBASE) . . . . . . . . . . . . . 104 3.5.3 0x78-Reassembly Free Buffer Queue Base Register (RSM_FBASE). . . . . . . . . . 104 3.5.4 0x7C-Reassembly Hash Table Base Register (RSM_HBASE) . . . . . . . . . . . . . . . 104 3.5.5 0x80-Reassembly Time-out Register (RSM_TO) . . . . . . . . . . . . . . . . . . . . . . . . 105 3.5.6 0x84-Reassembly Firewall Register (RSM_FW) . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.5.7 0x88-Reassembly/Segmentation Queue Register (RS_QBASE) . . . . . . . . . . . . . 106 3.6.8 0xC0-Host Interrupt Status Register (HOST_ISTAT0) . . . . . . . . . . . . . . . . . . . . 106 3.6.9 0xCC-Host Interrupt Mask Register (HOST_IMASK0) . . . . . . . . . . . . . . . . . . . . 108 3.6.10 0xD8-Host Mailbox Register (HOST_MBOX) . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.7.11 0xE0-Local Processor Interrupt Status Register (LP_ISTAT0) . . . . . . . . . . . . . 110 3.7.12 0xEC-Local Processor Interrupt Mask Register (LP_IMASK0) . . . . . . . . . . . . . 112 3.7.13 0xF8-Local Processor Mailbox Register (LP_MBOX) . . . . . . . . . . . . . . . . . . . . 113 Brooktree ® v Table of Contents Bt8230 4.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 ATM Physical Interface Timing-UTOPIA and Slave UTOPIA . . . . . . . . . . . . . . . . 4.1.3 ATM Physical Interface Timing-Bt8222 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 Bt8230 Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 PHY Interface Timing (Stand-Alone Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 Local Processor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 119 122 124 126 130 131 4.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.4 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Relevant ITU and ANSI Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 vi Brooktree ® Bt8230 List of Figures List of Figures Figure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 2-17. Figure 2-18. Figure 2-19. Figure 2-20. Figure 2-21. Figure 2-22. Figure 2-23. Figure 2-24. Figure 2-25. Figure 2-26. Figure 2-27. Figure 2-28. Figure 2-29. Figure 2-30. Figure 2-31. Figure 2-32. Figure 2-33. Brooktree ® Bt8230 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Bt8230 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Bt8230 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Little Endian Aligned Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Little Endian Misaligned Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Big Endian Aligned Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Big Endian Misaligned Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bt8230 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 0.5 MB SRAM Bank Utilizing by_8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 MB SRAM Bank Utilizing by_16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bt8230-Local Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Local Processor Single Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Local Processor Single Read Cycle with Arbitration Wait States . . . . . . . . . . . . . . . . . . . 23 Local Processor Double Read with Wait States Inserted . . . . . . . . . . . . . . . . . . . . . . . . . 24 Local Processor Single Write with One Wait State by_16 SRAM . . . . . . . . . . . . . . . . . . . 25 Local Processor Quad Write, No Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 i960CA/CF to the Bt8230 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Bt8230 to the 8222 Microprocessor Interface (Stand-Alone Operation). . . . . . . . . . . . . . 30 Bt8230/PHY Functional Timing with Inserted Wait States . . . . . . . . . . . . . . . . . . . . . . . . 31 Bt8230/Bt8222 Read/Write Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bt8230 Transmit Hardware Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bt8230 Transmit Software Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Segmentation Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Bt8230 Segmentation Linked Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Bt8230 Receive Hardware Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bt8230 Receive Software Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bt8230 Reassembly Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Bt8230 Register and Memory Structure to Perform Intelligent Scatter Algorithm . . . . . . 56 Linked Cell Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Free Buffer Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Status Queue Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Receive Timing in Bt8222 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Transmit Timing in Bt8222 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Receive Timing in UTOPIA Mode with Cell Handshake. . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Transmit Timing in UTOPIA Mode with Cell Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . 81 vii List of Figures Figure 2-34. Figure 2-35. Figure 2-36. Figure 2-37. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. Figure 4-18. viii Bt8230 Receive Timing in UTOPIA Mode with Octet Handshake . . . . . . . . . . . . . . . . . . . . . . . . . 82 Transmit Timing in UTOPIA Mode with Octet Handshake. . . . . . . . . . . . . . . . . . . . . . . . . 83 Receive Timing in Slave UTOPIA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Transmit Timing in Slave UTOPIA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PCI Bus Input Timing Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 PCI Bus Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 UTOPIA and Slave UTOPIA Input Timing Measurement Conditions . . . . . . . . . . . . . . . . 121 UTOPIA and Slave UTOPIA Output Timing Measurement Conditions. . . . . . . . . . . . . . . 121 Bt8222 Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Bt8222 Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Input System Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Output System Clock Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Bt8230 Memory Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Bt8230 Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Synchronous PHY Interface Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Synchronous PHY Interface Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Synchronous Local Processor Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Synchronous Local Processor Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Local Processor Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Local Processor Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 208-Pin Plastic Quad Flat Pack (PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Bt8230 Pinout Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Brooktree ® Bt8230 List of Tables List of Tables Table 1-1. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 2-15. Table 2-16. Table 2-17. Table 2-18. Table 2-19. Table 2-20. Table 2-21. Table 2-22. Table 2-23. Table 2-24. Table 2-25. Table 2-26. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 4-1. Brooktree ® Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory Bank Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Processor Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Stand-Alone Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bt8230 Segmentation Local Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Buffer Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Buffer Descriptor Format Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Segmentation VCC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Segmentation VCC Structure Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Transmit Ring Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Status Queue Entry Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Status Queue Entry Format Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PM Table Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Bt8230 Header Source Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AAL3/4 SAR-PDU Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Bt8230 Reassembly Local Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Bt8230 Hash Table Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Hash Bucket Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Hash Bucket Format Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Reassembly VCC Table Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Reassembly VCC Table Format Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Status Queue Entry Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Local Resources Used in Place of Host Memory Resources . . . . . . . . . . . . . . . . . . . . . . 70 ATM Physical Interface Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Bt8230 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 UTOPIA Mode Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Slave UTOPIA Mode Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Bt8230 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Bt8230 Register Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Segmentation MAXx Size Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TAB_SIZE Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Reassembly Buffer Size Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PCI Configuration Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 PCI Configuration Registers Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 PCI Bus Interface Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ix List of Tables Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 4-14. Table 4-15. x Bt8230 UTOPIA Interface Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave UTOPIA Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bt8222 Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Organization Loading Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Memory Output Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Timing Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bt8230 Memory Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Interface Timing (PROCMODE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Processor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Processor Memory Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 120 122 124 126 126 127 128 130 131 133 136 137 140 Brooktree ® 1.0 Product Description 1.1 Introduction The highly integrated CMOS Bt8230 ATM Segmentation and Reassembly Controller Chip (SRC) combines unique features making it a state-of-the-art ATM controller. At introduction, the Bt8230 will support all requirements contained in ATM Forum UNI 3.1 and the related ANSI and ITU standards. The architecture of the device is such that the new traffic management algorithms for Available Bit Rate (ABR) service to be defined in UNI 4.0 can be supported in a future version. The Bt8230 combines a Peripheral Component Interconnect (PCI) bus interface, segmentation and reassembly controllers, local memory controller, DMA coprocessor, and a proprietary scheduling algorithm that enables each segmentation channel to achieve an independent bit rate of up to 200 Mbit/s per channel. The Bt8230 is especially suited for today's terminal adapters, routers/hubs, and other Wide Area Network (WAN) applications. The device supports thousands of open connections simultaneously with robust Operation and Maintenance (OAM), signaling, and Interim Local Management Interface (ILMI) features. Other key features include support for random Virtual Path Indicator/ Virtual Channel Indicator (VPI/VCI) assignment, interleaved AAL5 and AAL3/4 support, and termination of signaling and ILMI into local memory to maintain management connections independent of the host. Incorporated into the Bt8230 is a simplified traffic priority management scheme that allows each connection to be individually monitored. Both segmentation and reassembly processes deal with host buffers as pipelines of information. Partial packets may be added to the transmit stream or released as they are received for additional processing by the host. The host buffer structures resemble those found in common operating systems so the data can be processed by the host without the need to physically copy the information to another memory location. A send immediate mode supports low-latency connections. The Bt8230 transmit scheduling algorithm supports the currently defined "leaky buckets" and will be upgraded to support the ABR algorithms as defined in UNI 4.0. The optional local processor architecture provides the flexibility for system designers and programmers to track the rapidly changing ATM standards. OAM, ILMI, and signaling can all be ported to this processor to off-load the host system. At the same time, a processor-less system is a cost-effective option with the Bt8230 architecture. Therefore, this architecture is especially suited to ATM network interfaces for file servers, routers/hubs, Digital Service Units (DSUs), and Brooktree ® 1 Bt8230 1.0 Product Description 1.1 Introduction WAN Data Terminal Equipment (DTE), as well as cost-sensitive PCI ATM cards. Combined with the Bt8222 ATM Receiver/Transmitter, the Bt8230 provides an ATM solution capable of full-duplex operations at bit rates up to 155.52 Mbps ATM speed without the cost constraints of requiring a large amount of local memory to buffer incoming ATM cells. The Bt8230 is implemented as a 33 MHz CMOS device in a 208-pin Plastic Quad Flat Pack (PQFP) with direct TTL-level interfaces to the PCI bus. The device allows incoming ATM cells to be transferred directly into the main system CPU without local buffering. The Bt8230 architecture uniquely balances the strengths of the PCI bus with the need to achieve sustained 155.52 Mbps ATM speeds. With the Bt8230 and Bt8222, a highly integrated and economical PCI ATM adapter can be built. The interface card could, therefore, consist of the Bt8230, an ATM link interface or framer chip, the Bt8222, an optional external control processor, a suitable physical transceiver device capable of driving optical fibers or twisted pair cable, interface connectors, and SRAM for control memory. The SRAM size is driven primarily by the number of connections to be supported. Approximately 250 kbytes are needed per 1000 connectors. Figure 1-1 shows the Bt8230 connected to an ATM physical device and an optional local processor. Figure 1-1. Bt8230 System Block Diagram x c v r s Host System µP PCI Interface Bt8230 SRC Address Dir OE Control Status Address Data Control Data Optional Local Processor System UTOPIA Bus Bt8222 ATM PHY Local SRAM µP ROM Logic Packet Memory RAM Data Control/Status ATM UNI Data Stream 1.1.1 DMA Coprocessor The Bt8230 incorporates an on-chip DMA coprocessor that works in close conjunction with the segmentation and reassembly processors. Once a transfer has been initiated by either the reassembly or segmentation coprocessor, the DMA coprocessor is responsible for gaining access to the PCI bus, transferring the requested data, and notifying the segmentation or reassembly coprocessor that the transfer is complete. The DMA coprocessor transfers all data using the read and write burst buffers in the PCI bus interface, and depends on the PCI bus master logic to execute the PCI bus burst protocol. 2 Brooktree ® Bt8230 1.0 Product Description 1.1 Introduction 1.1.2 Segmentation Coprocessor The segmentation coprocessor is responsible for transmitting 52-octet data to the ATM physical interface block. This coprocessor segments large (up to 64 kbyte) ATM Adaptation Layer (AAL) Service Data Units (SDUs) located in host or local RAM into a controlled stream of 44- or 48-byte ATM cell payloads, which are then formatted into 52-byte ATM cells, not including the Header Error Control (HEC) byte. (A blank HEC byte is added by the ATM physical interface block.) This task is performed with the help of state tables in local RAM memory. Rate entries for each segmentation connection allow the segmentation coprocessor to automatically multiplex cells from a number of outgoing channels onto a single outgoing link while preserving the bandwidth relations between the channels. The segmentation coprocessor can also supply the CPCS-PDU header, trailer, and pad fields as part of the segmentation process. 1.1.3 Reassembly Coprocessor The reassembly coprocessor processes the 52-octet cells from the ATM physical interface block. The ATM physical block strips the HEC byte before passing the cell to the reassembly coprocessor. It controls the writing of the Common Part Conversion Sublayer (CPCS) payload to host memory and performs all necessary SAR and CPCS checks. A scatter method is used by the reassembly coprocessor to write the payload portion of the ATM cell to host memory. It maintains a free buffer queue and status queue in local memory to control the scatter operation. The free buffer queue is updated by the host processor to point to available cell buffers in host memory. The status queue is updated by the reassembly coprocessor with information about how the cell buffers are used. A hash table and a reassembly VCC table located in local memory operate the various CPCS connections and are maintained by the reassembly coprocessor. The hash table allows the reassembly coprocessor to quickly locate the appropriate reassembly VCC table based upon the received VPI/VCI value in the ATM cell header, and permits the assignment of any VPI/VCI value to a particular connection. 1.1.4 PCI Bus Interface The PCI bus interface responds to read and write requests by the host CPU as a PCI slave, allowing access to the chip resources by software on the host. The Bt8230 is capable of acting as a DMA bus master on the PCI bus. As a result, the PCI bus interface implements the full set of address, data, and control signals required to drive the bus as a master, and contains the logic required to support arbitration for the PCI bus. This interface is PCI Version 2.0 compliant. Brooktree ® 3 Bt8230 1.0 Product Description 1.2 Logic Diagram and Pin Descriptions 1.1.5 Local Memory Interface The Bt8230 contains a memory controller that allows the device to access up to 8 Mbytes of static RAM memory. The memory controller also coordinates access to the internal control and status registers by the host and local processors. Both zero and single wait state access are supported to SRAM, which enables various price and performance trade-offs to be made. In addition, SRAM devices organized by_4, by_8, and by_16 may be used. Access to internal control and status registers follows the timing requirements of SRAM access, which simplifies system implementations. 1.1.6 Local Processor Interface The local processor interface in the Bt8230 allows an external Reduced Instruction Set Computer (RISC) CPU to be directly connected to the device to serve as a local controlling intelligence that can handle initialization, connection management, overall data management, error recovery, and OAM functions. The interface is designed to connect directly to Intel i960CA/CF/Jx processors, but is generic enough to connect to other popular processors with little additional logic. The processor interface is "loosely coupled," meaning that the processor connects to the Bt8230 through bidirectional transceivers and buffers for the address and data buses. This allows the processor fast access to Bt8230 memory and registers, but insulates the Bt8230 from processor instruction and data cache fills. It also allows the processor to control multiple Bt8230 or physical devices if desired. 1.1.7 ATM Physical Interface The ATM physical interface communicates with and controls the ATM link interface chip, which carries out all the transmission convergence and physical media dependent functions defined by the ATM protocol. This block strips the HEC byte from the received cell and adds a blank HEC byte to the transmit cell. No HEC processing is performed in the Bt8230. Three modes of operation are provided: standard UTOPIA, slave UTOPIA, and Bt8222. Standard UTOPIA mode conforms to the UTOPIA standard. Slave UTOPIA mode reverses the control direction to allow the ATM physical chip to drive the interface. Bt8222 mode allows the Brooktree physical framer part to be connected directly to the Bt8230. 1.2 Logic Diagram and Pin Descriptions The Bt8230 is packaged in a 208­pin Plastic Quad Flat (PQFP). A functionally partitioned logic diagram of the Bt8230 is shown in Figure 1-2. Pin descriptions, names, input/output assignments are detailed in Table 1-1. 4 Brooktree ® Bt8230 1.0 Product Description 1.2 Logic Diagram and Pin Descriptions Figure 1-2. Bt8230 Logic Diagram 109­116, 121­128, 144­151, Address/Data Bus I/O 155­162 119,239, Command/Byte Enable I/O 143,154 142 Address/Data Command Parity I/O 133 Framing Signal I/O 134 Transactor Initiator Ready I/O 135 Transaction Target Ready I/O 137 Transaction Termination I/O 136 Bus Device Acknowledge I/O 120 Bus Device Slot Select I 107 Bus Grant I 138 Bus Parity Error I/O 132 Bus Clock I 106 System Reset I Framer Configuration Transmit Cell Marker Transmit Flag Transmit Enable Receive Data I I/O I/O I/O I Receive Data Parity Receive Cell Marker Receive Flag Receive Enable Framer Control/Clock I I I/O I/O I 77,78 83 84 82 64­70, 73 63 74 76 75 79 165 186,187 184,185 178­180, 183 I 172 I/O 173 I/O 174 I/O 175 I 177 I/O 168 I Processor Mode Select I Word Select I Bank Select I Write Byte-Enables SRC/ATM Chip Select Address Strobe Burst Last Local Processor Wait Write not Read Self-Test Failed HAD[31:0] HC/BE[3:0]* HPAR HFRAME* Host HIRDY* PCI Interface HTRDY* Signals HSTOP* HDEVSEL* HIDSEL HGNT* HPERR* HCLK HRST* 86,87, TXD[7:0] 90­95 O Transmit Data O Transmit Data Parity TXPAR 85 PROCMODE PADDR[1,0] PBSEL[1,0] PRDY* PDAEN* PINT* PRST* Local Processor Interface PBE*[3:0] PCS* (PHYCS1*) PAS* PBLAST*(PHYCS2*) PWAIT* PWNR PFAIL* Local Memory Interface 23 CLK2X Clocks/Status Test Logic Reset Test Clock Test Mode Select Serial Test Data I I I I 99 97 100 102 O Arbiter Bus Request OD Interrupt Request OD System Error FRCFG[1,0] TXMARK TXFLAG* TXEN* RXD[7:0] ATM Physical Interface RXPAR RXMARK RXFLAG* RXEN* FRCTRL 25­32, 35­40, 42­42, 48­52, 54­61 LDATA[31:0] Memory Data Bus I/O 1,2, 188­192 Memory Address Bus I/O 195­206 LADDR[18:2] 5 RAMMODE RAM Mode Select I 2X Clock Input I HREQ* 108 HINT* 105 HSERR* 139 TRST* TCLK TMS TDI 176 171 167 166 O Memory Ready I/O Data/Address Enable OD Interrupt Output O Reset Output MCS[3:0]* 14­17 O O MOE* 12 6,7, MWE[3:0]* 10,11 O MWR* 13 O LADDR[1,0] 1,2 O SYSCLK 21 CLKD3 19 STAT[1,0] 3,4 TDO 101 Boundary Scan Test Signals Memory Bank Chip Selects Memory Read Enable Memory Write Enable Write Enable for by 16 RAM Memory Address Bus O System Clock Output O Divide by 3 Clock Output O SRC Status O Serial Test Data I = Input, O = Output, OD = Open Drain Output * Indicates Active Low Brooktree ® 5 Bt8230 1.0 Product Description 1.2 Logic Diagram and Pin Descriptions Table 1-1. Hardware Signal Definitions (1 of 5) Pin Label Signal Name I/O Definition I/O Used by the PCI host or the Bt8230 to transfer addresses or data over the PCI bus. Command/Byte Enable I/O Outputs a command (during PCI address phases) or byte enables (during data phases) for each bus transaction. HPAR Address/Data Command Parity I/O Supplies the even parity computed over the HAD[31:0] and HC/BE[3:0]* lines during valid data phases; it is sampled (when the Bt8230 is acting as a target) or driven (when the Bt8230 acts as an initiator) one clock edge after the respective data phase. HFRAME* Framing Signal I/O A high-to-low HFRAME* transition indicates that a new transaction is beginning (with an address phase). A low-to-high transition indicates that the next valid data phase will end the current transaction. HIRDY* Transaction Initiator Ready I/O Used by the transaction initiator or bus master (either the Bt8230 or the PCI host) to indicate ready for data transfer. A valid data phase ends when both HIRDY* and HTRDY* are sampled asserted on the same clock edge. HTRDY* Transaction Target Ready I/O Used by the transaction target or bus slave (either the Bt8230 or the PCI bus memory) to indicate that it is ready for a data transfer. A valid data phase ends when both HIRDY* and HTRDY* are sampled asserted on the same clock edge. HSTOP* Transaction Termination I/O Driven by the current target or slave (either the Bt8230 or the PCI bus memory) to abort, disconnect, or retry the current transfer. The HSTOP* line is used by the PCI master in conjunction with the HTRDY* and HDEVSEL* lines to determine the type of transaction termination. HDEVSEL* Bus Device Acknowledge I/O Driven by a target to indicate to the initiator that the address placed on the HAD[31:0] lines (together with the command on the HC/BE[3:0]* lines) has been decoded and accepted as a valid reference to the target's address space. Once asserted, it is held by the Bt8230 (when acting as a slave) until HFRAME* is deasserted; otherwise, it indicates (in conjunction with HSTOP* and HTRDY*) a target abort. HIDSEL Bus Device Slot Select I Signals the Bt8230 that it is being selected for a configuration space access. HREQ* Arbiter Bus Request O Asserted by the Bt8230 to request control of the PCI bus. HGNT* 6 Multiplexed Address/Data Bus HC/BE[3:0]* Host PCI Interface Signals HAD[31:0] Bus Grant I Asserted to indicate to the Bt8230 that it has been granted control of the PCI bus, and may begin driving the address/data and control lines after the current transaction has ended (indicated by HFRAME*, HIRDY* and HTRDY* all deasserted simultaneously). Brooktree ® Bt8230 1.0 Product Description 1.2 Logic Diagram and Pin Descriptions Table 1-1. Hardware Signal Definitions (2 of 5) Pin Label Signal Name I/O Definition OD Signals an interrupt request to the PCI host, and is tied to the INTA* line on the PCI bus. Bus Parity Error I/O Driven asserted by the Bt8230 (as a bus slave) or by a target addressed by the Bt8230 when it acts as a bus master to indicate a parity error on the HAD[31:0] and HC/BE[3:0]* lines. It is asserted when the Bt8230 is a bus slave or sampled when the Bt8230 is a bus master on the second clock edge after a valid data phase. The Bt8230 drives the HPERR* line only when acting as a slave. HSERR* System Error OD Indicates a system error or a parity error on the HAD[31:0] and HC/BE[3:0]* lines during an address phase. This pin is handled in the same way as HPERR*, and is only driven by the Bt8230 when it acts as a bus slave. HCLK Bus Clock I Supplies the PCI bus clock signal. HRST* System Reset I Performs a hardware reset of the Bt8230 and associated peripherals when asserted. Must be asserted for 16 cycles of HCLK. FRCFG[1,0] Framer Configuration I Configuration pins FRCFG[1,0] determine what framer interface Bt8230 supports. 00 = Bt8222 interface 01 = UTOPIA interface 10 = Slave UTOPIA interface 11 = Reserved, do not use TXD[7:0] Transmit Data O Carries outgoing data bytes to the framer chip in all framer modes. TXPAR Transmit Data Parity O Outputs the 8-bit odd parity computed over the TXD[7:0] lines in all framer modes. TXMARK Transmit Cell Marker I/O In both UTOPIA and slave UTOPIA modes, the TXMARK line is asserted by the Bt8230 when the starting byte of a 53-byte cell is being output. In Bt8222 mode, this pin is asserted by the framer to indicate that it is expecting the starting byte of a 53byte ATM cell to be transferred on the TXD[7:0] lines as the next valid data byte. TXFLAG* Transmit Flag I/O In UTOPIA mode, TXFLAG* indicates that the transmit buffer in the downstream link interface chip is full, and no more data can be accepted. In slave UTOPIA mode, this pin indicates to the link interface chip that the Bt8230 transmit buffer is empty. In Bt8222 mode, TXFLAG* indicates that no more data is available in the transmit buffer of the Bt8230. TXEN* Transmit Enable I/O Indicates that valid data has been placed on the TXD[7:0], TXPAR, and TXMARK lines in the current clock cycle when the Bt8230 is in UTOPIA or slave UTOPIA mode. This pin is an output in UTOPIA mode and an input in slave UTOPIA mode. In Bt8222 mode, the TXEN* input indicates that the downstream framer device is requesting the Bt8230 to transfer a byte of data on the TXD[7:0] lines. RXD[7:0] ATM Physical Interface Interrupt Request HPERR* PCI Interface Signals HINT* Receive Data I Transfers incoming data bytes from the link interface or framer chip to the Bt8230 in all framer modes. Brooktree ® 7 Bt8230 1.0 Product Description 1.2 Logic Diagram and Pin Descriptions Table 1-1. Hardware Signal Definitions (3 of 5) Pin Label Signal Name I/O Definition Should be driven with the 8-bit odd parity computed over the RXD[7:0] lines by the link interface or framer chip in all framer modes. Receive Cell Marker I Indicates that the current byte being transferred on the RXD[7:0] lines is the starting byte of a 53-byte cell. Receive Flag I/O In UTOPIA mode, RXFLAG* indicates that the receive buffer in the downstream link interface chip is empty, no more data can be transferred, and the RXD[7:0], RXPAR, and RXMARK lines are invalid. In slave UTOPIA mode, this pin indicates to the framer chip that the receive FIFO in the Bt8230 is full. In Bt8222 mode, the RXFLAG* output indicates that the Bt8230 internal FIFO buffer is full and any subsequent attempts to transfer data will be ignored. RXEN* Receive Enable I/O In UTOPIA mode, RXEN* indicates that the Bt8230 is ready to receive data on the RXD[7:0], RXPAR, and RXMARK lines in the next clock cycle. This pin is an output in UTOPIA mode, and an input in slave UTOPIA mode. In Bt8222 mode, the RXEN* input is driven active by the framer to signify that valid data has been presented on the RXD[7:0], RXPAR, FRCTRL, and RXMARK lines. FRCTRL Framer Control/Clock I In UTOPIA and slave UTOPIA mode, the FRCTRL line should be driven with a clock that is synchronous to that used by the framer device for interfacing to the Bt8230. The TXD[7:0], TXPAR, TXMARK, TXFLAG* TXEN*, RXD[7:0], RXPAR, RXMARK, RXFLAG*, and RXEN* lines must be synchronous to this clock in UTOPIA mode, and maintain the specified setup and hold times with reference to its rising edge. In Bt8222 mode, this pin marks a cell as invalid and the Bt8230 discards the cell. PROCMODE Local Processor Interface I RXFLAG* 8 Receive Data Parity RXMARK ATM Physical Interface RXPAR Processor Mode Select I When grounded, this input selects the local processor mode. When pulled to a logic high, the stand-alone mode is selected. PADDR[1,0] Word Select Inputs I The PADDR[1,0] inputs are connected to the word select field of the CPU address bus (address bits [3, 2] for the Intel i80960CA processor, which can perform 4-word burst transactions). These inputs are used by the Bt8230 to allow singlecycle bursts to be performed without requiring very short memory access times. PBSEL[1,0] Bank Select Inputs I Select one of four banks of memory to be accessed. They are decoded by the memory controller to generate the appropriate chip/bank selects to the external memory. Brooktree ® Bt8230 1.0 Product Description 1.2 Logic Diagram and Pin Descriptions Table 1-1. Hardware Signal Definitions (4 of 5) Pin Label Signal Name I/O Definition Write Byte Enable I Supply byte enables for each local processor memory access. These pins are only relevant during writes by the local processor to local memory. Each byte enable line corresponds to a specific byte lane in the LDATA[31:0] data bus: PBE[0]* corresponds to LDATA[7:0], PBE[1]* to LDATA[15:8], PBE[2]* to LDATA[23:16], and PBE[3]* to LDATA[31:24]. PCS* SRC Chip Select I/O (PHYCS1*) ATM PHY Chip Select (in stand-alone mode) In local processor mode with PROCMODE tied low, PCS* is the SRC chip select input. In stand-alone mode, this pin is PHYCS1*, which may be connected to the chip select input of the Bt8222 PHY device. PAS* Address Strobe I/O Indicates a local processor address cycle. In stand-alone mode, PAS* is used to drive the AS* pin of the Bt8222 device. PWNR Write/not Read I/O The PWNR input indicates the direction of a local processor transfer. A logic one indicates a write while a logic zero indicates a read. During stand-alone mode, this output provides the same function for the Bt8222. PWAIT* Processor Wait I PBLAST* Burst Last (PHYCS2*) ATM PHY Chip Select (in stand-alone mode) PRDY* Memory Ready O Signals that the memory or control register has accepted the data on a write, or that data is available to latch by the local processor on a read cycle. PDAEN* Data/Address Enable I/O Connected to the output enable input of the bidirectional transceivers and buffers used to isolate the Bt8230 data and address bus from the local processor. In stand-alone mode, this input is connected to the physical device's interrupt output(s). PFAIL* Self-Test Failed I The local processor can indicate a failure of its internal selftest or initialization processes by asserting the PFAIL* input to the Bt8230. PINT* Interrupt Output OD Asserted by the Bt8230 to the local processor to signal an interrupt request in local processor mode. PRST* Local Processor Interface PBE[3:0]* Reset Output O Asserted by the Bt8230 to the local processor whenever the HRST* input is asserted, or when the LP_ENABLE bit in the CONFIG0 register is a logic low. Brooktree ® I/O Used by the local processor or external logic to insert wait states for read or write transactions. In local processor mode, this input is used by the processor to indicate the end of a transaction. If burst transfers are not required, tie this input low. During stand-alone mode, this output is a second chip select, PHYCS2*. 9 Bt8230 1.0 Product Description 1.2 Logic Diagram and Pin Descriptions Table 1-1. Hardware Signal Definitions (5 of 5) Pin Label Signal Name I/O Definition I/O Address I/O bus. Used for memory reads and writes as well as Control and Status Register access by the local processor. Memory Address Bus O The two least significant bits of address I/O bus. Used for memory reads and writes as well as CSR access by the local processor. MCS[3:0]* Memory Bank Chip Selects O Selects one of four addressable banks of SRAM memory. MOE* Memory Read Enable O Indicates that a read cycle is proceeding and the memory device output buffers should be enabled, driving data onto the LDATA[31:0] lines. MWE[3:0]* Memory Byte Write Enables O Memory byte write enables for by_4 or by_8 SRAMs. For by_16 devices, these outputs are byte enables that are active on writes and reads. Memory Write O Memory write enable for by_16 SRAMs. RAM Mode Select I Selects RAM chips supported. 1 = by_16 memory devices. 0 = by_4 or by_8 memory devices. CLK2X 2x Clock Input I Double frequency (from SYSCLK) TTL clock input. SYSCLK System Clock O This divide by 2 of CLK2X is the internal system clock as well as the external system clock. CLKD3 Divide by 3 Clock O This output clock is a 50% duty cycle one-third divide of CLK2X; it may be used for the UTOPIA interface clock. STAT[1,0] SRC Status O Bt8230 internal status outputs. Internal status controlled by the STAT_MODE[3:0] field in the CONFIG0 Register. TRST* Test Logic Reset I When a logic low, this signal asynchronously resets the boundary scan test circuitry and puts the test controller into the reset state. This state allows normal system operation. Tie to ground when boundary scan is not implemented TCLK Test Clock I Generated externally by the system board or by the tester. Tie to ground when boundary scan is not implemented. TMS Test Mode Select I Decoded to control test operations. TDO Serial Test Data O Outputs serial test pattern data. TDI Clocks and Status Memory Address Bus RAMMODE Boundary Scan Test Signals Data I/O bus. Used for memory reads and writes as well as Control and Status Register access by the local processor. MWR* Supply Voltage I/O LADDR[1,0] 10 Memory Data Bus LADDR[18:2] Local Memory Interface LDATA[31:0] Serial Test Data I Input for serial test pattern data. PWR Power ­ Sixteen pins are provided for supply voltage. GND Ground ­ Twenty-two pins are provided for ground. Brooktree ® 2.0 Functional Description 2.1 Overview The functional description section assumes that the reader is familiar with and has access to the standards listed in Appendix A. The Bt8230 consists of three coupled coprocessors: a DMA coprocessor that performs data transfers to and from the memory of the host system; a segmentation coprocessor, and a reassembly coprocessor; both of which handle high-speed I/O between the Bt8230 and an external ATM Physical Device (PHY) chip. In addition, the Bt8230 contains local processor support logic that allows a local processor to be connected to the Bt8230; a PCI bus interface responsible for accepting read and write commands from the DMA coprocessor (passed through the burst FIFO buffers), and which performs actual data transfers on the PCI bus; and a boundary scan testing facility. Figure 2-1 depicts the overall Bt8230 functional blocks and organization. Figure 2-1. Bt8230 Functional Block Diagram Burst FIFO PCI Bus Master Logic DMAC Incoming Channel Burst FIFO DMAC Outcoming Channel DMA Coprocessor PCI Bus Interface Device Reg R/W Ctrl Control CPU Port Logic Local Processor Interface Brooktree ® RX FIFO Physical RX Port ATM Physical Receive Interface Segmentation Coprocessor Tx FIFO Physical Tx Port ATM Physical Transmit Interface Scheduler CPU/Memory Interface Drivers PCI Slave Logic Reassembly Coprocessor Memory Controller Logic Memory Address/ Control Clock/ Timer Logic Boundary Scan 1149.1 Test Bus 11 Bt8230 2.0 Functional Description 2.2 DMA Coprocessor 2.2 DMA Coprocessor The Direct Memory Access (DMA) coprocessor is intended to perform highspeed sustained data transfers to and from the host memory space. It is controlled by the segmentation and reassembly coprocessors. The major functions of the DMA coprocessor are to transfer data from the host memory (through the PCI bus) to the segmentation coprocessor, and to transfer data from the reassembly coprocessor to the host memory space (through the PCI bus). In all modes of operation, the DMA coprocessor maintains a high level of performance. It uses burst transfers when possible to maximize utilization of the host bus bandwidth, performs byte switching to accommodate misaligned transfers, and carries out concurrent input and output transfers (alternating burst reads and burst writes) to support simultaneous input and output data streams. 2.2.1 DMA Read For outgoing messages, DMA read cycles move data from host memory to the segmentation coprocessor using a gather DMA method. The maximum burst size is thirteen 32-bit words which correspond to one cell. The burst size can be reduced by setting the MAX_BURST_LEN field in the PCI Configuration Register at a value less than 13 words. 2.2.2 DMA Write For incoming messages, DMA write cycles move data from the reassembly coprocessor to host memory using a scatter DMA method. The maximum burst size is fourteen 32-bit words which correspond to one ATM cell and a status word appended to performance monitoring cells. The burst size can be reduced by setting the MAX_BURST_LEN field in the PCI Configuration Register at a value less than 13 words. 2.2.3 Misaligned Transfers The reassembly and segmentation processors handle data internally on word addresses. The DMA coprocessor must be capable of handling transfers from the PCI bus without the same constraint (i.e., with data that is not aligned on word boundaries). In addition, the length of the transfer is specified in bytes, not 32-bit words, even though the data bus widths are all 32 bits. To facilitate this, byte-switching logic is used within the Bt8230. When the Bt8230 specifies a host address with the LSBs = 00, it is implied that the data is byte aligned. Figure 2-2 shows how a byte-aligned address would map into the PCI host address space for a little endian system. Selecting between big and little endian systems is done through ENDIAN [bit 12] in the Configuration Register 0 [CONFIG0;0x14]. 12 Brooktree ® Bt8230 2.0 Functional Description 2.2 DMA Coprocessor Figure 2-2. LIttle Endian Aligned Transfer ATM Cell 0 1 2 3 Length(# of 32 bit words) = 3 4 5 6 7 8 9 10 11 PCI Host Address Space Host Address = 0x00 0 Bits 31 3 2 1 0 0x00 7 6 5 4 0x04 11 10 9 8 0x08 Address When the Bt8230 specifies a host address with the LSBs 00, it is implied that the data is misaligned. Figure 2-3 shows how a misaligned address would map into the PCI host address space for a little endian system. Figure 2-3. Little Endian Misaligned Transfer ATM Cell 0 1 2 3 4 5 6 7 8 9 10 11 Length(# of 32 bit words) = 3 PCI Host Address Space Host Address = 0x01 2 1 0 6 5 4 31 0 Bits 31 0 5 0x04 0 Bits 1 0x00 3 4 31 3 2 ® 7 0x08 11 Brooktree 8 0x0C 0 Bits 0 0x00 0x00 4 0x04 3 2 1 0x04 8 7 6 5 0x08 11 10 9 0x0C Address Address 10 9 Host Address = 0x11 Host Address = 0x10 9 8 7 6 0x08 11 10 0x0C Address 13 Bt8230 2.0 Functional Description 2.2 DMA Coprocessor Figure 2-4 shows how a byte-aligned address would map into the PCI host address space for a big endian system. Figure 2-4. Big Endian Aligned Transfer ATM Cell 0 1 2 3 4 5 6 7 8 9 10 11 PCI Host Address Space Length(# of 32 bit words) = 3 Host Address = 0x00 31 0 Bits 0 1 2 3 4 5 6 7 8 9 10 11 0x00 0x04 Address 0x08 When the Bt8230 specifies a host address with the LSBs 00, it is implied that the data is not aligned. Figure 2-5 shows how an unaligned address would map into the PCI host address space for a big endian system. Figure 2-5. Big Endian Misaligned Transfer ATM Cell 0 1 2 3 4 5 6 7 8 9 10 11 Length(# of 32 bit words) = 3 PCI Host Address Space Host Address = 0x10 Host Address = 0x01 31 31 0 Bits 0 3 7 11 14 1 2 4 5 6 0x04 8 9 10 0x08 0x0C 0 Bits 0x00 31 0 Address 2 6 3 7 10 11 Host Address = 0x11 1 0x00 4 5 0x04 8 9 0 Bits 0 0x00 1 2 3 4 0x04 0x08 5 6 7 8 0x08 0x0C 9 10 11 Address Address 0x0C Brooktree ® Bt8230 2.0 Functional Description 2.3 Memory Interface 2.3 Memory Interface To simplify system implementations, the Bt8230 integrates a complete memory controller designed for direct interface to common Static RAMs (SRAMs). The control and status registers, as well as the physical interface devices in the standalone mode of operation, are mapped into the bottom of the memory map. Consequently, accesses to these resources are also controlled by the memory controller. Figure 2-6 shows the Bt8230 address map. Up to 8 MByte of external memory using SRAM devices can be accessed by the Bt8230. The amount of memory required is heavily dependent on the number of Virtual Channel Connections (VCCs) implemented, as well as the number of VCCs that are currently active. Memory requirements are discussed in detail in subsection 2.5.1. Figure 2-6. Bt8230 Memory Map(1) (0x7FFFFFh >> (5-BANKSIZE) MCS[3]* (0x600000h >> (5-BANKSIZE) (0x5FFFFFh >> (5-BANKSIZE) MCS[2]* (0x400000h >> (5-BANKSIZE) (0x3FFFFF >> (5-BANKSIZE) MCS[1]* (0x200000h >> (5-BANKSIZE) (0x1FFFFFh >> (5-BANKSIZE) MCS[0]* 0x001000h 0x000800h­0x000FFFh PHYCS2* (T1/E1 Framer)(2) 0x000400h­0x0007FFh Reserved(2) 0x000200h­0x0003FFh PHYCS1* (Bt8222)(2) 0x000000h­0x0001FFh Bt8230 Internal Registers Notes: (1). All addresses in this illustration are byte addresses (2). These device selects are available in stand-alone mode only; otherwise, this memory is mapped to MCS[0]*. Brooktree ® 15 Bt8230 2.0 Functional Description 2.3 Memory Interface 2.3.1 Memory Bank Characteristics The external memory is organized in 1 to 4 banks of up to 2 MByte each. The system may use any number of banks to fulfill the memory requirements, the only requirement is that the banks must be of the same size and organization. The local processor selects between the banks via the PBSEL[1,0] inputs. BANKSIZE[2:0] [bits 9­7] in the CONFIG0 register denote the size of the memory banks and allow the Bt8230 to incorporate the various bank sizes into contiguous memory. Table 2-1 gives the coding of the BANKSIZE[2:0] control bits. Table 2-1. Memory Bank Size BANKSIZE Bank Memory Organization Total Bank Size (Bytes) PBSEL[1,0] Connection 111 Reserved 110 Reserved 101 512 K x 32 2M A[22:21] Four 512 K x 8 100 256 K x 32 1M A[21:20] Two 256 K x 16, Eight 256 K x 4 011 128 K x 32 512 K A[20:19] Four 128 K x 8 010 64 K x 32 256 K A[19:18] Two 64 K x 32, Eight 64 K x 4 001 32 K x 32 128 K A[18:17] Four 32 K x 8 000 16 K x 32 64 K A[17:16] Two 16 K x 16, Eight 16 K x 4 Typical Implementation The memory controller is designed to work with standard by_8 and by_4 SRAM devices as well as with by_16 devices. Grounding the RAMMODE input selects the by_4 or by_8 mode of operation, pulling RAMMODE to a logic one selects by_16 operation. When by_16 operation is selected, the MWE[3:0]* outputs become byte enables for both reads and writes. Figure 2-7 shows a typical half MB bank implementation using by_8 SRAM devices. Figure 2-8 shows a typical 1 MB bank using by_16 RAM. To connect different sized RAM banks, simply use more or less address bits, all other control remains the same. NOTE: 16 The number and type of SRAM chips used affect the address and data bus capacitance and, therefore, the AC timing specifications and the required SRAM speed. Also note that the use of by_4 devices causes more address bus loading than the use of by_8 or by_16 devices. See Chapter 4.0 for detailed timing information. Brooktree ® Bt8230 2.0 Functional Description 2.3 Memory Interface Figure 2-7. 0.5 MB SRAM Bank Utilizing by_8 Devices LADDR[16:0] LDATA[31:0] A[16:0] SRAM 128 K x 8 A[16:0] A[16:0] D[23:16] D[31:24] SRAM 128 K x 8 SRAM 128 K x 8 SRAM 128 K x 8 Bt8230 A[16:0] D[15:8] D[7:0] D[7:0] D[7:0] D[7:0] /CS MCSx* MOE* D[7:0] /CS /CS /CS /OE /OE /OE /OE MWE[0]* /WE MWE[1]* /WE MWE[2]* /WE MWE[3]* /WE MWR* RAMMODE GND Figure 2-8. 1 MB SRAM Bank Utilizing by_16 Devices SRAM 256 K x 16 SRAM 256 K x 16 Bt8230 LADDR[17:0] LDATA[31:0] A[17:0] A[17:0] D[31:16] D[15:0] D[15:0] D[15:0] MCSx* /CS /CS MOE* MWE[0]* MWE[1]* MWE[2]* /OE /OE /BEL /BEH /BEL /BEH MWE[3]* MWR* RAMMODE Brooktree ® /WE /WE Pullup 17 2.0 Functional Description Bt8230 2.3 Memory Interface The memory map contains space allocated to the Bt8222 physical interface IC, and to a future Brooktree T1/E1 framer. This mapping is only valid when the PROCMODE input pin is pulled high indicating stand-alone operation with no local processor present. Stand-alone operation is detailed in a subsection 2.4.6. When PROCMODE is logic low and the local processor is present, addresses 0x100h through 0xFFFh are available for general use and are mapped to MCS[0]*. The MEMCTRL bit in the CONFIG0 Register selects the number of wait states that the memory controller uses to access the SRAM. A logic zero indicates zero wait state or single-cycle memory, while a logic one indicates one wait state or two-cycle memory. The power-on default is MEMCTRL = 1, selecting one wait state or two-cycle memory accesses. Accesses made to the control registers by the local processor follow the convention for SRAM accesses, that is, either zero or one wait state depending on MEMCTRL programming. Subsequently, the local processor sees no functional timing differences between accesses to registers or SRAM. The internal register accesses from the PCI slave interface are always zero wait state. SRAM access time requirements are directly proportional to the system clock speed, as well as the amount and organization of the memory. The required system clock speed for a given application is dependent on the physical line rate, number of VCCs, and the percentage on idle cells versus assigned cells. Refer to subsection 2.4.7 for more information. Memory access times and other requirements are specified at three typical implementations of 1, 2, and 4 banks of by_8 SRAM. In terms of address bus loading, one bank of by_8 SRAM equals one-half bank of by_16 or two banks of by_4. In this way, the system designer may choose the appropriate SRAM characteristics to suit the amount of memory and organization required for the application. See Chapter 4.0 for timing information. 18 Brooktree ® Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4 Local Processor Interface 2.4.1 Overview The Bt8230 integrated circuit may be used in conjunction with an external processor that performs initialization, link management, monitoring, and control functions. The local processor interface consists of a "loosely coupled" architecture where it interfaces to the Bt8230 through bidirectional transceivers and buffers that are controlled by the local processor and the Bt8230, as shown in Figure 2-9. This architecture allows the processor access to all of the Bt8230 local SRAM memory and control registers, while insulating the Bt8230 from processor instruction and data cache fills. This also allows the local processor the option to control multiple Bt8230 and/or physical interface devices. Figure 2-9. Bt8230-Local Processor Interface Local Processor Bt8230 Clock Clock Data Data Enable x32 Xcvr /OE Dir Data Dir x17 Buff(1) Address Address /OE Chip Select Control Status Decode High Address Optional Logic(2) Control Status Notes: (1). Required to address full 8 MByte range, typically fewer address lines are used. (2). Required for non-i960 processors. The processor interface is a generic synchronous interface based on the Intel i960CA 32-bit architecture, and is completely compatible with the i960CA/CF and the new i960Jx processors. Other synchronous and asynchronous processors (e.g., from Motorola, AMD, IDT) can be interfaced using external circuitry. The only requirement is that the processor have a 32-bit bus and that the control signals be synchronized to SYSCLK. Brooktree ® 19 Bt8230 2.0 Functional Description 2.4 Local Processor Interface To access the Bt8230 local memory or control registers, the processor must arbitrate with the Bt8230 for access to the memory controller. Due to the requirements of reassembly and segmentation access to SRAM, and the implications of PCI bus utilization, the local processor has the lowest priority in the memory arbitration scheme. Since the local processor is typically used for low bandwidth supervision and maintenance functions, this should be acceptable. When the local processor accesses the Bt8230's control registers or local memory, a local processor memory request is generated internal to the Bt8230. The memory arbiter then coordinates this request with requests from other memory consumers and grants the memory bus to the local processor at the appropriate time. The local processor is held off during this process by the insertion of a variable number of wait states; accomplished by the i960 withholding READY* or RDYRCV*. Once the local processor is granted the memory system, the transceivers are enabled to allow the local processor's address and data to access the SRAM or control registers. The conclusion of the data transaction is signaled by the assertion of PRDY*. Wait states may be inserted by the processor at any time by asserting PWAIT*. The last data cycle in a burst is indicated by the PBLAST* signal. In this manner, non-i960 processor half-speed buses or slow transceivers can be accounted for. The LP_BWAIT bit in the CONFIG0 Register will automatically add a single wait state between the first access in a burst and subsequent accesses. This can be used to simplify the design of memory controllers for processors that do not produce a wait output and which require more time between data cycles in a burst. 2.4.2 Interface Pin Description The local processor bus interface consists of the control, address, and status signals described in Table 2-2. Reference Table 1-1 and Figure 2-15, i80960CA/CF interface description for the following discussion Table 2-2. Processor Interface Pins (1 of 2) Dir(1) Description PROCMODE I Processor interface mode select input-A logic low on this input enables the local processor mode of operation. PCS* I Processor interface chip select-A logic low on this signal in conjunction with a logic low on PAS* at the rising edge of SYSCLK initiates a memory request to the memory controller. PAS* I Processor address strobe- A logic low on this signal in conjunction with a logic low on PCS* latches the value of PWNR, PBSEL[1,0], PADDR[1,0], and PBE[3:0]* at the rising edge of SYSCLK. PWNR I Processor write/read select-A logic one on this input indicates a write cycle, a logic zero indicates a read cycle. Latched at rising edge of SYSCLK when PAS* and PCS* are active. PADDR[1,0] I Word select address inputs-Indicates the word address for a single cycle access, or the first word for a multi-cycle burst access. Latched at rising edge of SYSCLK when PAS* and PCS* are active. PBSEL[1,0] I Bank select inputs-Decode to select MCS[3:0]*; see Figure 2-6 for details. Latched at rising edge of SYSCLK when PAS* and PCS* are active. Signal 20 Brooktree ® Bt8230 2.0 Functional Description 2.4 Local Processor Interface Table 2-2. Processor Interface Pins (2 of 2) Dir(1) Description PBE[3:0]* I Byte select inputs-Active low. Allows individual bytes of selected word to be written. Not active on reads. Latched at rising edge of SYSCLK when PAS* and PCS* active. PBE[3]* controls writes to LDATA[31:24], PBE[2]* controls LDATA[23:16], etc. PWAIT* I Processor wait input-Allows processor to insert variable number of wait states to extend memory transaction. Must be active on rising edge of SYSCLK with PRDY* active to insert wait cycle. May be used to interface to half speed or slow processor bus or to allow the use of slow transceivers. If the insertion of wait states is not required, set this input to a logic high. PBLAST* I Processor burst last input-Indicates the last word of a cycle. Must be active on rising edge of SYSCLK with PRDY* active to indicate last cycle. If burst accesses are not required, this signal should be set to a logic low. PRDY* O Processor interface ready signal-A logic low on this signal at rising edge of SYSCLK indicates that the present cycle has been completed. If a read cycle, the data is valid to latch by the processor; if a write cycle, the data has been written and may be removed from the bus. When PRDY* is active, wait states may be inserted with PWAIT*, or a single or burst cycle may be terminated by PBLAST*(2). PDAEN* O Processor data and address bus enable-Connects to output enable input of bidirectional transceiver and buffer to enable data and address for processor cycles and disable otherwise. May also be used to indicate that the processor has successfully arbitrated for access to the memory controller(3). Signal Notes: (1). Direction given with respect to the Bt8230. (2). This output corresponds to the READY* or RDYRCV* input in the i960 architecture. (3). The processor system is responsible for controlling the direction of the bidirectional data bus transceiver. In the i960 architecture, this may be controlled by the DT/R* signal. 2.4.3 Bus Cycle Descriptions Throughout the bus cycle descriptions, cycle refers to a single SYSCLK cycle ending with a rising edge. An arbitration cycle is one in which the memory requests from the local processor and internal memory consumers are compared and the one with the highest priority is granted the memory access on the next cycle. A memory access that was previously arbitrated may occur on an arbitration cycle. Once the local processor has successfully acquired the memory controller, it holds the bus until it is relinquished by the assertion of PBLAST* on the last data cycle. Therefore, local processor burst transfers will always be completed and may theoretically be of arbitrary length. However, in practice, burst transfers should be limited to four or less. The maximum arbitration delay for a local processor access is on the order of 20 cycles; however, it will typically be from 1 to 4 cycles. This parameter is heavily influenced by the SYSCLK frequency, line rate, number of VCCs, idle cell ratio, and SRAM access speed. Therefore, a system design in which local processor accesses must occur within a fixed time period is not recommended. Brooktree ® 21 Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4.3.1 Single Read Cycle, Zero Wait State Example Figure 2-10 illustrates a single read cycle with zero wait states. During the address cycle (cycle 1) at the rising edge of SYSCLK with PCS* and PAS* active, a memory request is generated by the processor interface circuitry. Also at this time, the read/write select, bank select, and word select inputs (PWNR, PBSEL[1,0], and PADDR[1,0]) are internally latched. Note that the byte enables (PBE[3:0]*) are don't cares during reads. During cycle 2, this local processor memory request is processed by the memory arbitration circuitry. If no other memory consumers request an access on the same cycle, the local processor is granted access on cycle 3. However, to take into account bus transceiver turnaround, cycle 3 is always a wait or bus recovery state which gives sufficient time for the address from the processor to access the SRAM. For zero wait state SRAM, unless a wait state is inserted by the processor, the data is available to be latched into the processor on cycle 4, which is indicated by the assertion of PRDY*. Cycle 5 is an arbitration cycle for the internal memory consumers which may have requested access during the processor access. It also serves as a bus recovery cycle for the processor. Note that once the PCS*, PAS*, PWNR, PBSEL[1,0], and PADDR[1,0] are sampled at cycle 1, they are don't cares for the remainder of the access. Also note that DT/R* is an output supplied by the local processor to indicate the direction of the data transceivers, and that the Bt8230 PDAEN* signal is active to enable data and address. Figure 2-10. Local Processor Single Read Cycle tarb ta tbr td tbr/tabr SYSCLK PCS* PAS* PWNR PBSEL[1,0] 11 PADDR[1,0] 10 PBE[3:0] DT/R* PWAIT* PBLAST* PRDY* D[31:0] D0 A[20:4] A0 LADDR[18:2] A0 10 LADDR[1,0] LDATA[31:0] PDAEN* D0 0111 MCS*[3:0] MOE* MWE*[3:0] 1. Address Cycle 22 2. Arbitration Cycle 3. Bus Recovery Cycle 4. Data Cycle 5. Bus Recovery/ Next Arbitration Cycle Brooktree ® Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4.3.2 Single Read Cycle, Wait States Inserted By Memory Arbitration Figure 2-11 illustrates a local processor single read cycle with arbitration wait states. This example is similar to the preceding one, except that here the local processor is not able to access the RAM immediately because of higher priority memory requests on cycles 2 and 3. On cycle 4, the memory controller allows the local processor access to the address and data bus and the transaction takes place at the end of cycle 6. Figure 2-11. Local Processor Single Read Cycle with Arbitration Wait States ta 1 SYSCLK tarb 2 tarb 3 tarb tbr 4 5 td 6 tarb 7 PCS* PAS* PWNR PBSEL[1,0] 11 PADDR[1,0] 10 PBE[3:0] DT/R* PWAIT* PBLAST* PRDY* D[31:0] D0 A[20:4] A0 LADDR[18:2] A0 LADDR[1,0] 10 LDATA[31:0] D0 PDAEN* MCS*[3:0] 0111 MOE* MWE*[3:0] 1. Address Cycle Brooktree ® 2. Arbitration Cycle 3. Arbitration Cycle 4. Arbitration 5. Bus Recovery Cycle Cycle 6. Data Cycle 7. Arbitration Cycle 23 Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4.3.3 Double Read Burst With Processor Wait States In Figure 2-12 the processor inserts wait states on cycle 4 and cycle 6 to allow additional time for the reads to occur. At the rising edge of SYSCLK on cycle 4 and cycle 6, the combination of PWAIT* low and PRDY* low extends the read by one more cycle. Note that the local processor word select inputs (PADDR[1,0]) are latched at cycle 1, and the Bt8230 word select address lines, LADDR[1,0], are incremented automatically at the beginning of cycle 6. Figure 2-12. Local Processor Double Read with Wait States Inserted ta 1 SYSCLK tarb 2 tbr 3 tw 4 td 5 tw 6 td 7 PCS* PAS* PWNR PBSEL[1,0] 10 PADDR[1,0] 00 PBE[3:0] DT/R* PWAIT* PBLAST* PRDY* D[31:0] D0 D1 LADDR[1,0] 00 01 LDATA[31:0] D0 D1 A[20:4] A0 LADDR[18:2] A0 PDAEN* MCS*[3:0] 1101 MOE* MWE*[3:0] 1. Address Cycle 24 2. Arbitration Cycle 3. Bus Recovery Cycle 4. Wait Cycle 5. Data Cycle 6. Wait Cycle 7. Data Cycle Brooktree ® Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4.3.4 Single Write With One-Wait-State Memory In Figure 2-13, the local processor performs a single write into one-wait-state memory. There is no arbitration delay. Note that RAMMODE is a logic high, indicating that by_16 RAM is used. Here the PBE[3:0]* inputs are latched at cycle 1 and are used to select the byte enables that are active during the cycle when MWR* is active. In this case, the two most significant bits are active, indicating a 16-bit write to the two most significant bytes. Figure 2-13. Local Processor Single Write with One Wait State by_16 SRAM ta 1 SYSCLK tarb 2 tbr 3 tw 4 td 5 PCS* PAS* PWNR PBSEL[1,0] 00 PADDR[1,0] 01 PBE*[3:0] 0011 DT/R* PWAIT* PBLAST* PRDY* D[31:0] D0 A[20:4] A0 LADDR[18:2] A0 01 LADDR[1,0] LDATA[31:0] D0 PDAEN* MCS*[3:0] 1110 MOE* RAMMODE MWE*[3:0] 0011 MWR* 1. Address Cycle Brooktree ® 2. Arbitration Cycle 3. Bus Recovery Cycle 4. Wait Cycle 5. Data Cycle 25 Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4.3.5 Quad Write Burst, No Wait States In Figure 2-14, a quad burst write access to zero-wait-state memory is shown. RAMMODE is logic low, selecting by_8 or by_4 RAM mode. Here PBE[3:0]* is latched on cycle 1, indicating that the write is active on all bytes and the MWE*[3:0] outputs are active as write strobes while MWR* is not used. Note that the local memory word select addresses, LADDR[1,0], are incremented automatically by the Bt8230 on each successive write cycle. Although the i960 architecture has the limitation that a quad word transfer must start on a quad word boundary, the Bt8230 does not have that limitation, the PADDR[1,0] bits may be any value and are incremented as long as the burst transfer proceeds. Figure 2-14. Local Processor Quad Write, No Wait States ta SYSCLK tarb 1 tbr 2 td 3 td td 4 td 5 6 7 D1 D2 D3 01 10 11 PCS* PAS* PWNR PBSEL[1,0] 01 PADDR[1,0] 00 PBE[3:0] 0000 DT/R* PWAIT* PBLAST* PRDY* D[31:0] D0 A[20:4] Address LADDR[18:2] Address 00 LADDR[1,0] LDATA[31:0] D3 D2 D1 D0 PDAEN* 1011 MCS*[3:0] MOE* RAMMODE MWE*[3:0] F 1. Address Cycle 26 2. Arbitration 3. Bus Recovery Cycle Cycle 0 4. Data0 Cycle F 0 5. Data1 Cycle F 0 6. Data2 Cycle F 0 F 7. Data3 Cycle Brooktree ® Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4.4 i80960CA/CF Processor Interface Figure 2-15 illustrates the signal interface between the Bt8230 device and the i960CA/CF processor. The memory region decoded for PCS* should be set for NRAD and NWAD = 2, NRDD and NWDD = 0 or 1 depending on the use of zero or one wait state SRAM, and NXDA = 1. In addition, external ready control must be enabled and burst may be enabled or disabled at the system designers option. Pulling up the i960 CLKMODE input to a logic one selects the divide-by-one clock mode, making i960 PCLK synchronous to SYSCLK. Figure 2-15. i960CA/CF to the Bt8230 Interface i960CA/CF Bt8230 PCS* PROCMODE SYSCLK PRST* PINT* PFAIL* PAS* PWNR PWAIT* PBLAST* PRDY* PBE[3:0]* PBSEL[1,0] PADDR[0] PADDR[1] GND LDATA[31:0] Decode A[31:28] Pullup D[31:0] DT/R* x32 Xcvr PDAEN* LADDR[18:2] CLKMODE CLKIN RESET* XINT0 FAIL* AS* W/R* WAIT* BLAST* READY* BE[3:0]* A[22:21] A[2] A[3] A[20:4] x17 Buff(1) NC PCLK MOE* MWE[3:0]* MCS[3]* MCS[2]* MCS[1]* MCS[0]* SRAMCS* SRAMCS* SRAMCS* SRAMCS* LADDR[1] LADDR[0] MWR* RAMMODE SRAM OE WE[3:0] For by_16 SRAM GND for by_8 or by_4, VCC for by_16 D[31:0] A[18:2] A[1] A[0] Note (1): Required for full 8 MByte address range Brooktree ® 27 Bt8230 2.0 Functional Description 2.4 Local Processor Interface This configuration is for addressing the entire 8 MB of SRAM. In the majority of systems, the SRAM requirements will be considerably less. The implications of this are that the PBSEL[1,0] inputs may be driven by lower order address lines and there will be less than 17 address lines to buffer. Therefore, in most applications, the data transceivers may utilize two x16 parts, such as a 74ABT16245 74ABT16245, and the address buffer may utilize a single x16 74ABT16244 74ABT16244. NOTE: The i960CA/CF signals a failure of its internal self-test upon reset or power-up by asserting its FAIL* output. This line is connected to the PFAIL* pin of the Bt8230, and the status of this pin is reflected in the Host Interrupt Status Register [HOST_ISTAT0;0xC0]. 2.4.5 i80960Jx Operating Mode The major difference between the i80960Jx processor and the i80960CA is that the Jx utilizes a multiplexed address/data bus structure while the CA/CF is nonmultiplexed. However, in the Bt8230 system. The demultiplexing of address/data takes place on the processor side of the address buffers and, therefore, does not affect the Bt8230. Otherwise, the Jx has the same bus control signals as the CA/CF with the exception of the WAIT* signal, which the Jx does not possess. The insertion of wait states, if required, must be accomplished by an external memory controller which in any case, is required for a Jx implementation. 2.4.6 Stand-Alone Operation Stand-alone interface pins and descriptions are given in Table 2-3. Figure 2-16 shows the signal interface between the Bt8230 and the Bt8222 ATM receiver/transmitter device with no local processor. The PCS*, PAS*, and PWNR pins are now outputs providing chip select, address strobe, and write/read control to the Bt8222. PDAEN* is now an input connected to the interrupt sources of the Bt8222. PBLAST* is a second chip select which may be used to connect a future Brooktree T1/E1 framer since the Bt8222 does not contain this function. The PRDY* output is active and indicates the cycles in which the data transaction occurs. The PWAIT* input is active and may be used to prolong the cycle as shown in Figure 2-17. Physical interface devices other than the Bt8222 may be connected by using PWAIT* to extend the read or write cycle and by using external logic to translate the Bt8230 control signals. 28 Brooktree ® Bt8230 2.0 Functional Description 2.4 Local Processor Interface Table 2-3. Stand-Alone Interface Pins Dir(1) Description PROCMODE I Processor interface mode select input. A logic one enables stand-alone operation without a local processor. PCS* O Chip select output for PHY device number 1. Synchronous to SYSCLK. See Figure 2-6. PBLAST* O Chip select output for PHY device number 2. Synchronous to SYSCLK. See Figure 2-6. PAS* O PHY address strobe. Synchronous to SYSCLK. PWNR O PHY write/read select. A logic one on this output indicates a write cycle, a logic zero indicates a read cycle. Synchronous to SYSCLK. PRDY* O PHY interface ready signal. A logic low on this signal at rising edge of SYSCLK indicates that the data cycle has been completed PWAIT* I PHY wait input. Allows external logic to insert wait states to extend data cycles. Only active when PRDY* is active. PDAEN* I PHY interrupt input, active low, level sensitive(2). PADDR[1,0] I Not used, pull to logic zero. PBSEL[1,0] I Not used, pull to logic zero. PBE[3:0]* I Not used, pull to logic zero. Signal Notes: (1). Direction given with respect to the Bt8230. (2). See the HOST_ISTAT0 Register for details. Brooktree ® 29 Bt8230 2.0 Functional Description 2.4 Local Processor Interface Figure 2-16. Bt8230 to the 8222 Microprocessor Interface (Stand-Alone Operation) Bt8222 Bt8230 PCS* SYSCLK PRST* PDAEN* PFAIL* PAS* PWNR PWAIT* PBLAST* PBE[3:0]* PBSEL[1,0] PADDR[0] PADDR[1] PROCMODE LADDR[18:2] LDATA[31:0] Pullup GND Pullup(1) PHYCS2* to T1/E1 Framer GND GND GND GND Pullup GND OE* A[7:3] D[15:0] A[2] A[1] LADDR[1] LADDR[0] PRDY* CS* PRCLK RESET STAT_INT* DL_INT* AS* W/R* N/C(2) MOE* MWR[3:0]* MCS[3]* MCS[2]* MCS[1]* MCS[0]* SRAMCS* SRAMCS* SRAMCS* SRAMCS* For x16 SRAM MWR* RAMMODE SRAM OE* WE[3:0]* D[31:0] GND for x8 or x4 Pullup for x16 A[18:2] A[1] A[0] Notes: (1). May be driven by external circuitry to extend cycles. (2). May be used by external circuitry. 30 Brooktree ® Bt8230 2.0 Functional Description 2.4 Local Processor Interface Figure 2-17. Bt8230/PHY Functional Timing with Inserted Wait States ta tw 1 tw td 2 3 4 5 SYSCLK PCS* PAS* PWNR PWAIT* PRDY* LADDR[6:0] Write Address LDATA[15:0] Write Data Figure 2-18 shows a read and write Bt8222 access. At cycle 1 (the rising edge of SYSCLK) the Bt8222 samples PCS*, PAS*, and PWNR low, indicating a read cycle. By the next rising edge of SYSCLK at cycle 2, the data is output by the Bt8222 to be latched by the Bt8230. The same procedure occurs for a write except that at cycle 4, PWNR is sampled high. The Bt8222 then latches the data to the appropriate internal register on the next SYSCLK rising edge at cycle 5. Figure 2-18. Bt8230/Bt8222 Read/Write Functional Timing tD tA SYSCLK tD tA 2 1 3 4 5 6 PCS* PAS* PWNR PWAIT* PRDY* LADDR[6:0] Read Address LDATA[15:0] Read Data 1, 2 Read Cycle Brooktree ® Write Address Write Data 4, 5 Write Cycle 31 Bt8230 2.0 Functional Description 2.4 Local Processor Interface 2.4.7 System Clocking The Bt8230 derives all of its timing from a 2x clock input, CLK2X. This clock is internally divided by 2 to create the system clock, SYSCLK. This system clock is used internal to the device and is output to the system to provide the clock to an external processor or PHY device. All processor interface signals are synchronous to SYSCLK. In addition, a CLK2X asymmetrically divided by 3, CLKD3, output is provided and may be used as the clock for the UTOPIA ATM physical interface. Alternatively, SYSCLK may be used as the clock source for the UTOPIA ATM physical interface if the frequency is 25 MHz or less. In either case, the clock signal would be looped externally to the FRCTRL input. For example, if CLK2X is 66 MHz, then CLKD3 is 22 MHz and is suitable for the UTOPIA interface. If CLK2X is 50 MHz, then SYSCLK is 25 MHz and is suitable for the UTOPIA interface. The CLK2X frequency required for a given application is a function of the physical li