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Block Interleaver time

Catalog Datasheet MFG & Type PDF Document Tags

DVB-T Schematic set top box

Abstract: VIRTEX7-XC7VX485T . Unlike the Convolutional Interleaver, where symbols can be continuously input, the Rectangular Block Interleaver inputs one block of symbols and then outputs that same block with the symbols rearranged. No new , -1) The Rectangular Block Interleaver operates as follows: 1. 2. 3. 4. All the input symbols in an entire , . An example of Rectangular Block Interleaver operation is shown in Figure 4. This example has 3 rows , , row and column permutations are not supported. If the block size is less than R * C, the interleaver
Xilinx
Original

vhdl code for interleaver

Abstract: vhdl code for block interleaver Operation The rectangular block interleaver works by writing the input data symbols into a rectangular , continuously input, the rectangular block interleaver inputs one block of symbols and then outputs that same , -2) (C-1) 0 1 : (R-2) (R-1) The rectangular block interleaver operates as follows: 1. All , rectangular block interleaver operation is shown in Figure 4. This example has 3 rows, 4 columns and a block , Interleaver, except for Mode.) Output Data = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11} Figure 7: Block
Xilinx
Original

turbo encoder model simulink

Abstract: vhdl code for interleaver . 802.14 Transmitter & Receiver .27 Block Interleaver Example: UMTS Transmitter & Receiver , .32 Block Interleaver/Deinterleaver , 110 Block interleaver using single-port RAM Block length = 36, Span delay = 20, Data width = , the type of algorithm (convolutional or block) and the direction (interleaver or deinterleaver) and , shows a block diagram of a system using the convolutional interleaver/deinterleaver with a Reed-Solomon
Altera
Original

vhdl code for interleaver

Abstract: vhdl code for block interleaver .9 Block Interleaver/Deinterleaver , a convolutional or a block interleaver/deinterleaver. Convolutional interleaver/deinterleaver , used with Reed-Solomon functions. Block interleaver/deinterleavers process data in a discrete stream , . Data Stream Comparison A A1 B B1 C Convolutional Interleaver A1 Block , Interleaver/Deinterleaver The block interleaver/deinterleaver uses single-port SRAM memory configured as a
Altera
Original

Convolutional Encoder

Abstract: CS3530 encoder, and the interleaver storage supplies the interleaved data block to the second convolutional , address generator requires a certain initialisation time between receiving an updated data block length , the new data block length. While the interleaver is initialising, reading from the interleaver , completes before interleaver initialisation to that new block length. If this condition occurs, the core , Description int_ram_blksel 1 O Interleaver RAM block. Selects between interleaver storage banks
Amphion Semiconductor
Original

Block Interleaver

Abstract: correction. The Lattice Interleaver/de-interleaver IP core supports rectangular block type and convolutional , described in this chapter. Figure 2-1 shows a convolutional interleaver/de-interleaver block diagram. Figure 2-2 shows a rectangular interleaver/de-interleaver block diagram. Block Diagrams Figure 2-1. Convolutional Interleaver/De-interleaver Block Diagram rstn dout clk obstart din ibstart inpvalid , Pins zeronewblk sr Figure 2-2. Rectangular Interleaver/De-interleaver Block Diagram rstn
Lattice Semiconductor
Original

Interleaver-De-interleaver

Abstract: interleaver Block Diagrams Figure 1. Convolutional Interleaver/De-interleaver Block Diagram rst_b d_out clk , Figure 2. Rectangular Interleaver De-interleaver Block Diagram rst_b d_out clk first_dout , correction. The Lattice Interleaver/De-interleaver IP Core supports rectangular block type and convolutional , output data {1, 2, 3,.,20}. The block interleaver reads in one block of symbols and then outputs the , Interleaver/De-interleaver IP Core December 2003 IP Data Sheet Full Handshake Capability
Lattice Semiconductor
Original

32-Bit Parallel-IN Serial-OUT Shift Register

Abstract: 32-Bit sipo Shift Register receiver, because the phases are B instead of B x N, where B is the number of block interleaver rows and N is the number of block interleaver columns. D_IN 0 1 1 2 2 31 S/P 0 31 , convolutional interleaver technique is used in telecommunication applications such as SDH and PDH radio systems , transmission channels from noise. On the transmit side, the convolutional interleaver parallelizes serial , interleavers (block or convolutional) are popular techniques for protecting data from noise. Interleavers are
Xilinx
Original

vhdl code for interleaver

Abstract: transistors BC 543 a block interleaver/de-interleaver. Convolutional interleaver/de-interleaver functions process data , functions. Block interleaver/de-interleavers process data in a discrete stream and are used in , A A1 B B1 C Convolutional Interleaver A1 Block Interleaver C1 A1 B1 , Interleaver/De-Interleaver The block interleaver/de-interleaver uses single-port SRAM memory configured as a , the span) is the interleaver delay. Figure 3 illustrates block function operation using a 6
Altera
Original

convolutional interleaver

Abstract: Convolutional shows a functional block diagram of the convolutional interleaver megafunction. Figure 1. Convolutional Interleaver Megafunction Functional Block Diagram Convolutional Interleaver Megafunction , Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal , www.ktechtelecom.com March 1997, ver. 1 s s s s Implements a convolutional interleaver function Accepts a , cable modems General Description The convolutional interleaver megafunction implements a
Altera
Original

3GPP turbo decoder log-map

Abstract: sova requires a certain initialisation time between receiving an updated data block length from the , block. Selects between interleaver storage banks. Low when data writes should be applied to bank 0 , Input De-puncture De-interleaver Interleaver Decoder 2 Decoder 1 Figure 1: A Turbo Decoder Overview Diagram FEATURES Supports full range of W-CDMA and CDMA2000 data block lengths , Up to four different block length and coding rate combinations can be pre-loaded to the
Amphion Semiconductor
Original
CS3630 3GPP turbo decoder log-map sova Turbo Decoder satellite turbo decoder Turbo Decoder wcdma sova Iterative Decoding for turbo codes DS3630

Implementation of convolutional encoder

Abstract: DN504 FEC with something so that a full interleaver block can be transmitted. Our FEC implementation appends , sequences are used to terminate the trellis and the rest are used to fill up the last interleaver block , of FEC: linear block codes (BCH, Reed-Solomon, etc) and convolutional codes. An (n,k) linear block encoder takes k-bit block of message data and appends n-k redundant bits algebraically related to the k message bits, producing a n-bit code block. There are 2k valid code words, which is far less than the 2n
Texas Instruments
Original
DN504 CC1100 CC1101 CC1110 CC1150 CC2500 Implementation of convolutional encoder DN504 FEC design for block interleaver deinterleaver Convolutional viterbi algorithm Block Interleaver CC1111

block convolutional interleaving

Abstract: convolutional interleaver shows a functional block diagram of the convolutional interleaver megafunction. Figure 1. Convolutional Interleaver Megafunction Functional Block Diagram Convolutional Interleaver Megafunction , Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal , www.ktechtelecom.com March 1997, ver. 1 s s s s Implements a convolutional interleaver function Accepts a , cable modems General Description The convolutional interleaver megafunction implements a
Altera
Original
EPF10K10 EPF8452A EPM9320 EPF10K100 block convolutional interleaving convolutional interleaver

vhdl code for ofdm

Abstract: ofdm matlab simulation block 744 V1.5.1 (2004-11) specifies a block based bit interleaver concatenated with a symbol interleaver , Energy Dispersal Outer Coder Inner Coder Inner Interleaver Mapper Guard Interval , Flags Figure 1: MW_DVB-T/H Modulator Core Block Diagram Applications DVB Terrestrial/Handheld , supplied to an external upconverter. Functional Description Energy Dispersal This block receives an , 300 744 V1.5.1 (2004-11).This block inverts a sync byte every eight sync byte received.The polynomial
Xilinx
Original
vhdl code for ofdm ofdm matlab simulation block vhdl code for 16 prbs generator prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for block interleaver

vhdl code for ofdm

Abstract: vhdl code for ofdm transmitter V1.5.1 (2004-11) specifies a block based bit interleaver concatenated with a symbol interleaver. If , Inner Coder Inner Interleaver Mapper Frame Adaptation Linear Magnitude Precorrection , /H_P Modulator Core Block Diagram Applications DVB Terrestrial/Handheld Transmission Systems , upconverter. Functional Description Energy Dispersal This block receives an MPEG-2 transport packet and , block inverts a sync byte every eight sync byte received.The polynomial for the pseudo random binary
Xilinx
Original
vhdl code for ofdm transmitter OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation VHDL PROGRAM for ofdm OFDM matlab program CODES

mcm6306

Abstract: ONU block diagram interleaver block spreads the blocks of payload data over a large period of time. Transmitting interleaved , codes. Interleaver block and 12 payload blocks. It transmits a serial data stream along with a , of errors in each block. Frame Header Interpretation Block The interleaver separates the data , =0 effectively disables the interleaver. The data link extraction block optionally provides the data link , . The block is then sent to the interleaver. Frame headers are generated internally. The frame
Motorola
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MC92053 mcm6306 ONU block diagram MCM6206 interleaver time datasheet Reed-Solomon Decoder MC68360 MC92053/D

VHDL code for interleaver block in turbo code

Abstract: vhdl code for interleaver ) Includes 3GPP-compliant mother interleaver Interleaver block sizes from 40 to 5,114 bits Block size can change between each block Soft values (logarithmic likelihood) from 3 to 8 bits Optional two memory , . Figure 1 shows a basic block diagram of the turbo encoder/decoder function. Figure 1. Turbo Encoder/Decoder Block Diagram Turbo Encoder Turbo Decoder Information Bits Received Information Bits Transmitted InformationBits max-logMAP Decoder 1 Interleaver Channel Encoder 1 De-puncture
Altera
Original
VHDL code for interleaver block in turbo code vhdl code for interleaver vhdl code for turbo decoder verilog code for parallel turbo interleaver by vhdl design for convolutional interleaver deinterleaver

R02 motorola 2903

Abstract: AMCC STS-192 -192 SONET/SDH Interleaver/Disinterleaver Product Brief Part Number S19201CAI12, Revision 2.9, March 2003 , Figure 1: Block Diagram MX_TOH_FRAME_OUT DX_REF_CLK_OUT MX_TOH_DATA-IN MX_TOH_CLK_OUT RDYB , _[1:4]_[15:0] MX_CLK_OUT MX_DATA_OUT_[15:0] FRGEN192 X TOH MONITOR Interleaver BUFF x4 , ] DX_TOH_INS_FRAME DX_TOH_DATA_OUT DX_TOH_CLK_OUT DX_TOH_INS_CLK INDUS STS-192 SONET/SDH Interleaver , :// S19201CAI12: INDUS Revision 2.5 - March 2003 S19201 STS-192 INTERLEAVER/DISINTERLEAVER DATASHEET
Applied Micro Circuits
Original
R02 motorola 2903 AMCC STS-192 108 046f STS-48/STM16 STS-192/STM-64 STS-48/STM-16 STS-48 STS-12

rsc Encoder

Abstract: convolutional encoder interleaving design. Dual Port RAM and Interleaver Module The dual port RAM module stores the incoming data block , the block. The interleaver is a mapping between input and output bit positions and involves a , C.S0002-A - CCSDS 101.0-B-5 Up to 60 MHz Clock Speed Variable Input Block Sizes User Defined Number , separate entity as the interleaver and control logic for each encoder is completely different. Fixed , secured simulation model - Behavioral testbench Block Diagram Figure 1. Turbo Encoder Block Diagram
Lattice Semiconductor
Original
LFX500B-04F516C LFEC20E-5F672C rsc Encoder convolutional encoder interleaving Turbo Encoder interleaver ccsds

convolutional interleaver

Abstract: ipad Convolutional Interleaver The Convolutional Interleaver block sits between the output of the Outer Coder and , Coder The Inner Coder block sits between the output of the Convolutional Interleaver and the input to , .1.2 · Byte wide data path · Test points at the output of each block and at the input to the Baseband Shaping block · 204/188 Reed-Solomon Outer Coder · Selectable convolutional code rates , =8) Convolutional Interleaver: Forney I=12, M=17 Inner Coder: Convolutional Rate 1/2, K=7 Punctured to 2/3
Memec Design
Original
ipad block interleaver in modelsim randomizer solomon Block Interleaver time EN-300-421 digital FIR Filter verilog HDL code
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