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PCI1510RGVF Texas Instruments PCMCIA BUS CONTROLLER, PBGA253, PLASTIC, BGA-253 visit Texas Instruments
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Bellcore-GR-253

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Provides on-chip clock and data recovery and clock synthesis Exceeds Bellcore-GR-253 jitter requirements -
OCR Scan
cd 1619 PM5357 S/UNI-622-POS 100MH OC-12
Abstract: PM5349 S/UNI- 155-QUAD Preliminary Information Quad 155 Mbit/s ATM Physical Layer Device FEATURES ATM PROCESSOR synchronization status byte (S1) GENERAL · Counts received section BIP-8 (B1), line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs · Quad channel ATM OC-3c (155 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis · Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI · Exceeds Bellcore-GR-253 jitter tolerance and PMC-Sierra
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PMC-980863 LASAR-155 S/UNI-155-QUAD
Abstract: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES microprocessor interface for device control and register access · Provides standard IEEE 1149.1 JTAG test port for boundary scan GENERAL · ATM and Packet over SONET/SDH (POS) OC-12c (622 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis · Exceeds Bellcore-GR-253 jitter requirements · Inserts and extracts ATM cells or POS packets into/from SONET SPE · PMC-Sierra
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CRC-32 TERR PMC-981280
Abstract: PMC-Sierra,Inc. PM5356 S/UNI-622-MAX Preliminary 622 Mbit/s ATM Physical Layer Device FEATURES · Counts received section BIP-8 (B1), line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs. · Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI. · Provides divide by 8 recovered clock. · Provides 8 KHz receive frame pulses. GENERAL · ATM OC-12c (622 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis. · Exceeds Bellcore-GR-253 PMC-Sierra
Original
rfpo PMC-981279
Abstract: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES microprocessor interface for device control and register access · Provides standard IEEE 1149.1 JTAG test port for boundary scan GENERAL · ATM and Packet over SONET/SDH (POS) OC-12c (622 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis · Exceeds Bellcore-GR-253 jitter requirements · Inserts and extracts ATM cells or POS packets into/from SONET SPE · PMC-Sierra
Original
Abstract: Bellcore-GR-253 jitter requirements. · Provides a generic 8-bit microprocessor interface for device PMC-Sierra
Original
BIP-8
Abstract: Bellcore-GR-253 jitter requirements. · Provides a generic 8-bit microprocessor interface for device PMC-Sierra
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radr
Abstract: Bellcore-GR-253 jitter requirements. · Provides a generic 8-bit microprocessor interface for device PMC-Sierra
Original
Abstract: Exceeds Bellcore-GR-253 jitter requirements. · Inserts and extracts ATM cells or POS packets into/from PMC-Sierra
Original
PM5352 S/UNI-155-STAR PMC-991722
Abstract: PM5351 S/UNI-155-TETRA PMC-Sierra,Inc. Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device FEATURES · Quad channel ATM and Packet over SONET OC-3c (155 Mbit/s) PHY. · Provides on-chip clock and data recovery and clock synthesis. · Exceeds Bellcore-GR-253 jitter requirements. · Inserts and extracts ATM cells or POS packets into/from SONET SPE. · Filters and captures Automatic Protection Switch byes (K1 and K2) and detects APS byte failure. · Detects signal degrade and PMC-Sierra
Original
tetra system block diagram STM-1 Physical interface PHY PMC-1980862
Abstract: PMC-Sierra,Inc. PM5351 S/UNI-155-TETRA Preliminary Quad 155 Mb/s ATM and Packet Over SONET/SDH Physical Layer Device FEATURES · Quad channel ATM and Packet over SONET OC-3c (155 Mb/s) PHY. · Provides on-chip clock and data recovery and clock synthesis. · Exceeds Bellcore-GR-253 jitter requirements. · Inserts and extracts ATM cells or POS packets into/from SONET SPE. · Filters and captures Automatic Protection Switch byes (K1 and K2) and detects APS byte failure. · Detects PMC-Sierra
Original
CRC32 PMC-980862
Abstract: Exceeds Bellcore-GR-253 jitter requirements. · Inserts and extracts ATM cells or POS packets into/from PMC-Sierra
Original
Abstract: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES microprocessor interface for device control and register access · Provides standard IEEE 1149.1 JTAG test port for boundary scan GENERAL · ATM and Packet over SONET/SDH (POS) OC-12c (622 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis · Exceeds Bellcore-GR-253 jitter requirements · Inserts and extracts ATM cells or POS packets into/from SONET SPE · PMC-Sierra
Original
Abstract: PM5356 S/UNI-622-MAX PMC-Sierra,Inc. 622 Mbit/s ATM Physical Layer Device FEATURES · Counts received section BIP-8 (B1), line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs. · Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI. · Provides divide by 8 recovered clock. · Provides 8 KHz receive frame pulses. GENERAL · ATM OC-12c (622 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis. · Exceeds Bellcore-GR-253 jitter tolerance PMC-Sierra
Original
THE ATM PHYSICAL LAYER ATM circuit diagram TSOC PMC-1981279
Abstract: PM5351 Preliminary Information S/ UNI- 155-TETRA Quad 155 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES · Provides a generic 8-bt microprocessor interface for device control and register access GENERAL · Quad channel ATM and Packet over SONET OC-3c (155 Mbit/s) PHY · Provides standard IEEE 1149.1 JTAG test port for boundary scan · Provides on-chip clock and data recovery and clock synthesis ATM · Exceeds Bellcore-GR-253 jitter requirements · PMC-Sierra
Original
RLD14 TXC14 RSD14 RXD14
Abstract: FD H A S t , c , F I'/lv _ lsrra' "c' Preliminary PM5356 S/UNI-622-MAX 622 Mbit/s ATM Physical Layer Device FEATURES GENERAL · ATM OC-12c (622 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis. · Exceeds Bellcore-GR-253 jitter tolerance and transm it jitter requirements. · Provides a generic 8-bit microprocessor interface for device control and register access. · Provides standard IEEE 1149.1 JTAG test port for boundary scan. · Counts received section BIP-8 (B1), line -
OCR Scan
S/UNI-622-M
Abstract: Characteristic Table. Jitter Tolerance The VSC8101 and VSC8102 are designed to meet the BellcoreGR-253-CORE Vitesse Semiconductor
Original
28PLCC-JEDEC LT1086 REG1117 VSC8101/8102 28PLCC 100PQFP G52087-0 VSC8101JA VSC8102QB
Abstract: are designed to meet the BellcoreGR-253-CORE, section 5.6.2.2.2 litter Tol erance specification -
OCR Scan
VITESSE VSC8 YSC8102
Abstract: designed to meet the BellcoreGR-253-CORE, section 5.6.2.2.2 Jitter Tol­ erance specification. Figure 1 -
OCR Scan
T502331
Abstract: are designed to meet the BellcoreGR-253-CORE, section 5.6.2.2.2 Jitter Tol erance specification -
OCR Scan
I-1121
Abstract: Bellcore-GR-253 jitter requirements. · Provides a generic 8-bit microprocessor interface for device OptronX
Original
OPX10G200S-SR113U-SC1 OPX10G200S-IR113U-SC1 OPX10G300S-SR113U-SC1 OPX10G300S-IR113U-SC1 lvds connector 31 pin GR253 OC-192 OPX-010 622MH 155/622MH
Abstract: PM5357 S/UNI-622-POS PMC-Sierra,Inc. 622 Mbit/s ATM and Packet Over SONET Physical Layer Device FEATURES microprocessor interface for device control and register access · Provides standard IEEE 1149.1 JTAG test port for boundary scan GENERAL · ATM and Packet over SONET/SDH (POS) OC-12c (622 Mbit/s) PHY · Provides on-chip clock and data recovery and clock synthesis · Exceeds Bellcore-GR-253 jitter requirements · Inserts and extracts ATM cells or POS packets into/from SONET SPE · Cypress Semiconductor
Original
T1X15 National Standards Institute ncp 1662 POS-PHY ATM format CY7C9537B OC-48/STM-16 OC-48/STS-48/STM-16 OC-12/STS-12/STM-4 707/Y OC-48
Abstract: PM5351 S/UNI-155-TETRA PMC-Sierra,Inc. Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device FEATURES · Quad channel ATM and Packet over SONET OC-3c (155 Mbit/s) PHY. · Provides on-chip clock and data recovery and clock synthesis. · Exceeds Bellcore-GR-253 jitter requirements. · Inserts and extracts ATM cells or POS packets into/from SONET SPE. · Filters and captures Automatic Protection Switch byes (K1 and K2) and detects APS byte failure. · Detects signal degrade and Cypress Semiconductor
Original
CYS25G0101DX OC48 OC-12/STM-4 9537B 0101D