BS2M18 PQ208 IEEE1149 QL6250-PQ208 QL6250 QL6250-6P T280C - Datasheet Archive

 

Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Slave to Utopia Level 1 Master Bridge

 

BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Slave to Utopia Level 1 Master Bridge Datasheet 1 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 CONTENTS 1 INTRODUCTION . 3 1.1 2 UTOPIA OVERVIEW . 3 UTOPIA L2 SLAVE TO L1 MASTER BRIDGE APPLICATION . 4 UTOPIA LEVEL 2/1 BRIDGE CORE FEATURES. 5 3 APPLICATION. 6 4 CORE PINOUT . 7 4.1 SIGNAL DESCRIPTIONS . 8 5 GLOBAL SIGNAL DISTRIBUTION . 12 6 FUNCTIONAL DESCRIPTION ­ UTOPIA INTERFACE . 13 6.1 UTOPIA INTERFACE SINGLE PHY TRANSMIT INTERFACE (L1) . 13 Cell Level Transfer ­ Single Cell . 13 Cell Level Transfer ­ Back to Back Cells.13 6.2 UTOPIA INTERFACE SINGLE PHY RECEIVE INTERFACE (L1) . 14 Cell Level Transfer ­ Single Cell . 14 Cell Level Transfer ­ Back to Back Cells.15 6.3 UTOPIA INTERFACE MPHY TRANSMIT (L2) . 16 MPHY Operation with Direct Status. 16 6.4 UTOPIA INTERFACE MPHY RECEIVE (L2) . 17 MPHY Operation with Direct Status. 17 7 CORE MANAGEMENT AND ERROR HANDLING . 18 8 COMPLEXITY AND PERFORMANCE SUMMARY. 19 8.1 8.2 9 TIMING PARAMETERS DEFINITION . 19 ECLIPSE IMPLEMENTATION . 20 DEVICE PINOUT . 21 9.1 9.2 9.3 9.4 9.5 SIGNALS OVERVIEW . 21 PQ208 PQ208 PINOUT TABLE . 22 PQ208 PQ208 DEVICE DIAGRAM . 23 280 PIN FPBGA PINOUT TABLE. 24 280 PIN FPBGA DEVICE DIAGRAM . 25 10 REFERENCES . 26 11 CONTACT . 26 2 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 1 Introduction 1.1 Utopia Overview The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by the ATM Forum to provide a standard interface between ATM devices and ATM PHY or SAR (segmentation and Re-assembly) devices. Higher Layers Management AAL Master Utopia Slave ATM Master Utopia Slave PHY Figure 1: Utopia Reference Model The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The Slave interface responds to the requests from the Master. The Master performs PHY arbitration and initiates data transfers to and from the Slave device. The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps (L2) to 3.2Gbit/s (L3). The following Table 1 gives an overview of the main differences in these three levels. Table 1: Utopia Level Differences Utopia Level Interface Width Max. Interface Speed Theoretic (typical) Throughput 1 8 bit 25 MHz 200Mbps (typ. OC3 155Mbps) 2 8 bit, 16 bit 50 MHz 800Mbps (typ. OC12 622MBps) 3 8 bit, 32 bit 104MHz 3.2Gbps (typ. OC 48 2.5GBps) Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16 Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the interface. 3 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to physically share a single interface bus between one master and up to 31 slave devices (Multi-PHY or MPHY operation). This allows the implementation of aggregation units that multiplex several slave devices to a single Master device. The Level 1 and Level 3 are point-to-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion of multiple slaves, but they must be implemented in a single physical device connected to the Utopia Interface. 2 Utopia L2 Slave to L1 Master Bridge Application Utopia Level 2 offers the notion of multiple PHYs (MPHY) and a shared bus topology to connect several PHY devices to an ATM Layer device. The L2 Slave to L1 Master bridge implements the necessary interfaces enabling to connect Level 1 PHY devices to such a Level 2 topology. Each Bridge still implements a single Port, but it can be addressed individually using the Level 2 MPHY protocol. Utopia Slave Utopia Master Utopia Slave PHY Device 0 Bridge * Utopia Master * * ATM Layer Device Utopia Slave Utopia Master Utopia Slave PHY Device N Bridge Utopia Level 2 shared bus Utopia Level 1 Figure 2: Utopia Shared Bus Topology 4 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 Utopia Level 2/1 Bridge Core Features · Implements an Utopia L2 Slave and Utopia L1 Master providing a solution to bridge Utopia Level 1 Slave devices to a Level 2 Master · Compliant with ATM-Forum af-phy-0039.000 (Level 2) and af-phy-0017.000 (Level 1) · Implements 8bit data busses · Level 2 interface implements a single PHY using MPHY mode with direct status indication · Level 2 interface meets 50MHz performance offering up to 400Mbps cell rate transfers · Level 1 interface meets 25MHz performance offering up to 200Mbps cell rate transfers · Single chip solution for improved system integration · Supports cell level transfer mode · Cell and clock rate decoupling with on chip FIFOs · Up to 2 KByte of on chip FIFO per data direction · Integrated management interface and built-in errored cell discard · ATM Cell size programmable via external pins from 16 to 128 bytes · Level 2 MPHY address programmable via external pins · Optional Utopia parity generation/checking enable/disable via external pin · Built in JTAG port (IEEE1149 IEEE1149 compliant) · Simulation model available for system level verification (Contact Quicklogic or MorethanIP for details) · Solution also available as flexible Soft-IP core, delivered with a full device modelization and verification testbenches. 5 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 3 Application Slave TxClk TxData[31:0] TxSoc Egress Port TxClav TxEnb* TxAddr[4:0] TxEnb* TxAddr[4:0] Master Egress Port TxClk TxClav TxData[7:0] Ing. Port RxData[7:0] RxSoc RxClk ATM Device 1 RxClav RxEnb* RxEnb* RxAddr[4:0] RxClk TxData[7:0] TxSoc RxClav RxEnb* Slave L1 TxClav TxEnb* TxSoc RxClav RxClav RxEnb* RxAddr[4:0] RxData[31:0] RxSoc TxClk TxClk TxClav TxEnb* TxData[7:0] TxSoc Ing. Port Master RxData[7:0] RxSoc RxData[7:0] RxSoc RxClk RxClk Device 2 Slave/Master Bridge Figure 3: Slave/Master Bridge converting Utopia Levels Data flows from the Bridge's TX Ports to the corresponding TX Port on the other side of the bridge and the RX Port to the RX Port accordingly. The following figure shows an application using two bridges to connect two PHY devices to a single, dual-PHY master device. The cell-available signals of the two slaves are connected to the according ports of the master (direct status indication). The two bridges would usually have the addresses 0 and 1 set to each other. rxclav[0] txclav[0] Utopia Slave Utopia Master Utopia Slave PHY Device 0 Bridge (waddr := 0) rxclav[0] rxclav[1] Utopia Master shared TX and RX data and address busses txclav[0] txclav[1] ATM Layer Device: 2 PHY support with direct status indication rxclav[0] txclav[0] Utopia Slave Utopia Master Utopia Slave Bridge (waddr := 1) Utopia Level 2 Utopia Level 1 Figure 4: Dual PHY application 6 PHY Device 1 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 4 Core Pinout On the Utopia interfaces, the Core implements all the required Utopia signals and provides all the Utopia optional signals (Indicated by an `O' in the following tables). The optional Utopia signals are activated during the Core configuration and inactive Utopia signals should be left unconnected (Outputs) or tied to a zero logic level (inputs) as specified in the following Tables. In addition to the Utopia Interface signals, error indication signals are available for error monitoring or statistics. An error indication always shows that a cell has been discarded by the bridge. Possible errors are parity or cell-length errors on the receive interface of the corresponding Utopia Interfaces. All Utopia interfaces work in the same transfer mode (cell level). A mix is not possible. To identify the sides of the core the notion "WEST" and "EAST" for the corresponding interfaces is used. WEST EAST Slave Interface (L2) Master Interface (L1) wtxclav[3:0] Utopia Transmit etxclav etxenb wtxenb wtxaddr[4:0] etxdat[7:0] wtxdat[N:0] wtxsoc wtxprty Egress Egress Utopia Receive wrxclav[3:0] Utopia L2 Slave/ Utopia L1 Master Bridge erxclk erxclav erxenb wrxenb erxdat[7:0] wrxaddr[4:0] wrxdat[N:0] wrxsoc wrxprty Error Indication from Transmit etxsoc etxprty etxclk wtxclk wrxclk Utopia Transmit Ingress Ingress erxsoc erxprty erx_err erx_err_stat[1:0] wtx_err wtx_err_stat[1:0] waddr[4:0] prty_en reset Utopia Receive Error Indication from Receive Configuration cellsize[7:0] Figure 5: Utopia Level 2 Slave to Level 1 Master Bridge Top Entity 7 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 4.1 Signal descriptions Table 2: Global Signal Pin Mode reset In Description Active high chip reset. Table 3: Device Management Interface Pin wtx_err Mode Out Description Transmit error indication on west interface. When driven high, indicates that an errored cell (Wrong parity or wrong length) was received from the device connected to the west interface and is discarded. Transmit error status information for west interface. When wtx_err is driven, indicates the error status of the discarded cell: · wtx_err_stat(1:0) erx_err(n) Out Out wtx_err_stat(0) : When set to `1' indicates that a cell is discarded because of a parity error. · wtx_err_stat(1) : When set to `1' indicates that a cell is discarded because it has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia interface within less than a complete cell time). Receive error indication on east interface. When driven high, indicates that an errored cell (Wrong parity or wrong length) was received from the device connected to the east interface side. Receive error status information for east receive interface. When etx_err is driven, indicates the error status of the discarded cell: · erx_err_stat(n)(1:0) Out etx_err_stat(0) : When set to `1' indicates that a cell is discarded because of a parity error. · etx_err_stat(1) : When set to `1' indicates that a cell is discarded because it has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia interface within less than a complete cell time). Note: wtx_. signals are sampled with west transmit clock (wtxclk). erx_. signals are sampled with west receive clock (wrxclk). Table 4: West Utopia Level 2 Slave Transmit Interface Pin Mode Description wtxclk In 50MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk rising edge. wtxdata[N:0] In Transmit data bus. The width of the data bus is be 8 Bit. N is the MSB. 8 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. wtxprty(O) In wtxsoc In Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. wtxenb In Active low transmit data transfer enable. wtxclav[0] wtxclav[3:1] (O) Out Out When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be tied to '0'. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected during the Core configuration, one txclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. Not used and not available. wtxaddr[4:0] In Utopia transmit address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. Note: (O) indicates optional signals. Table 5: West Utopia Level 2 Slave Receive Interface Pin Mode wrxclk In 50MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. wrxdata[N:0] Out Receive data bus. The width of the data bus is 8 bit. Bit N is the MSB. wrxprty (O) Out wrxsoc Out wrxenb In wrxclav[0] Out Description Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. Receive start of cell. Asserted to indicate that the current word is the first word of a cell. Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. 9 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 wrxclav[3:1] (O) Out Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected, one rxclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. Not used and not available. wrxaddr(4:0) In Utopia receive address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. Table 6: East Utopia Level 1 Master Transmit Interface Pin Mode etxclk In etxdata[7:0] Out Description 25MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk rising edge. Transmit data bus. The width of the data bus is 8 bit. Bit N is the MSB. Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. etxprty(O) Out etxsoc Out Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. etxenb Out Active low transmit data transfer enable. etxclav In When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be left open. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. Note: (O) indicates optional signals. Table 7: East Utopia Level 1 Master Receive Interface Pin Mode erxclk In 25MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. erxdata[7:0] In Receive data bus. The width of the data bus can be 8 or 16bit. Bit N is the MSB. erxprty (O) In erxsoc In Description Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. Receive start of cell. Asserted to indicate that the current word is the first word of a cell. 10 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 erxenb erxclav Out In Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. Table 8: Device Configuration Pins Pin Mode Description waddr[4:0] In Programs the Utopia L2 Slave address used on the west interfaces (tx and rx). Enable parity checking on the Utopia interface. prty_en In cellsize[7:0] In If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and the rx parity input should be tied to 0. Also the tx parity pins can be left open. Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by board wiring. The configuration pins are not intended for change during operation. They are usually board wired to configure the device for operation. 11 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 5 Global Signal Distribution The externally provided Utopia Transmit and Receive clocks are connected to global resources to provide low skew and fast chip level distribution. In both data directions, the two corresponding Utopia Interfaces are decoupled by asynchronous FIFOs. Therefore each interface runs completely independently each at its own tx and rx clocks which typically are up to 50 MHz on the WEST and up to 25 MHz on the EAST interface. The Error indications of the two receive interfaces are always sampled within the west clock domains. The errors of the east rx interface is available on the erx_err signal, which is handled using the west clock domain (wrxclk). The west tx (receiving) error is directly derived from the west tx block (wtxclk). wrxclk WEST Interface (SLAVE) EAST Interface (MASTER) ~ read erxclk ~ write (Ingress clock) RX RX erx_err wtxclk ~ write etxclk ~ read (Egress clock) TX TX wtx_err Clocks West Clocks East Figure 6: Slave/Master Bridge Clock Distribution 12 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 6 Functional Description ­ Utopia Interface The Utopia Bridge implements a single port. The West Interface (Utopia L2) operates in MPHY mode with direct status indication. This offers to connect up to 4 bridges to a single Master (exceeding the Utopia L2 bus bandwidth). It implements a single clav signal per direction (clav[0]) and the address bus to select the device within a shared bus topology. The East Interface (L1) has no notion of MPHY. It has a single clav signal and no address bus. 6.1 Utopia Interface Single PHY Transmit Interface (L1) The Transmit interface is controlled by the Master. The transmit interface has data flowing in the same direction as the ATM enable ut_tx_enb. The ATM transmit block generates all output signals on the rising edge of the ut_txclk. Transmit data is transferred from the Master to Slave via the following procedure. The Slave indicates it can accept data using the ut_txclav signal, then the Master drives data onto ut_txdat and asserts ut_txenb. The Slave controls the flow of data via the ut_txclav signal. Cell Level Transfer ­ Single Cell The Slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole cell. The Master asserts ut_txenb (Low) to indicates that it drives valid data to the Slave 2. Together with the first octet of a cell, the Master device asserts ut_txsoc for one clock cycle 3. To ensure that the Master does not cause transmit overrun, the Slave deasserts ut_txclav at least 4 cycles before the end of a cell if it cannot accept the immediate transfer of the subsequent cell 4. The Master can pause the cell transfer by de-asserting ut_txenb 5. To complete the transfer to the Slave, the Master de-asserts ut_tx_enb 6. 4 1 2 6 5 3 ut_txclk ut_txclav_dir ut_txenb ut_txsoc /ut_txdat 1 1 19 1A 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 ut_txprty Figure 7: Single Cell Transfer ­ Cell Level Transfer Cell Level Transfer ­ Back to Back Cells When, during a cell transfer, the Slave is able to receive a subsequent cell, the Master can keep ut_txenb asserted between two cells 1 and asserts ut_txsoc, to start a new cell transfer, immediately after the last octet of the previous cell 2. 13 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 1 2 ut_txclk ut_txclav ut_txenb ut_txsoc ut_txdat 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 0000 ut_txprty Cell N Cell N+1 Figure 8: Back to Back Cell Transfer ­ Cell Level Transfer 6.2 Utopia Interface Single PHY Receive Interface (L1) The Receive interface is controlled by the Master. The receive interface has data flowing in the opposite direction to the Master enable ut_rxenb. Receive data is transferred from the Slave to Master via the following procedure. The Slave indicates it has valid data, then the Master asserts ut_rxenb to read this data from the Slave. The Slave indicates valid data (thereby controlling the data flow) via the ut_rxclav signal. Cell Level Transfer ­ Single Cell The Slave asserts ut_rx_clav when it is ready to send a complete cell to the Master device 1. The Master interface asserts ut_rxenb to start the cell transfer. The Slave samples ut_rxenb and starts driving data 2. The Slave asserts ut_rxsoc together with the cell first word to indicate the start of a cell 3. The Master can pause a transfer by de-asserting ut_rxenb 4. The Slave samples high ut_rxenb and stops driving data 5. To resume the transfer, the Master re-asserts ut_rxenb 6. The Slave samples low ut_rxenb and starts driving valid data 7. The Master drives ut_txenb high one before the expected end of the current cell if the Slave has no more cell to transfer 8. The Slave de-asserts ut_rxclav to indicate that no new cell is available 9. 14 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 1 3 6 4 8 9 ut_rclk ut_rclav ut_renb ut_rsoc ut_rdat Z ut_rprty Z 2 7 5 Figure 9: Single Cell Transfer ­ Cell Level Transfer Cell Level Transfer ­ Back to Back Cells If the Master keeps ut_rxenb asserted at the end of a cell transfer 1 and if the Slave has a new cell to send, the Slave keeps ut_rxclav asserted 2 and immediately drives the new cell asserting ut_rxsoc to indicate the start of a new cell 3. 1 2 3 ut_rxclk ut_rxclav ut_rxenb ut_rxsoc ut_rxdat ut_rxprty Cell N Cell N+1 Figure 10: Back to Back Cells Transfer ­ Cell Level Transfer Note: If the Master keeps ut_rxenb asserted at the end of a packet and if the Slave does not have a new cell available, the Slave de-asserts ut_rxclav and the data of the bus ut_rxdat are invalid. 15 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 6.3 Utopia Interface MPHY Transmit (L2) When operating in MPHY mode, the Master checks, (Typically in a round robin fashion) the status of all the Slave ports. Two options are defined by the Utopia standard: · Polled status indication with all the PHY ports using a shared single CLAV signal to report their status to the Master · Direct status indication with one CLAV implemented per PHY port or per Utopia group. In MPHY mode only one transmit PHY port is selected at a time for data transfers but the Master continuously polls the status of the Slave's other PHY ports. The Bridge implements the second approach, using direct status indication. MPHY Operation with Direct Status For each PHY port, a status signal ut_txclav is permanently available. The Utopia Bus then supports up to four PHY ports, each using one CLAV signal (Slave port ut_txclav_dir(n). For each port independently, ut_txclav_dir(n) is asserted when enough space is available for a complete cell in the port FIFO 1 and ut_txclav_dir(n) is de-asserted when the corresponding port FIFO cannot receive the subsequent cell 2. Status signals and cell transfers are independent of each other for each port. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. To select a port, the Master deasserts ut_txenb 3, puts address port on ut_txaddr(4:0) 4, the port is selected by the Slave when ut_txenb goes low (Re-asserted by the Master) 5. 1 5 4 2 ut_txclk ut_txclav_dir(3) ut_txclav_dir(2) ut_txclav_dir(1) ut_txclav_dir(0) ut_txaddr x n m x x ut_txenb ut_txsoc ut_txdat ut_txprty Port m Port n 3 Figure 11: MPHY Transmit ­ Direct Status Indication As defined for single CLAV Utopia Transmit, the Master can pause a transfer and implicitly reselect a PHY port. 16 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 6.4 Utopia Interface MPHY Receive (L2) When operating in MPHY mode, the Master checks, (Typically in a round robin fashion) the status of all the Slave ports. Two options are defined by the Utopia standard: · Polled status indication with all the PHY ports using a signal CLAV signal to report their status to the Master · Direct status indication with one CLAV implemented per PHY port or per Utopia group. In MPHY mode only one receive PHY port is selected at a time for data transfers but the Master can continuously polls the status of the Slave PHY ports. MPHY Operation with Direct Status For each PHY port, a status signal ut_rxclav_dir(n) is permanently available. For each port independently, ut_rxclav_dir(n) is asserted when the corresponding PHY port has a cell available in its FIFO 1 and ut_rxclav_dir(n) is de-asserted when the corresponding port FIFO cannot transmit a complete cell to the Master 2. Status signals and cell transfers are independent of each other for each port. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. To select a port, the Master deasserts ut_rxenb 3, puts address port on ut_rxaddr(4:0) 4, the port is selected by the Slave when ut_rxenb goes low (Re-asserted by the Master) 5. 4 2 3 1 ut_rxclk ut_rxaddr(4:0) x n x m x ut_rxclav_dir(3) ut_rxclav_dir(2) ut_rxclav_dir(1) ut_rxclav_dir(0) ut_rxenb ut_rxsoc ut_rxdat ut_rxprty Port n Port m 5 Figure 12: MPHY Receive ­ Direct Status Indication 17 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 7 Core Management and Error Handling On Egress, the Core is designed to handle and report Utopia errors such as Parity error or wrong cell length. Errored cells are discarded with an error status indication provided to the user PHY application. When an errored cell is received on the Utopia interface, the Core discards the complete cell and provides a cell discard indication to the User PHY application (Signal eg_err(n) asserted) 1 together with a cell discard status (Signal eg_err_stat(1:0) 2. Note: eg_err is routed to the corresponding wtx_err and erx_err respectively (see Figure 5). 1 ff_eg_clk(0) ff_eg_cav(0) ff_eg_rdy(0) ff_eg_dval(0) ff_eg_soc(0) ff_eg_data(0) 000A 000B 000C 000D 000E ff_eg_err(0) ff_eg_err_stat(0) Cell N+2 Cell N 2 Figure 13: Cell Discard Indication Table 9: Error Status Word Bit Coding Error Status Bit Name Description 0 PARITY_ERR Valid when wtx/etx_err is asserted. If set to one indicates that a cell is discarded with a parity error decoded by the Core. 1 LENGTH_ERR Valid when wtx/etx_err is asserted. If set to one indicates that a cell is discarded with a cell length error detected on the Utopia interface. The signals are sampled on the corresponding clocks from the west interface: · erx_. sampled with wrxclk (west receive clock) · wtx_. sampled with wtxclk (west transmit clock) 18 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 8 Complexity and Performance Summary 8.1 Timing Parameters Definition ut_tclk ut_rclk tco ut_rxdat, ut_rxsoc ut_rxprty, ut_rxenb ut_rxclav, ut_txclav Figure 14: Tco Timing Parameter Definition ut_tclk ut_rclk tsu ut_txdat, ut_txsoc ut_txprty, ut_txaddr ut_rxaddr, ut_txenb ut_rxenb Figure 15: Tsu Timing Parameter Definition 19 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 8.2 Eclipse Implementation Table 10: Eclipse Implementation Summary Selected Options FIFO depth Utopia Interface Implementation MPHY Ingress 8 Bit 1 512 per port Cells RAM Blocks odd 1024 per port Parity Egress 842 14 Table 11: 8-Bit Utopia Interface Timing Characteristics QL6250-PQ208 QL6250-PQ208 typ Max Unit Parameter -5 -6 tco 7.5 9.5 7.0 ns tsu 2.5 3.2 2.4 ns wrxclk 52 70 MHz wtxclk 57 76 MHz erxclk 45 61 MHz etxclk 54 74 MHz minimum reset time 50 ns Note: QL6250 QL6250 with timing model "worst" at 25 degrees used. 20 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 9 Device Pinout 9.1 Signals Overview Signals Description wrxclk, wrxclav, wrxenb*, wrxdat, wrxsoc, wrxaddr West Utopia L2 Receive Interface. wtxclk, wtxclav, wtxenb*, wtxdata, wtxsoc, wtxaddr West Utopia L2 Transmit Interface. wtx_err, wtx_err_stat West Interface error indication (sampled with wtxclk). erxclk, erxclav, erxenb*, erxdata, erxsoc East Utopia L1 Receive Interface. etxclk, etxclav, etxenb*, etxdata, etxsoc East Utopia L1 Transmit Interface. erx_err, erx_err_stat East Interface error indication (sampled with wrxclk). prty_en, cellsize, waddr Configuration Pins to be board wired. Usual values for waddr are between 0 and 3. reset Active high device reset GND Ground VCC Device Power 3.3 V clk(x) unused clock inputs should be tied to GND IOCTRL(x) VCCIO(x) IO Power 3.3 V INREF(x) connect to GND PLLRST(x) connect to GND or VCC PLLOUT(x) connect to GND or VCC VCCPLL(x) GNDPLL(x) TCK, TRSTB JTAG signals. connect to GND TMS, TDI JTAG signals. connect to VCC TDO JTAG signal. leave open iov nc not connected. should be left open *: active low signal 21 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 9.2 PQ208 PQ208 Pinout Table PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Function pllrst(3) vccpll(3) gnd gnd wtxclav[0] wtxprty wtxenb vccio(a) wtxsoc wtxdat[0] ioctrl(a) vcc inref(a) ioctrl(a) wtxdat[1] wtxdat[2] wtxdat[3] wtxdat[4] vccio(a) wtxdat[5] gnd wtxdat[6] tdi wtxclk clk(1) vcc wrxclk clk(3) vcc clk(4) wtxdat[7] wtxaddr[4] gnd vccio(b) wtxaddr[3] wtxaddr[2] wtxaddr[1] wtxaddr[0] ioctrl(b) inref(b) ioctrl(b) nc nc vccio(b) nc vcc nc wrxclav[0] gnd tdo pllout(1) gndpll(2) PIN 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Function gnd vccpll(2) pllrst(2) vcc wrxprty gnd wrxenb vccio(c) wrxsoc wrxdat[0] wrxdat[1] wrxdat[2] wrxdat[3] wrxdat[4] ioctrl(c) inref(c) ioctrl(c) wrxdat[5] wrxdat[6] vccio(c) wrxdat[7] wrxaddr[4] gnd vcc wrxaddr[3] trstb vcc wrxaddr[2] wrxaddr[1] wrxaddr[0] gnd vccio(d) nc vcc nc nc vcc wtx_err wtx_err_stat[0] ioctrl(d) inref(d) ioctrl(d) wtx_err_stat[1] erx_err erx_err_stat[0] vccio(d) erx_err_stat[1] reset gnd pllout(0) gnd gndpll(1) PIN 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 22 Function pllrst(1) vccpll(1) etxclav[0] gnd etxprty etxenb vccio(e) etxsoc vcc etxdat[0] etxdat[1] etxdat[2] ioctrl(e) inref(e) ioctrl(e) etxdat[3] etxdat[4] vccio(e) gnd etxdat[5] etxdat[6] etxdat[7] clk(5) etxclk vcc erxclk vcc clk(8) tms nc nc nc gnd vccio(f) nc nc nc nc nc ioctrl(f) inref(f) vcc ioctrl(f) nc erxclav[0] vccio(f) erxprty erxenb gnd erxsoc pllout(3) gndpll(0) PIN 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function gnd vccpll(0) pllrst(0) gnd erxdat[0] vccio(g) erxdat[1] erxdat[2] vcc erxdat[3] erxdat[4] erxdat[5] ioctrl(g) inref(g) ioctrl(g) erxdat[6] erxdat[7] iov vcc nc vccio(g) gnd nc waddr[4] vcc tck vcc waddr[3] waddr[2] waddr[1] gnd vccio(h) waddr[0] cellsize[7] ioctrl(h) cellsize[6] inref(h) vcc ioctrl(h) cellsize[5] cellsize[4] cellsize[3] cellsize[2] cellsize[1] cellsize[0] vccio(h) gnd prty_en pllout(2) gnd gndpll(3) BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 9.3 PQ208 PQ208 Device Diagram Figure 16: PQ208 PQ208 top view 23 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 9.4 280 Pin FPBGA Pinout Table PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Function pllout(3) gndpll(0) erx_err erx_err_stat[0] erx_err_stat[1] ioctrl(f) wtxclav[0] wtxprty wtxenb wtxclk wtxsoc wtxdat[0] wtxdat[1] ioctrl(e) wtxdat[2] wtxdat[3] wtxdat[4] pllrst(1) gnd pllrst(0) gnd wtxdat[5] wtxdat[6] wtxdat[7] inref(f) nc nc tms clk(6) nc nc ioctrl(e) nc nc nc vccpll(1) gndpll(1) pllout(0) nc vccpll(0) nc nc vccio(f) ioctrl(f) nc nc vccio(f) wrxclk vccio(e) nc nc wtxaddr[4] vccio(e) wtxaddr[3] wtxaddr[2] wtxaddr[1] wtxaddr[0] PIN D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 Function nc nc nc nc nc cellsize[0] prty_en reset clk(8) wrxclav[0] wrxprty wrxenb inref(e) wrxsoc wrxdat[0] wrxdat[1] wrxdat[2] wrxdat[3] wrxdat[4] cellsize[3] cellsize[2] vccio(g) cellsize[1] gnd vcc vcc vcc vcc gnd gnd vcc vcc gnd gnd wrxdat[5] vccio(d) inref(d) ioctrl(d) inref(g) ioctrl(g) cellsize[5] cellsize[4] gnd vcc ioctrl(d) wrxdat[6] wrxdat[7] nc waddr[4] cellsize[7] ioctrl(g) cellsize[6] vcc vcc nc nc nc PIN G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 Function nc waddr[3] waddr[2] waddr[1] waddr[0] vcc vcc vcc nc nc nc nc nc vccio(g) nc gnd vcc nc vccio(d) wrxaddr[4] wrxaddr[3] vcc tck nc nc gnd gnd wrxaddr[2] wrxaddr[1] wrxaddr[0] trstb nc nc vccio(h) nc vcc gnd nc vccio(c) nc nc nc nc nc nc vcc vcc inref(c) nc nc nc ioctrl(h) nc nc nc vcc vcc 24 PIN N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 Function nc nc ioctrl(c) ioctrl(c) nc nc ioctrl(h) inref(h) vcc gnd nc nc wtx_err wtx_err_stat[0] erxdat[7] nc vccio(h) nc gnd gnd vcc vcc gnd gnd vcc vcc vcc vcc gnd etxdat[3] vccio(c) etxenb wtx_err_stat[1] erxdat[2] erxdat[3] erxdat[4] erxdat[5] erxdat[6] ioctrl(a) nc nc nc nc clk(3) nc nc nc nc etxdat[4] vccpll(2) etxsoc etxclav[0] erxsoc erxdat[0] vccpll(3) erxdat[1] vccio(a) PIN U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function inref(a) nc nc vccio(a) erxclk vccio(b) nc nc ioctrl(b) vccio(b) etxdat[5] tdo pllrst(2) etxprty pllout(2) gndpll(3) gnd erxprty erxenb ioctrl(a) nc nc nc clk(1) clk(4) nc nc inref(b) nc etxdat[6] etxdat[1] gndpll(2) gnd gnd pllrst(3) nc nc nc erxclav[0] nc nc tdi etxclk nc nc nc ioctrl(b) nc etxdat[7] etxdat[2] etxdat[0] pllout(1) BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 280 Pin FPBGA Device Diagram EAST receive error indication WEST TX A18 wtxda t[3] wtxda t[2 ] A17 A16 A15 P LLRST1 I/O I/O wtxd a t[1] A14 wtxda t[0] wtxsoc wtxc lk wtxe nb wtxprty wtxcla v[0] A13 A12 A11 A10 A9 A8 A7 I/O I/O GCLK/I I/O I/O B12 B11 B10 B9 B8 I/O GCLK/I TMS I/O I/O IOCTL I/O erx_e rr_st at [1] erx_e rr_ st at [0] A6 A5 A4 erx_e rr A3 A2 A1 B19 B18 B17 B16 PLLOUT0G NDP LL1 VCCPLL1 I/O wtxa d dr[0] wtxa dd r[1] wtxaddr[2] B15 B14 I/O wtxaddr[3 ] B13 I/O IOCTL I/O wtxadd r[4] I/O IO CTL I/O I/O I/O GNDPLL0 PLLOUT3 wt xda t [7 ] GND wt xda t [6] wt xda t [5] B5 B4 B3 B2 B1 I/O I/O GND PLLRST0 C3 C2 C1 B7 B6 I/O INREF I/O wrxclk C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 I/O I/O I/O I/O VCCIO I/O I/O I/O VCCIO GCLK/I VCCIO I/O wrxda t[4 ] wrxda t[3] wrxd a t[2] wrxda t[1] wrxda t[0 ] wrxsoc wrxe n b wrxprty wrx cla v[0] re se t prt y_e n D19 D18 D17 D16 D15 D14 D12 D11 D10 D9 D8 D7 D6 D5 I/O I/O I/O I/O I/O I/O I/O GCLK/I I/O I/O I/O I/O D13 I/O INRE F I/O C7 C6 C5 I/O IO CTL VCCIO E19 E18 E17 I/O VCCPLL0 I/O c e llsiz e [0] wrxda t[5] IO CTL INREF VCCIO C4 I/O D4 D3 I/O I/O D2 D1 I/O I/O ce lls ize [2] c e llsiz e [1 ] ce lls ize [3] E16 E15 E14 E13 E12 E11 E 10 E9 E8 E7 E6 E5 E4 E3 E2 E1 I/O GND G ND VCC VCC GND GND VCC VCC VCC VCC GND I/O VCCIO I/O I/O c e llsiz e [4 ] c e llsiz e [5] F16 F15 F2 F1 wrxda t[7] wrxd a t[6] F19 F18 F17 I/O I/O G19 G18 G 17 G 16 G 15 I/O I/O I/O I/O VCC I/O IOCTL VCC QuickLogic F5 F4 GND I/O F3 I/O IOCTL INRE F c e llsiz e [6 ] G5 G4 ce lls ize [7] G3 G2 wa d dr[4] G1 I/O IOCTL I/O I/O wa dd r[0] VCC wa d dr[3] wa ddr[1] wa ddr[2] WEST RX H19 H18 H17 H16 H15 H5 H4 H3 H2 H1 I/O I/O I/O VCC VCC VCC I/O I/O I/O I/O wrx ad dr[3] wrxadd r[4] I/O J 16 J 15 J5 J4 J3 J2 J1 I/O VCCIO I/O VCC GND I/O VCCIO I/O I/O wrxadd r[0] J 19 wrxaddr[1] wrxaddr[2 ] J 18 J 17 K19 K18 K17 K16 K15 K5 K4 K3 K2 K1 TRSTB I/O I/O I/O GND GND I/O I/O TCK VCC L19 L18 L17 L16 L15 L5 L4 L3 L2 L1 I/O I/O VCCIO I/O GND VCC I/O VCCIO I/O I/O M17 M16 M15 M5 M4 M3 M2 M1 VCC VCC I/O I/O I/O I/O N2 N1 M19 WEST receive error Indication device configuration wtxd a t[4] A19 M18 I/O I/O N19 N18 I/O INREF N17 IO IO CTL CTL I/O wtx_e rr_s ta t[0] N16 pAS IC N15 I/O VCC N5 P18 P17 P16 I/O I/O I/O GND e tx en b QL6250-6P QL6250-6P T280C T280C P15 I/O wtx_e rr_s ta t[1] e t xda t [3] R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 I/O VCCIO I/O GND VCC VCC VCC VCC GND GND VCC VCC GND et xso c T18 T17 T16 I/O VCCPLL2 I/O T15 T14 T13 T12 T11 T10 T9 T8 I/O I/O I/O I/O GCLK/I I/O I/O I/O U15 U14 U13 U12 U11 U10 U9 U8 I/O VCCIO GCLK/I VCCIO I/O e t xda t [5] U18 V18 U16 TDO I/O e t xda t [1] I/O P LLRST2 U17 V17 V16 I/O e tx da t[0] e t xda t [2] W17 W16 I/O I/O PLLOUT1 I/O T7 T6 R5 R4 R3 R2 R1 I/O VCCIO I/O I/O e rxda t[5] e rxda t[4] e rxda t[3] e rxda t[2] T5 erxc lk VCCIO IOCTL I/O V15 V14 V13 I/O INRE F I/O V12 I/O V10 V11 HWCLK GCLK/I U6 U5 I/O INREF VCCIO V9 V8 I/O I/O V7 W14 W13 I/O IOCTL I/O V6 V5 I/O IOCTL I/O e txc lk W15 T4 T3 T2 T1 I/O I/O I/O I/O e rxda t[0] e rxsoc e rxda t[1] U7 e rxe nb e t xda t [7] W18 P1 I/O GND I/O IOCTL I/O e t xda t [6] GND G NDP LL2 I/O P2 INREF IOCTL I/O e rxd a t[6] e t xda t [4] e txprty W19 P3 I/O IOCTL e rxda t[7] R19 V19 P4 P5 e tx cla v[0] U19 I/O VCC I/O T19 N3 I/O wtx _e rr P19 I/O N4 VCC U4 U1 I/O e rxprty V4 V3 I/O GND V2 V1 GNDPLL3 PLLOUT2 e rxc la v[0] W11 W10 W9 W8 W7 W6 W5 W4 I/O I/O GCLK/I TDI I/O I/O I/O I/O I/O 25 U2 I/O VCCP LL3 I/O W12 EAST TX U3 W3 W2 I/O PLLRST3 W1 GND EAST RX 9.5 BS2M18 BS2M18 Utopia Level 2 to 1 Bridge Device Datasheet Version 1.0 - July 2001 10 References · · · ATM Forum, Utopia Level 1, af-phy-0017.000, 1994 ATM Forum, Utopia Level 2, af-phy-0039.000, 1995 Quicklogic, Eclipse Family Datasheet (Preliminary, 8/24/2000) 11 Contact MorethanIP Tel : +49 (0) 89 3219599 0 FAX : +49 (0) 89 3219599 1 E-Mail : info@morethanip.com Internet : www.morethanip.com QuickLogic Corp. Tel : 408 990 4000 (US) : + 44 1932 57 9011 (Europe) : + 49 89 930 86 170 (Germany) : + 852 8106 9091 (Asia) : + 81 45 470 5525 (Japan) E-mail : info@quicklogic.com Internet : www.quicklogic.com 26