BR93L46-W BR93L56/66-W BR93L76/86-W

CS tCS 1 SK 2 4 STATUS n BR93L46-W : n=25, m=5 BR93L56/66-W : n=27, m=7 DI 1 0 Am 1 A1 A0 D15 D14 D1 D0 BR93L76/86-W : n=29, m=9

1) Write cycle (WRITE) CS tCS 1 SK 2 4 STATUS n BR93L46-W BR93L46-W : n=25, m=5 BR93L56/66-W BR93L56/66-W : n=27, m=7 DI 1 0 Am 1 A1 A0 D15 D14 D1 D0 BR93L76/86-W BR93L76/86-W : n=29, m=9 tSV BUSY READY DO High-Z tE/W Fig. Write cycle In this command, input 16bit data (D15 ~ D0) are written to designated addresses (Am ~ A0). The actual write starts by the fall of CS of D0 taken SK clock. When STATUS is not detected, (CS = "L" fixed) Max. 5ms in conformity with tE/W, and when STATUS is detected (CS = "H"), all commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any command. 2) Write all cycle (WRAL) CS STATUS tCS 1 SK 2 5 n BR93L46-W BR93L46-W : n=25 BR93L56/66-W BR93L56/66-W : n=27 DI 1 0 0 0 D15 D14 1 D1 D0 BR93L76/86-W BR93L76/86-W : n=29 tSV BUSY READY DO High-Z tE/W Fig. Write all cycle In this command, input 16bit data is written simultaneously to all addresses. Data is not written continuously per one word but is written in bulk, the write time is only Max. 5ms in conformity with tE/W. Copyright © 2007 ROHM Co., Ltd. All rights reserved.