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Part : BL/HLT Supplier : EATON Manufacturer : Chip One Exchange Stock : 100 Best Price : - Price Each : -
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BL/HLT

Catalog Datasheet MFG & Type PDF Document Tags

ST486SLC

Abstract: ST486DX2 bl,0f4h not_hlt ;was it a HLT instruction? ;if not a F4 then not a HLT ;set up SMM header to , Shadowing and Emulation . . . . . . . . . . . 3.8 Return to HLT Instruction . . . . . . . . . . . . . . . . , instruction executing, when an SMI occurred, was a HLT instruction, the HLT instruction it should be restarted , not enter suspend mode following execution of a HLT instruction HALT = 1: CPU enters suspend mode following execution of a HLT instruction. SUSP Enable Suspend Pins. SUSP = 0: SUSP
STMicroelectronics
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ST486DX ST486SLC ST486DX2 RSM AH-16 0000004E

IRP 028H

Abstract: STPC Atlas 9.2.2. SMI routine installation 9.2.3. Main SMI routine 9.2.4. Return to HLT instruction 9.2.5 , ; Determine the memory configuration. ; Inputs: ; DS: 4GB access ; SDRAM only: ; BL: bits 0-3: read , movzx and shl mov and shl or eax, bl al, 10000000b ; set registered DIMM ax, 2 al, bl al , , Read CL=CL mov mov esi, STPC_MEM_REG0 ds:[esi], eax movzx and or add mov eax, bl al , STPC_MEM_REG2 BL = SDRAM configuration that gives the highest size BH = this size sub bx, bx
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IRP 028H STPC Atlas STPC 486 Core Guide IRP 034H stpc client set es segment to register to 4gb

TLR324

Abstract: LDI 001 b 3 b 2 bl bO b 3 b 2 bl bO b 3 b2 bl bO PHY13 X' AC 16 «rBftHEf* NJU3101 RH â A , itz, y"-> 3 ¡i, yn/7 AX NJU3101 4mm?i &zt&T'ètt. mf-liliLTft^ZmTt Z Z ¿T-WíéLit. HLT ^co-fr^-i 7 , =1 RPC=0 RPC=1 NOP HLT MDT 00 07 06 No Operation CPU Halted m-^y'-fn IC xXhffl , 1 - 4 6 on off * * 1 0 * * HOLT tëlfclà, "HLT CANCEL" X ^ â â /f-iCTfî T â'ž HOLTSifîBfiOS/S , HLT CANCEL : on HOLTtttScof®0 HOLT'£ÃTB#A> tSi RESET : on /N- K7iT 'J-fe'y h NJU3101 7-? + 1 > b
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D3101 TLR324 LDI 001 l4 tam TBA 427 147006c NJU31011 NJU3101D NJU3101M CNT10 PROG3101

PO3C

Abstract: 5K324 unit Bm, Bl: RAM address register C: Carry flag I FA, IFB, I FT: Interrupt request fl IME: Interrupt , = 2.2 V to 3.3 V 200 600 MA 8 Supply current 'hlt fosc = 1 MHz, Vdd = 4.5 V to 5.5 V 400 900 MA 8 , MHz> VDD = 2.7 V to 3.3 V 300 900 MA 8 fosc = 1 0 mhz> vdd = 4 5 v to 5.5 V 600 1,400 MA 8 'hlt , Supply current 'hlt fOSc = 32.768 kHz (crystal OSC mode) Vdd = 2.2 V to 3.3 V 15 60 MA 7 fOSc = , C flag. B Register and SB Register B Register (BM, BL) The B register is an 8-bit register that
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QFP036-P-1010 PO3C 5K324 SM5* sharp 30-PIN 32-PIN P42C SDIP030-P-0400 SSQP024-P-0275

M5L8284

Abstract: M5L8289 access states L Single bus mode RESB H (SYSB/RESB=shIgh), (Memofy access states) HLT , Access s ta te + T l)â'˜ C B RQ )+HLT I/O Bus mode only +HPERQ ( (I/O Access state +(SY SB /R Ã' SB =low )ï* I/O Bus mode CBRQ + HPBRQ HLT +HPBRQ resident bus mode Note 1 : W hen L O C K = , released even when low-priority arbiters request it. 2 : HLT. Halt state T l , setup time tpNSBL 15 ns taU(BÃSY) BUSY t i t o BCLK i setup time ♦b ys bl 20
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M5L8284 M5L8289 m5l8288 M5L8289P 5L8289P

Bus Arbiters

Abstract: bus arbiter lines go active SYSB/R ESB + High · ACTIVE STATUS M em ory Commands SURRENDERED* HLT + Tl · CBRQ + HPBRQ $ Single Bus M ulti-M aster Mode RESB M ode Only (SYSB/RESB = Low + T l) · CBRQ + HLT + HPBRQ (I/O Status + T l) · CBRQ + HLT + HPBRQ (I/O Status Com mands) + SYSB/R ESB = Low) · CBRQ + H P B R Q + HLT IOB Mode Only IOB Mode RESB Mode (M em ory Com mand) · (SYSB/RESB = High , . Tl = Processor Idle Status S2, S 1 , SO = 111 5. HLT = Processor Halt Status S2, S 1 , SO = 011
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Bus Arbiters bus arbiter 82C89 82C88 80C86 80C88 80C86/80C88 82C88/8288
Abstract: active HLT + Tl â'¢ CBRQ + HPBRQ * RESB M ode Only iO B = High RESB = High SYSB/R ESB + High â'¢ ACTIVE STATUS (SYSB/RESB = Low + T l) â'¢ CBRQ + HLT + HPBRQ IOB Mode Only IOB = Low RESB = Low M em ory Commands (I/O Status + T l) â'¢ CBRQ + HLT + HPBRQ IOB Mode RESB Mode , SYSB/R ESB = Low) â'¢ CBRQ + H P B R Q + HLT NOTES: * LOCK prevents surrender of Bus to any , , S 1 , SO = 111 5. HLT = Processor Halt Status S2, S 1 , SO = 011 4-351 82C89 Absolute -
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80C86/8086 80C88/8088 CP82C89 MD82C89 MR82C89 F13/2

HD404314

Abstract: ncr03 Type Circuit Input/output pins Pins VCC HLT VCC Pull-up control signal Buffer control , Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data , Input/ output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC SCK Pull-up control signal PMOS control signal Output data VCC SCK HLT VCC Pull-up control signal Output data SO MIS3 MIS2 SO HLT VCC SCK MIS3
Hitachi Semiconductor
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HD404314 ncr03 HD404314H HD404314S HD404316 HD404316H

HD404316

Abstract: HD404314 Type Circuit Input/output pins Pins VCC HLT VCC Pull-up control signal Buffer control , Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data , Input/ output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC SCK Pull-up control signal PMOS control signal Output data VCC SCK HLT VCC Pull-up control signal Output data SO MIS3 MIS2 SO HLT VCC SCK MIS3
Hitachi Semiconductor
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HD404318 HD404316s tmb12 Hitachi DSA00164 Nippon capacitors ecg Fluorescent reference design HMCS400- HD4074318 D-85622

HD-4043

Abstract: HD404314 Type Circuit Input/output pins Pins VCC HLT VCC Pull-up control signal Buffer control , Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data , Input/ output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC SCK Pull-up control signal PMOS control signal Output data VCC SCK HLT VCC Pull-up control signal Output data SO MIS3 MIS2 SO HLT VCC SCK MIS3
Renesas Electronics
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HD-4043 PKW 1000 mitsubishi semiconductors power modules mos HD404318H HD404318S 1S207

AMR11

Abstract: HD404314 Type Circuit Input/output pins Pins VCC HLT VCC Pull-up control signal Buffer control , Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data , Input/ output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC SCK Pull-up control signal PMOS control signal Output data VCC SCK HLT VCC Pull-up control signal Output data SO MIS3 MIS2 SO HLT VCC SCK MIS3
Hitachi Semiconductor
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AMR11 Hitachi DSA00304 application note an-7

intel 8080A instruction set

Abstract: M58710S three-state, and remain in the floating state during the HLT instruction execute cycle TW"R or in the hold , during the HLT instruction execute cycle (TWH] and in the hold state. SYNC Synchronizing signal Out , , and instruction HLT. The duration of Tw is an integral multiple of the clock cycle. The first machine , bus holds the pushdown stack address from the stack pointer. D, HLTA HLT instruction acknowledge Goes high when the CPU executes the HLT instruction and maintains the halt state. 0. OUT Output instruction
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M5L8080A M5L8080AP M5L8080AS intel 8080A instruction set M58710S M58710 M5871 SBIN10

AVAL DATA "PKW-1000"

Abstract: DCR63 HLT VCC Pull-up control signal Buffer control signal R0 0, R0 1, R0 3, MIS3 R3 0­R3 3 , control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R0 2 , pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC , SO HLT Pull-up control signal Output data 32 SCK HLT VCC SCK MIS3 MIS3 , / pins pins SI HLT MIS3 PDR SI Input data VCC AN 0­AN 11 HLT MIS3 PDR A/D input
Renesas Electronics
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AVAL DATA "PKW-1000" DCR63 Tda 9032 i6458 HD4043312 HD404334

Nippon capacitors

Abstract: Hitachi DSA002753 of Standard I/O Pins Circuit VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2 , Output data Input data Input control signal Peripheral function Input/ pins output pins VCC HLT , HLT VCC Pull-up control signal MIS3 SO PMOS control signal Output data MIS2 SO HLT VCC , Type Peripheral function Input/ pins pins Circuit VCC HLT MIS3 PDR SI Pins SI Input data VCC
Hitachi Semiconductor
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Hitachi DSA002753 HD404339 HMCS400-S HD404338 HD404336 HD4074339

Tda 9032

Abstract: HD404338 HLT VCC Pull-up control signal Buffer control signal R0 0, R0 1, R0 3, MIS3 R3 0­R3 3 , control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R0 2 , pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC , SO HLT Pull-up control signal Output data 32 SCK HLT VCC SCK MIS3 MIS3 , / pins pins SI HLT MIS3 PDR SI Input data VCC AN 0­AN 11 HLT MIS3 PDR A/D input
Hitachi Semiconductor
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HD404334FS HD404334S HD404336FS HD404336S

PKW-1000

Abstract: MX-38T HLT VCC Pull-up control signal Buffer control signal R0 0, R0 1, R0 3, MIS3 R3 0­R3 3 , control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R0 2 , pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC , SO HLT Pull-up control signal Output data 32 SCK HLT VCC SCK MIS3 MIS3 , / pins pins SI HLT MIS3 PDR SI Input data VCC AN 0­AN 11 HLT MIS3 PDR A/D input
Hitachi Semiconductor
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PKW-1000 MX-38T mitsubishi fx 128 mr adru ssi r63

MIS1

Abstract: ssi r63 HLT VCC Pull-up control signal Buffer control signal R0 0, R0 1, R0 3, MIS3 R3 0­R3 3 , control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R0 2 , pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC , SO HLT Pull-up control signal Output data 32 SCK HLT VCC SCK MIS3 MIS3 , / pins pins SI HLT MIS3 PDR SI Input data VCC AN 0­AN 11 HLT MIS3 PDR A/D input
Hitachi Semiconductor
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MIS1 DCR03 DSA003664 Hitachi DSA003664 Hitachi DSA00366 000017FF

aval PKW1000

Abstract: HD-4043 /output pins Circuit Pins R00, RO i, ROß, R3 q-R33, R4 0 - R 4 3 input control signal - vcc O 1 HLT , function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes. Table 7 Circuit Configurations for High-Voltage Input/Output Pins I/O Pin Type Input/output pins With Pull-Down Resistance vcc HLT Output data , Output pins HLT Output data BU ZZ vc c HLT Output data : Pull-down "resistance ''oisp Input
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aval PKW1000 ADE-202-06KO HD4043I6 HD4074318S HD4074318H DP-42S FP-44A
Abstract: ~R33, R4q-R43 Input control signal= £ > -I HLT I Pull-up control signal Buffer control , cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT , and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes. 3. The circuits , '¢ By setting timer read register BL, BU (TRBL, BU: $00A, $OOB), the contents of timer counter B can -
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MIMI Ti PROM programming procedure

Abstract: murata 55E ceramic filter the pull-up MOS (C). When the HLT signal becomes 0 in the stop mode, MOS (A), (B), and (C) turn off. D , MOS (B) CMOS (C) Applicable Pin* I/O Common Pins HLT -fâ'"V Input -1â'"data HLÃ-fâ'"V, lnPut â'"LJ>â'"data HLT Output data HlT-r-v lnPut â'"\-Pâ'" data D0-D3 R3O-R33 R4O-R43 R5O-R53 R60-R63 R7o-R73 R80-R83 Input Pins O hlt j )o- Input data hlt O Dr, Input data R9O-R93 Table 17 I/O Pin Circuit Types , Pins Vcc o> Output data HLT-f-Input -L^r data Veci ' Output data Vdi5p HLT Hâ'"V_ Input -1_" data D4-D
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MIMI Ti PROM programming procedure murata 55E ceramic filter RA20A PROM programming instructions murata 7nb D404019/H D4074019 HD404019 HD4074019 D03S11 HD404019/HD4074019
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