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Part : BI 1-EH03-AP7X Supplier : TURCK Manufacturer : Newark element14 Stock : - Best Price : $138.00 Price Each : $138.00
Part : BI1-EH03-AP7X-0.5M-RS4T Supplier : TURCK Manufacturer : Newark element14 Stock : - Best Price : $148.00 Price Each : $148.00
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BI 1-EH03-AP7X

Catalog Datasheet MFG & Type PDF Document Tags

M1619323

Abstract: S4609740 Number Bi 1-EH03-AN7X* M1619323 Features TTL Compatible Sen s Ran ing ge (m m) Inductive Sensors Output 1 3-Wire DC NPN Bi 1-EH03-AP7X* M1619322 TTL Compatible 1 3-Wire DC PNP 4 mm - Embeddable, Miniature Smooth Barrel, Potted-In Cable Bi 1-EH04-AN6X S4609640 1 3-Wire DC NPN Bi 1-EH04-AP6X S4609540 1 3-Wire DC PNP Bi 1-EH04-Y1 5 mm - Embeddable, Miniature Threaded Barrel, Potted-In Cable S1003040 1 Bi 1-EG05-AN6X S4609840 1
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S4609740 1-EG05-AP6X 1-EG05-Y1 S1003240

1SG14

Abstract: 1SG23 271 1SG11 1SG12 1SG13 1SG14 1SG15 ft * £ a « 01 BI BI BI ai Vdc (V) 12. 5 14 24 12 , 10. 3'â'"10.7 10. 7±0. 2 ffl m tt 1SG16 1SG17 1SG18 1SG19 1SG20 ai ai BI ai ai 24 24 17 15 12 , 1SG22 1SG23 1SG24 1SG25 BI BI BI BI BI 14 14 14 14 19 230 230 230 230 230 2.8-4. 5 2. 8 â'" 4. 5 2 , 1SG27 1SG28 1SG29 1SG30 BI BI BI BI BI 19 19 15 11 11 230 230 230 230 230 5. 4 5. 4 2. 7 2. 2 2. 2 , GD308C GD308D B® BI BI BI BI Vop+1 Vop+1 Vop+1 Vop+1 Vop+1 70» 70» 70* 70» 70» 0. 25 0. 2 0. 4
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OCR Scan
1SG21 GD311C 1SG26 GD308A GD308AA GD308B GD308E

1SG12

Abstract: 1SG24 271 1SG11 1SG12 1SG13 1SG14 1SG15 ft * £ a « 01 BI BI BI ai Vdc (V) 12. 5 14 24 12 , 10. 3'â'"10.7 10. 7±0. 2 ffl m tt 1SG16 1SG17 1SG18 1SG19 1SG20 ai ai BI ai ai 24 24 17 15 12 , 1SG22 1SG23 1SG24 1SG25 BI BI BI BI BI 14 14 14 14 19 230 230 230 230 230 2.8-4. 5 2. 8 â'" 4. 5 2 , 1SG27 1SG28 1SG29 1SG30 BI BI BI BI BI 19 19 15 11 11 230 230 230 230 230 5. 4 5. 4 2. 7 2. 2 2. 2 , GD308C GD308D B® BI BI BI BI Vop+1 Vop+1 Vop+1 Vop+1 Vop+1 70» 70» 70* 70» 70» 0. 25 0. 2 0. 4
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OCR Scan
GD408A GD311A GD311AA GD311B GD311D GD311E GD314A

1SG19

Abstract: 1SG23 271 1SG11 1SG12 1SG13 1SG14 1SG15 ft * £ a « 01 BI BI BI ai Vdc (V) 12. 5 14 24 12 , 10. 3'â'"10.7 10. 7±0. 2 ffl m tt 1SG16 1SG17 1SG18 1SG19 1SG20 ai ai BI ai ai 24 24 17 15 12 , 1SG22 1SG23 1SG24 1SG25 BI BI BI BI BI 14 14 14 14 19 230 230 230 230 230 2.8-4. 5 2. 8 â'" 4. 5 2 , 1SG27 1SG28 1SG29 1SG30 BI BI BI BI BI 19 19 15 11 11 230 230 230 230 230 5. 4 5. 4 2. 7 2. 2 2. 2 , GD308C GD308D B® BI BI BI BI Vop+1 Vop+1 Vop+1 Vop+1 Vop+1 70» 70» 70* 70» 70» 0. 25 0. 2 0. 4
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OCR Scan
GD314AA GD314B GD314C GD314D GD314E GD318A

bi 240

Abstract: SnAgCu 3-2 Dependence of bonding reliability on Bi density (1) Bonding reliability of Sn-Bi plating/Sn-Ag-Cu , Temperature Profile Used in Mount Testing 5. Sn Whisker Evaluation (Bi Density Dependence) 6. Soldering , * Dependence of lead bend appearance on Bi density Cu frame Sn-1.5% Bi -3.0% Bi -4.5% Bi -6.0% Bi -3.0% Bi -4.5% Bi -6.0% Bi 42 alloy frame Sn-1.5% Bi · Plating cracks on lead bend increase as the Bi density increases. (Plating cracks are not deep enough to expose the lead
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NA200 bi 240 SnAgCu NA200 flux NA-200 QFP-208

ICS950208

Abstract: pin DIAGRAM OF IC 7400 from X 2 Logi c i nput frequency select bi t. Input latched at power on. 6 P C IC LK 0 FS 3 O UT IN 3.3V P C I clock output Logi c i nput frequency select bi t. Input latched at power on. 7 P C IC LK 1 FS 4 O UT IN 3.3V P C I clock output Logi c i nput frequency select bi t , clock outputs for HUB Logi c i nput frequency select bi t. Input latched at power on. 3.3V F i xed 48MHz clock output. Logi c i nput frequency select bi t. Input latched at power on. S electable 24 or
Integrated Circuit Systems
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ICS950208 CK-408 pin DIAGRAM OF IC 7400 318MH VDD3V66 S3V66-PCI MO-118

BC 536

Abstract: FRB CRS prediction, as part of the instruction mnemonic rather than as numeric operands (the BO and BI operands). , branch instructions that include BO and BI operands; there is no need to simplify unconditional branch , Conditional target_addr bc (bca bcl bcla) BO,BI,target_addr Branch Conditional to Link Register Freescale Semiconductor, Inc. Syntax bclr (bclrl) Branch Conditional to Count Register BO,BI bcctr (bcctrl) BO,BI The BO and BI operands correspond to two fields in the instruction opcode, as
Motorola
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AN2491 BC 536 FRB CRS

CK-408

Abstract: ICS950208 Byte 4: Output Control Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 31 30 48 1 27 28 PWD X X 1 1 1 1 1 1 Description , (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin , enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name , : Revision ID and Device ID Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Integrated Circuit Systems
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7400 series CMOS Logic ICs FS0/48MH FS1/24 AVDD48 0464B--08/04/03

X2453

Abstract: CK408 (Default=0) Description Bi t Bit2 Bi t (2,7:4) Bi t 3 Bi t 1 Bi t 0 PWD Bit7 Bit6 Bit5 , Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , /Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description DDRC3 , : Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t
Integrated Circuit Systems
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ICS950910 CK408 X2453 CPU408 P4X/P4M/KT/KN266/333 0735B--09/21/07

0735A

Abstract: CK408 (Default=0) Description Bi t Bit2 Bi t (2,7:4) Bi t 3 Bi t 1 Bi t 0 PWD Bit7 Bit6 Bit5 , Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , /Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description DDRC3 , : Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t
Integrated Circuit Systems
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0735A kn266 PC133-SDRAM VX550 200MH

EF232

Abstract: 6666M Logi c i nput frequency select bi t. Input latched at power on. 3.3V P C I clock output. 6 FS 1 9 , bi t. Input latched at power on. O UT 17, 16, 15, 12, 11, 10 P C IC LK (6:1) 23 IN This , internal VCO or 48MHz (non-SSC). Logi c i nput frequency select bi t. Input latched at power on. A nalog power 3.3V. 3.3V F i xed 48MHz clock output for D OT. Logi c i nput frequency select bi t. Input , external resistors are required for voltage bias. Logi c i nput frequency select bi t. Input latched at
Integrated Circuit Systems
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ICS950202 EF232 6666M 48MHZ PS-0500 VCH/3V66
Abstract: : Frequency Select Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 0475F-10/13/03 Pin# 20 21 1 PWD X X X X 1 1 1 Description Latched , Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description SDRAM7/DDRC3 (Active , (Active/Inactive) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Integrated Circuit Systems
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ICS950902 408/K7/AGPCLK1 GND48 FS3/48MH FS2/24 0475F--10/13/03

p4m 29

Abstract: kn266 Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , /Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 , /Inactive) SDRAM0/DDRT0 (Active/Inactive) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 Revision ID
Integrated Circuit Systems
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p4m 29 ICS-950902 0475E--12/19/02 MO-153

CK408

Abstract: ICS950902 Select Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 20 21 1 PWD X X X X 1 1 1 Description Latched FS3 , . Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 , = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name
Integrated Circuit Systems
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0475G--03/23/04

48MHZ

Abstract: CK-408 Logi c i nput frequency select bi t. Input latched at power on. 3.3V P C I clock output. FS 1 IN Logi c i nput frequency select bi t. Input latched at power on. WDEN IN Hardware enable of , internal VCO or 48MHz (non-SSC). Logi c i nput frequency select bi t. Input latched at power on. A nalog power 3.3V. 3.3V F i xed 48MHz clock output for D OT. Logi c i nput frequency select bi t. Input , external resistors are required for voltage bias. Logi c i nput frequency select bi t. Input latched at
Integrated Circuit Systems
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0461M--02/10/06

48MHZ

Abstract: CK-408 i nput frequency select bi t. Input latched at power on. 3.3V P C I clock output. 6 FS 1 9 IN Logi c i nput frequency select bi t. Input latched at power on. WDEN IN Hardware , 66MHz from internal VCO or 48MHz (non-SSC). Logi c i nput frequency select bi t. Input latched at , select bi t. Input latched at power on. 3.3V F i xed 48MHz clock output for US B . This pin establishes , frequency select bi t. Input latched at power on. 3.3V, 14.318MHz reference clock output. 0461L-04/23
Integrated Circuit Systems
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lk61 0461L--04/23/03
Abstract: IN IN I/O OUT IN P WR O UT IN O UT O UT IN O UT O UT IN O UT Logi c i nput frequency select bi t , frequency select bi t. Input latched at power on. A nalog power 3.3V. 3.3V F i xed 48MHz clock output for D OT. Logi c i nput frequency select bi t. Input latched at power on. 3.3V F i xed 48MHz clock output , . Logi c i nput frequency select bi t. Input latched at power on. 3.3V, 14.318MHz reference clock output , C I clock output Logi c i nput frequency select bi t. Input latched at power on. 3.3V P C I clock Integrated Circuit Systems
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0461L--05/19/03

ICS950219

Abstract: 7400 series CMOS Logic ICs _0 Byte 4: Output Control Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 31 30 48 1 27 28 PWD X X 1 1 1 1 1 1 Description , Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# X X X X X X X PWD 1 1 1 1 1 1 1 0 Description , bi t 0 = 0 66.01MHz/33.00MHz (Async with CPU) 66.66MHz/33.33MHz (Sync with CPU) B 5 bi t 0 =
Integrated Circuit Systems
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ICS950219 pci 32 bit 5v 318M 0640D--12/30/03

RD272

Abstract: bc 303 transistor mnemonic rather than as numeric operands (the BO and BI operands). Table 4 shows the four general types of , BI operands; there is no need to simplify unconditional branch mnemonics. Table 4. Branch , (bca bcl bcla) BO,BI,target_addr Branch Conditional to Link Register Freescale Semiconductor, Inc. Syntax bclr (bclrl) Branch Conditional to Count Register BO,BI bcctr (bcctrl) BO,BI The BO and BI operands correspond to two fields in the instruction opcode, as Figure 1 shows for Branch
Freescale Semiconductor
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RD272 bc 303 transistor

ICS950213

Abstract: ef232 Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , ) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 , Device ID Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Device , Byte 8: Byte Count Read Back Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0 PWD Description 0 0 0
Integrated Circuit Systems
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ICS950213
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