ADSP-BF512/BF512F BF514/BF514F BF516/BF516F BF518/BF518F ADSP-BF518/ADSP-BF518F - Datasheet Archive

 

Embedded Processor ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F FEATURES PERIPHERALS Up to 400 MHz high

 

Blackfin Embedded Processor ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages. See Operating Conditions on Page 20 Qualified for Automotive Applications. See Automotive Products on Page 65 168-ball CSP_BGA or 176-lead LQFP with exposed pad IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588 support (ADSP-BF518/ADSP-BF518F ADSP-BF518/ADSP-BF518F only) Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats 2 dual-channel, full-duplex synchronous serial ports (SPORTs), supporting 8 stereo I2S channels 12 peripheral DMAs, 2 mastered by the Ethernet MAC 2 memory-to-memory DMAs with external request lines Event handler with 56 interrupt inputs 2 serial peripheral interfaces (SPI) Removable storage interface (RSI) controller for MMC, SD, SDIO, and CE-ATA 2 UARTs with IrDA support 2-wire interface (TWI) controller Eight 32-bit timers/counters with PWM support 3-phase 16-bit center-based PWM unit 32-bit general-purpose counter Real-time clock (RTC) and watchdog timer 32-bit core timer 40 general-purpose I/Os (GPIOs) Debug/JTAG interface On-chip PLL capable of frequency multiplication MEMORY 116K bytes of on-chip memory External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Optional 4M bit SPI flash with boot option Flexible booting options from internal SPI flash, OTP memory, external SPI/parallel memories, or from SPI/UART host devices Code security with Lockbox secure technology One-time-programmable (OTP) memory Memory management unit providing memory protection RTC WATCHDOG TIMER OTP PERIPHERAL ACCESS BUS COUNTER JTAG TEST AND EMULATION 3-PHASE PWM TIMER7­0 B TWI INTERRUPT CONTROLLER SPORT1-0 RSI (SDIO) L1 INSTRUCTION MEMORY L1 DATA MEMORY DMA CONTROLLER PORTS PPI UART1­0 16 DMA CORE BUS EXTERNAL ACCESS BUS EXTERNAL PORT FLASH, SDRAM CONTROL DMA EXTERNAL BUS EMAC SPI1 BOOT ROM SPI0 4 Mbit SPI Flash (See Table 1) Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2011 Analog Devices, Inc. All rights reserved. ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F TABLE OF CONTENTS Features . 1 Related Signal Chains . 16 Memory . 1 Lockbox Secure Technology Disclaimer . 16 Peripherals . 1 Signal Descriptions . 17 Revision History . 2 Specifications . 20 General Description . 3 Operating Conditions . 20 Portable Low Power Architecture . 3 Electrical Characteristics . 22 System Integration . 3 Flash Memory Characteristics . 24 Blackfin Processor Core . 3 Absolute Maximum Ratings . 25 Memory Architecture . 5 Package Information . 26 Event Handling . 6 ESD Sensitivity . 26 DMA Controllers . 7 Timing Specifications . 27 Processor Peripherals . 7 Output Drive Currents . 50 Dynamic Power Management . 11 Test Conditions . 52 Voltage Regulation Interface . 13 Thermal Characteristics . 56 Clock Signals . 13 176-Lead LQFP Lead Assignment . 57 Booting Modes . 14 168-Ball CSP_BGA Ball Assignment . 60 Instruction Set Description . 15 Outline Dimensions . 63 Development Tools . 15 Surface-Mount Design . 64 Designing an Emulator-Compatible Processor Board (Target) . 16 Automotive Products . 65 Ordering Guide . 65 Related Documents . 16 REVISION HISTORY 1/11-Rev. A to Rev. B This data sheet release coincides with the release of the revised ADSP-BF51x Blackfin Processor Hardware Reference. All redundant information has been removed. Revised several specifications in Operating Conditions . 20 Revised fVCO specification in Phase-Locked Loop Operating Conditions . 21 Revised tWL, tWH and tOH specification in RSI Controller Timing (High Speed Mode) . 36 Revised tMDCIH and tMDCOH specifications in 10/100 Ethernet MAC Controller Timing: MII Station Management . 48 Corrected dimensions in 168-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-168-1 BC-168-1) . 64 Revised several specifications in Electrical Characteristics 22 Added additional fCKIN specification for automotive models in Clock and Reset Timing . 27 Changed the parameter VDDMEM to VDDEXT in Asynchronous Memory Read Cycle Timing . 29 SDRAM Interface Timing . 31 Parallel Peripheral Interface Timing . 33 Serial Ports . 37 Revised tHFSPE specification in Parallel Peripheral Interface Timing . 33 Revised tHFSPE specification and added the tPSUD specification in Parallel Peripheral Interface Timing . 33 Revised the tWL and tWH specifications in RSI Controller Timing . 35 Rev. B | Page 2 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F GENERAL DESCRIPTION The ADSP-BF512/ADSP-BF512F ADSP-BF512/ADSP-BF512F, ADSP-BF514/ADSPBF514F ADSP-BF514/ADSPBF514F, ADSP-BF516/ADSP-BF516F ADSP-BF516/ADSP-BF516F, ADSP-BF518/ADSPBF518F ADSP-BF518/ADSPBF518F processors are members of the Blackfin® family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The processors are completely code compatible with other Blackfin processors. Memory (bytes) ADSP-BF518F ADSP-BF518F ADSP-BF518 ADSP-BF518 ADSP-BF516F ADSP-BF516F ADSP-BF516 ADSP-BF516 ADSP-BF514F ADSP-BF514F ADSP-BF514 ADSP-BF514 ADSP-BF512F ADSP-BF512F ADSP-BF512 ADSP-BF512 ­ ­ ­ ­ ­ ­ 1 1 ­ ­ ­ ­ 1 1 1 1 ­ ­ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 8 8 8 8 8 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ­ 1 ­ 1 ­ 1 ­ 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 40 40 40 40 40 40 40 40 32K 16K 32K 32K 4K 32K 400 MHz 176-Lead LQFP with Exposed Pad 168-Ball CSP_BGA By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package. Rev. B Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances. SYSTEM INTEGRATION Table 1. Processor Comparison Feature IEEE-1588 IEEE-1588 Ethernet MAC RSI TWI SPORTs UARTs SPIs GP Timers Watchdog Timers RTC PPI Internal 4 Mbit SPI flash Rotary Counter 3-Phase PWM Pairs GPIOs L1 Instruction SRAM L1 Instruction SRAM/Cache L1 Data SRAM L1 Data SRAM/Cache L1 Scratchpad L3 Boot ROM Maximum Speed Grade Package Options PORTABLE LOW POWER ARCHITECTURE The ADSP-BF51x processors are highly integrated system-on-achip solutions for the next generation of embedded network connected applications. By combining industry-standard interfaces with a high performance signal processing core, costeffective applications can be developed quickly, without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC with IEEE-1588 IEEE-1588 support (ADSP-BF518/ADSP-BF518F ADSP-BF518/ADSP-BF518F only), an RSI controller, a TWI controller, two UART ports, two SPI ports, two serial ports (SPORTs), nine general-purpose 32-bit timers (eight with PWM capability), 3-phase PWM for motor control, a real-time clock, a watchdog timer, and a parallel peripheral interface (PPI). BLACKFIN PROCESSOR CORE As shown in Figure 1, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. The compare/select and vector search instructions are also provided. | Page 3 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F ADDRESS ARITHMETIC UNIT I3 L2 B2 M2 L1 B1 M1 I0 L0 B0 SP FP M3 I1 M0 P5 DAG1 P4 P3 DAG0 P2 32 32 P1 P0 TO MEMORY DA0 B3 I2 DA1 L3 32 PREG 32 RAB SD LD1 LD0 32 32 32 ASTAT 32 32 SEQUENCER R7.H R6.H R7.L R6.L R5.H R5.L R4.H R4.L R3.H R3.L R2.H R1.L R0.H R0.L ALIGN 16 8 8 8 R2.L R1.H 16 8 DECODE BARREL SHIFTER 40 40 A0 32 40 40 A1 LOOP BUFFER CONTROL UNIT 32 DATA ARITHMETIC UNIT Figure 1. Blackfin Processor Core For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Rev. B Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit | Page 4 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C+ compiler, resulting in fast and efficient software implementations. The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces. MEMORY ARCHITECTURE The ADSP-BF51x processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. The memory map for both internal and external memory space is shown in Figure 2. Internal (On-Chip) Memory The ADSP-BF51x processors have three blocks of on-chip memory that provide high bandwidth access to the core. The first block is the L1 instruction memory, consisting of 48K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed. 0xFFFF FFFF CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000 SCRATCHPAD SRAM (4K BYTES) The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. RESERVED External (Off-Chip) Memory INSTRUCTION BANK C SRAM/CACHE (16K BYTES) External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 0xFFB0 0000 INTERNAL MEMORY MAP 0xFFA1 4000 0xFFA1 0000 RESERVED 0xFFA0 8000 INSTRUCTION BANK B SRAM (16K BYTES) 0xFFA0 4000 INSTRUCTION BANK A SRAM (16K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTES) 0xFF90 4000 DATA BANK B SRAM (16K BYTES) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTES) 0xFF80 4000 DATA BANK A SRAM (16K BYTES) 0xFF80 0000 RESERVED 0xEF00 8000 BOOT ROM (32K BYTES) EXTERNAL MEMORY MAP 0xEF00 0000 RESERVED 0x2040 0000 ASYNC MEMORY BANK 3 (1M BYTES) 0x2030 0000 ASYNC MEMORY BANK 2 (1M BYTES) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTES) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTES) 0x2000 0000 0x08 00 0000 RESERVED SDRAM MEMORY (16M BYTES - 128M BYTES) 0x0000 0000 Figure 2. ADSP-BF51x Internal/External Memory Map Rev. B The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank, and the SDRAM controller supports up to four internal SDRAM banks, improving overall performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory. Flash Memory The ADSP-BF512F/ADSP-BF514F/ADSP-BF516F/ ADSP-BF512F/ADSP-BF514F/ADSP-BF516F/ ADSP-BF518F ADSP-BF518F processors contain a SPI flash memory within the package of the processor and connected to SPI0. The SPI flash memory has a 4M bit capacity and 1.8V (nominal) operating voltage. The program/erase endurance is 100,000 cycles per block, and this memory has greater than 100 years of data retention capability. Also included are support for software write protection and for fast erase and byte-program. | Page 5 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F The processors internally connect to the flash memory die with the SPI0SCK, SPI0SEL4 or PH8, SPI0MOSI, and SPI0MISO signals similar to an external SPI flash. To further provide a secure processing environment, these internally connected signals are not exposed outside of the package. For this reason, programming the ADSP-BF51xF flash memory is performed by running code on the processor andcannot be programmed from external signals. Data transfers between the SPI flash and the processor cannot be probed externally. The flash memory has the following additional features · Serial Interface Architecture-SPI compatible with Mode 0 and Mode 3 · Superior Reliability-Endurance of 100,000 cycles and greater than 100 years data retention · Flexible Erase Capability-Uniform 4K Byte sectors and uniform 32 and 64K Byte overlay blocks · Fast Erase and Byte-Program-Chip-erase time = 125 ms (typical), Sector-/Block-Erase Time = 62 ms (typical) ByteProgram Time = 50 S (typical) · Auto Address Increment (AAI) Programming-Decreases total chip programming time over byte-program operations · End-of-Write Detection-Software polling the BUSY bit in status register, busy status readout on SO pin · Software Write Protection-Write protection through block-protection bits in status register One-Time Programmable Memory The processors have 64K bits of one-time programmable nonvolatile memory that can be programmed by the developer only once. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. The OTP memory allows both public and private data to be stored on-chip. In addition to storing public and private key data for applications requiring security, OTP allows developers to store completely user-definable data such as customer ID, product ID, and MAC address. Therefore, generic parts can be supplied which are then programmed and protected by the developer within this non-volatile memory. I/O Memory Space The processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memorymapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Rev. B Booting from ROM The processors contain a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processors are configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 14. EVENT HANDLING The event controller handles all asynchronous and synchronous events to the processor. The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: · Emulation-An emulation event causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface. · Reset-This event resets the processor. · Nonmaskable Interrupt (NMI)-The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. · Exceptions-Events that occur synchronously to program flow; that is, the exception is taken before the instruction is allowed to complete. Conditions such as data alignment violations and undefined instructions cause exceptions. · Interrupts-Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15 IVG15­7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15 IVG15­14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processors. The inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities are described in the ADSP-BF51x Blackfin Processor Hardware Reference Manual "System Interrupts" chapter. | Page 6 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F System Interrupt Controller (SIC) The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor Hardware Reference Manual "System Interrupts" chapter for the inputs into the SIC and the default mappings into the CEC. The SIC allows further control of event processing by providing three pairs of 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events. For more information, see the ADSP-BF51x Blackfin Processor Hardware Reference Manual "System Interrupts" chapter. DMA CONTROLLERS The ADSP-BF51x processors have multiple independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor's internal memories and any of its DMAcapable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The processors' DMA controller supports both one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. Examples of DMA types supported by the DMA controller include: · A single, linear buffer that stops upon completion · A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer · 1-D or 2-D DMA using a linked list of descriptors · 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, there are two memory DMA channels that transfer data between the various memories of the processor system. This enables transfers of blocks of data between any of the memories-including external SDRAM, ROM, SRAM, and flash memory-with minimal pro- Rev. B cessor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. The processors also have an external DMA controller capability via dual external DMA request signals when used in conjunction with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core. PROCESSOR PERIPHERALS The ADSP-BF51x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see Figure 1 on Page 4). The processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for the general-purpose I/O, rotary counter, TWI, three-phase PWM, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. Real-Time Clock The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the processors. The RTC peripheral has a dedicated power supply so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. | Page 7 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode or cause a transition from the hibernate state. Connect RTC signals RTXI and RTXO with external components as shown in Figure 3. RTXO RTXI The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. R1 X1 C1 mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the several other associated PF signals, an external clock input to the PPI_CLK input signal, or to the internal SCLK. C2 3-Phase PWM The processors integrate a flexible and programmable 3-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction (ACIM) or permanent magnet synchronous (PMSM) motor control. In addition, the PWM block contains special functions that considerably simplify the generation of the required PWM switching patterns for control of the electronically commutated motor (ECM) or brushless dc motor (BDCM). Software can enable a special mode for switched reluctance motors (SRM). SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J EC38J (THROUGH-HOLE PACKAGE) OR EPSON MC405 MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M: NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. Figure 3. External Components for RTC Features of the 3-phase PWM generation unit are: Watchdog Timer · 16-bit center-based PWM generation unit The ADSP-BF51x processors include a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. · Programmable PWM pulse width If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK) at a maximum frequency of fSCLK. Timers There are nine general-purpose programmable timer units in the ADSP-BF51x processors. Eight timers have an external signal that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a Rev. B · Single/double update modes · Programmable dead time and switching frequency · Twos-complement implementation which permits smooth transition to full ON and full OFF states · Possibility to synchronize the PWM generation to an external synchronization · Special provisions for BDCM operation (crossover and output enable functions) · Wide variety of special switched reluctance (SR) operating modes · Output polarity and clock gating control · Dedicated asynchronous PWM shutdown signal General-Purpose (GP) Counter A 32-bit GP counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. The counter can also operate in generalpurpose up/down count modes. Then, count direction is either controlled by a level-sensitive input signal or by two edge detectors. | Page 8 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three signals have a programmable debouncing circuit. An internal signal forwarded to the GP timer unit enables one timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. Serial Ports The ADSP-BF51x processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. In this configuration, one SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes: · Standard DSP serial mode · Multichannel (TDM) mode · I2S mode bit can be transferred to interrupt only addressed nodes in multi-drop bus (MDB) systems. A frame is terminates by one, one and a half, two or two and a half stop bits. The UART ports support automatic hardware flow control through the Clear To Send (CTS) input and Request To Send (RTS) output with programmable assertion FIFO levels. To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a programmable inter-frame space. The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) serial infrared physical layer link specification (SIR) protocol. 2-Wire Interface (TWI) The processors include a TWI module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I2C® bus standard. The TWI module offers the capabilities of simultaneous master and slave operation, support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two signals for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface signals are compatible with 5 V logic levels. Additionally, the processor's TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. · Packed I2S mode · Left-justified mode Removable Storage Interface (RSI) Serial Peripheral Interface (SPI) Ports The processors have two SPI-compatible ports (SPI0 and SPI1) that enable the processor to communicate with multiple SPIcompatible devices. The SPI interface uses three signals for transferring data: two data signals (master output-slave input­MOSI, and master input-slave output­MISO) and a clock signal (serial clock­SCK). An SPI chip select input signal (SPIxSS) lets other SPI devices select the processor, and multiple SPI chip select output signals let the processor select other SPI devices. The SPI select signals are reconfigured general-purpose I/O signals. Using these signals, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. The SPI port baud rate and clock phase/polarities are programmable, and it has an integrated DMA channel, configurable to support transmit or receive data streams. The SPI's DMA channel can only service unidirectional accesses at any given time. UART Ports The processors provide two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. Optionally, an additional address Rev. B The RSI controller, available on the ADSP-BF514 ADSP-BF514, ADSPBF516 ADSPBF516, ADSP-BF518 ADSP-BF518, and ADSP-BF518F ADSP-BF518F acts as the host interface for multi-media cards (MMC), secure digital memory cards (SD Card), secure digital input/output cards (SDIO), and CEATA hard disk drives. The following list describes the main features of the RSI controller. · Support for a single MMC, SD memory, SDIO card or CEATA hard disk drive · Support for 1-bit and 4-bit SD modes · Support for 1-bit, 4-bit and 8-bit MMC modes · Support for 4-bit and 8-bit CE-ATA hard disk drives · A ten-signal external interface with clock, command, and up to eight data lines · Card detection using one of the data signals · Card interface clock generation from SCLK · SDIO interrupt and read wait features · CE-ATA command completion signal recognition and disable | Page 9 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F 10/100 Ethernet MAC The ADSP-BF516/ADSP-BF516F ADSP-BF516/ADSP-BF516F and ADSPBF518/ADSPBF518F ADSPBF518/ADSPBF518F processors offer the capability to directly connect to a network by way of an embedded fast Ethernet media access controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. Some standard features are: · Support of MII and RMII protocols for external PHYs · Full duplex and half duplex modes · Data framing and encapsulation: generation and detection of preamble, length padding, and FCS · Media access management (in half-duplex operation): collision and contention handling, including control of retransmission of collision frames and of back-off timing · Flow control (in full-duplex operation): generation and detection of pause frames · Station management: generation of MDC/MDIO frames for read-write access to PHY registers · Programmable receive address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames · Advanced power management supporting unattended transfer of receive and transmit frames and status to/from external memory via DMA during low power sleep mode · System wakeup from sleep operating mode upon magic packet or any of four user-definable wakeup frame filters · Support for 802.3Q tagged VLAN frames · Programmable MDC clock rate and preamble suppression · In RMII operation, seven unused signals may be configured as GPIO signals for other purposes IEEE 1588 Support The IEEE 1588 standard is a precision clock synchronization protocol for networked measurement and control systems. The ADSP-BF518/ADSP-BF518F ADSP-BF518/ADSP-BF518F processors include hardware support for IEEE 1588 with an integrated precision time protocol synchronization engine (PTP_TSYNC). This engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the PTP_SYNC engine are: · Operating range for active and sleep operating modes, see Table 43 on Page 45 and Table 44 on Page 46 · Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards · Internal loopback from transmit to receive · Hardware assisted time stamping capable of up to 12.5 ns resolution Some advanced features are: · Buffered crystal output to external PHY for support of a single crystal system · Lock adjustment · Programmable PTM message support · Automatic checksum computation of IP header and IP payload fields of Rx frames · Dedicated interrupts · Independent 32-bit descriptor-driven receive and transmit DMA channels · Multiple input clock sources (SCLK, MII clock, external clock) · Frame status delivery to memory through DMA, including frame completion semaphores for efficient buffer queue management in software · Programmable pulse per second (PPS) output · Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations · Convenient frame alignment modes support even 32-bit alignment of encapsulated receive or transmit IP packet data in memory after the 14-byte MAC header · Programmable Ethernet event interrupt supports any combination of: · Selected receive or transmit frame status conditions · PHY interrupt condition · Wakeup frame detected · Selected MAC management counter(s) at half-full · DMA descriptor error · 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value Rev. B · Programmable alarm · Auxiliary snapshot to time stamp external events Ports Because of the rich set of peripherals, the processors group the many peripheral signals to four ports-port F, port G, port H, and port J. Most of the associated pins/balls are shared by multiple signals. The ports function as multiplexer controls. General-Purpose I/O (GPIO) The ADSP-BF51x processors have 40 bidirectional, generalpurpose I/O (GPIO) signals allocated across three separate GPIO modules-PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and Port H, respectively. Each GPIO-capable signal shares functionality with other peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output nor input drivers are active by default. Each general-purpose port signal can be individually controlled by manipulation of the port control, status, and interrupt registers. | Page 10 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology The ADSP-BF51x processors provide a parallel peripheral interface (PPI) that can connect directly to parallel analog-to-digital and digital-to-analog converters, ITU-R-601/656 ITU-R-601/656 video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock signal, up to three frame synchronization signals, and up to 16 data signals. A security system consisting of a blend of hardware and software provides customers with a flexible and rich set of code security features with Lockbox® secure technology. Key features include: In ITU-R-656 ITU-R-656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported. Three distinct ITU-R-656 ITU-R-656 modes are supported: · Active video only mode-The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. · Vertical blanking only mode-The PPI only transfers vertical blanking interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines. · Entire field mode-The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Though not explicitly supported, ITU-R-656 ITU-R-656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor's 2-D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle: · Data receive with internally generated frame syncs · Data receive with externally generated frame syncs · Data transmit with internally generated frame syncs · Data transmit with externally generated frame syncs These modes support ADC/DAC connections, as well as video communication with hardware signalling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data. Rev. B · OTP memory · Unique chip ID · Code authentication · Secure mode of operation The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. DYNAMIC POWER MANAGEMENT The ADSP-BF51x processors provide four operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. When configured for a 0 V core supply voltage, the processor enters the hibernate state. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 2 for a summary of the power settings for each mode. Table 2. Power Settings Mode/State PLL Core PLL Clock Bypassed (CCLK) System Clock (SCLK) Core Power Full On Enabled No Enabled Enabled On Active Enabled/ Yes Disabled Enabled Enabled On Sleep Enabled - Disabled Enabled On Deep Sleep Disabled - Disabled Disabled On Hibernate Disabled - Disabled Disabled Off Full-On Operating Mode-Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed. Active Operating Mode-Moderate Power Savings In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. DMA access is available to appropriately configured L1 memories. | Page 11 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F In the active mode, it is possible to disable the PLL through the PLL control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the full-on or sleep modes. Sleep Operating Mode-High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity wakes up the processor. When in the sleep mode, asserting wakeup causes the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full on mode. If BYPASS is enabled, the processor transitions to the active mode. System DMA access to L1 memory is not supported in sleep mode. Deep Sleep Operating Mode-Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode. Hibernate State-Maximum Static Power Savings The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and system blocks (SCLK). Any critical information stored internally (for example memory contents, register contents) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. Writing b#00 to the FREQ bits in the VR_CTL register also causes the EXT_WAKE signal to transition low, which can be used to signal an external voltage regulator to shut down. Since VDDEXT is still supplied in this mode, all of the external signals three-state, unless otherwise specified. This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. The Ethernet module can signal an external regulator to wake up using the EXT_WAKE signal. If PF15 does not connect as a PHYINT signal to an external PHY device, it can be pulled low by any other device to wake the processor up. The processor can also be woken up by a real-time clock wakeup event or by asserting the RESET pin. All hibernate wakeup events initiate the hardware reset sequence. Individual sources are enabled by the VR_CTL register. The EXT_WAKE signal is provided to indicate the occurrence of wakeup events. With the exception of the VR_CTL and the RTC registers, all internal registers and memories lose their content in the hibernate state. State variables may be held in external SRAM or Rev. B SDRAM. The SCKELOW bit in the VR_CTL register controls whether or not SDRAM operates in self-refresh mode, which allows it to retain its content while the processor is in hibernation and through the subsequent reset sequence. Power Savings As shown in Table 3, the processors support up to six different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor Operating Conditions; even if the feature/peripheral is not used. Table 3. Power Domains Power Domain VDD Range All internal logic, except RTC, Memory, OTP VDDINT RTC internal logic and crystal I/O VDDRTC Memory logic VDDMEM OTP logic VDDOTP Optional internal flash VDDFLASH All other I/O VDDEXT The dynamic power management feature of the processor allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. Power Savings Factor f CCLKRED V DDINTRED 2 T RED = - × - × - T NOM f CCLKNOM V DDINTNOM % Power Savings = ( 1 ­ Power Savings Factor ) × 100% where the variables in the equations are: fCCLKNOM is the nominal core clock frequency fCCLKRED is the reduced core clock frequency VDDINTNOM is the nominal internal supply voltage VDDINTRED is the reduced internal supply voltage | Page 12 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F TNOM is the duration running at fCCLKNOM BLACKFIN TRED is the duration running at fCCLKRED CLKOUT VOLTAGE REGULATION INTERFACE TO PLL CIRCUITRY The ADSP-BF51x processors require an external voltage regulator to power the VDDINT domain. To reduce standby power consumption in the hibernate state, the external voltage regulator can be signaled through EXT_WAKE to remove power from the processor core. The EXT_WAKE signal is high-true for power-up and may be connected directly to the low-true shut down input of many common regulators. The Power Good (PG) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of the PG functionality, refer to the ADSP-BF51x Blackfin Processor Hardware Reference. CLOCK SIGNALS The ADSP-BF51x processors can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor CLKIN signal. When an external clock is used, the XTAL pin/ball must be left unconnected. Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade crystal is connected across the CLKIN and XTAL pins/balls. The on-chip resistance between the CLKIN pin/ball and the XTAL pin/ball is in the 500 k range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in Figure 4 fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 4 are typical values only. The capacitor values are dependent upon the crystal manufacturers' load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range. A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in Figure 4. A design procedure for third-overtone operation is discussed in detail in application note (EE-168 EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)-use site search on "EE-168 EE-168." EN CLKBUF 560 EN 330 * 18 pF * FOR OVERTONE OPERATION ONLY: 18 pF * NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED RESISTOR VALUE SHOULD BE REDUCED TO 0 . Figure 4. External Crystal Connections 25 MHz or 50 MHz crystal may be applied directly to the processor. The 25 MHz or 50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device. The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 5, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a programmable 5× to 64× multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 6×, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be done simply by writing to the PLL_DIV register. The maximum allowed CCLK and SCLK rates depend on the applied voltages VDDINT, VDDEXT, and VDDMEM, and the VCO is always permitted to run up to the frequency specified by the part's speed grade. The CLKOUT signal reflects the SCLK frequency to the off-chip world. It belongs to the SDRAM interface, but it functions as a reference signal in other timing specifications as well. While active by default, it can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL registers. "FINE" ADJUSTMENT REQUIRES PLL SEQUENCING "COARSE" ADJUSTMENT ON-THE-FLY ÷ 1, 2, 4, 8 CLKIN | Page 13 of 68 | January 2011 CCLK ÷ 1 to 15 PLL 5u to 64u The CLKBUF signal is an output signal, which is a buffered version of the input clock. This signal is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single Rev. B XTAL CLKIN SCLK VCO Figure 5. Frequency Modification Methods ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3­0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 4 illustrates typical system clock ratios. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). bits of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the modes shown in Table 6. Table 6. Booting Modes BMODE2­0 Description Table 5. Core Clock Ratios Signal Name CSEL1­0 Example Frequency Ratios Divider Ratio (MHz) VCO/CCLK VCO CCLK 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 Table 4. Example System Clock Ratios Signal Name SSEL3­0 Example Frequency Ratios Divider Ratio (MHz) VCO/SCLK VCO SCLK 0010 2:1 0110 1010 100 50 6:1 300 50 10:1 400 40 Idle - No boot 001 Boot from 8- or 16-bit external flash memory 010 Boot from internal SPI memory 011 Boot from external SPI memory (EEPROM or flash) 100 Boot from SPI0 host 101 Boot from OTP memory 110 Boot from SDRAM 111 The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1­0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 5. This programmable core clock capability is useful for fast core frequency modifications. 000 Boot from UART0 Host · Idle/no boot mode (BMODE = 0x0)-In this mode, the processor goes into idle. The idle boot mode helps recover from illegal operating modes, such as when the user has mis configured the OTP memory. · Boot from 8-bit or 16-bit external flash memory (BMODE = 0x1)-In this mode, the boot kernel loads the first block header from address 0x2000 0000 and-depending on instructions containing in the header-the boot kernel performs 8-bit or 16-bit boot or starts program execution at the address provided by the header. By default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup). The ARDY is not enabled by default, but it can be enabled by OTP programming. Similarly, all interface behavior and timings can be customized by OTP programming. This includes activation of burst-mode or page-mode operation. In this mode, all signals belonging to the asynchronous interface are enabled at the port muxing level. The maximum CCLK frequency not only depends on the part's speed grade (see Page 65), it also depends on the applied VDDINT voltage. See Table 9 for details. The maximal system clock rate (SCLK) depends on the chip package and the applied VDDINT, VDDEXT, and VDDMEM voltages (see Table 11 on Page 21). · Boot from internal SPI memory (BMODE = 0x2)-The processor uses the internal PH8 GPIO signal to load code previously loaded to the 4 Mbit internal SPI flash connected to SPI0. Only available on the ADSP-BF512F/ ADSP-BF512F/ ADSP-BF514F/ADSP-BF516F/ADSP-BF518F ADSP-BF514F/ADSP-BF516F/ADSP-BF518F. BOOTING MODES · Boot from external SPI EEPROM or flash (BMODE = 0x3)-8-bit, 16-bit, 24-bit or 32-bit addressable devices are supported. The processor uses the PG15 GPIO signal (at SPI0SEL2) to select a single SPI EEPROM/flash device connected to the SPI0 interface; then submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SSEL and MISO signals. By default, a value of 0x85 is written to the SPI0_BAUD register. The processor has several mechanisms (listed in Table 6) for automatically loading internal and external memory after a reset. The boot mode is defined by three BMODE input bits dedicated to this purpose. There are two categories of boot modes. In master boot modes the processor actively loads data from parallel or serial memories. In slave boot modes the processor receives data from external host devices. The boot modes listed in Table 6 provide a number of mechanisms for automatically loading the processor's internal and external memories after a reset. By default, all boot modes use the slowest meaningful configuration settings. Default settings can be altered via the initialization code feature at boot time or by proper OTP programming at pre-boot time. The BMODE Rev. B · Boot from SPI0 host device (BMODE = 0x4)-The processor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. In the host, the HWAIT signal must be interrogated by the | Page 14 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F host before every transmitted byte. A pull-up resistor is required on the SPI0SS input. A pull-down on the serial clock may improve signal quality and booting robustness. · Boot from OTP memory (BMODE = 0x5)-This provides a stand-alone booting method. The boot stream is loaded from on-chip OTP memory. By default the boot stream is expected to start from OTP page 0x40 on and can occupy all public OTP memory up to page 0xDF. This is 2560 bytes. Since the start page is programmable the maximum size of the boot stream can be extended to 3072 bytes. · Boot from SDRAM (BMODE = 0x6)-This is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured by the OTP settings. · Boot from UART0 host (BMODE = 0x7)-Using an autobaud handshake sequence, a boot-stream formatted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities. When performing the autobaud, the UART expects a "@" (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the RX0 signal to determine the bit rate. The UART then replies with an acknowledgement composed of 4 bytes (0xBF-the value of UART0_DLL and 0x00-the value of UART0_DLH). The host can then download the boot stream. To hold off the host the Blackfin processor signals the host with the boot host wait (HWAIT) signal. Therefore, the host must monitor HWAIT before every transmitted byte. For each of the boot modes, a 16-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the address stored in the EVT1 register. Prior to booting, the pre-boot routine interrogates the OTP memory. Individual boot modes can be customized or even disabled based on OTP programming. External hardware, especially booting hosts may watch the HWAIT signal to determine when the pre-boot has finished and the boot kernel starts the boot process. By programming OTP memory, the user can instruct the preboot routine to also customize the PLL, the SDRAM Controller, and the Asynchronous Interface. The boot kernel differentiates between a regular hardware reset and a wakeup-from-hibernate event to speed up booting in the later case. Bits 6-4 in the system reset configuration (SYSCR) register can be used to bypass pre-boot routine and/or boot kernel in case of a software reset. They can also be used to simulate a wakeup-from-hibernate boot in the software reset case. The boot process can be further customized by "initialization code." This is a piece of code that is loaded and executed prior to the regular application boot. Typically, this is used to configure the SDRAM controller or to speed up booting by managing PLL, clock frequencies, wait states, or serial bit rates. Rev. B The boot ROM also features C-callable function entries that can be called by the user application at run time. This enables second-stage boot or boot management schemes to be implemented with ease. INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C+ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: · Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations. · A multi-issue load/store modified-harvard architecture, which supports two 16-bit MACs or four 8-bit ALUs plus two load/store plus two pointer updates per cycle. · All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. · Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. · Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS The ADSP-BF51x processors are supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP+® development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF51x processors. For more information about development tools, visit www.analog.com. EZ-KIT Lite Evaluation Board For evaluation of the processors, use the EZ-KIT Lite® board being developed by Analog Devices. The board comes with onchip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. | Page 15 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET) The Application Signal Chains page in the Circuits from the LabTM site (http://www.analog.com/circuits) provides: The Analog Devices family of emulators are tools that every system developer needs in order to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (EE-68 EE-68) Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)- use site search on "EE-68 EE-68." This document is updated regularly to keep pace with improvements to emulator support. RELATED DOCUMENTS The following publications that describe the ADSP-BF512/ ADSP-BF512/ ADSP-BF514/ADSP-BF516/ADSP-BF518 ADSP-BF514/ADSP-BF516/ADSP-BF518 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: · Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications · Drill down links for components in each chain to selection guides and application information · Reference designs applying best practice design techniques LOCKBOX SECURE TECHNOLOGY DISCLAIMER Analog Devices products containing Lockbox Secure Technology are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowledge, the Lockbox Secure Technology, when used in accordance with the data sheet and hardware reference manual specifications, provides a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. · Getting Started With Blackfin Processors · ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Blackfin Processor Hardware Reference · ADSP-BF53x/BF56x Blackfin Processor Programming Reference · ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Blackfin Processor Anomaly List RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the "signal chain" entry in Wikipedia or the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. Rev. B | Page 16 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F SIGNAL DESCRIPTIONS The processors' signal definitions are listed in Table 7. In order to maintain maximum function and reduce package size and signal count, some signals have dual, multiplexed functions. In cases where signal function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. All pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchronous and synchronous memory control, and the buffered XTAL output pin (CLKBUF). On the external memory interface, the control and address lines are driven high, with the exception of CLKOUT, which toggles at the system clock rate. During hibernate all outputs are three-stated unless otherwise noted in Table 7. All I/O signals have their input buffers disabled with the exception of the signals noted in the data sheet that need pull-ups or pull downs if unused. The SDA (serial data) and SCL (serial clock) pins/balls are open drain and therefore require a pullup resistor. Consult version 2.1 of the I2C specification for the proper resistor value. It is strongly advised to use the available IBIS models to ensure that a given board design meets overshoot/undershoot and signal integrity requirements. If no IBIS simulation is performed, it is strongly recommended to add series resistor terminations for all Driver Types A, C and D. The termination resistors should be placed near the processor to reduce transients and improve signal integrity. The resistance value, typically 33 or 47 , should be chosen to match the average board trace impedance. Additionally, adding a parallel termination to CLKOUT may prove useful in further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual hardware. Table 7. Signal Descriptions Type Function Driver Type1 ADDR19 ADDR19­1 O Address Bus A DATA15 DATA15­0 I/O Data Bus A Signal Name EBIU ABE1­0/SDQM1­0 O Byte Enable or Data Mask A AMS1­0 O Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used) A ARE O Asynchronous Memory Read Enable A AWE O Asynchronous Memory Write Enable A SRAS O SDRAM Row Address Strobe A SCAS O SDRAM Column Address Strobe A SWE O SDRAM Write Enable A SCKE O SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-refresh A is used) CLKOUT O SDRAM Clock Output B SA10 O SDRAM A10 Signal A SMS O SDRAM Bank Select A PF0/ETxD2/PPI D0/SPI1SEL2/TACLK6 I/O GPIO/Ethernet MII Transmit D2/PPI Data 0/SPI1 Slave Select 2/Timer6 Alternate Clock C PF1/ERxD2/PPI D1/PWM AH/TACLK7 I/O GPIO/Ethernet MII Receive D2/PPI Data 1/PWM AH Output/Timer7 Alternate Clock C PF2/ETxD3/PPI D2/PWM AL I/O GPIO/Ethernet Transmit D3/PPI Data 2/PWM AL Output PF3/ERxD3/PPI D3/PWM BH/TACLK0 I/O GPIO/Ethernet MII Data Receive D3/PPI Data 3/PWM BH Output/Timer0 Alternate C Clock PF4/ERxCLK/PPI D4/PWM BL/TACLK1 I/O GPIO/Ethernet MII Receive Clock/PPI Data 4/PWM BL Out/Timer1 Alternate CLK C PF5/ERxDV/PPI D5/PWM CH/TACI0 I/O GPIO/Ethernet MII Receive Data Valid/PPI Data 5/PWM CH Out /Timer0 Alternate Capture Input C PF6/COL/PPI D6/PWM CL/TACI1 I/O GPIO/Ethernet MII Collision/PPI Data 6/PWM CL Out/Timer1 Alternate Capture Input C PF7/SPI0SEL1/PPI D7/PWMSYNC I/O GPIO/SPI0 Slave Select 1/PPI Data 7/PWM Sync Port F: GPIO and Multiplexed Peripherals Rev. B | Page 17 of 68 | January 2011 C C ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Table 7. Signal Descriptions Signal Name Type Function Driver Type1 PF8/MDC/PPI D8/SPI1SEL4 I/O GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4 C PF9/MDIO/PPI D9/TMR2 I/O GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2 C PF10/ETxD0/PPI D10/TMR3 D10/TMR3 I/O GPIO/Ethernet MII or RMII Transmit D0/PPI Data 10/Timer 3 C PF11/ERxD0/PPI D11/PWM D11/PWM AH/TACI3 I/O GPIO/Ethernet MII Receive D0/PPI Data 11/PWM 11/PWM AH output /Timer3 Alternate Capture Input C PF12/ETxD1/PPI D12/PWM D12/PWM AL I/O GPIO/Ethernet MII Transmit D1/PPI Data 12/PWM 12/PWM AL Output C PF13/ERxD1/PPI D13/PWM D13/PWM BH I/O GPIO/Ethernet MII or RMII Receive D1/PPI Data 13/PWM 13/PWM BH Output C PF14/ETxEN/PPI D14/PWM D14/PWM BL I/O GPIO/Ethernet MII Transmit Enable/PPI Data 14/PWM 14/PWM BL Out C PF152/RMII PF152/RMII PHYINT/PPI D15/PWM D15/PWM_SYNCA I/O GPIO/Ethernet MII PHY Interrupt/PPI Data 15/Alternate PWM Sync C PG0/MIICRS/RMIICRS/HWAIT 3/SPI1SEL3 I/O GPIO/Ethernet MII or RMII Carrier Sense or RMII Data Valid/HWAIT/SPI1 Slave Select3 C PG1/ERxER/DMAR1/PWM CH I/O GPIO/Ethernet MII or RMII Receive Error/DMA Req 1/PWM CH Out C GPIO/Ethernet MII or RMII Reference Clock/DMA Req 0/PWM CL Out C Port G: GPIO and Multiplexed Peripherals PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3 I/O GPIO/SPORT0 Primary Rx Data/RSI Data 0/SPI0 Slave Select 5/Timer3 Alternate CLK C PG4/RSCLK0/RSI_DATA1/TMR5/TACI5 I/O GPIO/SPORT0 Rx Clock/RSI Data 1/Timer 5/Timer5 Alternate Capture Input D PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK I/O GPIO/SPORT0 Rx Frame Sync/RSI Data 2/PPI Clock/External Timer Reference C PG6/TFS0/RSI_DATA3/TMR0/PPIFS1 I/O GPIO/SPORT0 Tx Frame Sync/RSI Data 3/Timer0/PPI Frame Sync1 C PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2 I/O GPIO/SPORT0 Tx Primary Data/RSI Command/Timer 1/PPI Frame Sync2 C PG8/TSCLK0/RSI_CLK/TMR6/TACI6 I/O GPIO/SPORT0 Tx Clock/RSI Clock/Timer 6/Timer6 Alternate Capture Input D PG9/DT0SEC/UART0TX/TMR4 I/O GPIO/SPORT0 Secondary Tx Data/UART0 Transmit/Timer 4 C PG10/DR0SEC/UART0RX/TACI4 PG10/DR0SEC/UART0RX/TACI4 I/O GPIO/SPORT0 Secondary Rx Data/UART0 Receive/Timer4 Alternate Capture Input C PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2 PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2 I/O GPIO/SPI0 Slave Device Select/Asynchronous Memory Bank Select 2/SPI1 Slave Select 5/Timer2 Alternate CLK C PG12/SPI0SCK/PPICLK/TMRCLK/PTP PG12/SPI0SCK/PPICLK/TMRCLK/PTP_PPS I/O GPIO/SPI0 Clock/PPI Clock/External Timer Reference/PTP Pulse Per Second Out D PG13/SPI0MISO4/TMR0/PPIFS1/ PG13/SPI0MISO4/TMR0/PPIFS1/ PTP_CLKOUT I/O GPIO/SPI0 Master In Slave Out/Timer0/PPI Frame Sync1/PTP Clock Out C PG14/SPI0MOSI/TMR1/PPIFS2/PWM PG14/SPI0MOSI/TMR1/PPIFS2/PWM TRIP /PTP_AUXIN I/O GPIO/SPI0 Master Out Slave In/Timer 1/PPI Frame Sync2/PWM Trip/PTP Auxiliary Snapshot Trigger Input C PG15/SPI0SEL2/PPIFS3/AMS3 PG15/SPI0SEL2/PPIFS3/AMS3 I/O GPIO/SPI0 Slave Select 2/PPI Frame Sync3/Asynchronous Memory Bank Select 3 C PH0/DR1PRI/SPI1SS/RSI_DATA4 I/O GPIO/SPORT1 Primary Rx Data/SPI1 Device Select/RSI Data 4 C PH1/RFS1/SPI1MISO/RSI_DATA5 I/O GPIO/SPORT1 Rx Frame Sync/SPI1 Master In Slave Out/RSI Data 5 C PH2/RSCLK1/SPI1SCK/RSI DATA6 I/O GPIO/SPORT1 Rx Clock/SPI1 Clock/RSI Data 6 D Port H: GPIO and Multiplexed Peripherals PH3/DT1PRI/SPI1MOSI/RSI DATA7 I/O GPIO/SPORT1 Primary Tx Data/SPI1 Master Out Slave In/RSI Data 7 C PH4/TFS1/AOE/SPI0SEL3/CUD I/O GPIO/SPORT1 Tx Frame Sync/Asynchronous Memory Output Enable/SPI0 Slave Select 3/Counter Up Direction C PH5/TSCLK1/ARDY/PTP_EXT_CLKIN/CDG I/O GPIO/SPORT1 Tx Clock/Asynchronous Memory Hardware Ready Control/ External Clock for PTP TSYNC/Counter Down Gate D PH6/DT1SEC/UART1TX/SPI1SEL1/CZM I/O GPIO/SPORT1 Secondary Tx Data/UART1 Transmit/SPI1 Slave Select 1 /Counter Zero Marker C PH7/DR1SEC/UART1RX/TMR7/TACI2 I/O GPIO/SPORT1 Secondary Rx Data/UART1 Receive/Timer 7/Timer2 Alternate Clock C Input Rev. B | Page 18 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Table 7. Signal Descriptions Signal Name Type Function Driver Type1 Port J PJ0:SCL E I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up resistor. Consult version 2.1 of the I2C specification for the proper resistor value.) PJ1:SDA E I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up resistor. Consult version 2.1 of the I2C specification for the proper resistor value.) Real Time Clock RTXI I RTC Crystal Input (This ball should be pulled low when not used.) RTXO O RTC Crystal Output (Does not three-state during hibernate) TCK I JTAG Clock TDO O JTAG Serial Data Out TDI I JTAG Serial Data In JTAG Port TMS I JTAG Mode Select TRST I JTAG Reset (This signal should be pulled low if the JTAG port is not used.) EMU O Emulation Output C C Clock CLKIN I Clock/Crystal Input XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate) CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate) RESET I Reset NMI I Non-maskable Interrupt (This signal should be pulled high when not used.) BMODE2-0 I Boot Mode Strap 2-0 PG I Power Good (This signal should be pulled low when not used.) EXT_WAKE O Wake up Indication (Does not three-state during hibernate) C Mode Controls Voltage Regulation Interface Power Supplies C ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page 20. VDDEXT P I/O Power Supply VDDINT P Internal Power Supply VDDRTC P Real Time Clock Power Supply VDDFLASH P Internal SPI Flash Power Supply VDDMEM P MEM Power Supply VPPOTP P OTP Programming Voltage VDDOTP P OTP Power Supply GND G Ground for All Supplies 1 See Output Drive Currents on Page 50 for more information about each driver type. When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor. 3 Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity. 4 A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3). 2 Rev. B | Page 19 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS Parameter VDDINT Internal Supply Voltage Internal Supply Voltage Conditions Industrial Models Commercial Models Min 1.14 1.10 Internal Supply Voltage Automotive Models 1.33 1.8 V I/O, Nonautomotive Models 2.5 V I/O, Nonautomotive Models 1.7 2.25 VDDEXT1, 2 External Supply Voltage External Supply Voltage External Supply Voltage VDDMEM3 MEM Supply Voltage MEM Supply Voltage MEM Supply Voltage VDDRTC4 RTC Power Supply Voltage VDDFLASH4 Internal SPI Flash Supply Voltage VDDOTP OTP Supply Voltage VPPOTP OTP Programming Voltage For Reads1 For Writes5 VIH High Level Input Voltage6, 7 High Level Input Voltage6, 7 High Level Input Voltage6, 7 VIHTWI High Level Input Voltage VIL Low Level Input Voltage6, 7 Low Level Input Voltage6, 7 Low Level Input Voltage6, 7 VILTWI Low Level Input Voltage Junction Temperature Junction Temperature Junction Temperature Junction Temperature Nominal Max 1.47 1.47 Unit V V 1.47 1.8 2.5 V 1.9 2.75 V V 3.3 V I/O, All Models 3.0 3.3 3.6 V 1.8 V I/O, Nonautomotive Models 2.5 V I/O, Nonautomotive Models 1.7 2.25 1.8 2.5 1.9 2.75 V V 3.3 V I/O, All Models 3.0 3.6 V 1.8 3.6 1.9 V V 2.25 VDDEXT/VDDMEM = 1.90 V VDDEXT/VDDMEM = 2.75 V VDDEXT/VDDMEM = 3.6 V VDDEXT = 1.90 V/2.75 V/3.6 V VDDEXT/VDDMEM = 1.7 V VDDEXT/VDDMEM = 2.25 V VDDEXT/VDDMEM = 3.0 V VDDEXT = Minimum 168-Ball CSP_BGA @ TAMBIENT = 0°C to +70°C 168-Ball CSP_BGA @ TAMBIENT = ­40°C to +85°C 176-Lead LQFP @ TAMBIENT = 0°C to +70°C 176-Lead LQFP @ TAMBIENT = ­40°C to +85°C 3.3 2.25 1.7 2.5 2.75 V 2.25 2.5 6.9 7.0 1.2 1.7 2 0.7 x VBUSTWI 2.75 7.1 V V V V V V V V V V °C °C °C °C 0 ­40 0 ­40 1 VBUSTWI8 0.6 0.7 0.8 0.3 x VBUSTWI9 +95 +105 +95 +105 Must remain powered (even if the associated function is not used). VDDEXT is the supply to the GPIO. 3 Pins/balls that use VDDMEM are DATA15 DATA15­0, ADDR19 ADDR19­1, ABE1­0, ARE, AWE, AMS1­0, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These pins/balls are not tolerant to voltages higher than VDDMEM. When using any of the asynchronous memory signals AMS3­2, ARDY, or AOE VDDMEM and VDDEXT must be shorted externally. 4 If not used, power with VDDEXT. 5 The VPPOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent on voltage and junction temperature) over the lifetime of the part. 6 Bidirectional pins/balls (PF15­0, PG15­0, PH7­0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2­0) of the ADSP-BF51x are 3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 7 Parameter value applies to all input and bidirectional pins/balls except SDA and SCL. 8 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 8. 9 SDA and SCL are pulled up to VBUSTWI. See Table 8. 2 Rev. B | Page 20 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Table 8 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port. Table 8. TWI_DT Field Selections and VDDEXT/VBUSTWI TWI_DT 000 (default) 001 010 011 100 101 110 111 (reserved) VDDEXT Nominal 3.3 1.8 2.5 1.8 3.3 1.8 2.5 - VBUSTWI Minimum 2.97 1.7 2.97 2.97 4.5 2.25 2.25 - VBUSTWI Nominal 3.3 1.8 3.3 3.3 5 2.5 2.5 - VBUSTWI Maximum 3.63 1.98 3.63 3.63 5.5 2.75 2.75 - Unit V V V V V V V - Clock Related Operating Conditions Table 9 describes the timing requirements for the processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. Table 10 describes phase-locked loop operating conditions. Table 9. Core Clock (CCLK) Requirements Parameter fCCLK Nominal Voltage Setting Core Clock Frequency (VDDINT =1.33 V Minimum, All Models) 1.400 V Core Clock Frequency (VDDINT =1.23 V Minimum, Industrial/Commercial Models) 1.300 V Core Clock Frequency (VDDINT = 1.14 V Minimum, Industrial Models Only) 1.200 V Core Clock Frequency (VDDINT = 1.10 V Minimum, Commercial Models Only) 1.150 V Maximum 400 300 200 200 Unit MHz MHz MHz MHz Table 10. Phase-Locked Loop Operating Conditions Parameter Min Max Unit 1 MHz MHz 1 Voltage Controlled Oscillator (VCO) Frequency (Commercial/Industrial Models) 72 Instruction Rate Voltage Controlled Oscillator (VCO) Frequency (Automotive Models) fVCO 84 Instruction Rate1 For more information, see Ordering Guide on Page 65. Table 11. SCLK Conditions VDDEXT/VDDMEM 1.8 V Nominal Parameter1 VDDEXT/VDDMEM 2.5 V or 3.3 V Nominal Max Max Unit fSCLK CLKOUT/SCLK Frequency (VDDINT 1.230 V Minimum) 80 100 MHz fSCLK CLKOUT/SCLK Frequency (VDDINT < 1.230 V) 80 80 MHz 1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 28 on Page 31. Rev. B | Page 21 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min High Level Output Voltage VDDEXT /VDDMEM = 1.7 V, IOH = ­0.5 mA 1.35 V High Level Output Voltage VDDEXT /VDDMEM = 2.25 V, IOH = ­0.5 mA 2 V High Level Output Voltage VDDEXT /VDDMEM = 3.0 V, IOH = ­0.5 mA 2.4 V VOL Low Level Output Voltage VDDEXT /VDDMEM = 1.7/2.25/3.0 V, IOL = 2.0 mA 0.4 V IIH1 High Level Input Current VDDEXT /VDDMEM =3.6 V, VIN = 3.6 V 10 A Low Level Input Current VDDEXT /VDDMEM =3.6 V, VIN = 0 V 10 A High Level Input Current JTAG VDDEXT = 3.6 V, VIN = 3.6 V 75 A IOZH3 Three-State Leakage Current VDDEXT /VDDMEM= 3.6 V, VIN = 3.6 V 10 A IOZHTWI4 Three-State Leakage Current VDDEXT =3.0 V, VIN = 5.5 V 10 A IOZL3 10 A 8 pF 15 pF VOH IIL1 IIHP 2 Typical Max Unit Three-State Leakage Current VDDEXT /VDDMEM= 3.6 V, VIN = 0 V 5, 6 Input Capacitance fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V CINTWI4, 6 Input Capacitance fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V IDDDEEPSLEEP7 VDDINT Current in Deep Sleep Mode VDDINT = 1.3 V, fCCLK = 0 MHz, fSCLK = 0 MHz, TJ = 25°C, ASF = 0.00 2.1 mA IDDSLEEP VDDINT Current in Sleep Mode VDDINT = 1.3 V, fSCLK = 25 MHz, TJ = 25°C 5.5 mA IDD-IDLE VDDINT Current in Idle VDDINT = 1.3 V, fCCLK = 50 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 0.41 12 mA IDD-TYP VDDINT Current VDDINT = 1.3 V, fCCLK = 300 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 77 mA IDD-TYP VDDINT Current VDDINT = 1.4 V, fCCLK = 400 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 108 mA IDDHIBERNATE8 Hibernate State Current VDDEXT =VDDMEM =VDDRTC = 3.30 VVDDOTP =VPPOTP =2.5 V, TJ = 25°C, CLKIN = 0 MHz @ TJ = 25°C 40 A IDDRTC VDDRTC Current VDDRTC = 3.3 V, TJ = 25°C 20 A VDDINT Current in Sleep Mode fCCLK = 0 MHz, fSCLK > 0 MHz Table 13 + (0.20 × VDDINT × fSCLK) mA10 IDDDEEPSLEEP8, 10 VDDINT Current in Deep Sleep Mode fCCLK = 0 MHz, fSCLK = 0 MHz Table 13 mA CIN IDDSLEEP 8, 9 Rev. B | Page 22 of 68 | January 2011 5 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Parameter IDDINT 10, 11 Test Conditions VDDINT Current Min Typical Max Table 13 + (Table 14 × ASF) + (0.20 × VDDINT × fSCLK) fCCLK> 0 MHz, fSCLK 0 MHz Unit mA IDDFLASH1 Flash Memory Supply Current 1 -Asynchronous Read 10 6 mA IDDFLASH2 Flash Memory Supply Current 2 -Standby 4 12 A IDDFLASH3 Flash Memory Supply Current 3 -Program and Erase 11 16 mA IDDOTP VDDOTP Current VDDOTP = 2.5 V, TJ = 25°C, OTP Memory Read 2 mA IDDOTP VDDOTP Current VDDOTP = 2.5 V, TJ = 25°C, OTP Memory Write 2 mA IPPOTP VPPOTP Current VPPOTP = 2.5 V, TJ = 25°C, OTP Memory Read 100 A IPPOTP VPPOTP Current VPPOTP = Table 19 V, TJ = 25°C, OTP Memory Write 3 mA 1 Applies to input balls. Applies to JTAG input balls (TCK, TDI, TMS, TRST). 3 Applies to three-statable balls. 4 Applies to bidirectional balls SCL and SDA. 5 Applies to all signal balls, except SCL and SDA. 6 Guaranteed, but not tested. 7 See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 8 Includes current on VDDEXT, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low. 9 Guaranteed maximum specifications. 10 Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. 11 See Table 12 for the list of IDDINT power vectors covered. 2 The ASF is combined with the CCLK Frequency and VDDINT dependent data in Table 14 to calculate this part. The second part is due to transistor switching in the system clock (SCLK) domain, which is included in the IDDINT specification equation. Total Power Dissipation Total power dissipation has two components: 1. Static, including leakage current 2. Dynamic, due to transistor switching characteristics Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 22 shows the current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and temperature (see Table 13), and IDDINT specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (VDDINT) and frequency (Table 14). There are two parts to the dynamic component. The first part is due to transistor switching in the core clock (CCLK) domain. This part is subject to an Activity Scaling Factor (ASF) which represents application code running on the processor core and L1 memories (Table 12). Rev. B Table 12. Activity Scaling Factors (ASF)1 IDDINT Power Vector IDD-PEAK IDD-HIGH IDD-TYP IDD-APP IDD-NOP IDD-IDLE 1 Activity Scaling Factor (ASF) 1.29 1.25 1.00 0.85 0.70 0.41 See Estimating Power for ASDP-BF534/BF536/BF537 ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297 EE-297). The power vector information also applies to the ADSP-BF51x processors. | Page 23 of 68 | January 2011 ADSP-BF512/BF512F ADSP-BF512/BF512F, BF514/BF514F BF514/BF514F, BF516/BF516F BF516/BF516F, BF518/BF518F BF518/BF518F Table 13. Static Current-IDD-DEEPSLEEP (mA) 1 TJ (°C) ­40 ­20 0 25 40 55 70 85 100 105 1 1.10 V 0.9 1.0 1.2 1.8 2.4 3.3 4.6 6.5 9.2 10.3 1.15 V 1.0 1.1 1.3 1.9 2.6 3.5 5.0 7.1 10.0 11.1 1.20 V 1.0 1.2 1.4 2.1 2.8 3.8 5.4 7.7 10.8 12.1 1.25 V 1.1 1.3 1.6 2.3 3.0 4.3 6.0 8.3 11.7 13.1 Voltage (VDDINT)1 1.30 V 1.35 V 1.1 1.2 1.4 1.6 1.8 2.0 2.5 2.8 3.3 3.7 4.6 5.0 6.4 7.0 9.1 9.9 12.7 13.7 14.2 15.3 1.40 V 1.3 1.7 2.2 3.1 4.0 5.5 7.7 10.8 15.0 16.6 1.45 V 1.7 1.9 2.3 3.3 4.4 6.1 8.4 11.8 16.1 18.0 1.50 V 1.9 2.0 2.5 3.7 4.9 6.7 9.2 12.8 17.5 19.4 1.40 V 102.1 90.1 78.1 66.1 54.1 42.1 30.1 1.45 V 106.5 94.0 81.5 69.0 56.5 44.0 31.5 1.50 V 111.0 98.0 85.0 71.9 58.9 45.9 33.0 Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20. Table 14. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1 fCCLK (MHz)2 400 350 300 250 200 150 100 1 2 1.10 V N/A N/A N/A N/A 40.2 31.1 22.0 1.15 V N/A N/A N/A N/A