BA7230LS 2SC2021 S-0174-0101 RC-875 TZ03R200E SZIP24 - Datasheet Archive

 

NTSC color TV signal encoder BA7230LS The BA7230LS comprises an RGB signal matrix circuit, balanced modulator circuit

 

Multimedia ICs NTSC color TV signal encoder BA7230LS BA7230LS The BA7230LS BA7230LS comprises an RGB signal matrix circuit, balanced modulator circuit (rectangular 2-phase modulation), oscillator circuit (VCXO) for a 3.58MHz subcarrier synchronized with video input burst signals, luminosity and color difference signal mixing circuit, and a high speed switch for selecting composite signals of video input and RGB input. RGB signals, synch signals, BFP (burst flag pulses), PCP (pedestal clamp pulses) are input, and an NTSC composite signal is output. ·Applications Televisions (Teletext-capable), captain systems, video cameras, personal computers ·Featuressuperimposition of video images (VIDEO IN) 1) Allows 4) Using a half down pulse, the video signal can be reduced by 5dB to darken the background and make the superimposed RGB image easier to see. 5) Carrier leak is suppressible to less than 70mVP-P (VOUT = 2VP-P) without adjustment. 6) Can be adapted for analog RGB input. 7) Compact 24-pin SZIP package minimizes external components. and computer images (RGB IN). 2) During superimposition, the subcarrier locked onto the video input burst signal RGB is modulated with the RGB signals by the APC circuit, preventing unnatural color disturbance due to switching. 3) Both the RGB and video input signals are pedestalclamped, maintaining a natural image even during fluctuation in luminosity. ·Block diagram BA7230LS BA7230LS VIDEO OUT 1 Y IN 3 R-Y IN 5 VC 7 VA 9 2 4 B-Y IN 6 BURST LEVEL ADJUSTMENT 8 + SYNC IN VB + MOD MOD VCXO 10 BFP IN APC PHASE 11 ADJUSTMENT PD 12 PD AR 13 14 AG AB 15 16 Y OUT MATRIX B-Y OUT 17 B-Y 18 R-Y OUT R-Y GND 19 20 VIDEO IN HD PCP IN 21 22 HDP IN YSP IN 23 VCC 24 VCC 1 Multimedia ICs BA7230LS BA7230LS 2 1 CLAMP 5 1k 9.1k 500 2V 5.6k VCC 22 10k 15k GND 7 10k 3.4V 11k 10 5.1k 15k 5k 16 1k 10k 6.8k 9 17 1k 1k 5.1k 1.2k 4.3k 18 VCC 6.8k 2.7V 11 12 13 14 15 Fig. 1 ·Absolute maximum ratings (Ta = 25°C) Symbol Limits Unit Power supply voltage VCC 7.0 V Power dissipation Pd 500 mW Operating temperature Topr ­ 20 ~ + 70 °C Storage temperature Tstg ­ 55 ~ + 125 °C Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. ·Recommended operating conditions Parameter Symbol Limits Unit VCC 4.5 ~ 5.5 V R input level VR 0 ~ 0.7 VP-P G input level VG 0 ~ 0.7 VP-P B input level VB 0 ~ 0.7 VP-P Video input level VIN 0 ~ 1.0 VP-P Power supply voltage 2 19 10k BA7230LS BA7230LS 1V Parameter 20 500 6 8 21 10k CLAMP 2V 1k 4 23 2.2V 10k 15k 3.2V 24 15k 3 15k 7.5k ·Input / output circuits Multimedia ICs BA7230LS BA7230LS ·Electrical characteristics (unless otherwise noted, Ta = 25°C, V CC Parameter Quiescent current = 5.0V) Symbol Min. Typ. Max. Unit Conditions IQ - 38 54 mA - 2.6 VP-P Video output level VOV Half down level change GVH ­3 DC offset VOF - 50 160 Crosstalk CT - ­ 46 ­ 40 ER-EY output level VR-Y 0.3 0.42 0.55 VP-P VR = 0.7VP-P EB-EY output level VB-Y 0.2 0.31 0.42 VP-P VB = 0.7VP-P YOUT output level VY 1.0 1.4 1.8 VP-P VR = VG = VB = 0.7VP-P Ys switching delay time TD - 60 - ns SYNC output level VOS 0.4 0.65 0.9 VP-P Burst output level VOB 0.25 0.46 0.8 VP-P RE = 1.8k Composite output level VOY 1.7 2.2 2.6 VP-P YIN = 0.7VP-P 1.7 2.2 ­5 ­7 VIDEO IN = 1VP-P dB - mVP-P VIDEO IN = 1VP-P dB VIDEO IN = 1VP-P - - R-Y modulation gain GR-Y 9 11 13 dB R - YIN = 0.3VP-P B-Y modulation gain GB-Y 9 11 13 dB B - YIN = 0.2VP-P (R-Y) / (B-Y) modulation gain differential GR-B - - 2 dB (R-Y) / (B-Y) orthogonal phase shift R ­6 - 6 deg Difference between above gains - (R - Y) ·Burst orthogonal phase shift B ­6 - 6 deg Carrier leak LSC - 30 70 mVP-P APC capture range fCAP ± 100 - - Hz Burst = 0.1VP-P, 2.8µS Carrier phase range SC ± 30 ± 45 - deg Superimposition ­ 3dB when f = 100kHz Video frequency characteristic - VOUT = 2VP-P fV 4.5 - MHz Video output DG DG - ± 3.5 - % VIDEO IN = 1VP-P Video output DP DP - ± 2.5 - deg VIDEO IN = 1VP-P Input impedance (SY, BF, PC, HD) ZT 8 15 - k - Input impedance (Ys) ZTY 3 7.5 - k - Threshold level (SY, BF, PC, HD) VT 0.9 2.0 2.8 V - Threshold level (Ys) VTY 0.5 1.1 1.8 V - 6 3 Multimedia ICs BA7230LS BA7230LS ·Measurement circuit VCC 0.7VP-P ~ S1 S2 1µF S3 1µF 10µF S4 SYNC + ICC 0.047µF 1µF + + + 13 14 15 24 2 CLAMP 19 6dB MATRIX v 16 v ~ ~ 18 R - Y 1k 1k +4 +5 BA7230LS BA7230LS B-Y R-Y MOD +1µF MOD + + 6 S5 a v ~ EB - E Y ER - EY 17 B - Y 1µF 1µF 75 75 YOUT Y YIN b 3 23 YS 1.8k PCP 21 6dB VIDEO 1µF + 20 S6 12 BG PD BG VCXO 1VP-P 2.7k HDP 68pF TC 7 0.047µF + VCC 1 470 9 8 560 82pF X'TAL 10k 22 BFP 1µF 1.2k 10 Oscilloscope Fig. 2 4 10k 11 ­ 5dB 75 Vector scope 820 75 Multimedia ICs BA7230LS BA7230LS C1 1µF C17 0.047µF B R2 560 C15 G R1 20pF C14 33pF R R17 1k R3 560 LPF 1.2mH L2 560 ·Application example + + 14 SYNC + 13 C16 + 10µF 15 VCC (5V) 24 2 19 GND 20pF C12 33pF C13 1.2 mH L1 R16 1k CLAMP 6dB MATRIX YOUT 16 Y R4 Q1 ER - E Y 2SC2021 2SC2021 EB - E Y 17 VR2 3k 2SC2021 2SC2021 3k +4 +5 1k 1µF C4 1µF MOD MOD R5 Video YS + R6 300 YIN Y 3 R7 1k 5k 23 VR4 VCC 21 6dB 11 VR1 ­ 5dB VIDEO IN 1µF 20 PD R12 2.7k BG 22 9 ­ 5dB 0dB R14 560 68pF C8 DL1 , DL2 : Part No.:YM-3 Plan No.:S-0174-0101 S-0174-0101 (SUMIDA) 8 TC1 R13 X'TAL1 C61µ COMPOSITE 1.2k OUT R6 82pF C7 (2VP-P) C19 10pF 0.047µF C5 + C15 0.047µF 7 470 HDP VCXO R9 R15 10 1k APS PHASE ADJ 12 BG C9 10k BFP + DL 2 B-Y + + 6 PCP 1k DLY R-Y Burst LEVEL ADJ RGB BA7230LS BA7230LS 10k Q2 VR3 TRP (3.58M) 1µF C11 300 C10 VCC DL1 DLY (400ns) 18 VCC 1k R11 75 VCC OUT 820 R10 Q3 2SC2021 2SC2021 L1 , L2 : RC-875 RC-875 1.2mH (SUMIDA) TC1 : TZ03R200E TZ03R200E (MURATA) Q1 , Q2 , Q3 : 2SC2021 2SC2021 (ROHM) XTAL1 : HC ­ 43U 3579.545kHz (NIKKO DENSHI) Fig. 3 5 Multimedia ICs BA7230LS BA7230LS ·Circuit operation (1) Matrix circuit The R, G and B inputs are clamped to 3.2V by the clamp circuit and combined into signals EY, ER-EY and EB-EY by the resistance-adding matrix circuit. EY = 0.30ER + 0.59EG + 0.11EB ER ­ EY = 0.70ER ­ 0.59EG ­ 0.11EB EB ­ EY = ­ 0.30ER ­ 0.59EG + 0.89EB Signal EY is then amplified by the 6dB amplifier (pin 16) to compensate for the signal's 6dB attenuation in the delay line. To prevent overmodulation, signal ER-EY is output at 1 / 1.14 and signal EB-EY at 1 / 2.03 (pins 17 and 18). BA7230LS BA7230LS The carrier color signal is mixed with color burst signals and luminosity signals EY' (to which a horizontal synchronization signal is added) to create the NTSC composite signal (EN). ER ­ EY EN = EY' + cos2fst 1.14 EB ­ EY + sin2fst 2.03 (3) Switch circuit Signal Ys (pin 23) switches between video input and RGB composite signals. Performing this switching at high speeds results in superimposition. 27k RGB COMPOSITE 5.1k Y YS 10k OUT 13 14 R 15 G VIDEO IN B Fig. 4 Fig. 6 (2) Balanced modulator circuit Color difference signals are modulated (rectangular 2phase balanced modulation) with color subcarriers (3.58MHz) having a 90° phase difference. This is called the carrier color signal. (4) Color subcarrier oscillator circuit The subcarrier oscillator circuit for RGB input. This circuit is synchronized with the video input color burst signal extracted by BFP (burst flag pulses) during superimposition, preventing any unnatural color disturbance due to switching between RGB and video input. This oscillator circuit generates the RGB color burst signal. An attached variable resistor can be used to change the amplitude of the color burst signal and to adjust its phase relative to the video color burst signal. This oscillator circuit remains in the free-running state when there is no video input. Amplitude C carrier color signal (combining of R-Y and B-Y) R-Y B-Y Time 90° RGB COMPOSITE VCXO 1 µs 3.58 YS 90° EB - EY ER - EY 3.58MHz (90°) Fig. 5 6 OUT R13 1.2k XT1 3.58MHz Fig. 7 + Balanced modulator 7 ­ 5dB VIDEO IN HDP (Half Down Pulse) B-Y Balanced modulator 3.58MHz (0°) 8 C7 82pF C6 68pF R14 560 R-Y 9 TC1 20pF Carrier color signal Fig. 8 (5) During superimposition, video input can be lowered by about 5dB using an HDP (half-down pulse), darkening the background and making RGB input easier to see. Multimedia ICs BA7230LS BA7230LS ·Input waveform and timing chart VIDEO IN 1VP-P CB SYNC VH TTL LEVEL ( 1) VL PCP VH TTL LEVEL ( 1) VL BFP VH TTL LEVEL ( 1) VL RGB IN 0.7VP-P VH TTL LEVEL ( 1) HDP VL VH YS TTL LEVEL ( 2) VL COMPOSITE OUT from RGB 2VP-P CB SUPER IMPOSE 2VP-P CB CB: COLOR BURST VH: 3.0V ~ VCC VH: 2.0V ~ VCC 1 VL: 0 ~ 0.8V 2 VL: 0 ~ 0.4V Fig. 9 ·Electrical characteristic curves 80 3580.5 f0 = 3579.545kHz VIN = 0.1VP-P 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 POWER SUPPLY VOLTAGE: VCC (V) Fig. 10 Quiescent current vs. power supply voltage 8 FREQUENCY: f (cap. lock) (Hz) 600 FREQUENCY: f (free run) (kHz) QUIESCENT CURRENT: IQ (mA) f0 = 3579.545kHz 70 3580.0 3579.5 3579.0 + lock 400 + cap 200 f0 = 0 ­ cap ­ 200 ­ lock ­ 400 ­ 600 3578.5 3 4 5 6 7 POWER SUPPLY VOLTAGE: VCC (V) Fig. 11 VCXO free-run frequency vs. power supply voltage 3 4 5 7 6 POWER SUPPLY VOLTAGE: VCC (V) Fig. 12 Capture range and lock range (!) vs. power supply voltage 7 Multimedia ICs BA7230LS BA7230LS FREQUENCY: f (cap. lock) (Hz) 600 f0 = 3579.545kHz + lock VCC = 5V 400 + cap 200 f0 = 0 ­ 200 ­ cap ­ 400 ­ lock ­ 600 0 100 200 300 800 400 500 600 700 INPUT VOLTAGE: VIN (mVp-p) Fig. 13 Capture range and lock range (@) vs. input voltage 1µF 1k + + 1µF LPF · VCC 2.8 ± 0.2 0.3 + 0.1 ­ 0.05 2 23 24 SZIP24 SZIP24 +4 +5 1µF (ROHM) Fig. 15 9.9 ± 0.5 2.0Min. 5.8 ± 0.2 1 300 C10 300 Q1, Q2: 2SC2021 2SC2021 2.54 ± 0.25 8 C15 17 Q1 C11 1µF 3k 3k 0.5 ± 0.1 20pF 18 VCC Q2 External dimensions (Units: mm) 0.889 20pF C14 33pF 1.2mH L1 R16 1k Fig. 14 21.8 ± 0.2 0.5MHz 1.2mH L 2 R17 1k 33pF C13 (2) The VCXO remains in a free-running state except during superimposition. (4) Pin 4 (B-YIN) and pin 5 (R-Y IN) have high impedance and are susceptible to the effects of noise and other external factors during pattern generation. For this reason, we recommend adding the circuit in Fig. 15 to lower the input impedance. Adding this circuit can also reduce carrier leakage. C12 When only RGB is input, connect VIDEO IN (pin 20) to GND with a 1µF capacitor, and synchronize PCP and BFP to RGB. (3) Input pins with pedestal clamps cannot be left open and must be grounded with a low impedance. When not used, ground with a 1µF capacitor. Input pins with pedestal clamps: YIN (pin 3), B-YIN (pin 4), R-YIN (pin 5), VIDEO IN (pin 20) Additional circuit ·Operation notes inputs should be synchronized. (1) RGB and video