BA000109BB 10LAN 11USB 12BIOS 13POST 10ATX 11JTAG 12GPIO 13I2C PB3301 P4205 - Datasheet Archive

 

STPC Vega PC Evaluation Kit User Manual For use with BA000109BB Board uc d te le (s) ct du o Pr e s) t( ro P so Ob - Rev. 1 May

 

VEGABD STPC Vega PC Evaluation Kit User Manual For use with BA000109BB BA000109BB Board uc d te le (s) ct du o Pr e s) t( ro P so Ob - Rev. 1 May 2004 let o bs O 1 Table of Contents 1 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 ASSOCIATED DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 ELECTROSTATIC DISCHARGE (ESD) PRECAUTIONS . . . . . . . . . . . . . . . . . . 4 1.4 MOUNTING CASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5.1 PSU Form Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5.2 Heatsink/Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5.3 Power Signal Control Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 CABLEFORMS AND CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.7 SUPER I/O DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 s) t( 1.8 HARD DISK AND CD ROM DRIVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 uc d 1.9 DISK-ON-CHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ro P 1.10LAN 10LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.11USB 11USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 te le 1.12BIOS 12BIOS DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 so Ob - 1.13POST 13POST DISPLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 MOTHERBOARD FUNCTIONAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 VEGABD AT A GLANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 STPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.3 Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.6 Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 (s) ct du o Pr e let o 3 HARDWARE INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 JUMPERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 Setting Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.2 Jumper Setting Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bs O 3.2 DEFAULT JUMPER SETTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 Step 1: Installing DIMM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 Step 2: Clearing CMOS memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36. . 16 . 3.3.3 Step 3: Using default jumper setting to run BIOS setup . . . . . . . . . . . . . . 17 2/36 1 Table of Contents 3.3.4 Step 4: Setting HCLK and PCI_CLK Speed . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.5 Step5: Setting MCLK and HCLK Synchronisation (S501 - SW6) . . . . . . . 18 3.3.6 Step6: Setting the CPU Core Clock / HCLK Ratio . . . . . . . . . . . . . . . . . . . 18 3.3.7 Step 7: Setting the UIDE Clock Speed (S501 - SW9 and SW10) . . . . . . . 18 3.3.8 Step 8: Enabling Local or ISA Bus (S501 - SW11) . . . . . . . . . . . . . . . . . . 19 3.3.9 Step 9: Local Bus Boot Flash Width (S501, SW12) . . . . . . . . . . . . . . . . . . 19 3.3.10Jumper Setting Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 MOTHERBOARD RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 MOTHERBOARD HARDWARE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 CONNECTOR DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 ISA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.2 Local Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.3 Mouse Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.4 Keyboard Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.5 Parallel Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.6 PCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.7 COM (Serial Port) Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.8 IDE Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.9 Floppy Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.10ATX 10ATX Power Supply Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.11JTAG 11JTAG Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.12GPIO 12GPIO Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.13I2C 13I2C Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.14Ethernet/Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.15Dual USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.16Reset Button Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.17On/Off Button Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 uc d te le (s) ct s) t( ro P so Ob - du o Pr e let o 5.3 GROUND TEST POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 bs O 6 TROUBLESHOOTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 BOOT FAILS WITH SOME ISA CARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.2 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.3 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 TECHNICAL SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3/36 GENERAL INFORMATION 1 GENERAL INFORMATION 1.1 INTRODUCTION The purpose of the Vega Evaluation board is to provide the customer with the opportunity to evaluate the STPC Vega device and to enable the prototyping of a final system to the required design with the minimum of delay. This chapter provides general information and covers topics including electrostatic discharge (ESD) precautions, power supply requirements and general details of additional external equipment requirements. Refer to: ­ Section 2 , Motherboard Functional Specifications, for a description of the Vega Evaluation Board, ­ Section 3 , Hardware Installation, for board switch and jumper settings, ­ Section 5 , Motherboard Hardware Specifications, for board external connection details. uc d 1.2 ASSOCIATED DOCUMENTS s) t( ro P The following associated documents are available from the STPC website. They are provided in Adobe Acrobat PDF format (for which a free viewer is available) for display purposes (the Schematic Diagrams are also provided in Orcad9 format). The documents can also be printed using a suitable printer. For the Schematic Diagrams, an A3 or larger size high-definition colour printer is recommended. te le so Ob - ­ STPC Vega Datasheet Manual ­ STPC Vega Programming Manual ­ STPC Vega Evaluation Board, ISA/LB version, Schematic Diagram (32 sheets) (s) ct du o 1.3 ELECTROSTATIC DISCHARGE (ESD) PRECAUTIONS Pr e Many components on the STPC Vega Evaluation Board, as well as components contained in disk drives and on adaptor cards, especially processor and memory devices, can be damaged by ESD when handled by the operator. It is important therefore to observe the standard sensitive device handling procedures, such as the use of anti-static mats and the wearing of a wrist strap connected to earth or to a non-painted part of the case or chassis assembly. let o bs O If a wrist strap is not available, it is good practice to touch an earth connection or the case or chassis assembly from time to time while handling the board to equalise any charge that might have built up. Handle adaptor cards by grasping the metal bracket first. If no bracket is attached to the card, handle the card by the outer edges only and try not to touch any of the components or connections. 4/36 1 GENERAL INFORMATION 1.4 MOUNTING CASE Some sort of mounting case for the Evaluation Board should be considered. This could also include the ATX Power Supply Unit (see section Section 1.5) and could include bays for a Floppy Disk Drive, Hard Drive, CD ROM Drive, etc., depending on the system requirements. At the very least, the Evaluation Board should be mounted on insulating pillars, one at each corner of the board using the holes provided. 1.5 POWER SUPPLY A Power Supply Unit (PSU) conforming to the ATX standard will be required. This must be suitable to be run from the local source of AC power and will provide the necessary DC voltages required by the system. If a case is obtained to house the Evaluation Board, it may already include a suitable ATX PSU. If not, then check that the form factor (see below) of the PSU obtained conforms to the ATX standard. The standard 90 Watt ATX PSU is suitable. uc d 1.5.1 PSU Form Factor s) t( The physical shape and layout of a PSU is known as the form factor. Although several form factors have emerged over the years, the ATX has become the industry standard. This design is fitted with a unique 20-pin keyed connector to prevent users connecting to an unsuitable PSU. Unlike earlier designs, the ATX PSU does not include an input power switch but relies on remote power switching. For the Vega Evaluation Board, this is via the board-mounted POWER push button PB3301 PB3301. te le 1.5.2 Heatsink/Cooling Fan (s) ct ro P so Ob - The STPC Vega device mounted on the Evaluation Board does not normally require a heatsink and the fan in the power supply unit may provide sufficient forced air cooling within the case, assuming it is mounted in the same case as the Evaluation Board. If high internal temperatures are expected however, an additional fan should be provided, typically mounted at the front of the chassis, taking air in at the front and directing it over the Evaluation Board. du o Pr e 1.5.3 Power Signal Control Definitions let o (1) PS-ON: PS-ON is an active low signal that is used to turn on the main power rails including 3.3 V, 5 V, -5 V, 12 V, and -12 V power rails. When this signal is held high by the Evaluation Board, the power rail outputs should not deliver current and should be held at a zero potential with respect to ground. Power should be delivered to the rails only if the PS-ON signal is held at ground potential. This signal is held at +5 VDC by a pull-up resistor within the PSU. bs O Note: The 1.8 V STPC Core supply voltage is derived on the Evaluation Board from the 3.3 V supply. 5/36 1 GENERAL INFORMATION (2) 5 VSB: The 5 VSB supply is a standby voltage that may be used to power circuits that require power input during the powered-down state of the power rails. The 5 VSB pin should deliver 5 V plus or minus 5% at a minimum of 10 mA for external board circuits to operate. Conversely, no more than 10mA maximum should be drawn from this pin unless a power supply with higher current capabilities is clearly specified. The 5 VSB supply is not used on the Vega Evaluation Board. (3) PW-OK: PW-OK is a power good signal, asserted high by the power supply to indicate that the +5 VDC and +3.3 VDC outputs are above the undervoltage thresholds of the power supply. When this signal is asserted high, there should be sufficient mains energy stored by the converter to guarantee continuous power operation within specification. Conversely, when either the +5 VDC or the +3.3 VDC output voltage falls below the undervoltage threshold, or when mains power has been removed for a time sufficiently long so that power supply operation is no longer guaranteed, PW-OK is deasserted to a low state. s) t( On the Vega Evaluation Board the PW_OK signal is applied as a sense signal to the STPC Reset signal generation circuit. uc d 1.6 CABLEFORMS AND CONNECTORS te le ro P Before starting the installation procedure, ensure that all of the required interconnecting cableforms and connectors are available. These are usually provided with the respective items of equipment. 1.7 SUPER I/O DEVICE (s) ct so Ob - The Super I/O (SIO) device mounted on the Evaluation Board provides for the Keyboard and Mouse, the Floppy Disk Drive connected via a 34-way ribbon cable assembly to P4205 P4205 (see Section 5 ) and a flying-lead power supply connection from the ATX Power Supply Unit, a standard PC/AT Keyboard (required together with a mouse) and are connected to the Evaluation Board using 6-pin Mini DIN connectors and one full RS-232 RS-232 and Serial Port and parallel port (26 pin connector). The device, type FDC37B782 FDC37B782, is manufactured by Standard Microsystems Corporation (SMSC) and full details are available on the Internet at: du o Pr e let o bs O http://www.smsc.com/main/catalog/fdc37b78x.html Note however that the Floppy Disk Drive and the Keyboard/Mouse Controller are not available in the Local Bus mode (no DMA in LB mode and the "Gate A20" signal is not accessible). 6/36 GENERAL INFORMATION 1.8 HARD DISK AND CD ROM DRIVES Provision is included for the fitting of up to two hard drives, known as Master and Slave. However, if a CD ROM Drive is also required, then the Hard Drive will be the Master and the CD ROM Drive will be the Slave. Set the select jumper on the hard drive to Master before installing the drive. Always install the ribbon cables before fitting the drive and cage into the case. Common mistakes made by beginner and experienced PC assemblers alike include the misalignment of the floppy drive ribbon connector, the failure to make the connection with the red key wire adjacent to the pin 1 or 2 side of the connector, the accidental forcing of the connector between a vertical line of pins, or even missing an entire row of pins. These mistakes are due in general to poor visibility once the drive is in the case. The connections from a CD ROM drive usually include a patch cable for sound. This can only be fitted if a suitable Sound Card is also installed. The CD ROM drive selection jumper must be set to "Slave", assuming a hard drive is also being installed. uc d s) t( The ribbon cables are connected to the Evaluation Board with the red key wire in the ribbon towards pin one on the connector. The hard drive cable is fitted to the connector marked "Primary" (P2100 P2100). The CD ROM drive cable is connected to the identical connector marked "Secondary" (P2101 P2101). te le 1.9 DISK-ON-CHIP ro P so Ob - A 32-pin DIP socket is provided on the Vega Evaluation Board (U1510 U1510) to accommodate a Disk-On-Chip (DOC) device, such as the 16 MB MD2211-D16-V3 MD2211-D16-V3, based on the M-System patented Disk-On-Chip technology. (s) ct Disk-On-Chip is a flash disk that provides full hard disk emulation using solid-state flash memory technology. It combines a disk controller with flash memory in a single chip providing a complete, easily integrated, flash disk solution. du o Pr e By placing the Disk-On-Chip 2000 in a standard socket, physical space requirements are reduced. Unlike standard IDE drives, no cables or extra space are required. The Disk-On-Chip 2000 has no moving parts, resulting in significantly decreased power consumption and increased reliability. It is easy to use and reduces integration overhead. The Disk-On-Chip 2000 is therefore a very attractive alternative to conventional hard and floppy disk drives. let o bs O For full information on the DOC, refer to the M-System website at: 7/36 GENERAL INFORMATION 1.10 LAN The STPC contains an internal LAN MAC layer. The evaluation also includes an external Physical layer that is able to work up to 100Mbit/sec. 1.11 USB The Evaluation board has two standard USB connectors which can be used to connect USB devices or hubs. 1.12 BIOS DETAILS There is a pre-loaded BIOS on board that is customised for the Evaluation platform. The BIOS is supplied by General Software. http://www.gensw.com/pages/partners/stjmp.htm s) t( The nature of the development platform suggests that it goes into the field for evaluation and may move around from customer to customer. It may contain a BIOS image that was created several months ago or contain code that has been altered or corrupted by previous users. uc d ro P To encourage you to register your use of the platform and ensure that you have the latest BIOS binary image available, we have purposely implemented a 15-second, BIOS boot-time delay. When you register, you will receive a Registration Key that will disable the delay. In addition, registration gives you important benefits, such as access to technical support and updates to your evaluation BIOS, if available. te le so Ob - To receive your Registration Key, fill out the form that is located on the General Software web site (Address is given on the BIOS setup screen). Enter the System ID displayed in Setup, your email address, and your company name. Complete the additional optional information, and Submit. Your Registration Key will be sent immediately to the email address you supply. When you receive it, go to the Setup screen, enter the Registration Key and the email address exactly as it was submitted here. Your registration will be complete and the boot delay will be disabled. (s) ct du o Pr e let o 1.13 POST DISPLAY bs O The POST Code display is a numerical display on the board which indicates the progress of the BIOS. If there is any problems at the Boot, make a note of the Post Code value at which the system stops and communicate it to your local support engineer. 8/36 MOTHERBOARD FUNCTIONAL SPECIFICATIONS 2 MOTHERBOARD FUNCTIONAL SPECIFICATIONS The VEGABD evaluation board is a high-performance personal computer system board based on the STPC Vega microprocessor running with an external 14.31818 MHz crystal oscillator. The VEGABD system board supports either the ISA or the Local Bus Mode, selection being achieved by the setting of a single jumper. Other jumpers are provided for the selection of various parameters and functions. 2.1 VEGABD AT A GLANCE 2.1.1 STPC I Pentium® II Class Processor Core running at up to 200 MHz. I 64-Bit SDRAM Controller running at up to 100 MHz. I PCI 2.2 Compliant Master/Slave Controller. I ISA Master/Slave. I Dual Port USB Host Controller (OHCI). I 10/100 Ethernet MAC. I Integrated Peripheral Controller with support for external RTC. I Ultra DMA-66 DMA-66 IDE Controller. I Power Management Unit. I 16-bit Local Bus Interface. I I2C Bus Controller. I UART (1 RxTx). I IEEE 1149.1 JTAG Interface. I Eight General Purpose IO lines. I Programmable Clocks. I 0.18 MICRON Technology. uc d te le (s) ct s) t( ro P so Ob - du o Pr e let o bs O I 1.8 V Core & 3.3 V I/O. 2.1.2 Cache Memory I Integrated L1 write back cache. I No L2 cache subsystem can be installed. 2.1.3 Main Memory I One SDRAM 168-pin DIMM socket is provided, together with four 54-pin sockets for soldered RAM devices. Two configurations are available: (1) Soldered memory plus one 9/36 MOTHERBOARD FUNCTIONAL SPECIFICATIONS single-sided DIMM or (2) One single-sided or double-sided DIMM with soldered RAM disabled. For configuration (1), soldered RAM devices can be 64 Mbit (4 M x 16-bit), 128 Mbit (8 M x16-bit) or 256 Mbit (16 M x 16-bit). A standard board is fitted with active soldered 64 Mbit memory chips and with single-sided DIMM activated by fitting jumpers P710 and P712, and by not fitting jumpers P711 and P713. To disable the soldered RAM devices and make use of single-sided or double-sided DIMM, jumpers P711 and P713 are fitted, and jumpers P710 and P712 are removed. 2.1.4 Slots I Three 32-bit PCI Bus slots. I One 16-bit ISA Bus slot (not usable in Local Bus mode). I One Local Bus slot (not usable in ISA mode). 2.1.5 Interfaces s) t( I Power supply with standard ATX connector and linear regulator for the 1.8 V supply. I Super I/O chip providing: Keyboard and Mouse (not available in Local Bus mode) One Serial Port Real Time Clock (RTC) Floppy Drive (not available in Local Bus mode). te le uc d ro P so Ob - I Two off UIDE 66 connectors (Primary and Secondary). I IEEE1149 IEEE1149.1 JTAG interface. I Eight General Purpose Inputs/Outputs on a 16-pin header. I I2C Bus 3-pin connector (SDA, SCL and Gnd). I Dual USB Port with automatic USB power switch. I LAN RJ-45 RJ-45 Physical Layer. I One UART Serial Port. I Disk-on-Chip: common for ISA and Local Bus modes. I One common 8-bit flash ROM (DIP or PLCC socket) for ISA and Local Bus modes. (s) ct du o Pr e let o bs O I Loudspeaker, Reset button, ATX Power On/Off button. I Port 80h display for BIOS POST code (useful for software debug purposes). Dimensions: 20.0 cm x 28.0 cm x four layer PCB. Mounting: Four 4 mm mounting holes, connected to board Gnd, one in each corner of board. 10/36 MOTHERBOARD FUNCTIONAL SPECIFICATIONS Figure 1. Block Diagram: Vega Evaluation Board 1 SDRAM DIMM 1.8 V Linear Regulator 32 Mbyte Soldered SDRAM 3.3 V Dual USB On/Off & Reset 8 GPIO UART RxTx only RS-232 RS-232 STPC VEGA 3 PCI Slots I2C ATX Connector LAN Physical Layer Port 2 UIDE Headers Dynamic MUX du o Pr e uc d ro P so Ob - s) (Static MUX ct 1 ISA Slot POST Code 80h te le s) t( 10-pin header RJ-45 RJ-45 Local Bus Connector Static MUX ISA/LB Bus Exchange ISA/LB/POST Decoder Keyboard & Mouse let Floppy o O bs Header Serial Port Parallel Port RTC Disk-on-Chip RS-232 RS-232 Buffers Super I/O 256 Kbyte 8-bit Flash 11/36 MOTHERBOARD FUNCTIONAL SPECIFICATIONS Figure 2. Layout Diagram: Vega Evaluation Board GPIO Power Connector LAN SPKr I2C STPC Serial COM1 so (s) ct Ob - Floppy Connector IDE Connectors te le uc d ro P JTAG Parallel Port Mem Configuration STPC VEGA Poste Code BIOS Reset S500 Super IO Serial 1 COM2 S501 Memory DIMM Module Soldered Memory PWR ATX CTRL USB On/Off Pr e du o PCI Connectors let o bs O Disk On Chip Connector ISA Connector Local Bus Connector 12/36 CMOS Battery s) t( MOTHERBOARD FUNCTIONAL SPECIFICATIONS 2.1.6 Controls and Indicators The board is fitted with two pushbutton switches, one for Power ON/OFF, the other for Reset, and a number of LED indicators, as listed below. It is also fitted with a two-digit hexadecimal seven-segment Power On Self Test (POST) display for use with the debug facility. Power Supply: D3300 D3300 Red LED: 3.3 V supply indicator D3301 D3301 Red LED: 5 V supply indicator D3302 D3302 Green LED: 5 V SB supply indicator IDE/UMDA Indicators: D2100 D2100 Green LED: Primary Hard Disk uc d D2101 D2101 Green LED: Secondary Hard Disk LAN (MAC) Indicators: te le D4501 D4501 Green LED: Data Transmitted D4503 D4503 Green LED: Collision Detected s) t( ro P so Ob - D4504 D4504 Green LED: 100 Mbi/s Detected (s) ct du o Pr e let o bs O 13/36 HARDWARE INSTALLATION 3 HARDWARE INSTALLATION The installation of the system board includes the configuration of switches, the setting of jumpers and the attachment of connectors. 3.1 JUMPERS Jumpers on the system board provide information to the system about installed options and system settings. 3.1.1 Setting Jumpers Configure the system board options by setting jumpers and switches. Note: When a jumper is left open, leave the plastic jumper cap attached to one of the pins to save losing it. 3.1.2 Jumper Setting Symbols uc d For 2-pin jumpers, the following symbols are used: - Close pins 1 and 2 with a jumper cap. te le 1 2 ro P so Ob - - Open pins 1 and 2 without a jumper cap. 1 2 (s) ct For 3-pin jumpers, the following symbols are used: du o Pr 1 2 3 ete ol bs O 1 2 - Close pins 1 and 2 with a jumper cap. - Close pins 2 and 3 with a jumper cap. 3 For the S2, S500 and S501 DIP switches, the following symbols are used: 14/36 s) t( HARDWARE INSTALLATION ON - Push the button to the top side of the switch (ON) to set to logical "0". - Pull the button to the bottom (OFF) side of the switch to set to logical "1". 3.2 DEFAULT JUMPER SETTING Table 1. Default Jumper Settings Jumper Purpose Setting J518 1 J3300 J3300 CMOS RAM - Clear: 2 - 3 (s) ct J4200 J4200 - Default: 1 - 2 du o Pr e J3301 J3301 let o bs O J3302 J3302 ro P te le Reset so uc d 2 s) t( 1 2 Ob - 1 2 3 Power 1 2 ATX Power Supply Control - default: 1 - 2: Soft and Button control 1 2 3 15/36 HARDWARE INSTALLATION Jumper Purpose Setting Flash EPROM VPP J1501 J1501 - default: 2 - 3: 12 V 2 - 1: 5 V 1 2 3 - default: HCLK (CPU) = 100 MHz S500 ON PCI Clock = 30 MHz SW1-6 CPU Clk/HCLK Ratio = 2 1 2 Note: These settings override Strap Options set by the BIOS. 3 4 5 6 - default: ON uc d S501 SW7-12 SW7-12 Note: These settings override Strap Options set by the BIOS. 3.3 INSTALLATION e2 let 1 ro P 3 4 5 s) t( 6 so Ob - For the mainboard installation, it is important that the jumper settings are set correctly. Improper jumper settings can cause system instability or system hang-ups. Please refer to the installation procedures below. (s) ct 3.3.1 Step 1: Installing DIMM Module du o The main board supports one DIMM module and has four 54-pin sockets for the fitting of 16 Mbit, 128 Mbit or 256 Mbit soldered SDRAM devices. There are two memory configurations available: I Pr e let o Soldered DRAM active (resistors R710 and R712 fitted, R711, R713, R714 and R715 not fitted) and a single-sided DIMM fitted. bs O I Soldered DRAM not active (resistors R711, R713, R714 and R715 fitted, R710 and R712 not fitted) and a single or double-sided DIMM fitted. If using Registered DIMMs, SDRAM Register 1 bit 27 must be set to `1' (see the Vega Programming Manual). 3.3.2 Step 2: Clearing CMOS memory 1) IF THE BOARD IS OPERATING, switch off the board using PB3301 PB3301 button and remove the ATX connector. 16/36 HARDWARE INSTALLATION 2) Place J4200 J4200 in 1-2 position for two seconds and then reposition it to the default 2-3 position. 3) Verify that S2 and S500 DIP switches are configured with the default settings given in Table 1 Default Jumper Settings 4) Select the 66 MHz CPU speed using SW500 SW500 DIP switch (SW1: ON, SW2: OFF, SW3 -5: ON), then switch on the board. This will allow the board to boot safely and enter the BIOS setup menu. 3.3.3 Step 3: Using default jumper setting to run BIOS setup Power, keyboard, mouse and screen must be correctly connected. 1) Switch on the board by pressing the Power button, PB3301 PB3301. 2) During the memory test sequence, press `DEL' to enter the BIOS setup. This corresponds to post code 2Ch. - Menu options available: - Basic CMOS configuration: configure hardware, as required, e.g. Boot sequence - Customer Configuration: used to set memory cache, UIDE, ISA Clock parameters, etc. uc d 3) Press Esc to return to the main menu. s) t( ro P 4) Reset by switching the board OFF and then back to ON using the Power button, PB3301 PB3301. te le 5) During the memory test sequence, press `DEL' to launch BIOS SETUP again. so Ob - 6) Go to the Setup menu `Chipset Setup/SDRAM Banks'. 7) Configure the SDRAM Type and Speed according to the plugged-in memory modules. 8) Select `User Setup' then quit and save configuration by selecting `Write to CMOS and exit'. (s) ct 9) Configure the final settings using DIP switches S2 and S500. 10) Reset the board by pressing the PB3300 PB3300 Reset button. du o 3.3.4 Step 4: Setting HCLK and PCI_CLK Speed Pr e Using the S500 DIP switch, set the SW1TO SW5 keys for the required speeds, as follows: !Warning: Improper speed setting might cause serious damage to the STPC. Table 2. S500, SW1 - SW5 Settings let o O bs Settings HCLK PCI_CLK 100 MHz 33.3MHz S500, SW1 S500, SW2 S500,SW3 S500, SW4 S500, SW5 OFF ON ON OFF OFF 17/36 HARDWARE INSTALLATION 90MHz 30MHz 75 MHz 25 MHz OFF ON OFF OFF OFF OFF OFF ON ON OFF 3.3.5 Step5: Setting MCLK and HCLK Synchronisation (S501 - SW6) The setting of S501 - SW6 specifies whether or not the Memory clock (MCLK) is synchronized with the internal Host clock (HCLK). Table 3. S501 - SW6 Settings Setting S501 - SW6 MCLK and HCLK have the same frequency s) t( OFF uc d MCLK and HCLK have different frequencies te le 3.3.6 Step6: Setting the CPU Core Clock / HCLK Ratio ro P so Ob - ON Using the S500 DIP switch, set the SW7 and SW8 keys for the required ratio, as follows. Table 4. S500 - SW7 and SW8 Settings Setting S500 - SW7 Ratio of 2.5 x Ratio of 2 x ro P e uc d (s) t S500 - SW8 ON ON ON OFF 3.3.7 Step 7: Setting the UIDE Clock Speed (S501 - SW9 and SW10) Table 5. S501 - SW9 and SW10 Settings let o 18/36 S501 - SW9 S501 - SW10 UIDECLK33 UIDECLK33 MHz ON OFF UIDECLK66 UIDECLK66 MHz bs O Setting ON ON HARDWARE INSTALLATION 3.3.8 Step 8: Enabling Local or ISA Bus (S501 - SW11) Table 6. S501 - SW11 Setting Setting S501 - SW11 ISA Bus Enabled OFF Local Bus Enabled ON In order to operate in Local Bus mode, some hardware modifications are necessary and are described below; To set the VEGABD into LOCAL BUS mode, the signal ISA_MCS16 MCS16# has to be disconnected. On the board, the pin 3 of U1300 U1300 has to be lifted up (schematics page 19/32). To reset the board into ISA mode, ISA_MCS16 MCS16# has to be put back in place. uc d 3.3.9 Step 9: Local Bus Boot Flash Width (S501, SW12) s) t( ro P The setting of S501 - SW12 specifies whether the Local Bus boot flash width is 8-bit or 16-bit, as below: Table 7. S501 - SW12 Setting te le Setting so 16-bit (s) ct 8-bit S501 - SW12 Ob - OFF ON du o 3.3.10 Jumper Setting Summary Table 8. Jumper Setting Summary Jumper let o Pr e bs O J518 Title Setting OFF 1 - 2: 5 V J1501 J1501 Flash EPROM VPP J3300 J3300 Reset OFF J3301 J3301 Power OFF 2 - 3: 12 V (default) 19/36 HARDWARE INSTALLATION Jumper Title Setting J3302 J3302 ATX Power Supply Control J4200 J4200 CMOS RAM S500 - SW1, SW2, SW3, SW4 and SW5 HCLK & PCI_CLK Speed S500 - SW6 HCLK/MCLK Synchronization S501 - SW7 and SW8 CPU Core Clock / HCLK Ratio See Table 4 S501 SW9 and SW10 UIDE Speed See Table 5 S501 - SW11 Local Bus / ISA Bus select S501 - SW12 Boot Flash Width Select DIMM+SOLDRED RAM Activated (s) ct u od Pr e let o bs O 20/36 See Table 2 See Table 4 uc d See Table 6 See Table 7 te le ro P P710- P710- P712: OFF P711- P711- P713: ON so Ob - Only SOLDRED RAM Activated P712-P713 P712-P713 2 - 3: Soft control & switch (default) 1 - 2: Normal mode (default) 2 - 3: Clear CMOS Only DIMM Activated P710-P711 P710-P711 1 - 2: Force ATX always ON P710: ON P711- P711- P712- P712- P713: OFF P710- P710- P712: ON P711- P711- P713: OFF s) t( MOTHERBOARD RESOURCES 4 MOTHERBOARD RESOURCES The Vega Evaluation Board is implemented at a specific I/O address range: 0072h - 0073h: Reserved for board information 0080h:Post code 0370h - 0371h: Super I/O uc d te le (s) ct s) t( ro P so Ob - du o Pr e let o bs O 21/36 MOTHERBOARD HARDWARE SPECIFICATION 5 MOTHERBOARD HARDWARE SPECIFICATION 5.1 CONNECTORS The following table lists the connectors implemented on the Vega Evaluation Board. Table 9. List of Connectors Identification Name Type No. of Pins Ref. Table P1300 P1300 ISA (16-bit) ISA 98 Table 10 P1700A/B/C P1700A/B/C Local Bus DIN41612 DIN41612 3 X 32 Table 11 P4206 P4206 Mouse (up), Keyboard (down) Dual Mini DIN 2x6 Table 12 and Table 13 P4207 P4207 Parallel Straight Pin header 26 Table 14 P900, P901, P902 PCI Slots A, B & C PCI 124 Table 15, Table 16, Table 17 & Table 18 P4208 P4208 COM 1 DB9 9 P4209 P4209 COM 2 Straight Pin Header 5x2 P2100 P2100 UIDE - Primary Straight Pin header 40 P2101 P2101 UIDE - Secondary Straight Pin header P4205 P4205 Floppy Straight Pin header P3300 P3300 ATX Power Supply ATX P4000 P4000 JTAG P3700 P3700 te le uc d s) t( Table 19 ro P Table 20 34 Table 21 20 Table 22 40 Straight Pin header 10 Table 23 General Purpose I/O so Straight Pin header 16 Table 24 P4400 P4400 I2C Bus Header Straight Pin header 3 Table 25 U4502 U4502 Ethernet/Filter RJ-45 RJ-45 8 Table 26 P2301 P2301 Dual USB USB RA_F 12 Table 27 J3300 J3300 Reset Button Straight Pin header 2 Table 28 Straight Pin header 2 ro P e J3301 J3301 let o bs O 22/36 uc d On/Off Button (s) t Ob - MOTHERBOARD HARDWARE SPECIFICATION 5.2 CONNECTOR DEFINITIONS 5.2.1 ISA Connector Table 10. ISA Connector Pin Definitions (P1300 P1300) Signal Name Pin Pin Signal Name GND B1 A1 PA10_IOCHCK# ISA_RESET B2 A2 PD7_SD7 5 V (Vcc) B3 A3 PD6_SD6 IRQ9 B4 A4 PD5_SD5 -5V B5 A5 PD4_SD4 ISA_DRQ2 B6 A6 PD3_SD3 -12V B7 A7 PD1_SD2 PA8_ZWS B8 A8 PD1_SD1 +12V B9 A9 PD0_SD0 GND B10 A10 ISA_IOCHRDY PBE1#_SMEMW# B11 A11 PA16_AEN PA19_SMEMR# B12 A12 PA12_IOW# B13 A13 PA13_IOR# B14 A14 ISA_DACK3# B15 A15 ISA_DREQ3 B16 ISA_DACK1# B17 ISA_DRQ1 B18 uc d ro P ISA_SA19 te le so Ob A16 ISA_SA18 ISA_SA17 ISA_SA16 ISA_SA15 A17 ISA_SA14 A18 ISA_SA13 A19 ISA_SA12 B20 A20 ISA_SA11 B21 A21 ISA_SA10 B22 A22 ISA_SA9 B23 A23 ISA_SA8 IRQ4 B24 A24 PA7_SA7 IRQ3 B25 A25 PA6_SA6 ISA_DACK2# B26 A26 PA5_SA5 PA0_TC B27 A27 PA4_SA4 PA15_ALE B28 A28 PA3_SA3 5V (Vcc) B29 A29 PA2_SA2 BCLK2X B30 A30 PA1_SA1 GND B31 A31 PRDY_SA0 KEY KEY D1 C1 (s) PA11_REF# B19 ct BCLK IRQ7 ro P e IRQ6 IRQ5 let o bs O s) t( PWR#_MEMCS16 MEMCS16# du PA17_BHE# 23/36 MOTHERBOARD HARDWARE SPECIFICATION Signal Name Pin Pin Signal Name PBE0_IOCS16 IOCS16# D2 C2 ISA_LA23 IRQ10 IRQ10 D3 C3 LA22 IRQ11 IRQ11 D4 C4 ISA_LA21 IRQ12 IRQ12 D5 C5 ISA_LA20 IRQ15 IRQ15 D6 C6 ISA_LA19 IRQ14 IRQ14 D7 C7 ISA_LA18 ISA_DACK0# D8 C8 ISA_LA17 ISA_DRQ0 D9 C9 PA14_MEMR# ISA_DACK5# D10 C10 PA18_MEMW# ISA_DRQ5 D11 C11 PD8_SD8 ISA_DACK6# D12 C12 PD9_SD9 ISA_DRQ6 D13 C13 PD10_SD10 ISA_DACK7# D14 C14 PD11_SD11 ISA_DRQ7 D15 C15 PD12_SD12 5 V (Vcc) D16 C16 PRD#_MASTER# D17 C17 GND D18 C18 uc d Signal Name Pin Signal Name PD0_SD0 A1 SYSRESET0# PD1_SD1 A2 ro P PD13_SD13 PD14_SD14 te le so Ob - 5.2.2 Local Bus Connector Table 11. Local Bus Connector Pin Definitions s) t( PD15_SD15 Pin Signal Name Pin B1 PA0_TC C1 GND B2 PA1_SA1 C2 NC B3 PA2_SA2 C3 GND B4 PA3_SA3 C4 A5 NC B5 PA4_SA4 C5 PD5_SD5 A6 GND B6 PA5_SA5 C6 PD6_SD6 A7 NC B7 PA6_SA6 C7 PD7_SD7 A8 GND B8 PA7_SA7 C8 PD8_SD8 A9 P1702 P1702 B9 PA8_ZWS# C9 PD9_SD9 A10 GND B10 PA9_GPIOR# C10 PD10_SD10 A11 P1703 P1703 B11 PA10_IOCHCK# C11 PD11_SD11 A12 GND B12 PA11_REF# C12 PD12_SD12 A13 P1704 P1704 B13 PA12_IOW# C13 PD13_SD13 A14 GND B14 PA13_IOR# C14 PD14_SD14 A15 P1705 P1705 B15 PA14_MEMR# C15 du o PD2_SD2 PD3_SD3 Pr e PD4_SD4 let o bs O 24/36 ct A3 A4 (s) MOTHERBOARD HARDWARE SPECIFICATION Signal Name Pin Signal Name Pin Signal Name Pin PD15_SD15 A16 GND B16 PA15_ALE C16 IOSC0#_DACKENC0 A17 P1706 P1706 B17 PA16_AEN C17 IOCS1#_DACKENC1 A18 GND B18 PA17_BHE# C18 IOCS2#_DACKENC2 A19 P1707 P1707 B19 PA18_MEMW# C19 IOCS3#_ISAOE# A20 GND B20 PA19_SMEMR# C20 P1711 P1711 A21 P1708 P1708 B21 PA20_DREQMUX0 C21 P1701 P1701 A22 GND B22 PA21_DREQMUX1 C22 P1710 P1710 A23 P1709 P1709 B23 LB_PA22 C23 PRD#_MASTER A24 GND B24 LB_PA23 C24 PWR#_MCS16 MCS16# A25 IRQ11 IRQ11 B25 LB_PA24 C25 PBE0#_IOCS16 IOCS16# A26 5V B26 NC C26 PBE1#_SMEMW# A27 IRQ10 IRQ10 B27 GND PRDY_SA0 A28 5V B28 NC FCS0#_RTCAS A29 IRQ5 B29 3.3 V NC A30 GND B30 FCS1#_PERICLK A31 IRQ6 NC A32 GND s) t( C27 uc C28 B31 od r C29 3.3 V C31 B32 ISA_CLK C32 NC so Ob - eP let C30 5.2.3 Mouse Connector Table 12. Mouse Connector Pin Definitions (P2406 P2406 upper side) Signal Name (s) Dat Out ct NC du o GND 5V (Vcc) Pr e Pin 10 11 12 13 InClkOut let o 14 NC 15 5.2.4 Keyboard Connector Table 13. Keyboard Connector Pin Definitions (P4206 P4206 lower side) bs O Signal Name Pin Dat Out 1 NC 2 GND 3 5 V (Vcc) 4 InClkOut 5 NC 6 25/36 MOTHERBOARD HARDWARE SPECIFICATION 5.2.5 Parallel Connector Table 14. Parallel Connector Pin Definitions (P4207 P4207) Signal Name Pin Pin Signal Name STE#OUT 1 2 SIO_AFD#1 D0 Out 3 4 SIO_ERR# D1 Out 5 6 SIO_INIT# D2 Out 7 8 SIO_SLIN# D3 Out 9 10 GND D4 Out 11 12 GND D5 Out 13 14 GND D6 Out 15 16 GND D7 Out 17 18 GND SIO_ACK# 19 20 GND SIO_BUSY 21 22 GND SIO_PE 23 24 SIO_SLCT 25 26 Pin GND A1 +12V A2 NC A3 Pin so Ob B1 ro eP let 5.2.6 PCI Connectors Table 15. PCI Connector Pin Definitions (P900, P901, P902) Signal Name uc d GND s) t( NC Signal Name -12V B2 NC B3 GND B4 NC A5 B5 Vcc A6 B6 Vcc ref: Table 16 Table 17 Table 18 A7 B7 ref: Table 16 Table 17 Table 18 Vcc A8 B8 ref: Table 16 Table 17 Table 18 Reserved A9 B9 NC Vcc A10 B10 Reserved Reserved A11 B11 NC GND A12 B12 GND GND A13 B13 GND Reserved A14 B14 Reserved RESET# A15 B15 GND Vcc A16 B16 PCICLK ref: Table 16 Table 17 Table 18 A17 B17 GND GND A18 B18 ref: Table 16 Table 17 Table 18 NC 5 V Vcc uc d ref: Table 16 Table 17 Table 18 ro P e let o bs O 26/36 (s) t A4 MOTHERBOARD HARDWARE SPECIFICATION Signal Name Pin Pin Signal Name Reserved A19 B19 Vcc AD30 A20 B20 AD31 3.3V A21 B21 AD29 AD28 A22 B22 GND AD26 A23 B23 AD27 GND A24 B24 AD25 AD24 A25 B25 3.3V ref: Table 16 Table 17 Table 18 A26 B26 CBE3# 3.3V A27 B27 AD23 AD22 A28 B28 GND AD20 A29 B29 AD21 GND A30 B30 AD19 AD18 A31 B31 3.3V AD16 A32 B32 3.3V A33 B33 FRAME# A34 B34 GND A35 B35 TRDY# A36 B36 GND A37 B37 STOP# A38 3.3V A39 SDONE (s) uc d AD17 ro CBE2# eP let GND IRDY3.3V so DEVSEL# B38 GND B39 PCILOCK# B40 PERR# A41 B41 3.3V A42 B42 SERR# A43 B43 3.3V A44 B44 CBE1# 3.3V A45 B45 AD14 AD13 A46 B46 GND AD11 A47 B47 AD12 GND A48 B48 AD10 AD9 A49 B49 GND KEY A50 B50 KEY KEY A51 B51 KEY CBE0# A52 B52 AD8 3.3V A53 B53 AD7 AD6 A54 B54 3.3V A40 ct SBO# GND PAR du o Pr e AD15 let o bs O s) t( Ob - 27/36 MOTHERBOARD HARDWARE SPECIFICATION Signal Name Pin Pin Signal Name AD4 A55 B55 AD5 GND A56 B56 AD3 AD2 A57 B57 GND AD0 A58 B58 AD1 Vcc A59 B59 Vcc NC A60 B60 NC Vcc A61 B61 Vcc Vcc A62 B62 Vcc Pin Signal name B7 PCI_INT3# B8 PCI_INT1# Table 16. PCI Connector Pin Definition (P900) Signal name Pin PCI_INT0# A7 PCI_INT2# A6 PCI_GNT2# uc d A17 B18 IDSELB (AD29) Signal name Pin te le PCI_INT1# A6 PCI_INT3# A7 so Ob Pin ro P PCI_REQ2# A26 Table 17. PCI Connector Pin Definition (P901) s) t( Signal name B8 PCI_INT0# B18 PCI_REQ1# Pin Signal name B7 PCI_INT1# PCI_INT3# B18 ro P e IDSELA (AD30) uc d PCI_INT2# B8 PCI_GNT1# (s) t B7 PCI_REQ0# A17 A26 Table 18. PCI Connector Pin Definition (P902) let o Signal name bs O Pin PCI_INT0# A6 PCI_INT2# A7 PCI_GNT0# IDSELA (AD31) 28/36 A17 A26 MOTHERBOARD HARDWARE SPECIFICATION 5.2.7 COM (Serial Port) Connector Table 19. COM (Serial Port) Connector Pin Definition (P4208 P4208, P4209 P4209) Signal Name Pin (BD9_M P4208 P4208) Pin (Header P4209 P4209) RA1 1 - RA3 2 3 DY2 3 5 DY3 4 - GND 5 9 RA2 6 - DY1 7 - RA4 8 - RA5 9 - 5.2.8 IDE Connectors Table 20. UIDE Connectors Pin Definition (P2100 P2100, P2101 P2101) Signal Name Pin Pin IDE_RESET# 1 2 IDE_DD7 3 4 IDE_DD6 5 6 IDE_DD5 7 8 IDE_DD4 9 IDE_DD3 11 IDE_DD2 13 Signal Name te le so Ob 10 uc d s) t( ro P GND IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 12 IDE_DD12 14 IDE_DD13 16 IDE_DD14 17 18 IDE_DD15 19 20 NC 21 22 GND IDE_SIOW# 23 24 GND IDE_SIOR# 25 26 GND IDE_IORDY 27 28 GND IDE_SDACK# 29 30 GND IDE_SIRQ 31 32 NC IDE_DA1 33 34 NC IDE_DA0 35 36 IDE_DA2 IDE_SCS#1 37 38 IDE_P(S)CS#3 LED 39 40 GND IDE_DD1 IDE_DD0 GND ro P e IDE_SDRQ bs O let o (s) t 15 uc d 29/36 MOTHERBOARD HARDWARE SPECIFICATION 5.2.9 Floppy Connector Table 21. Floppy Connector Pin Definition (P4205 P4205) Signal Name Pin Pin Signal Name GND 1 2 DENSEL GND 3 4 NC GND 5 6 DRATE0 NC 7 8 INDEX# GND 9 10 MTR#0 GND 11 12 DR#1 NC 13 14 DR#0 GND 15 16 MTR#1 GND 17 18 DIR# GND 19 20 STEP# GND 21 22 WDATA# GND 23 24 WGATE# GND 25 26 GND 27 28 NC 29 30 GND 31 32 NC 33 Ob - ro TRK0# eP let so 34 uc d s) t( WP# RDATA# HDSEL DSKCHG 5.2.10 ATX Power Supply Connectors Table 22. ATX Power Supply Connector Pin Definition (P3300 P3300) Signal Name (s) t Pin Signal Name 11 1 +3.3 V 12 2 +3.3 V 13 3 GND ON# / OFF 14 4 +5 V GND 15 5 GND GND 16 6 +5 V GND 17 7 GND -5 V 18 8 POWER_OK +5 V 19 9 +5 V Supply Backup +5 V 20 10 +12 V +3.3 V -12 V ro P e GND let o bs O 30/36 Pin uc d MOTHERBOARD HARDWARE SPECIFICATION 5.2.11 JTAG Connectors Table 23. JTAG Connector Pin Definition (P4000 P4000) Signal Name Pin Pin Signal Name STPC_TCK 1 2 GND STPC_TDO 3 4 5V STPC_TMS 5 6 NC NC 7 8 NC STPC_TDI 9 10 GND 5.2.12 GPIO Connector Table 24. GPIO Connector Pin Definition (P3700 P3700) Signal Name Pin GPIO_7 1 GND 2 GPIO_6 3 GND 4 GPIO_5 te le GPIO_4 GND GPIO_3 GND GPIO_2 GND GPIO_1 uc d GND ro P e ro P 5 GND (s) t uc d 6 7 8 so Ob - 9 10 11 12 13 14 GPIO_0 15 GND let o s) t( 16 5.2.13 I2C Connector Table 25. I2C Connector Pin Definition (P4400 P4400) O bs Signal Name Pin SDA 1 SCL 2 GND 3 31/36 MOTHERBOARD HARDWARE SPECIFICATION 5.2.14 Ethernet/Filter Table 26. Ethernet/Filter Connector Pin Definitions (U4502 U4502) Signal Name Pin TxP RJ-1 TxN RJ-2 RxP RJ-3 RJ-4 Return RJ-5 RxN RJ-6 RJ-7 Return RJ-8 5.2.15 Dual USB Table 27. Dual USB Connector Pin Definitions (P2301 P2301) Signal Name Pin USB Vcc ro P 1 DATA0- te le DATA0+ GND USB Vcc DATA1DATA1+ GND uc d (s) t uc d so Ob - 2 3 4 5 6 7 8 5.2.16 Reset Button Header Table 28. Reset Button Header Connector Pin Definition (J3300 J3300) ro P e Signal Name Pin Remote Signal 1 GND 2 let o 5.2.17 On/Off Button Header Table 29. On/Off Button Header Connector Pin Definition (J3301 J3301) bs O Signal Name Pin Remote Signal 1 GND 2 5.3 GROUND TEST POINT Eighteen Ground test points are provided, numbered TP1 to TP18. 32/36 s) t( TROUBLESHOOTING 6 TROUBLESHOOTING 6.1 BOOT FAILS WITH SOME ISA CARDS 6.1.1 Description The Vega Evaluation board BA000109BB BA000109BB does not boot when some ISA cards are installed and POST CODE value is 00. When the ISA cards are removed, the Vega board boots and runs successfully. Some ISA cards have Pull Up resistors on SMEMR# and SMEMW# signals that are used as strap options by the STPC Vega. In fact, these Pull Up resistors act on the SMEMR# and SMEMW# signals and modify the value of the strap options. s) t( As a result, the strap options on the Vega Board are not valid which prevents the system from booting. uc d 6.1.2 Workaround ro P The figure below corresponds to the Pull Down resistor associated to SMEMR# /SMEMW# signals and the Pull Up resistor added by the ISA card. te le so Ob R Vcc (s) SMEMR# / SMEMW# signals 2 ct u od Pr e Vmea- R1 let o bs O Notes: ­ R1 is the Pull Down resistor linked to the SMEMR# or SMEMW# signals and it is used as strap option on the board. On the Vega Evaluation Board R1=470 KOhms. ­ R2 is the Pull Up resistor of the ISA card. 33/36 TROUBLESHOOTING ­ The maximum voltage recommended by the TTL technology for the Low level is 0.6 volts. (1) At this case the ideal value of Vmeasured must be the correct value of R1 is: uc d Vi × R2 R 1 = -V cc ­ V i s) t( ro P Note: the value calculated corresponds to the maximum value of the resistor. Therefore, the value chosen must not be larger or smaller as it could cause board instability. te le 6.1.3 Example so Ob - The Vega Evaluation board does not boot with the two ISA Ethernet cards: ­ 3COM Etherlink III (3C5098B-TP 3C5098B-TP) (s) ct ­ Realtek (RTL8019AS RTL8019AS). To obtain the correct strap options values: du o ­ The pull down resistor associated with the SMEMR# signal "R508" must be reduced to 15KOhms instead of 470 KOhms. Pr e ­ The pull down resistor associated with the SMEMW# signal "R509" must be reduced to 10KOhms instead of 470 KOhms. let o bs O 34/36 TECHNICAL SUPPORT 7 TECHNICAL SUPPORT STMicroelectronics has a World Wide Web (WWW) Internet site on which can be found product presentations, technical literature and product support information. A dedicated STPC section is available providing up-to-date hardware documentation and software tools. Check here to discover whether an updated version of this VEGABD User Manual is available. Technical queries regarding the VEGABD Evaluation Kit or any other STPC product can be addressed to your nearest ST Microelectronics Sales Office. The STMicroelectronics Website address is: http://www.st.com/ uc d te le (s) ct s) t( ro P so Ob - du o Pr e let o bs O 35/36 TECHNICAL SUPPORT THE SOFTWARE INCLUDED IN THIS MANUAL IS FOR GUIDANCE ONLY. STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THE SOFTWARE. uc d te le (s) ct s) t( ro P so Ob - du o Pr e let o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. bs O The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia ­ Belgium - Brazil - Canada - China ­ Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 36/36