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Applications of "XOR Gate"

Catalog Datasheet Results Type PDF Document Tags
Abstract: input of an exclusive-OR gate (XOR gate U2) as well as the input to a delay circuit. Consisting of R1, C1, and comparator U1, the delay circuit drives the XOR gate's second input. A resistive divider , , pin 4 of the XOR gate is low but pin 5 is high, due to signal inversion by the comparator. The XOR output is therefore high. If the pin-4 input is now driven high, the XOR gate responds immediately by , Input Frequency A simple circuit consisting of a comparator and an exclusive-OR gate is sufficient to ... Original
datasheet

3 pages,
28.78 Kb

XOR Gates AN3327 APP3327 comparator high fast& low delay time MAX9010 gate xor IC of XOR GATE "XOR Gate" Frequency Doubler 30Mhz comparator using 2 xor gates Applications of "XOR Gate" datasheet abstract
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Abstract: NC7SZ11 NC7SZ11 OR Gate Lower propagation delay by 50% XOR Gate Consume 50% less power Package , 3-Input Gate Function Pairs of 2-Input Gates Fairchild's 3-Input Gate NAND Gate `00 NC7SZ10 NC7SZ10 AND Gate `08 NC7SZ11 NC7SZ11 NOR Gate `02 NC7SZ27 NC7SZ27 OR Gate `32 NC7SZ332 NC7SZ332 XOR Gate `86 NC7SZ386 NC7SZ386 MicroPakTM 3-Input Gates (Coming Soon) 3-Input Gate Applications Mobile , Minimize Logic with TinyLogicTM 3-Input Gates 5-Lead 3-Input Gate Hook-up Fairchild's 3-Input ... Original
datasheet

2 pages,
918.53 Kb

xor ttl 2 input nand gate 18v NC7SZ10 NC7SZ11 NC7SZ27 NC7SZ332 NC7SZ386 SC70-6 5275 for 3 input xor gate "XOR Gate" 3 input or gates TTL TTL 3 input or gate Applications of "XOR Gate" datasheet abstract
datasheet frame
Abstract: HMC725LC3C HMC725LC3C v01.1208 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The , HMC725LC3C HMC725LC3C is a XOR/XNOR gate function designed to support data transmission rates of up to 13 Gbps, and , 13 Gbps, FAST RISE TIME XOR / XNOR GATE Electrical Specifi cations, (continued) Conditions , XOR / XNOR GATE Output Return Loss vs. Frequency Input Return Loss vs. Frequency 7 - 100 , , FAST RISE TIME XOR / XNOR GATE Eye Diagram 7 HIGH SPEED LOGIC - SMT [1] Test Conditions ... Original
datasheet

8 pages,
244.24 Kb

N4903A gate xnor xor logic table for 3 input xor gate circuit xnor Applications of "XOR Gate" 6_ INPUT XOR GATE XNOR GATE XNOR GATE application HMC725LC3C HMC725LC3C abstract
datasheet frame
Abstract: HMC725LC3C HMC725LC3C v00.0808 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The , Systems up to 13 GHz Functional Diagram General Description The HMC725LC3C HMC725LC3C is a XOR/XNOR gate , On-line at www.hittite.com HMC725LC3C HMC725LC3C v00.0808 13 Gbps, FAST RISE TIME XOR / XNOR GATE , www.hittite.com HMC725LC3C HMC725LC3C v00.0808 13 Gbps, FAST RISE TIME XOR / XNOR GATE Output Return Loss vs. , On-line at www.hittite.com HMC725LC3C HMC725LC3C v00.0808 13 Gbps, FAST RISE TIME XOR / XNOR GATE Eye ... Original
datasheet

8 pages,
652.41 Kb

xnor XNOR GATE application Applications of "XOR Gate" HMC725LC3C HMC725LC3C abstract
datasheet frame
Abstract: HMC725LC3C HMC725LC3C v02.1209 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The , Systems up to 13 GHz Functional Diagram General Description The HMC725LC3C HMC725LC3C is a XOR/XNOR gate , On-line at www.hittite.com HMC725LC3C HMC725LC3C v02.1209 13 Gbps, FAST RISE TIME XOR / XNOR GATE Electrical , www.hittite.com HMC725LC3C HMC725LC3C v02.1209 13 Gbps, FAST RISE TIME XOR / XNOR GATE Output Return Loss vs. , On-line at www.hittite.com HMC725LC3C HMC725LC3C v02.1209 13 Gbps, FAST RISE TIME XOR / XNOR GATE Eye ... Original
datasheet

8 pages,
447.77 Kb

Applications of "XOR Gate" HMC725LC3C HMC725LC3C abstract
datasheet frame
Abstract: rely on gate arrays to deliver the performance and features required for network peripherals. The current generation of FPGAs, however, allows the designer to achieve the performance and capacity required for ATM applications and to meet the key time-to-market goals of these fast-evolving applications , X8 + X2 + X + 1 and is implemented with XOR gates, as shown in Figure 5. A parallel implementation of , constraints can be met, prior to completion of the entire design. Applications like this, with complex ... Original
datasheet

4 pages,
30.92 Kb

FPGA based dma controller using vhdl Dual-Port V-RAM Applications of "XOR Gate" 3200DX 3200DX abstract
datasheet frame
Abstract: rely on gate arrays to deliver the performance and features required for network peripherals. The current generation of FPGAs, however, allows the designer to achieve the performance and capacity required for ATM applications and to meet the key time-to-market goals of these fast-evolving applications. Introduction An ATM network interface card (NIC) requires high-speed system logic functions , wide-decode function, provides just the right mix of capabilities for applications like ATM network interface ... Original
datasheet

4 pages,
26.82 Kb

8 bit XOR Gates AC100 Dual-Port V-RAM design of dma controller using vhdl asynchronous fifo vhdl fpga vhdl code CRC Controller System NIC vhdl code for 4 channel dma controller ATM machine using microprocessor Applications of "XOR Gate" FPGA based dma controller using vhdl 3200DX AC100 abstract
datasheet frame
Abstract: rely on gate arrays to deliver the performance and features required for network peripherals. The current generation of FPGAs, however, allows the designer to achieve the performance and capacity required for ATM applications and to meet the key time-to-market goals of these fast-evolving applications. Introduction An ATM network interface card (NIC) requires high-speed system logic functions , just the right mix of capabilities for applications like ATM network interface cards. These system ... Original
datasheet

4 pages,
33.96 Kb

design of dma controller using vhdl asynchronous fifo vhdl fpga FPGA based dma controller using vhdl 8 bit XOR Gates vhdl code for 4 channel dma controller Controller System NIC ATM machine using microprocessor Applications of "XOR Gate" 3200DX 3200DX abstract
datasheet frame
Abstract: output of the XOR Applications Circuit Design Figure 1 - Basic Flancter. There are a few , inverter, and an exclusive OR (XOR) gate. Notice that the asynchronous reset inputs to the flip-flops are , shown in Figure 1, but untwisted so that the two inputs to the XOR gate are clearly visible. You can see that the XOR gate's upper input is labeled Q1, while its lower input is labeled Q2. Also, Q1 and Q2 are , won't be clocked simultaneously (or within each other's setup and hold time windows). Applications of ... Original
datasheet

3 pages,
149.59 Kb

Applications of "XOR Gate" datasheet abstract
datasheet frame
Abstract: 12.5 Gb/sec XOR gate (Preliminary Information) Electrical Characteristics1 2. In the case of , DM4011 DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Description The DM4011 DM4011 is a high-speed , +39 (06) 5582904 FAX +39 (06) 5587394 DM4011 DM4011 12.5 Gb/sec XOR gate (Preliminary Information , (06) 5587394 DM4011 DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Eye Diagram Performance DM4011 DM4011 used as XOR gate. 10.709 Gb/s NRZ inputs, 1.8 Vpp differential on DIN1 and DIN2. Power supply ... Original
datasheet

8 pages,
547.01 Kb

4011 IC manchester encoder 4011 DELL power supply DM4011 differential manchester encoder XOR GATE uses 4011 IC data sheet Applications of "XOR Gate" DELL power supply diagram DATA SHEET IC 4011 IC of XOR GATE IC 4011 DM4011 abstract
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Datasheet Content (non pdf)

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Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
following test circuit shows how the inclusion of an XOR gate and invertor allows full 2 wire operation. allowing bi-phase encoding of the CANL and CANH lines; the recessive state is logic 0 on Rx1. The resistor divider across the Vdd - Vss supply provides a 75% of Vdd reference for a recessive state to force the XOR you explain bi-phase mode CAN? answer: This mode is intended for use in applications case with the single and two wire CAN bus modes of operation.An important difference in bi-phase mode
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Motorola 08/03/1998 4.07 Kb HTM biphase.htm
patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to V CC or GND. The three inputs (A, B and C) are capable of ; Low-power configurable multiple function gate V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I off . The I off circuitry
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The SY55851U SY55851U SY55851U SY55851U is a highly flexible, universal logic gate capable of upto 2.5GHz operation. Its differential inputs and outputs will produce any of 9 possible logic functions of two Boolean variables. It can be configured as any of the following gates: AND, NAND, OR, NOR, XOR, XNOR, DELAY, NEGATION (NOT). with a single resistor between the true and the complement pins of a given input. The SY55851U SY55851U SY55851U SY55851U is a member of MicrelÂ's new Super-Lite™ family of high-speed logic devices. This family features very
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Differential Smart Gate with Output Level Select NB7L86M NB7L86M NB7L86M NB7L86M 2.5V / 3.3V 12Gb/s Differential Clock/Data Smart Gate ( 2:1 Mux, AND/NAND, OR/NOR, XOR/XNOR) w/CML Output and voltage, high voltage, AC and DC solutions for driving LED lighting applications. You may download the latest versions or look through our library of technical information including SPICE models and other and the ON Semiconductor logo are registered trademarks of Semiconductor Components Industries
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causes the counter to become enabled on the next transition of the CLK. EN1 (or EN2) and CLK edges are coincident. Sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of various applications. The asynchronous enable input, A_Start, when asserted, enables the counter while
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Reset and Differential Clock Gate NB7L86M NB7L86M NB7L86M NB7L86M 2.5V / 3.3V 12Gb/s Differential Clock/Data Smart Gate ( 2:1 Mux, AND/NAND, OR/NOR, XOR/XNOR) w/CML voltage, high voltage, AC and DC solutions for driving LED lighting applications. You may download the latest versions or look through our library of technical information including SPICE models and other Differential Smart Gate with Output Level Select MC100EP101 MC100EP101 MC100EP101 MC100EP101 3.3V / 5V
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macrocell with the assistance of an XOR gate without incurring additional timing delays. This key matrices, enhanced logic arrays, intelligent logic allocator with an XOR gate and multi-clocking, the MACH state machines and dual-phase clock applications, allowing a greater integration of glue logic. MACH ® 4 Family High-Performance CPLDs With Maximum Ease of Use Maximum Ease of Use The MACH 4 family from Vantis offers an exceptionally flexible architecture and
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Field Programmable Gate Array Flash Memory/DataFlash FPGA Configuration Memory FPSLIC Gate Arrays/ Embedded Arrays Imaging Parallel EEPROM Power Metering Updated: August 9, 2000 Field Programmable Gate Array (FPGAs) - Application Notes of times. AT00 Series Configuration (21 pages, updated 9/99) This document suggests guidelines for device congifuration and describes each of the configuration modes in detail.
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ASIC Cores Dream Sound Synthesis EPROM Field Programmable Gate Array Flash Memory/DataFlash FPGA Configuration Memory FPSLIC Gate Arrays/ Embedded Arrays Updated: May 15, 2001 Field Programmable Gate Array (FPGAs) - Application Notes can be configured any number of times. HDLPlanner® Design Development Environment for performance delivering layouts. Replacement of a RAM with Atmel FreeRAM in VHDL (8 pages, updated
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No abstract text available
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Atmel 26/04/2000 1186.28 Kb ZIP a.zip