NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: input of an exclusive-OR gate (XOR gate U2) as well as the input to a delay circuit. Consisting of R1, C1, and comparator U1, the delay circuit drives the XOR gate's second input. A resistive divider , , pin 4 of the XOR gate is low but pin 5 is high, due to signal inversion by the comparator. The XOR output is therefore high. If the pin-4 input is now driven high, the XOR gate responds immediately by , Input Frequency A simple circuit consisting of a comparator and an exclusive-OR gate is sufficient to ... | Original |
3 pages, |
XOR Gates MAX9010 AN3327 APP3327 gate xor "XOR Gate" comparator using 2 xor gates IC of XOR GATE Frequency Doubler 30Mhz Applications of "XOR Gate" datasheet abstract |
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| Abstract: NC7SZ11 NC7SZ11 OR Gate Lower propagation delay by 50% XOR Gate Consume 50% less power Package , 3-Input Gate Function Pairs of 2-Input Gates Fairchild's 3-Input Gate NAND Gate `00 NC7SZ10 NC7SZ10 AND Gate `08 NC7SZ11 NC7SZ11 NOR Gate `02 NC7SZ27 NC7SZ27 OR Gate `32 NC7SZ332 NC7SZ332 XOR Gate `86 NC7SZ386 NC7SZ386 MicroPakTM 3-Input Gates (Coming Soon) 3-Input Gate Applications Mobile , Minimize Logic with TinyLogicTM 3-Input Gates 5-Lead 3-Input Gate Hook-up Fairchild's 3-Input ... | Original |
2 pages, |
SC70-6 2 input nand gate 18v NC7SZ10 NC7SZ11 NC7SZ27 NC7SZ332 NC7SZ386 5275 Applications of "XOR Gate" "XOR Gate" for 3 input xor gate 3 input or gates TTL datasheet abstract |
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| Abstract: HMC725LC3C HMC725LC3C v01.1208 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The , HMC725LC3C HMC725LC3C is a XOR/XNOR gate function designed to support data transmission rates of up to 13 Gbps, and , 13 Gbps, FAST RISE TIME XOR / XNOR GATE Electrical Specifi cations, (continued) Conditions , XOR / XNOR GATE Output Return Loss vs. Frequency Input Return Loss vs. Frequency 7 - 100 , , FAST RISE TIME XOR / XNOR GATE Eye Diagram 7 HIGH SPEED LOGIC - SMT [1] Test Conditions ... | Original |
8 pages, |
xor logic table N4903A gate xnor circuit xnor Applications of "XOR Gate" for 3 input xor gate 6_ INPUT XOR GATE XNOR GATE XNOR GATE application HMC725LC3C HMC725LC3C abstract |
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| Abstract: rely on gate arrays to deliver the performance and features required for network peripherals. The current generation of FPGAs, however, allows the designer to achieve the performance and capacity required for ATM applications and to meet the key time-to-market goals of these fast-evolving applications. Introduction An ATM network interface card (NIC) requires high-speed system logic functions , just the right mix of capabilities for applications like ATM network interface cards. These system ... | Original |
4 pages, |
design of dma controller using vhdl asynchronous fifo vhdl fpga vhdl code for 4 channel dma controller Controller System NIC ATM machine using microprocessor Applications of "XOR Gate" 3200DX 3200DX abstract |
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| Abstract: rely on gate arrays to deliver the performance and features required for network peripherals. The current generation of FPGAs, however, allows the designer to achieve the performance and capacity required for ATM applications and to meet the key time-to-market goals of these fast-evolving applications. Introduction An ATM network interface card (NIC) requires high-speed system logic functions , wide-decode function, provides just the right mix of capabilities for applications like ATM network interface ... | Original |
4 pages, |
AC100 asynchronous fifo vhdl fpga design of dma controller using vhdl Dual-Port V-RAM vhdl code CRC Controller System NIC vhdl code for 4 channel dma controller Applications of "XOR Gate" ATM machine using microprocessor FPGA based dma controller using vhdl 3200DX AC100 abstract |
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| Abstract: 12.5 Gb/sec XOR gate (Preliminary Information) Electrical Characteristics1 2. In the case of , DM4011 DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Description The DM4011 DM4011 is a high-speed , +39 (06) 5582904 FAX +39 (06) 5587394 DM4011 DM4011 12.5 Gb/sec XOR gate (Preliminary Information , (06) 5587394 DM4011 DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Eye Diagram Performance DM4011 DM4011 used as XOR gate. 10.709 Gb/s NRZ inputs, 1.8 Vpp differential on DIN1 and DIN2. Power supply ... | Original |
8 pages, |
4011 IC manchester encoder 4011 DELL power supply DM4011 differential manchester encoder XOR GATE uses 4011 IC data sheet Applications of "XOR Gate" DELL power supply diagram DATA SHEET IC 4011 IC 4011 IC of XOR GATE DM4011 abstract |
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| Abstract: demonstrates the usage of .OE and .OEMUX to control the AND/OR product term configuration and XOR configuration, respectively. Introduction The Exclusive-OR (XOR) gate can efficiently implement arithmetic , of product term usage in a highspeed system design, a high-speed device with a built-in XOR function , outputs to any combination of registers, combinatorial, XOR and AND/OR structures. Conclusion This design example illustrates the efficient usage of the XOR function by implementing the address counter ... | Original |
4 pages, |
XOR GATE uses SA3 357 GAL20XV10 20XV10 Applications of "XOR Gate" SA2 357 20XV10 abstract |
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| Abstract: demonstrates the usage of .OE and .OEMUX to control the AND/OR product term configuration and XOR configuration, respectively. Introduction The Exclusive-OR (XOR) gate can efficiently implement arithmetic , of product term usage in a highspeed system design, a high-speed device with a built-in XOR function , outputs to any combination of registers, combinatorial, XOR and AND/OR structures. Conclusion This design example illustrates the efficient usage of the XOR function by implementing the address counter ... | Original |
4 pages, |
GAL20XV10 20XV10 cupl 20XV10 abstract |
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| Abstract: HMC851LC3C HMC851LC3C v00.0610 28 Gbps, XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT VOLTAGE Typical , General Description The HMC851LC3C HMC851LC3C is a XOR/XNOR gate function designed to support data transmission , apps@hittite.com 3-2 HMC851LC3C HMC851LC3C v00.0610 28 Gbps, XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT VOLTAGE , apps@hittite.com HMC851LC3C HMC851LC3C v00.0610 28 Gbps, XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT VOLTAGE Eye , 3-4 HMC851LC3C HMC851LC3C v00.0610 28 Gbps, XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT VOLTAGE Absolute ... | Original |
8 pages, |
XNOR GATE application HMC851LC3C for 3 input xor gate XNOR GATE HMC851LC3C abstract |
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| Abstract: HMC721LP3E HMC721LP3E v00.0210 13 Gbps, FAST RISE TIME XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT VOLTAGE , mm SMT Package: 9 mm² Functional Diagram General Description The HMC721LP3E HMC721LP3E is a XOR/XNOR gate , apps@hittite.com HMC721LP3E HMC721LP3E v00.0210 13 Gbps, FAST RISE TIME XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT , apps@hittite.com 3-2 HMC721LP3E HMC721LP3E v00.0210 13 Gbps, FAST RISE TIME XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT , HMC721LP3E HMC721LP3E v00.0210 13 Gbps, FAST RISE TIME XOR / XNOR GATE w/ PROGRAMMABLE OUTPUT VOLTAGE Eye Diagram ... | Original |
8 pages, |
pin diagram of xor N4903A AP 1100 R1 XNOR GATE XNOR GATE application HMC721LP3E HMC721LP3E abstract |
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| statements have all be optimized to use 4-input XOR gates - wherever possible to fit efficiently in the - Staff Applications Engineer - - Video Applications - Advanced disclosed to others for the purpose of enhancing - and promoting design productivity in Xilinx give consideration to the productivity - enhancements afforded the user of this code by the - IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR - A PARTICULAR PURPOSE, OR AGAINST www.datasheetarchive.com/download/14784420-995965ZC/xapp299.zip (edh_crc16.vhd) |
Xilinx | 17/05/2002 | 200.97 Kb | ZIP | xapp299.zip |
| SY55851U SY55851U SY55851U SY55851U AnyGate CML Logic Chip SY55851U SY55851U SY55851U SY55851U AnyGate CML Logic Chip General Description Features The SY55851U SY55851U SY55851U SY55851U is a highly flexible, universal logic gate capable of upto 2.5GHz operation. Its differential inputs and outputs will produce any of 9 possible logic functions of two Boolean variables. It can be configured as any of the following gates: AND, NAND, OR, NOR, XOR, XNOR, DELAY www.datasheetarchive.com/files/micrel/products/products/sy55851u.shtml |
Micrel | 26/06/2002 | 4.98 Kb | SHTML | sy55851u.shtml |
| SY10/100EL07 SY10/100EL07 SY10/100EL07 SY10/100EL07 2-INPUT XOR/XNOR SY10/100EL07 SY10/100EL07 SY10/100EL07 SY10/100EL07 2-INPUT XOR/XNOR General Description The SY10/100EL07 SY10/100EL07 SY10/100EL07 SY10/100EL07 are 2-input XOR/XNOR gates. These devices are applications which require the ultimate in AC performance , navigate and print PDF files across many different platforms. If you wish to download a copy of the free www.datasheetarchive.com/files/micrel/products/products/sy10-100el07.html |
Micrel | 26/06/2002 | 5.33 Kb | HTML | sy10-100el07.html |
| /data/2vp50.spd" Reading design: edc.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL : YES XOR Collapsing : YES Resource Sharing : YES Complex Clock /./././src/VHDL/top.vhd in Library work. Architecture behavioral of Entity edc is up to date :/ line 125: Mux is complete : default of case is /./././src/VHDL/top.vhd line 324: Mux is complete : default of case is discarded Entity analyzed. Unit generated www.datasheetarchive.com/download/27223516-996011ZC/xapp645.zip (edc.syr) |
Xilinx | 01/09/2004 | 1241.36 Kb | ZIP | xapp645.zip |
| file "c:/MYXILINX/virtex2p/data/2vp4.spd" Reading design: EDC.prj TABLE OF CONTENTS 1) Synthesis : YES XOR Collapsing : YES Resource Sharing : YES Complex Clock * = Analysis of file succeeded. Analyzing top module . Module is correct for synthesis >. Found 64-bit register for signal . Found 64-bit xor2 for signal created at line 97 0003>. Found 64-bit xor2 for signal created at line 527. Found 64-bit xor2 for signal www.datasheetarchive.com/download/27223516-996011ZC/xapp645.zip (EDC.syr) |
Xilinx | 01/09/2004 | 1241.36 Kb | ZIP | xapp645.zip |
| , universal logic gates capable of up to 3.0GHz operation (SY55851A SY55851A SY55851A SY55851A). These AnyGate differential logic devices will produce all possible logic functions of two Boolean variables. They can be configured as any of the following gates: AND, NAND, OR, NOR, XOR, XNOR, DELAY, NEGATION (NOT). The SY55851 SY55851 SY55851 SY55851 and SY55851A SY55851A SY55851A SY55851A SY55851/851A SY55851/851A SY55851/851A SY55851/851A 2.5V/3V/5V, 3.0GHz CML AnyGateAny Logic W/50- Or 100- Outputs SY55851/851A SY55851/851A SY55851/851A SY55851/851A 2.5V/3V/5V, 3.0GHz CML AnyGateAny Logic W/50 Or 100 Outputs www.datasheetarchive.com/files/micrel/products/products/sy55851a.shtml |
Micrel | 26/06/2002 | 6.72 Kb | SHTML | sy55851a.shtml |
| ) . Transitions of the input square wave apply directly to the lower input of the exclusive-OR (XOR) gate, but are -to-voltage conversion. The XOR output's duty cycle is proportional to the sum of R1 + C1 delay plus comparator detector, this capacitance equals 48pF and produces a delay of 16.5ns at the upper XOR input. With a hand Application Note: Dual Comparator Forms Temperature proximity detector shown in Figure 1 , a 4-inch-square piece of copper-plated PC board serves as an antenna www.datasheetarchive.com/files/maxim/0004/appno083.htm |
Maxim | 04/04/2001 | 9.42 Kb | HTM | appno083.htm |
| ) . Transitions of the input square wave apply directly to the lower input of the exclusive-OR (XOR) gate, but are -to-voltage conversion. The XOR output's duty cycle is proportional to the sum of R1 + C1 delay plus comparator detector, this capacitance equals 48pF and produces a delay of 16.5ns at the upper XOR input. With a hand Application Note: Dual Comparator Forms Temperature proximity detector shown in Figure 1 , a 4-inch-square piece of copper-plated PC board serves as an antenna www.datasheetarchive.com/files/maxim/0003/appno058.htm |
Maxim | 04/04/2001 | 9.4 Kb | HTM | appno058.htm |
| for reception. The following test circuit shows how the inclusion of an XOR gate and invertor allows recessive state to force the XOR gate to read logic 1 on both Tx0 and Tx1, thus driving Rx0 to a logic 0 or for use in applications where there must be no DC component in the communication. Typically the signal physical interface just as is the case with the single and two wire CAN bus modes of operation.An important lines correctly while allowing bi-phase encoding of the CANL and CANH lines; the recessive state is www.datasheetarchive.com/files/motorola/cdcsic2/web/techhelp/faq/xfamily/biphase.htm |
Motorola | 08/03/1998 | 4.07 Kb | HTM | biphase.htm |
| 20 XOR gates generated by this statement convert the 21-bit wide - nrzi data to 20 bits of NRZ - Staff Applications Engineer - - Video Applications - Advanced disclosed to others for the purpose of enhancing - and promoting design productivity in Xilinx give consideration to the productivity - enhancements afforded the user of this code by the - IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR - A PARTICULAR PURPOSE, OR AGAINST www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (hdsdi_decoder.vhd) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |