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Catalog Datasheet | MFG & Type | Document Tags |

Abstract: hermetic standard package Applications ï· Well logging, ï· Automotive, Aeronautics & , OUT2 6 9 IN3 B VSS 7 8 OUT3 3 OUT1 Output of the XOR gate number 1 IN2 A Input A of the XOR gate number 2 5 IN2 B Input B of the XOR gate number 2 OUT2 Output of the XOR gate number 2 7 VSS Circuit core ground terminal. OUT3 Output of the XOR gate number 3 9 IN3 B Input B of the XOR gate number 3 IN3 A Input A of the XOR gate ... | CISSOID Original |
9 pages, |
7486 XOR GATE pin configuration CHT-7486 TEXT |

Abstract: HMC725LC3C HMC725LC3C v00.0808 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The HMC725LC3C HMC725LC3C is ideal for: · RF ATE Applications Features Inputs Terminated Internally in 50 Ohms , function designed to support data transmission rates of up to 13 Gbps, and clock frequencies as high as 13 , either AC or DC coupled. The differential outputs of the HMC725LC3C HMC725LC3C may be either AC or DC coupled , [1] Deterministic jitter calculated by simultaneously measuring the jitter of a 300 mV, 13 GHz, 215 ... | Hittite Microwave Original |
8 pages, |
XNOR GATE xnor circuit xnor Applications of "XOR Gate" XNOR GATE application HMC725LC3C TEXT |

Abstract: HMC725LC3C HMC725LC3C v01.1208 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The , Internally in 50 Ohms · RF ATE Applications 7 Features Propagation Delay: 105 ps Single Supply , HMC725LC3C HMC725LC3C is a XOR/XNOR gate function designed to support data transmission rates of up to 13 Gbps, and , to ground on-chip, and maybe either AC or DC coupled. The differential outputs of the HMC725LC3C HMC725LC3C , simultaneously measuring the jitter of a 300 mV, 13 GHz, 215 -1 PRBS input, and a single-ended output DC ... | Hittite Microwave Original |
8 pages, |
N4903A gate xnor xor logic table circuit xnor for 3 input xor gate N4903 6_ INPUT XOR GATE Applications of "XOR Gate" XNOR GATE XNOR GATE application HMC725LC3C TEXT |

Abstract: Input Frequency A simple circuit consisting of a comparator and an exclusive-OR gate is sufficient to double the frequency of a reference signal. The versatile phase-locked loop (PLL) allows multiplication of a reference frequency with an operating frequency that ranges from "DC to daylight." A PLL is overkill for some applications, however, especially if the input frequency needs only to be doubled. For , input of an exclusive-OR gate (XOR gate U2) as well as the input to a delay circuit. Consisting of R1 ... | Maxim Integrated Products Original |
3 pages, |
XOR Gates APP3327 comparator high fast& low delay time MAX9010 gate xor AN3327 IC of XOR GATE "XOR Gate" Frequency Doubler 30Mhz comparator using 2 xor gates Applications of "XOR Gate" TEXT |

Abstract: HMC725LC3C HMC725LC3C v02.1209 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The , Internally in 50 Ohms · RF ATE Applications 3 Features Propagation Delay: 105 ps Single Supply , HMC725LC3C HMC725LC3C is a XOR/XNOR gate function designed to support data transmission rates of up to 13 Gbps, and , to ground on-chip, and maybe either AC or DC coupled. The differential outputs of the HMC725LC3C HMC725LC3C , ] Deterministic jitter calculated by simultaneously measuring the jitter of a 300 mV, 13 GHz, 215 -1 PRBS input ... | Hittite Microwave Original |
8 pages, |
N4903A XNOR GATE XNOR GATE application HMC725LC3C TEXT |

Abstract: HMC725LC3C HMC725LC3C v02.1209 13 Gbps, FAST RISE TIME XOR / XNOR GATE Typical Applications The HMC725LC3C HMC725LC3C is ideal for: · RF ATE Applications Features Inputs Terminated Internally in 50 Ohms , function designed to support data transmission rates of up to 13 Gbps, and clock frequencies as high as 13 , either AC or DC coupled. The differential outputs of the HMC725LC3C HMC725LC3C may be either AC or DC coupled , [1] Deterministic jitter calculated by simultaneously measuring the jitter of a 300 mV, 13 GHz, 215 ... | Hittite Microwave Original |
8 pages, |
XNOR GATE application XNOR GATE Applications of "XOR Gate" HMC725LC3C TEXT |

Abstract: Typical Applications The HMC721LP3E HMC721LP3E is ideal for: Differential or Single-Ended Operation â¢ RF ATE Applications Fast Rise and Fall Times: 19 / 18 ps â¢ Broadband Test & Measurement Low Power , Description The HMC721LP3E HMC721LP3E is a XOR/XNOR gate function designed to support data transmission rates of up to , ] Deterministic jitter calculated by simultaneously measuring the jitter of a 300 mV, 13 GHz, 215 -1 PRBS input , peak reflow temperature of 235 Â°C [2] Max peak reflow temperature of 260 Â°C [3] 4-Digit lot number ... | Hittite Microwave Original |
8 pages, |
HMC721LP3E TEXT |

Abstract: Applications The HMC851LC3C HMC851LC3C is ideal for: HIGH SPEED LOGIC - SMT Inputs Terminated Internally in 50 Ohms â¢ RF ATE Applications 3 Features Differential & Singe-Ended Operation â¢ Broadband Test , transmission rates of up to 28 Gbps, and clock frequencies as high as 28 GHz. The HMC851LC3C HMC851LC3C also features an , DC coupled. The differential outputs of the HMC851LC3C HMC851LC3C may be either AC or DC coupled. Outputs can , ps [1] Deterministic jitter calculated by simultaneously measuring the jitter of a 300 mV, 28 Gbps ... | Hittite Microwave Original |
8 pages, |
HMC851LC3C TEXT |

Abstract: Features The HMC721LC3C HMC721LC3C is ideal for: HIGH SPEED LOGIC - SMT Typical Applications Inputs , ¢ RF ATE Applications Fast Rise and Fall Times: 19 / 18 ps â¢ Broadband Test & Measurement , rates of up to 14 Gbps, and clock frequencies as high as 14 GHz. All differential inputs to the , [1] Deterministic jitter calculated by simultaneously measuring the jitter of a 300 mV, 13 GHz, 215 , Rating MSL3 [1] Package Marking [2] H721 XXXX [1] Max peak reflow temperature of 260 Â°C [2 ... | Hittite Microwave Original |
8 pages, |
HMC721LC3C TEXT |

Abstract: Typical Applications The HMC721LC3C HMC721LC3C is ideal for: Differential & Singe-Ended Operation · Broadband , Inputs Terminated Internally in 50 Ohms · RF ATE Applications 3 Features Programmable , gate function designed to support data transmission rates of up to 13 Gbps, and clock frequencies as , Ohms to ground on-chip, and may be either AC or DC coupled. The differential outputs of the , measuring the jitter of a 300 mV, 13 GHz, 215 -1 PRBS input, and a single-ended output [1] [2] 3 tr ... | Hittite Microwave Original |
8 pages, |
N4903A XNOR GATE application HMC721LC3C TEXT |

Abstract | Saved from | Date Saved | File Size | Type | Download |

answer: This mode is intended for use in applications where there must be no DC component in the modes of operation.An important difference in bi-phase mode is that some active components must be used transmissions back into the correct data for reception. The following test circuit shows how the inclusion of are asserted on the Rx0 and Rx1 lines correctly while allowing bi-phase encoding of the CANL and CANH a 75% of Vdd reference for a recessive state to force the XOR gate to read logic 1 on both Tx0 and
/datasheets/files/motorola/cdcsic2/web/techhelp/faq/xfamily/biphase.htm |
Motorola | 08/03/1998 | 4.07 Kb | HTM | biphase.htm |

voltage, high voltage, AC and DC solutions for driving LED lighting applications. You may download the latest versions or look through our library of technical information including SPICE models and other the ON Semiconductor logo are registered trademarks of Semiconductor Components Industries, LLC. All other brand and product names appearing in this CD are registered trademarks or trademarks of
/datasheets/files/on-semiconductor/html/ds/13_datamanagement.html |
On Semiconductor | 28/08/2008 | 23.04 Kb | HTML | 13_datamanagement.html |

devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I off . The I off circuitry disables patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to V CC or GND. The three inputs (A, B and C) are capable of -40 Cel to +125 Cel. Applications PicoGate Logic footprints 2002-10-30
/datasheets/files/philips/pip/74lvc1g58_1.html |
Philips | 06/06/2005 | 4.79 Kb | HTML | 74lvc1g58_1.html |

high degree of flexibility for partitioning state machines and dual-phase clock applications, allowing MACH ® 4 Family High-Performance CPLDs With Maximum Ease of Use Maximum Ease of Use CPLD solution of easy-to-use silicon products and software tools. The overall benefits for users are a and manufacturing. The MACH 4 CPLDs are members of Vantis' high-performance 0.35-micron process and Switch Matrices for Highest Flexibility The MACH 4 products consist of multiple PAL ® blocks
/datasheets/files/vantis/docs/wcd00000/wcd00052.htm |
Vantis | 11/12/1997 | 10.75 Kb | HTM | wcd00052.htm |

voltage, high voltage, AC and DC solutions for driving LED lighting applications. You may download the latest versions or look through our library of technical information including SPICE models and other logo are registered trademarks of Semiconductor Components Industries, LLC. All other brand and product names appearing in this CD are registered trademarks or trademarks of their respective holders.
/datasheets/files/on-semiconductor/html/ds/07_multiplexers.html |
On Semiconductor | 27/08/2008 | 16.74 Kb | HTML | 07_multiplexers.html |

No abstract text available
/download/57335126-39502ZC/fitter.zip () |
Atmel | 13/01/1998 | 680.39 Kb | ZIP | fitter.zip |

No abstract text available
/download/78359419-847892ZC/bwg10src.zip () |
STMicroelectronics | 16/12/1998 | 15.66 Kb | ZIP | bwg10src.zip |

SY55851U SY55851U is a highly flexible, universal logic gate capable of upto 2.5GHz operation. Its differential inputs and outputs will produce any of 9 possible logic functions of two Boolean variables. It can be configured as any of the following gates: AND, NAND, OR, NOR, XOR, XNOR, DELAY, NEGATION (NOT). Also, the resistor between the true and the complement pins of a given input. The SY55851U SY55851U is a member of Micrel's new Super-Lite™ family of high-speed logic devices. This family features very small packaging
/datasheets/files/micrel/products/products/sy55851u.shtml |
Micrel | 26/06/2002 | 4.98 Kb | SHTML | sy55851u.shtml |

the device's flexibility for various applications. The asynchronous enable input, A_Start, when Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. of -4.2V to -5.5V Synchronous and asynchronous enable pins
/datasheets/files/micrel/products/products/sy10-100e137.html |
Micrel | 26/06/2002 | 7.98 Kb | HTML | sy10-100e137.html |

Recommended Design Methods (8 pages, updated Sep 16 1997) Described here are a series of guidelines for reconfigured to perform different applications in a system. Modeling Device Power the active and static power consumption of a AT6005 AT6005 design. Using Bit-Serial implementation of a FIR (Finite-Impulse Response) Filter with variable coefficients that fits in a single AT6002 AT6002 Application Note we present a reference design of a fully pipelined bit-parallel edge detection circuit that
/datasheets/files/atmel/atmel/prod100.htm |
Atmel | 14/09/1998 | 22.08 Kb | HTM | prod100.htm |