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1 - 50 of about 534 for Apex II |
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First line: Signal Processing Megafunctions Signal Processing Solutions System-on-a Programmable-Chip Designs Signal Processing Proven Abstract: .. Color Space Converter PLSM-CSC Altera Corporation APEX, APEX II, FLEX®, ACEXTM, MercuryTM. FIR Filter Compiler PLSM-FIR Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury. Numerically .. datasheet abstract.. |
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First line: Configuring SRAM-Based Devices Application Note June ver. Introduction APEX APEX Mercury ACEX Abstract: .. or universal serial bus USB hardware interface to download configuration data to APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, and FLEX 6000 devices. It supports operation with V. CC. at 5.0 V, 3 .. datasheet abstract.. |
667.82 Kb |
102 Pages 
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First line: Configuring SRAM-Based Devices Application Note February ver. Introduction APEX APEX Mercury ACEX Abstract: .. Introduction APEXTM II, APEX 20K, MercuryTM, ACEXTM 1K, FLEX® 10K, and FLEX 6000 devices can be configured using one of six configuration schemes. All configuration schemes use either a microprocessor .. datasheet abstract.. |
649.57 Kb |
101 Pages
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First line: Transitioning APEX Designs Stratix Stratix Devices S52012-3.0 Introduction Stratix Stratix devices Alteras Abstract: .. Stratix GX devices and provides assistance when transitioning designs from APEXTM II or APEX 20K devices to the Stratix or Stratix GX architecture. Designers using this chapter should be familiar .. datasheet abstract.. |
253.26 Kb |
32 Pages |
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First line: APEX Complete Solution April Altera introduces APEX device family highperformance high-bandwidth programmable Abstract: .. APEX II. Advanced High-Performance LVDS. 36 1-Gbps True-LVDS input and 36 1-Gbps True-LVDS. output channels. Up to 88 624-Mbps Flexible-LVDSTM input channels. and 88 624-Mbps Flexible-LVDS output .. datasheet abstract.. |
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First line: APEX Programmable Logic Device Family Data Sheet August ver. Features.. Programmable logic Abstract: .. APEX II. Programmable Logic Device Family. August 2002, ver. 3.0 Data Sheet. DS-APEXII-3.0. Features.. ■ Programmable logic device PLD manufactured using a 0.15-μm all- layer copper-metal .. datasheet abstract.. |
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99 Pages 
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First line: APEX Programmable Logic Device Family Data Sheet December ver. Features.. Programmable logic Abstract: .. APEX II. Programmable Logic Device Family. December 2001, ver. 1.3 Data Sheet. A-DS-APEXII-1.3. Features.. . Programmable logic device PLD manufactured using a 0.15-. μ. m all-. layer copper-metal .. datasheet abstract.. |
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96 Pages
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First line: APEX Programmable Logic Device Family Data Sheet ver. Features.. Preliminary Information Programmable Abstract: .. APEX II. Programmable Logic Device Family. May 2001, ver. 1.1 Data Sheet. A-DS-APEXII-1.1. Features.. . Programmable logic device PLD manufactured using a 0.15-. μ. m all-. layer copper-metal fabrication .. datasheet abstract.. |
648.01 Kb |
96 Pages
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First line: Using High-Speed Standards APEX Devices Application Note ver. Introduction Recent expansion telecommunications Abstract: .. ®. Altera Corporation 1. Using High-Speed I/O Standards in APEX II Devices. May 2003, ver. 1.8 Application Note 166. AN-166-1.8. Introduction Recent expansion in the telecommunications market and .. datasheet abstract.. |
288.8 Kb |
36 Pages
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First line: SignalTap Embedded Logic Analyzer Megafunction Data Sheet April ver. Features Provided with Abstract: .. II and APEX 20K devices including. APEX 20K, APEX 20KE, and APEX 20KC devices . Provides non-intrusive probing of ball-grid array BGA pins. . Logic analyzer controls available within the Quartus .. datasheet abstract.. |
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First line: Megafunctions Selector Guide System-on-a-Programmable-Chip Solutions June Contents Introduction Altera Megafunctions Digital Signal Abstract: .. Risk-Free OpenCore Evaluation The MAX+PLUS® II and QuartusTM software from Altera provide .. are optimized for the memory structure of the FLEX 10K and APEX device families. Digital Signal .. datasheet abstract.. |
557.59 Kb |
12 Pages
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First line: Description Architecture Features H51007-2.2 Introduction HardCopy APEX devices extend flexibility high-density FPGAs Abstract: .. requires the Quartus® II software-generated output files from a fully functional APEX 20KE or APEX 20KC device. Altera performs the migration and delivers functional prototypes in as few as .. datasheet abstract.. |
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First line: Intellectual Property Selector Guide Building Blocks System-on-a-ProgrammableChip Solutions March Contents Introduction Altera Abstract: .. APEX 20K, FLEX 10K, FLEX 8000, MAX 9000, MAX 7000 APEX 20K, FLEX 10K APEX 20K APEX 20K APEX 20K APEX .. the SignalTap® embedded logic analyzer available with the QuartusTM II development software .. datasheet abstract.. |
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16 Pages
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First line: Configuration Devices SRAM-Based Devices Data Sheet December ver. Features Serial device family Abstract: .. Features ■ Serial device family for configuring APEXTM II, APEX 20K including APEX 20K, APEX 20KC, and APEX 20KE , MercuryTM, ACEX® 1K, and FLEX® FLEX 6000, FLEX 10KE, and FLEX 10KA devices .. datasheet abstract.. |
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36 Pages
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First line: Configuration Devices SRAM-Based Devices Data Sheet February ver. Features Serial device family Abstract: .. Features ■ Serial device family for configuring APEXTM II, APEX 20K including APEX 20K, APEX 20KC, and APEX 20KE , MercuryTM, ACEX® 1K, and FLEX® FLEX 6000, FLEX 10KE, and FLEX 10KA devices .. datasheet abstract.. |
281.61 Kb |
36 Pages
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First line: Configuring APEX Devices CF51004-2.1 Introduction APEX devices configured using four configuration schemes. Abstract: .. 6. Configuring APEX II Devices. Introduction APEXTM II devices can be configured using one of four configuration schemes. All configuration schemes use either a microprocessor or configuration .. datasheet abstract.. |
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68 Pages
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First line: Introduction HardCopy APEX Devices H51006-2.2 Introduction HardCopy APEX devices enable high-density APEX Abstract: .. to providing a few Quartus® II software-generated output files. Features.. HardCopy APEX devices are manufactured using an 0.18-μm CMOS six-layer-metal process technology: ■ Preserves .. datasheet abstract.. |
64.65 Kb |
6 Pages
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First line: Configuring Altera FPGAs CF51001-2.1 Introduction Stratix series Cyclone series APEX APEX including Abstract: .. Introduction Stratix® series, CycloneTM series, APEXTM II, APEX 20K including APEX 20KE and APEX 20KC , MercuryTM, ACEX® 1K, FLEX® 10K including FLEX 10KE and FLEX 10KA , and FLEX 6000 devices .. datasheet abstract.. |
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First line: Using Flexible-LVDS Pins APEX Devices Application Note August ver. Introduction Recent expansion Abstract: .. Using Flexible-LVDS I/O Pins in APEX II Devices. August 2002, ver. 1.1 Application Note 167. AN-167-1.1. Introduction Recent expansion in the telecommunications market and growth in Internet .. datasheet abstract.. |
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14 Pages
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First line: Section Design Considerations This section provides documentation some functions offered Altera Stratix Abstract: .. ■ Chapter 10, Transitioning APEX Designs to Stratix & Stratix GX Devices. Revision History The .. You can find more information on XAUI support in Section II, Stratix GX Transceiver User Guide .. datasheet abstract.. |
461.93 Kb |
74 Pages
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First line: Second Quarter News Views Newsletter Altera Customers Altera Provides Complete Solution with Abstract: .. Altera Provides the Complete I/O Solution with the New APEX II Device Family. Views Views. News News. Altera introduces the APEXTM II device family— flexible, high-performance, high-density .. datasheet abstract.. |
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42 Pages |
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First line: Designing with ESBs APEX Devices March ver. Application Note Introduction APEX devices Abstract: .. Additionally, in APEX II devices, ESBs support bidirectional dual-port RAM. In this mode, each ESB has two ports that allow two different read or write operations simultaneously. In APEX II .. datasheet abstract.. |
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59 Pages
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First line: GRAPHICS PROCESSOR BACKPLANE LVDS Mbits / s SSTL -2 / 3 LVTTL HSTL LVTTL SDRAM MEMORY Abstract: .. Stub-Series Terminated Logic, 2.5 V SSTL-2 Class I, II. Stub-Series Terminated Logic, 3.3 .. APEX devices provide flexible support for emerging I/O standards with bandwidth of up to 622 .. datasheet abstract.. |
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First line: SRAM Controller Reference Design APEX Devices December ver. Application Note Introduction communication Abstract: .. ZBT SRAM Controller Reference Design for APEX II Devices. 2 Altera Corporation. AN 183: ZBT SRAM Controller Reference Design for APEX II Devices. ZBT SRAM is available with a pipelined or flow-through .. datasheet abstract.. |
162.92 Kb |
14 Pages
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First line: MasterBlaster Serial / USB Communications Cable Data Sheet April ver. Features Supports SignalTap embedded Abstract: .. This cable downloads configuration data to APEX II, APEX 20K including APEX 20K, APEX 20KE, and APEX 20KC , FLEX 10K including FLEX 10KA and FLEX 10KE , FLEX 8000, and FLEX 6000 devices, as .. datasheet abstract.. |
138.7 Kb |
8 Pages
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First line: Comparison APEX 20KE Virtex-E Devices Technical Brief December ver. Introduction Content-addressable memory Abstract: .. Now, by using APEX 20KE CAM, engineers can take advantage of the flexibility and simple design .. the Synopsys FPGA Compiler II version 3.3 software and transferred to the Xilinx Alliance .. datasheet abstract.. |
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4 Pages
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First line: LVDS Signaling Using APEX Device Pins Application Note ver. Introduction Density increases Abstract: .. This application note describes how to utilize APEX 20KE and APEX 20KC general purpose I/O pins .. QuartusTM II software implementation. LVDS Characteristics. Figures 1 and 2 show a typical LVDS .. datasheet abstract.. |
194.27 Kb |
15 Pages
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First line: Configuring APEX 20KE APEX 20KC Devices CF51005-2.2 Introduction APEX 20KE APEX 20KC Abstract: .. 7. Configuring APEX 20KE & APEX 20KC Devices. Introduction APEXTM 20KE and APEX 20KC devices can .. of the Quartus® II or MAX+PLUS® II software, all designs targeted for the same device will have .. datasheet abstract.. |
482.72 Kb |
70 Pages
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First line: APEX Devices November Version Errata Sheet Clock Data Synchronization Automatic clock-data synchronization Abstract: .. APEX II Devices. Clock Data Synchronization Automatic clock-data synchronization CDS was offered as a feature in APEXTM II devices. CDS uses a training pattern to synchronize between. clock .. datasheet abstract.. |
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First line: RELEASED ERRATA PMC-1991770 ISSUE PM7326 S / UNI-APEX ATM / PACKET TRAFFIC MANGER SWITCH PM7326 S / UNI Abstract: .. CUSTOMERS’ INTERNAL USE ii. This page left blank intentionally. RELEASED PM7326 S/UNI-APEX .. PMC-981224, PM7326 S/UNI-APEX ATM/Packet Traffic Manager and Switch Data Sheet, Issue 6 .. datasheet abstract.. |
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First line: Apex-ICE Emulator Hardware Installation Guide Notice Analog Devices reserves right make changes Abstract: .. The Apex-ICE hardware is warranted against defects in materials and workmanship for a period .. ii. Contents. 1. INTRODUCTION .. datasheet abstract.. |
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22 Pages
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First line: Using Selectable Standards APEX 20KE APEX 20KC 7000B Devices Application Note December Abstract: .. Altera’s revolutionary APEXTM 20KE and APEX 20KC devices offer the highest density, highest .. A future version of the Quartus II software will include the ability to choose PCI-X as an I/O .. datasheet abstract.. |
989.37 Kb |
32 Pages
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First line: Configuring APEX FLEX FLEX Devices Application Note December ver. Introduction APEX FLEX Abstract: .. or universal serial bus USB hardware interface that downloads configuration data to APEX .. II software versions 9.3. and higher. For more information on the MasterBlaster cable, see the .. datasheet abstract.. |
697.79 Kb |
72 Pages
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First line: Using Selectable Standards APEX 20KE APEX 20KC 7000B Devices Application Note October Abstract: .. Altera’s revolutionary APEXTM 20KE and APEX 20KC devices offer the highest density, highest .. A future version of the Quartus II software will include the ability to choose PCI-X as an I/O .. datasheet abstract.. |
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31 Pages
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First line: Increasing System Bandwidth with Application Note June ver. Introduction system speeds have Abstract: .. The look-up table LUT -based APEX. TM. II device family incorporates CDS. circuitry in its differential I/O circuitry. These devices offer four banks of high-speed differential I/O pins: two .. datasheet abstract.. |
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10 Pages
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First line: Power Analysis Quartus Development Tool Technical Brief January ver. Introduction Quartus development Abstract: .. The APEX power analyzer found within the Quartus II development tool provides an I. CC. estimate based on typical device operating conditions. The feature estimates the power consumption in the .. datasheet abstract.. |
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First line: ByteBlasterMV Parallel Port Download Cable Data Sheet July Version Features Allows users Abstract: .. , MAX 7000B, and MAX 3000A devices in-system via a standard parallel port ‐ Configure APEX. TM. II, APEX 20K including APEX 20K, APEX 20KE, and APEX 20KC , ACEX 1K, Mercury. TM. , FLEX. ®. 10K including .. datasheet abstract.. |
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12 Pages
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First line: APEX 20KC Programmable Logic Device Data Sheet February ver. Features.. Programmable logic Abstract: .. Note to Table 2: 1 APEX 20KC devices can be 5.0-V tolerant by using an external resistor. Table .. – Software design support and automatic place-and-route provided by the Altera® QuartusTM II .. datasheet abstract.. |
524.79 Kb |
90 Pages
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First line: APEX 20KC Programmable Logic Device Data Sheet April ver. Features.. Preliminary Information Abstract: .. ‐ Pin-compatible with APEX 20KE devices ‐ High-performance, low-power copper interconnect .. II development system for. Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 .. datasheet abstract.. |
838.3 Kb |
90 Pages
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First line: Section Design Guidelines This section provides information design transition board design guidelines Abstract: .. ■ Chapter 3, Transitioning APEX Designs to Stratix & Stratix GX Devices. ■ Chapter 4, Stratix GX .. ■ Chapter 5, Quartus II Software Fitter Warnings. Revision History The table below shows the .. datasheet abstract.. |
2361.59 Kb |
128 Pages
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First line: APEX 20KC Programmable Logic Device Data Sheet April ver. Features.. Programmable logic Abstract: .. Note to Table 2: 1 APEX 20KC devices can be 5.0-V tolerant by using an external resistor. Table .. – Software design support and automatic place-and-route provided by the Altera® QuartusTM II .. datasheet abstract.. |
450.91 Kb |
87 Pages
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First line: APEX 20KC Programmable Logic Device Data Sheet October ver. Features.. Preliminary Information Abstract: .. ‐ Pin-compatible with APEX 20KE devices ‐ High-performance, low-power copper interconnect .. II development system for. Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 .. datasheet abstract.. |
634.93 Kb |
88 Pages
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First line: APEX 20KC Programmable Logic Device Data Sheet February ver. Features.. Programmable logic Abstract: .. – Software design support and automatic place-and-route provided by the Altera® QuartusTM II .. megafunctions optimized for APEX 20KC architecture available – NativeLink TM integration .. datasheet abstract.. |
564.98 Kb |
86 Pages
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First line: Nios Embedded Processor Development Board March ver. Data Sheet Introduction Development Board Abstract: .. APEX device: 1. A JTAG connection JP3 that can be used with Quartus II software via a ByteBlaster or MasterBlaster programming cable. 2. A configuration controller U4 that configures the .. datasheet abstract.. |
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First line: Using ClockLock ClockBoost Features APEX Devices Application Note April ver. Introduction APEX Abstract: .. APEX 20K devices have one PLL that features ClockLock and ClockBoost circuitry. This PLL can be .. specification in the Quartus II software ClockBoost clock multiplication factor equals 1 .. datasheet abstract.. |
397.62 Kb |
56 Pages
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First line: Using ClockLock ClockBoost Features APEX Devices Application Note October ver. Introduction APEX Abstract: .. APEX 20K devices have one PLL that features ClockLock and ClockBoost circuitry. This PLL can be .. specification in the Quartus II software ClockBoost clock multiplication factor equals 1 .. datasheet abstract.. |
368.84 Kb |
56 Pages
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First line: Using Flash Memory Configure FPGAs CF52010-2.2 Introduction Altera introduces higher-density FPGAs configuration Abstract: .. APEX II, APEX 20K, ACEX 1K, Mercury, FLEX 10K, or FLEX 6000 Device. nSTATUS. INIT_DONE. CONF_DONE. DCLK. DATA0. nCONFIG. GND. GND. MSEL0 1 MSEL1 1 nCE. MSEL0 1 MSEL1 1 nCE. RESTART nCEO. GND. VCC. VCC. VCC .. datasheet abstract.. |
150.63 Kb |
14 Pages
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First line: Configuring Mixed Altera FPGA Chains CF52008-2.2 Introduction mixture Stratix series Cyclone series Abstract: .. Introduction A mixture of Stratix® series, Cyclone® series, APEXTM II, MercuryTM, APEX 20K, ACEX® 1K and FLEX® 10K devices can be configured in the same configuration chain, provided that all .. datasheet abstract.. |
53.02 Kb |
4 Pages
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First line: APEX Programmable Logic Device Family Data Sheet January ver. Features.. Preliminary Information Abstract: .. of MegaCore and AMPP functions make the APEX 20K architecture uniquely suited for system-on-a .. LVPECL data pins up to 156 Mbps in all devices HSTL Class I PCI-X SSTL-2 Class I and II SSTL-3 .. datasheet abstract.. |
598.64 Kb |
92 Pages
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First line: Configuration Devices ACEX APEX FLEX Mercury Devices Data Sheet March ver. Features Abstract: .. with the Altera® QuartusTM and MAX+PLUS® II development systems for Windows-based PCs as. well .. a JTAG instruction to initiate APEX, FLEX, or Mercury device configuration – Can be programmed .. datasheet abstract.. |
198.57 Kb |
28 Pages
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