Am79C940 10BASE-T 10BASE2 10BASE5 10BASE-F C16235D-1 AM79C940 PQR100 PQT080 - Datasheet Archive

 

Am79C940 Media Access Controller for Ethernet (MACETM) DISTINCTIVE CHARACTERISTICS s Integrated Controller with Manchester

 

FINAL Am79C940 Am79C940 Media Access Controller for Ethernet (MACETM) DISTINCTIVE CHARACTERISTICS s Integrated Controller with Manchester encoder/decoder and 10BASE-T 10BASE-T transceiver and AUI port s Arbitrary byte alignment and little/big endian memory interface supported s Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards s External Address Detection Interface (EADI) for external hardware address filtering in bridge/router applications s 84-pin PLCC and 100-pin PQFP Packages s Internal/external loopback capabilities s 80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA s JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test s Modular architecture allows easy tuning to specific applications s Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI) s High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer s Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: s Integrated Manchester Encoder/Decoder s Supports the following types of network interface: - AUI to external 10BASE2 10BASE2, 10BASE5 10BASE5 or 10BASE-F 10BASE-F MAU - Automatic retransmission with no FIFO reload - DAI port to external 10BASE2 10BASE2, 10BASE5 10BASE5, 10BASE-T 10BASE-T, 10BASE-F 10BASE-F MAU - Automatic receive stripping and transmit padding (individually programmable) - General Purpose Serial Interface (GPSI) to external encoding/decoding scheme - Automatic runt packet rejection - Internal 10BASE-T 10BASE-T transceiver with automatic selection of 10BASE-T 10BASE-T or AUI port - Automatic deletion of collision frames - Automatic retransmission with no FIFO reload s Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs s Direct FIFO read/write access for simple interface to DMA controllers or l/O processors s Sleep mode allows reduced power consumption for critical battery powered applications s 5 MHz-25 MHz system clock speed s Support for operation in industrial temperature range (­40°C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specifically designed to address applications where multiple I/O peripherals are present, and a centralized or system specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an external DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architecture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 The MACE device provides a complete Ethernet node solution with an integrated 10BASE-T 10BASE-T transceiver, and supports up to 25-MHz system clocks. The MACE device embodies the Media Access Control (MAC) and Physical Signaling (PLS) sub-layers of the IEEE 802.3 standard, and provides an IEEE defined Attachment Unit Interface (AUI) for coupling to an external Medium Attachment Unit (MAU). The MACE device is compliant with 10BASE2 10BASE2, 10BASE5 10BASE5, 10BASE-T 10BASE-T, and 10BASE-F 10BASE-F transceivers. Additional features also enhance over-all system design. The individual transmit and receive FIFOs optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the General Purpose Serial Interface (GPSI) allows direct access to/from the MAC. In addition, the Digital Attachment Interface (DAI), which is a simplified electrical attachment specification, allows implementation of MAUs that do not require DC isolation between the MAU and DTE. The DAI port can also be used to indicate transmit, receive, or collision status by connecting LEDs to the port. The MACE device also provides an External Address Detection Interface (EADI) to allow external hardware address filtering in internet working applications. 2 The Am79C940 Am79C940 MACE chip is offered in a Plastic Leadless Chip Carrier (84-pin PLCC), a Plastic Quad Flat Package (100-pin PQFP), and a Thin Quad Flat Package (TQFP 80-pin). There are several small functional and physical differences between the 80-pin TQFP and the 84-pin PLCC and 100-pin PQFP configurations. Because of the smaller number of pins in the TQFP configuration versus the PLCC configuration, four pins are not bonded out. Though the die is identical in all three package configurations, the removal of these four pins does cause some functionality differences between the TQFP and the PLCC and PQFP configurations. Depending on the application, the removal of these pins will or will not have an effect. (See section: "Pins Removed for TQFP Package and Their Effects.) With the rise of embedded networking applications operating in harsh environments where temperatures may exceed the normal commercial temperature (0°C to +70°C) window, an industrial temperature (-40°C to +85°C) version is available in all three packages; 84pin PLCC, 100-pin PQFP and 80-pin TQFP. The industrial temperature version of the MACE Ethernet controller is characterized across the industrial temperature range (-40° C to +85°C) within the published power supply specification (4.75 V to 5.25 V; i.e., ±5% VCC). Thus, conformance of MACE performance over this temperature range is guaranteed by the design and characterization monitor. Am79C940 Am79C940 BLOCK DIAGRAM XTAL1 XTAL2 DXCVR CLSN EADI Port Control DBUS 15­0 ADD 4­0 R/W CS FDS DTV EOF RDTREQ TDTREQ BE 1­0 INTR SCLK EDSEL TC SLEEP RESET RCV FIFO XMT FIFO 802.3 MAC Core AUI Port SRDCLK SRD SF/BD EAM/R EADI Port DO± DI± CI± AUI 10BASE-T 10BASE-T FIFO Control 10BASE-T 10BASE-T MAU Command & Status Registers DAI Port TXDAT± TXEN RXDAT RXCRS DAI Port GPSI Port Bus Interface Unit TXD± TXP± RXD LNKST RXPOL STDCLK TXDAT+ TXEN SRDCLK RXDAT RXCRS CLSN GPSI JTAG PORT CNTRL TDI TCK C16235D-1 C16235D-1 TDO TMS Notes: 1. Only one of the network ports AUI, 10BASE-T 10BASE-T, DAI port or GPSI can be active at any time. Some shared signals are active regardless of which network port is active, and some are reconfigured. 2. The EADI port is active at all times. Am79C940 Am79C940 3 TABLE OF CONTENTS AM79C940 AM79C940 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 CONNECTION DIAGRAMS PL 084 PLCC PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 CONNECTION DIAGRAMS PQR100 PQR100 PQFP PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 CONNECTION DIAGRAMS PQT080 PQT080 TQFP PACKAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PIN/PACKAGE SUMMARY (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CI+/CI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DI+/DI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DO+/DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Digital Attachment Interface (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 TXDAT+/TXDAT­. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 TXEN/TXEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Transmit Enable (Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 RXDAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 RXCRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 DXCVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 10BASE-T 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 TXD+, TXD­ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 TXP+, TXP­. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 RXD+, RXD­ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 LNKST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 RXPOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 STDCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 CLSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 SF/BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 SRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 EAM/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 SRDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 HOST SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 DBUS15-0 DBUS15-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 ADD4-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RDTREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 TDTREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 FDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 DTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 EOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 BE1­0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 EDSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 IEEE 1149.1 TEST ACCESS PORT (TAP) INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4 Am79C940 Am79C940 TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 GENERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 DVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PIN FUNCTIONS NOT AVAILABLE WITH THE 80-PIN 80-PIN TQFP PACKAGE . . . . . . . . . . . . . . . . . .28 PINS REMOVED FOR TQFP PACKAGE AND THEIR EFFECTS . . . . . . . . . . . . . . . . . . . . . . . . . . .28 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Block Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 BIU to FIFO Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Byte Alignment For FIFO Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 BIU to Control and Status Register Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 FIFO Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Digital Attachment Interface (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 10BASE-T 10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Internal/External Address Recognition Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 IEEE 1149.1 Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 SLAVE ACCESS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 TRANSMIT OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Transmit FIFO Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Transmit Status Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 RECEIVE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Receive FIFO Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Am79C940 Am79C940 5 Receive Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 LOOPBACK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 8-Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Programmer's Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Missing Table Title? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 SYSTEM APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Host System Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 MACE Compatible AUI Isolation Transformers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 MANUFACTURER CONTACT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 DC CHARACTERISTICS (UNLESS OTHERWISE NOTED, PARAMETRIC VALUES ARE THE SAME BETWEEN COMMERCIAL DEVICES AND INDUSTRIAL DEVICES.) . . . . . . . . . . . . . . . . . . . . . . .90 AC CHARACTERISTICS (UNLESS OTHERWISE NOTED, PARAMETRIC VALUES ARE THE SAME BETWEEN COMMERCIAL DEVICES AND INDUSTRIAL DEVICES.) . . . . . . . . . . . . . . . . . . . . . . .93 KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 PL 084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 84-Pin Plastic Leaded Chip Carrier (measured in inches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 PQR100 PQR100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 100-Pin Plastic Quad Flat Pack; Trimmed and Formed (measured in millimeters) . . . . . . . . . . . 118 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 PQR100 PQR100 100-Pin Plastic Quad Flat Pack with Molded Carrier Ring (measured in millimeters) . 119 PHYSICAL DIMENSIONS* PQT080 PQT080 80-Pin Thin Quad Flat Package (measured in millimeters)120 LOGICAL ADDRESS FILTERING FOR ETHERNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 BSDL DESCRIPTION OF AM79C940 AM79C940 MACE JTAG STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . .123 AM79C940 AM79C940 MACE REV C0 SILICON ERRATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 6 Am79C940 Am79C940 RXCRS RXDAT CLSN TXEN/ TXEN STDCLK DVSS TXDATTXDAT+ DVSS EDSEL DXCVR DVDD AVDD CI+ CIDI+ DIAVDD DO+ DOAV SS CONNECTION DIAGRAMS PL 084 PLCC PACKAGE 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 Am79C940JC Am79C940JC 65 21 MACE 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 XTAL2 AVSS XTAL1 AVDD TXD+ TXP+ TXDTXPAVDD RXD+ RXDDVDD TDI DVSS TCK TMS TDO LNKST RXPOL CS R/ W DBUS10 DBUS10 DBUS11 DBUS11 DBUS12 DBUS12 DBUS13 DBUS13 DV DD DBUS14 DBUS14 DBUS15 DBUS15 DV SS EOF DTV FDS BE0 BE1 SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 SRDCLK EAM/R SRD SF/BD RESET SLEEP DVDD INTR TC DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 16235D-2 16235D-2 Am79C940 Am79C940 7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 RXCRS RXDAT CLSN TXEN/TXEN STDCLK DVSS TXDATTXDAT+ DVSS EDSEL DXCVR DVDD AVDD CI+ CIDI+ DIAVDD DO+ DO- CONNECTION DIAGRAMS PQR100 PQR100 PQFP PACKAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MACE Am79C940KC Am79C940KC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC AVSS NC NC NC XTAL2 AVSS XTAL1 AVDD TXD+ TXP+ TXD TXP AVDD RXD+ RXD DVDD TDI DVSS TCK TMS TDO LNKST RXPOL CS R/W NC NC NC NC DBUS11 DBUS11 DBUS12 DBUS12 DBUS13 DBUS13 DVDD DBUS14 DBUS14 DBUS15 DBUS15 DVSS EOF DTV FDS BE0 BE1 SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC NC SRDCLK EAM/R SRD SF/BD RESET SLEEP DVDD INTR TC DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 NC NC NC DBUS10 DBUS10 NC 16235D-3 16235D-3 8 Am79C940 Am79C940 EDSEL DXCVR DVDD AVDD CI+ CIDI+ DIAVDD DO+ DOAVSS RXCRS RXDAT CLSN TXEN/ STDCLK DVSS TXDAT+ DVSS CONNECTION DIAGRAMS PQT080 PQT080 TQFP PACKAGE 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SRDCLK EAM/R SF/BD RESET SLEEP DVDD INTR TC DBUS0 DV SS DBUS1 DBUS2 DBUS3 DBUS4 DV SS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 1 2 3 4 5 6 60 59 58 57 56 55 7 8 9 10 11 12 13 14 15 16 17 18 19 20 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MACE Am79C940VC Am79C940VC XTAL2 AVSS XTAL1 AVDD TXD+ TXP+ TXDTXPAVDD RXD+ RXDDVDD TDI DVSS TCK TMS TD0 LNKST CS R/W DBUS10 DBUS10 DBUS11 DBUS11 DBUS12 DBUS12 DBUS13 DBUS13 DVDD DBUS14 DBUS14 DBUS15 DBUS15 DV SS EOF FDS BE0 BE1 SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 16235D-4 16235D-4 Notes: Four pin functions available on the PLCC and PQFP packages are not available with the TQFP package. (See full data sheet for description of pins not included with the 80-pin TQFP package. In particular, see section "Pin Functions not available with the 80-pin TQFP package.") Am79C940 Am79C940 9 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C940 AM79C940 V C \W ALTERNATE PACKAGING OPTION \W = Trimmed and Formed in a Tray OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0° to +70°C) I = Industrial (-40°C to +85°C) PACKAGE TYPE (per Prod. Nomenclature/16-038) J = 84-Pin Plastic Leaded Chip Carrier (PL 084) K = 100-Pin Plastic Quad Flat Pack (PQR100 PQR100) V = 80-Pin Thin Quad Flat Package (PQT080 PQT080) SPEED Not Applicable DEVICE NUMBER/DESCRIPTION (include revision letter) Am79C940 Am79C940 Media Access Controller for Ethernet Valid Combinations Valid Combinations AM79C940 AM79C940 JC, KC, KC\W, VC, VC\W AM79C940 AM79C940 The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. JI, KI, KI\W, VI, VI\W Note: Currently the silicon revision level of the MACE Ethernet controller is revision C0. This is designated by the marking on the package as Am79C940Bxx Am79C940Bxx, where "xx" indicate package type and temperature range. 10 Am79C940 Am79C940 PIN/PACKAGE SUMMARY (PLCC) PLCC Pin # Pin Name 1 DXCVR Disable Transceiver 2 EDSEL Edge Select 3 DVSS 4 TXDAT+ 5 TXDAT­ 6 DVSS 7 STDCLK 8 TXEN/TXEN 9 CLSN 10 RXDAT Pin Function Digital Ground Transmit Data + Transmit Data ­ Digital Ground Serial Transmit Data Clock Transmit Enable Collision Receive Data 11 RXCRS Receive Carrier Sense 12 SRDCLK Serial Receive Data Clock 13 EAM/R 14 SRD External Address Match/Reject Serial Receive Data 15 SF/BD Start Frame/Byte Delimiter 16 RESET Reset 17 SLEEP Sleep Mode 18 DVDD Digital Power 19 INTR Interrupt 20 TC 21 DBUS0 22 DVSS 23 DBUS1 Data Bus1 24 DBUS2 Data Bus2 25 DBUS3 Data Bus3 26 DBUS4 Data Bus4 Timing Control Data Bus0 Digital Ground Digital Ground 27 DVSS 28 DBUS5 Data Bus5 29 DBUS6 Data Bus6 30 DBUS7 Data Bus7 31 DBUS8 Data Bus8 32 DBUS9 Data Bus9 33 DBUS10 DBUS10 Data Bus10 34 DBUS11 DBUS11 Data Bus11 35 DBUS12 DBUS12 Data Bus12 36 DBUS13 DBUS13 Data Bus13 Digital Power 37 DVDD 38 DBUS14 DBUS14 Data Bus14 39 DBUS15 DBUS15 Data Bus15 40 DVSS Digital Ground 41 EOF End Of Frame 42 DTV Data Transfer Valid 43 FDS FIFO Data Strobe 44 BE0 Byte Enable0 Am79C940 Am79C940 11 PIN/PACKAGE SUMMARY (continued) PLCC Pin # Pin Name Pin Function 45 BE1 Byte Enable 1 46 SCLK System Clock 47 TDTREQ Transmit Data Transfer Request 48 RDTREQ Receive Data Transfer Request 49 ADD0 Address0 50 ADD1 Address1 51 ADD2 Address2 52 ADD3 Address3 53 ADD4 Address4 54 R/W Read/Write 55 CS Chip Select 56 RXPOL Receive Polarity 57 LNKST Link Status 58 TDO Test Data Out 59 TMS Test Mode Select 60 TCK Test Clock 61 DVSS Digital Ground 62 TDI Test Data Input 63 DVDD Digital Power 64 RXD­ Receive Data­ 65 RXD+ Receive Data+ 66 AVDD Analog Power 67 TXP­ Transmit Pre-distortion 68 TXD­ Transmit Data­ 69 TXP+ Transmit Pre-distortion+ 70 TXD+ Transmit Data+ 71 AVDD Analog Power 72 XTAL1 Crystal Output 73 AVSS Analog Ground 74 XTAL2 Crystal Output 75 AVSS Analog Ground 76 DO­ Data Out­ 77 DO+ Data Out+ 78 AVDD Analog Power 79 DI­ Data In­ 80 DI+ Data In+ 81 CI­ Control In­ 82 CI+ Control In+ 83 12 AVDD Analog Power 84 DVDD Digital Power Am79C940 Am79C940 PIN/PACKAGE SUMMARY (PQFP) (continued) PQFP Pin # Pin Name Pin Function 1 NC No Connect 2 NC No Connect 3 NC No Connect 4 NC No Connect 5 SHDCLK 6 EAM/R Serial Receive Data Clock External Address Match/Reject 7 SRD 8 SF/BD Serial Receive Data Start Frame/Byte Delimiter 9 RESET Reset 10 SLEEP Sleep Mode 11 DVDD Digital Power 12 INTR Interrupt 13 TC 14 DBUS0 Timing Control Data Bus0 Digital Ground 15 DVSS 16 DBUS1 Data Bus1 17 DBUS2 Data Bus2 18 DBUS3 Data Bus3 19 DBUS4 Data Bus4 20 Digital Ground 21 DVSS DBUS5 22 DBUS6 Data Bus6 23 DBUS7 Data Bus7 24 DBUS8 Data Bus8 25 DBUS9 Data Bus9 26 NC No Connect 27 NC No Connect 28 NC No Connect 29 DBUS10 DBUS10 Data Bus10 30 NC No Connect 31 DBUS11 DBUS11 Data Bus11 32 DBUS12 DBUS12 Data Bus12 33 DBUS13 DBUS13 Data Bus13 34 DVDD 35 DBUS14 DBUS14 Data Bus14 36 DBUS15 DBUS15 Data Bus15 37 38 DVSS EOF 39 DTV Data Transfer Valid 40 FDS FIFO Data Strobe 41 BE0 Byte Enable0 42 BE1 Byte Enable1 Data Bus5 Digital Power Digital Ground End of Frame Am79C940 Am79C940 13 PIN/PACKAGE SUMMARY (continued) PQFP Pin # Pin Name Pin Function 43 SCLK 44 TDTREQ Transmit Data Transfer Request 45 RDTREQ Receive Data Transfer Request 46 ADD0 Address0 47 ADD1 Address1 48 ADD2 Address2 49 ADD3 Address3 50 ADD4 Address4 51 NC No Connect 52 NC No Connect 53 NC No Connect 54 NC No Connect 55 R/W Read/Write 56 CS Chip Select 57 RXPOL Receive Polarity 58 LNKST Link Status 59 TDO Test Data Out 60 TMS Test Mode Select 61 TCK Test Clock 62 DVSS Digital Ground 63 TDI Test Data Input 64 DVDD System Clock Digital Power 65 RXD­ Receive Data­ 66 RXD+ Receive Data+ 67 AVDD Analog Power 68 TXP­ Transmit Pre-distortion­ 69 TXD­ Transmit Data­ 70 TXP+ Transmit Pre-distortion+ 71 TXD+ Transmit Data+ 72 AVDD Analog Power 73 XTAL1 74 AVSS Analog Ground 75 XTAL2 Crystal Output 76 NC No Connect 77 NC No Connect 78 NC No Connect 79 AVSS 80 NC Crystal Input Analog Ground No Connect 81 Data Out­ DO+ Data Out+ 83 AVDD Analog Power 84 DI­ Data In­ 85 14 DO­ 82 DI+ Data In+ Am79C940 Am79C940 PIN/PACKAGE SUMMARY (continued) PQFP Pin # Pin Name Pin Function 86 CI­ Control In­ 87 CI+ Control In+ 88 AVDD Analog Power 89 DVDD Digital Power 90 DXCVR Disable Transceiver 91 EDSEL Edge Select Digital Ground 92 DVSS 93 TXDAT+ Transmit Data + 94 TXDAT­ Transmit Data­ 95 DVSS Digital Ground 96 STDCLK 97 TXEN/TXEN Serial Transmit Data Clock 98 CLSN 99 RXDAT Receive Data 100 RXCRS Receive Carrier Sense Transmit Enable Collision Am79C940 Am79C940 15 PIN/PACKAGE SUMMARY (TQFP) (continued) TQFP Pin Number Pin Name Serial Receive Data Clock 41 R/W Read/Write EAM/R External Address Match/Reject 42 CS Chip/Select 3 SF/BD Start Frame/Byte Delimiter 43 LNKST Link Status 4 RESET Reset 44 TDO Test Data Out 5 SLEEP Sleep Mode 45 TMS Test Mode Select 6 DVDD Digital Power 46 TCK Text Clock 7 INTR Interrupt 47 DVSS Digital Ground 8 TC Timing Control 48 TDI Test Data Input 9 DBUS0 Data Bus0 49 DVDD Digital Power 10 DVSS Digital Ground 50 RXD­ Receive Data­ 11 DBUS1 Data Bus1 51 RXD+ Receive Data+ 12 DBUS2 Data Bus2 52 AVDD Analog Power 13 DBUS3 Data Bus3 53 TXP­ Transmit Pre-distortion­ 14 DBUS4 Data Bus4 54 TXD­ Transmit Data­ 15 DVSS Digital Ground 55 TXP+ Transmit Pre-distortion+ 16 DBUS5 Data Bus5 56 TXD+ Transmit Data+ 17 DBUS6 Data Bus6 57 AVDD Analog Power 18 DBUS7 Data Bus7 58 XTAL1 Crystal Output 19 DBUS8 Data Bus8 59 AVSS Analog Ground 20 DBUS9 Data Bus9 60 XTAL2 Crystal Output 21 DBUS10 DBUS10 Data Bus10 61 AVSS Analog Ground 22 DBUS11 DBUS11 Data Bus11 62 DO­ Data Out­ 23 DBUS12 DBUS12 Data Bus12 63 DO+ Data Out+ 24 DBUS13 DBUS13 Data Bus13 64 AVDD 25 DVDD Digital Power 65 DI­ Data In­ 26 DBUS14 DBUS14 Data Bus14 66 DI+ Data Out+ 27 DBUS15 DBUS15 Data Bus15 67 CI­ Control In­ 28 DVSS Digital Ground 68 CI+ Control In+ 29 EOF End of Frame 69 AVDD Analog Power 30 FDS FIFO Data Strobe 70 DVDD Digital Power 31 BE0 Byte Enable0 71 DXCVR Disable Transceiver 32 BE1 Byte Enable1 72 EDSEL Edge Select 33 SCLK System Clock 73 DVSS Digital Ground 34 TDTREQ Transmit Data Transfer Request 74 TXDAT+ Transmit Data+ 35 RDTREQ Receive Data Transfer Request 75 DVSS Digital Ground 36 ADD0 Address0 76 STDCLK 37 ADD1 Address1 77 TXEN/TXEN 38 ADD2 Address2 78 CLSN 39 ADD3 Address3 79 RXDAT Receive Data 40 ADD4 Address4 80 RXCRS Receive Carrier Sense TQFP # 1 SRDCLK 2 16 Pin Name Pin Function Am79C940 Am79C940 Pin Function Analog Power Serial Transmit Data Clock Transmit Enable Collision PIN SUMMARY Pin Name Pin Function Type Active Comment Attachment Unit Interface (AUI) DO+/DO­ Data Out O Pseudo-ECL DI+/DI­ Data In I Pseudo-ECL CI+/CI­ Control In I Pseudo-ECL RXCRS Receive Carrier Sense I/O High TTL output. Input in DAI, GPSI port TXEN Transmit Enable O High TTL. TXEN in DAI port CLSN Collision I/O High TTL output. Input in GPSI DXCVR Disable Transceiver O Low TTL low STDCLK Serial Transmit Data Clock I/O Output. Input in GPSI SRDCLK Serial Receive Data Clock I/O Output. Input in GPSI Digital Attachment Interface (DAI) TXDAT+ Transmit Data + O High TTL. See also GPSI TXDAT­ Transmit Data­ O Low TTL TXEN Transmit Enable O Low TTL. See TXEN in GPSI RXDAT Receive Data RXCRS Receive Carrier Sense I/O High TTL input. Output in AUI CLSN Collision I/O High TTL output. Input in GPSI DXCVR Disable Transceiver O High TTL high STDCLK Serial Transmit Data Clock I/O Output. Input in GPSI SRDCLK Serial Receive Data Clock I/O Output. Input in GPSI I TTL. See also GPSI 10BASE-T 10BASE-T Interface TXD+/TXD­ Transmit Data O TXP+/TXP­ Transmit Pre-distortion O RXD+/RXD­ Receive Data I LNKST Link Status O Low Open Drain RXPOL Receive Polarity O Low Open Drain TXEN Transmit Enable O High TTL. TXEN in DAI port RXCRS Receive Carrier Sense I/O High TTL output. Input in DAI, GPSI port CLSN Collision I/O High TTL output. Input in GPSI DXCVR Disable Transceiver O High TTL high STDCLK Serial Transmit Data Clock I/O Output. Input in GPSI SRDCLK Serial Receive Data Clock I/O Output. Input in GPSI I/O Input General Purpose Serial Interface (GPSI) STDCLK Serial Transmit Data Clock TXDAT+ Transmit Data + O High TTL. See also DAI port TXEN Transmit Enable O High TTL. TXEN in DAI port SRDCLK Serial Receive Data Clock I/O RXDAT Receive Data RXCRS Receive Carrier Sense I/O High TTL input. Output in AUI CLSN Collision I/O High TTL input DXCVR Disable Transceiver O Low TTL low Input. See also EADI port I Am79C940 Am79C940 TTL. See also DAI port 17 PIN SUMMARY (continued) Pin Name Pin Function Type Active Comment External Address Detection Interface (EADI) SF/BD Start Frame/Byte Delimiter O High SRD Serial Receive Data O High EAM/R External Address Match/Reject I Low SRDCLK Serial Receive Data Clock I/O Output except in GPSI Host System Interface DBUS 15­0 Data Bus I/O High ADD4­0 Address I High R/W Read/Write I High/Low RDTREQ Receive Data Transfer Request O Low TDTREQ Transmit Data Transfer Request O Low DTV Data Transfer Valid O Low EOF End Of Frame I/O Low BE0 Byte Enable 0 I Low BE1 Byte Enable 1 I Low CS Chip Select I Low FDS FIFO Data Strobe I Low INTR Interrupt O Low EDSEL Edge Select I High TC Timing Control I Low SCLK System Clock I High RESET Reset I Low Tristate Open Drain Internal pull-up IEEE 1149.1 Test Access Port (TAP) Interface TCK Test Clock I Internal pull-up TMS Test Mode Select I Internal pull-up TDI Test Data Input I Internal pull-up TDO Test Data Out O General Interface XTAL1 Crystal Input I CMOS XTAL2 Crystal Output O CMOS SLEEP Sleep Mode I DVDD Digital Power (4 pins) P DVSS Digital Power (6 pins) P AVDD Analog Power (4 pins) P AVSS Analog Power (2 pins) P 18 Am79C940 Am79C940 Low TTL PIN DESCRIPTION Network Interfaces DI+/DI Data In (Input) The MACE device has five potential network interfaces. Only one of the interfaces that provides physical network attachment can be used (active) at any time. Selection between the AUI, 10BASE-T 10BASE-T, DAI or GPSI ports is provided by programming the PHY Configuration Control register. The EADI port is effectively active at all times. Some signals, primarily used for status reporting, are active for more than one single interface (the CLSN pin for instance). Under each of the descriptions for the network interfaces, the primary signals which are unique to that interface are described. Where signals are active for multiple interfaces, they are described once under the interface most appropriate. Attachment Unit Interface (AUI) CI+/CI Control In (Input) A differential input pair, signaling the MACE device that a collision has been detected on the network media, indicated by the CI± inputs being exercised with 10 MHz pattern of sufficient amplitude and duration. Operates at pseudo-ECL levels. A differential input pair to the MACE device for receiving Manchester encoded data from the network. Operates at pseudo-ECL levels. DO+/DO Data Out (Output) A differential output pair from the MACE device for transmitting Manchester encoded data to the network. Operates at pseudo-ECL levels. Digital Attachment Interface (DAI) TXDAT+/TXDAT­ Transmit Data (Output) When the DAI port is selected, TXDAT± are configured as a complementary pair for Manchester encoded data output from the MACE device, used to transmit data to a local external network transceiver. During valid transmission (indicated by TXEN low), a logical 1 is indicated by the TXDAT+ pin being in the high state and TXDAT­ in the low state; and a logical 0 is indicated by the TXDAT+ pin being in the low state and TXDAT­ in the high state. During idle (TXEN high), TXDAT+ will be in the high state, and TXDAT­ in the low state. When the GPSI port is selected, TXDAT+ will provide NRZ data output from the MAC core, and TXDAT­ will be held in the LOW state. Operates at TTL levels. The operations of TXDAT+ and TXDAT­ are defined in the following tables: TXDAT + Configuration SLEEP 0 1 1 1 1 1 PORTSEL [1-0] XX 00 01 10 11 XX ENDPLSIO X 1 1 1 1 0 Interface Description Sleep Mode AUI 10BASE 10BASE­T DAI Port GPSI Status Disabled Pin Function High Impedance High Impedance (Note 2) High Impedance (Note 2) TXDAT+ Output TXDAT+ Output High Impedance (Note 2) TXDAT ­ Configuration SLEEP 0 1 1 1 1 1 PORTSEL [1-0] XX 00 01 10 11 XX ENDPLSIO X 1 1 1 1 0 Interface Description Sleep Mode AUI 10BASE 10BASE­T DAI Port GPSI Status Disabled Pin Function High Impedance High Impedance High Impedance TXDAT­ Output LOW High Impedance Notes: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if unused, to reduce power consumption. Am79C940 Am79C940 19 TXEN/TXEN Transmit Enable (Output) decoded data input to the MAC core of the MACE device, from an external Manchester encoder/decoder. Operates at TTL levels. When the AUI port is selected (PORTSEL [1-0] = 00), an output indicating that the AUI DO± differential output has valid Manchester encoded data is presented. When the 10BASE-T 10BASE-T port is selected (PORTSEL [1-0] = 01), indicates that Manchester data is being output on the TXD±/TXP± complementary outputs. When the DAI port is selected (PORTSEL [1­0] = 10), indicates that Manchester data is being output on the DAI port TXDAT± complementary outputs. When the GPSI port is selected (PORTSEL [1­0] =11), indicates that NRZ data is being output from the MAC core of the MACE device, to an external Manchester encoder/decoder, on the TXDAT+ output. Active low when the DAI port is selected, active high when the AUI, 10 BASE-T or GPSI is selected. Operates at TTL levels. RXCRS Receive Carrier Sense (Input/Output) When the AUI port is selected (PORTSEL [1­0] = 00), an output indicating that the DI± input pair is receiving valid Manchester encoded data from the external transceiver which meets the signal amplitude and pulse width requirements. When the 10BASE-T 10BASE-T port is selected (PORTSEL [1­0] = 01), an output indicating that the RXD± input pair is receiving valid Manchester encoded data from the twisted pair cable which meets the signal amplitude and pulse width requirements. RXCRS will be asserted high for the entire duration of the receive message. When the DAI port is selected (PORTSEL [1-0] = 10), an input signaling the MACE device that a receive carrier condition has been detected on the network, and valid Manchester encoded data is being presented to the MACE device on the RXDAT line. When the GPSI port is selected (PORTSEL [1-0] = 11), an input signalling the internal MAC core that valid NRZ data is being presented on the RXDAT input. Operates at TTL levels. RXDAT Receive Data (Input) When the DAI port is selected (PORTSEL [1­0] = 10), the Manchester encoded data input to the integrated clock recovery and Manchester decoder of the MACE device, from an external network transceiver. When the GPSI port is selected (PORTSEL [1­0] =11), the NRZ TXEN/TXEN Configuration SLEEP PORTSEL [1-0] ENDPLSIO 0 XX X Sleep Mode High Impedance 1 00 1 AUI TXEN Output 1 01 1 10BASE-T 10BASE-T TXEN Output 1 10 1 DAI Port TXEN Output 1 11 1 GPSI TXEN Output 1 XX 0 Status Disabled High Impedance (Note 3) Interface Description Pin Function Notes: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. When the GPSI port is selected, TXEN should have an external pull-down attached (e.g. 3.3k ) to ensure the output is held inactive before ENPLSIO is set. 3. This pin should be externally terminated, if unused, to reduce power consumption. 20 Am79C940 Am79C940 RXDAT Configuration SLEEP PORTSEL [1­0] ENPLSIO 0 XX X Sleep Mode High Impedance 1 00 1 AUI High Impedance (Note 2) 1 01 1 10BASE-T 10BASE-T High Impedance (Note 2) 1 10 1 DAI Port RXDAT Input 1 11 1 GPSI RXDAT Input 1 XX 0 Status Disabled High Impedance (Note 2) Interface Description Pin Function Notes: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if unused, to reduce power consumption. RXCRS Configuration SLEEP PORTSEL [1-0] ENDPLSIO 0 XX X Sleep Mode High Impedance 1 00 1 AUI RXCRS Output 1 01 1 10BASE-T 10BASE-T RXCRS Output 1 10 1 DAI Port RXCRS Output 1 11 1 GPSI RXCRS Output 1 XX 0 Status Disabled High Impedance (Note 2) Interface Description Pin Function Notes: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if unused, to reduce power consumption. DXCVR Disable Transceiver (Output) An output from the MACE device to indicate the network port in use, as programmed by the ASEL bit or the PORTSEL [1­0] bits. The output is provided to allow power down of an external DC-to-DC converter, typically used to provide the voltage requirements for an external 10BASE2 10BASE2 transceiver. When the Auto Select (ASEL) feature is enabled, the state of the PORTSEL [1­0] bits is overridden, and the network interface will be selected by the MACE device, dependent only on the status of the 10BASE-T 10BASE-T link. If the link is active (LNKST pin driven LOW) the 10BASE-T 10BASE-T port will be used as the active network interface. If the link is inactive (LNKST pin pulled HIGH) the AUI port will be used as the active network interface. Auto Select will continue to operate even when the SLEEP pin is asserted if the RWAKE bit has been set. The AWAKE bit does not allow the Auto Select function, and only the receive section of 10BASE-T 10BASE-T port will be active (DXCVR = HIGH). Active (HIGH) when either the 10BASE-T 10BASE-T or DAI port is selected. Inactive (LOW) when the AUI or GPSI port is selected. Am79C940 Am79C940 21 DXCVR Configuration-SLEEP Operation Sleep Pin RWAKE Bit AWAKE Bit ASEL Bit 0 0 0 X 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 LNKST Pin PORTSEL [1­0] Bits Interface Description Pin Function Sleep High Mode Impedance 00 AUI with EADI port LOW 01 10BASE-T 10BASE-T with EADI port HIGH 10 Invalid HIGH 11 Invalid LOW 0X AUI with EADI port LOW 0X 10BASE-T 10BASE-T with EADI port HIGH HIGH 0X AUI with EADI port LOW 1 LOW 0X 10BASE-T 10BASE-T with EADI port HIGH X X 0X 10BASE-T 10BASE-T HIGH High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance XX Note: 1. RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). All bits must be programmed prior to the assertion of the SLEEP pin. DXCVR Configuration-Normal Operation SLEEP Pin ASEL Bit LNKST Pin PORTSEL [1-0] Bits ENPLSIO BIT Interface Description Pin Function 1 X X XX X SIA Test Mode 1 0 X 00 X AUI LOW 1 0 X 01 X 10BASE-T 10BASE-T HIGH 1 0 X 10 X DAI port HIGH 1 0 X 11 X GPSI LOW 1 1 HIGH 0X X AUI LOW 1 1 LOW 0X X 10BASE-T 10BASE-T HIGH High Impedance Note: 1. RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 22 Am79C940 Am79C940 10BASE-T 10BASE-T INTERFACE TXD+, TXD­ RXPOL Transmit Data (Output) The twisted pair receiver is capable of detecting a receive signal with reversed polarity (wiring error). The RXPOL pin is normally in the LOW state, indicating correct polarity of the received signal. If the receiver detects a received packet with reversed polarity, then this pin is not driven (requires external pull-up) and the polarity of subsequent packets are inverted. In the LOW output state, this pin is capable of sinking a maximum of 12mA and can be used to drive an LED. Receive Polarity (Output, Open Drain) 10BASE 10BASE­T port differential drivers. TXP+, TXP­ Transmit Pre-Distortion (Output) Transmit wave form differential driver for pre-distortion. RXD+, RXD­ Receive Data (Input) The polarity correction feature can be disabled by setting the Disable Auto Polarity Correction (DAPC) bit in the PHY Configuration Control register. In this case, the Receive Polarity correction circuit is disabled and the internal receive signal remains non-inverted, irrespective of the received signal. Note that RXPOL will continue to reflect the polarity detected by the receiver. 10BASE 10BASE­T port differential receiver. These pins should be externally terminated to reduce power consumption if the 10BASE 10BASE­T interface is not used. LNKST Link Status (OutputOpen Drain) This pin is driven LOW if the link is identified as functional. If the link is determined to be nonfunctional, due to missing idle link pulses or data packets, then this pin is not driven (requires external pull-up). In the LOW output state, the pin is capable of sinking a maximum of 12 mA and can be used to drive an LED. General Purpose Serial Interface (GPSI) STDCLK Serial Transmit Data Clock (Input/Output) When either the AUI, 10BASE 10BASE­T or DAI port is selected, STDCLK is an output operating at one half the crystal or XTAL1 frequency. STDCLK is the encoding clock for Manchester data transferred to the output of either the AUI DO± pair, the 10BASE-T 10BASE-T TXD±/TXP± pairs, or the DAI port TXDAT± pair. When using the GPSI port, STDCLK is an input at the network data rate, provided by the external Manchester encode/decoder, to strobe out the NRZ data presented on the TXDAT+ output. This is also required for internal loopbacks while in GPSI mode. This feature can be disabled by setting the Disable Link Test (DLNKTST) bit in the PHY Configuration Control register. In this case the internal Link Test Receive function is disabled, the LNKST pin will be driven LOW, and the Transmit and Receive functions will remain active regardless of arriving idle link pulses and data. The internal 10BASE-T 10BASE-T MAU will continue to generate idle link pulses irrespective of the status of the DLNKTST bit. STDCLK Configuration SLEEP PORTSEL [1-0] ENDPLSIO 0 XX X Sleep Mode High Impedance 1 00 1 AUI STDCLK Output 1 01 1 10BASE-T 10BASE-T STDCLK Output 1 10 1 DAI Port STDCLK Output 1 11 1 GPSI STDCLK Output 1 XX 0 Status Disabled High Impedance (Note 2) Interface Description Pin Function Notes: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if unused, to reduce power consumption. Am79C940 Am79C940 23 CLSN External Address Detection Interface (EADI) SF/BD Collision (Input/Output) An external indication that a collision condition has been detected by the (internal or external) Medium Attachment Unit (MAU), and that signals from two or more nodes are present on the network. When the AUI port is selected (PORTSEL [1­0] = 00), CLSN will be activated when the CI± input pair is receiving a collision indication from the external transceiver. CLSN will be asserted high for the entire duration of the collision detection, but will not be asserted during the SQE Test message following a transmit message on the AUI. When the 10BASE-T 10BASE-T port is selected (PORTSEL [1­0] = 01), CLSN will be asserted high when simultaneous transmit and receive activity is detected (logically detected when TXD±/TXP± and RXD± are both active). When the DAI port is selected (PORTSEL [1­0] = 10), CLSN will be asserted high when simultaneous transmit and receive activity is detected (logically detected when RXCRS and TXEN are both active). When the GPSI port is selected (PORTSEL [1­0] = 11), an input from the external Manchester encoder/decoder signaling the MACE device that a collision condition has been detected on the network, and any receive frame in progress should be aborted. Start Frame/Byte Delimiter (Output) The external indication that a start of frame delimiter has been received. The serial bit stream will follow on the Serial Receive Data pin (SRD), commencing with the destination address field. SF/BD will go high for 4 bit times (400 ns) after detecting the second 1 in the SFD of a received frame. SF/BD will subsequently toggle every 400 ns (1.25 MHz frequency) with the rising edge indicating the start (first bit) in each subsequent byte of the received serial bit stream. SF/BD will be inactive during frame transmission. SRD Serial Receive Data (Output) SRD is the decoded NRZ data from the network. It is available for external address detection. Note that when the 10BASE-T 10BASE-T port is selected, transition on SRD will only occur during receive activity. When the AUI or DAI port is selected, transition on SRD will occur dur ing both transmit and receive activity. CLSN Configuration SLEEP PORTSEL [1-0] ENDPLSIO 0 XX X Sleep Mode High Impedance 1 00 1 AUI CLSN Output 1 01 1 10BASE-T 10BASE-T CLSN Output 1 10 1 DAI Port CLSN Output 1 11 1 GPSI CLSN Output 1 XX 0 Status Disabled High Impedance (Note 2) Interface Description Pin Function Notes: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if unused, to reduce power consumption. EAM/R SRDCLK External Address Match/Reject(Input) Serial Receive Data Clock (Input/Output) The incoming frame will be received dependent on the receive operational mode of the MACE device, and the polarity of the EAM/R pin. The EAM/R pin function is programmed by use of the M/R bit in the Receive Frame Control register. If the bit is set, the pin is configured as EAM. If the bit is reset, the pin is configured as EAR. EAM/R can be asserted during packet reception to accept or reject packets based on an external address comparison. The Serial Receive Data (SRD) output is synchronous to SRDCLK running at the 10MHz receive data clock frequency. The pin is configured as an input, only when the GPSI port is selected. Note that when the 10BASE 10BASE­T port is selected, transition on SRDCLK will only occur during receive activity. When the AUI or DAI port is selected, transition on SRDCLK will occur during both transmit and receive activity. 24 Am79C940 Am79C940 SRD Configuration SLEEP PORTSEL [1-0] ENDPLSIO 0 XX X Sleep Mode High Impedance 1 00 1 AUI SRD Output 1 01 1 10BASE-T 10BASE-T SRD Output 1 10 1 DAI Port SRD Output 1 11 1 GPSI SRD Output 1 XX 0 Status Disabled High Impedance Interface Description Pin Function Note: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). SRDCLK Configuration SLEEP PORTSEL [1-0] ENDPLSIO 0 XX X Sleep Mode High Impedance 1 00 1 AUI SRDCLK Output 1 01 1 10BASE-T 10BASE-T SRDCLK Output 1 10 1 DAI Port SRDCLK Output 1 11 1 GPSI SRDCLK Output 1 XX 0 Status Disabled High Impedance (Note 2) Interface Description Pin Function Notes: 1. PORTSEL [1­0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if unused, to reduce power consumption. Am79C940 Am79C940 25 HOST SYSTEM INTERFACE DBUS15-0 DBUS15-0 DBUS contains read and write data to and from internal registers and the Transmit and Receive FIFOs. request transmit data transfer when 16, 32 or 64 bytes are available in the Transmit FIFO, by programming the Transmit FIFO Watermark (XMTFW bits) in the FIFO Configuration Control register. TDTREQ will be asserted only when Enable Transmit (ENXMT) is set in the MAC Configuration Control register. ADD4-0 FDS Address Bus (Input) FIFO Data Select (Input) FIFO Data Select allows direct access to the transmit or Receive FIFO without use of the ADD address bus. FDS must be activated in conjunction with R/W. When the MACE device samples R/W as high and FDS low, a read cycle from the Receive FIFO will be initiated. When the MACE chip samples R/W and FDS low, a write cycle to the Transmit FIFO will be initiated. The CS line should be inactive (high) when FIFO access is requested using the FDS pin. If the MACE device samples both CS and FDS as active simultaneously, no cycle will be executed, and DTV will remain inactive. Data Bus (Input/Output/3-state) ADD is used to access the internal registers and FIFOs to be read or written. R/W Read/Write (Input) Indicates the direction of data flow during the MACE device register, Transmit FIFO, or Receive FIFO accesses. RDTREQ Receive Data Transfer Request(Output) Receive Data Transfer Request indicates that there is data in the Receive FIFO to be read. When RDTREQ is asserted there will be a minimum of 16 bytes to be read except at the completion of the frame, in which case EOF will be asserted. RDTREQ can be programmed to request receive data transfer when 16, 32 or 64 bytes are available in the Receive FIFO, by programming the Receive FIFO Watermark (RCVFW bits) in the FIFO Configuration Control register. The first assertion of RDTREQ will not occur until at least 64 bytes have been received, and the frame has been verified as non runt. Runt packets will normally be deleted from the Receive FIFO with no external activity on RDTREQ. When Runt Packet Accept is enabled (RPA bit) in the User Test Register, RDTREQ will be asserted when the runt packet completes, and the entire frame resides in the Receive FIFO. RDTREQ will be asserted only when Enable Receive (ENRCV) is set in the MAC Configuration Control register. The RCVFW can be overridden by enabling the Low Latency Receive function (setting LLRCV bit) in the Receive Frame Control register, which allows RDTREQ to be asserted after only 12 bytes have been received. Note that use of this function exposes the system interface to premature termination of the receive frame, due to network events such as collisions or runt packets. It is the responsibility of the system designer to provide adequate recovery mechanisms for these conditions. TDTREQ Transmit Data Transfer Request (Output) Transmit Data Transfer Request indicates there is room in the Transmit FIFO for more data. TDTREQ is asserted when there are a minimum of 16 empty bytes in the Transmit FIFO. TDTREQ can be programmed to 26 DTV Data Transfer Valid (Output/3-state) When asserted, indicates that the read or write operation has completed successfully. The absence of DTV at the termination of a host access cycle on the MACE device indicates that the data transfer was unsuccessful. DTV need not be used if the system interface can guarantee that the latency to TDTREQ and RDTREQ assertion and de-assertion will not cause the Transmit FIFO to be over-written or the Receive FIFO to be over-read. In this case, the latching or strobing of read or write data can be synchronized to the SCLK input rather than to the DTV output. EOF End Of Frame (Input/Output/3-state) End Of Frame will be asserted by the MACE device when the last byte/word of frame data is read from the Receive FIFO, indicating the completion of the frame data field for the receive message. End Of Frame must be asserted low to the MACE device when the last byte/word of the frame is written into the Transmit FIFO. BE1­0 Byte Enable (Input) Used to indicate the active portion of the data transfer to or from the internal FIFOs. For word (16-bit) transfers, both BE0 and BE1 should be activated by the external host/controller. Single byte transfers are performed by identifying the active data bus byte and activating only one of the two signals. The function of the BE1-0 pins is programmed using the BSWP bit (BIU Configuration Control register, bit 6). BE1-0 are not required for accesses to MACE device registers. Am79C940 Am79C940 CS Chip Select (Input) Used to access the MACE device FIFOs and internal registers locations using the ADD address bus. The FIFOs may alternatively be directly accessed without supplying the FIFO address, by using the FDS and R/W pins. INTR Interrupt (Output, Open Drain) An attention signal indicating that one or more of the following status flags are set: XMTINT, RCVINT, MPCO, RPCO, RCVCCO, CERR, BABL, or JAB. Each interrupt source can be individually masked. No interrupt condition can take place in the MACE device immediately after a hardware or software reset. RESET Reset (Input) Reset clears the internal logic. Reset can be asynchronous to SCLK, but must be asserted for a minimum duration of 15 SCLK cycles. IEEE 1149.1 TEST ACCESS PORT (TAP) INTERFACE TCK Test Clock (Input) The clock input for the boundary scan test mode operation. TCK can operate up to 10 MHz. TCK has an internal (not SLEEP disabled) pull up. TMS Test Mode Select (Input) A serial input bit stream used to define the specific boundary scan test to be executed. TMS has an internal (not SLEEP disabled) pull up. TDI Test Data Input (Input) The test data input path to the MACE device. TDI has an internal (not SLEEP disabled) pull up. TDO Test Data Out (Output) SCLK The test data output path from the MACE device. System Clock (Input) The system clock input controls the operational frequency of the slave interface to the MACE device and the internal processing of frames. SCLK is unrelated to the 20 MHz clock frequency required for the 802.3/ Ethernet interface. The SCLK frequency range is 1 MHz-25 MHz. GENERAL INTERFACE XTAL1 EDSEL System Clock Edge Select (Input) EDSEL is a static input that allows System Clock (SCLK) edge selection. If EDSEL is tied high, the bus interface unit will assume falling edge timing. If EDSEL is tied low, the bus interface unit will assume rising edge timing, which will effectively invert the SCLK as it enters the MACE device, i.e., the address, control lines (CS, R/W, FDS, etc) and data are all latched on the rising edge of SCLK, and data out is driven off the rising edge of SCLK. TC Timing Control (Input) The Timing Control input conditions the minimum number of System Clocks (SCLK) cycles taken to read or write the internal registers and FIFOs. TC can be used as a wait state generator, to allow additional time for data to be presented by the host during a write cycle, or allow additional time for the data to be latched during a read cycle. TC has an internal (SLEEP disabled) pull up. Timing Control TC 1 0 Number of Clocks 2 3 Crystal Connection (Input) The internal clock generator uses a 20 MHz crystal that is attached to pins XTAL1 and XTAL2. Internally, the 20 MHz crystal frequency is divided by two which determines the network data rate. Alternatively, an external 20 MHz CMOS-compatible clock signal can be used to drive this pin. The MACE device supports the use of 50 pF crystals to generate a 20 MHz frequency which is compatible with the IEEE 802.3 network fre quency tolerance and jitter specifications. XTAL2 Crystal Connection (Output) The internal clock generator uses a 20 MHz crystal that is attached to pins XTAL1 and XTAL2. If an external clock generator is used on XTAL1, then XTAL2 should be left unconnected. SLEEP Sleep Mode (Input) The optimal power savings made is extracted by asserting the SLEEP pin with both the Auto Wake (AWAKE bit) and Remote Wake (RWAKE bit) functions disabled. In this "deep sleep" mode, all outputs will be forced into their inactive or high impedance state, and all inputs will be ignored except for the SLEEP, RESET, SCLK, TCK, TMS, and TDI pins. SCLK must run for 5 cycles after the assertion of SLEEP. During the "Deep Sleep", the SCLK input can be optionally suspended for maximum power savings. Upon exiting "Deep Sleep", the hardware RESET pin must be asserted and the SCLK restored. The system must delay the setting Am79C940 Am79C940 27 of the bits in the MAC configuration Control Register of the internal analog circuits by 1 ns to allow for stabilization. If the AWAKE bit is set prior to the activation of SLEEP, the 10BASE 10BASE­T receiver and the LNKST output pin remain operational. power and ground pins are not deleted. The MACE device does have several sets of media interfaces which typically go unused in most designs, however. Pins from some of these interfaces are deleted instead. Removed are the following: s TXDAT­ (previously used for the DAI interface) If the RWAKE bit is set prior to SLEEP being asserted, the Manchester encoder/decoder, AUI and 10BASE-T 10BASE-T cells remain operational, as do the SRD, SRDCLK and SF/BD outputs. s SRD (previously used for the EADI interface) The input on XTAL1 must remain active for the AWAKE or RWAKE features to operate. After exit from the Auto Wake or Remote Wake modes, activation of hardware RESET is not required when SLEEP is reasserted. Note that pins from four separate interfaces are removed rather than removing all the pins from a single interface. Each of these pins comes from one of the four sides of the device. This is done to maintain symmetry, thus avoiding bond out problems. On deassertion of SLEEP, the MACE device will go through an internally generated hardware reset sequence, requiring re-initialization of MACE registers. Power Supply DVDD s RXPOL (previously used as a receive frame polarity LED driver) In general, the most critical of the four removed pins are TXDAT­ and SRD. Depending on the application, either the DAI or the EADI interface may be important. In most designs, however, this will not be the case. PINS REMOVED FOR TQFP PACKAGE AND THEIR EFFECTS Digital Power There are four Digital VDD pins. TXDAT­ DVSS Digital Ground There are six Digital VSS pins. AVDD Analog Power There are four analog VDD pins. Special attention should be paid to the printed circuit board layout to avoid excessive noise on the supply to the PLL in the Manchester encoder/decoder (pins 66 and 83 in PLCC, pins 67 and 88 in PQFP). These supply lines should be kept separate from the DVDD lines as far back to the power supply as is practically possible. AVSS Analog Ground There are two analog VSS pins. Special attention should be paid to the printed circuit board layout to avoid excessive noise on the PLL supply in Manchester encoder/decoder (pin 73 in PLCC, pin 74 in PQFP). These supply lines should be kept separate from the DV SS lines as far back to the power supply as is practically possible. PIN FUNCTIONS NOT AVAILABLE WITH THE 80-PIN 80-PIN TQFP PACKAGE In the 84-pin PLCC configuration, ALL the pins are used while in the 100-pin PQFP version, 16 pins are specified as No Connects. Moving to the 80-pin TQFP configuration requires the removal of 4 pins. Since Ethernet controllers with integrated 10BASE-T 10BASE-T have analog portions which are very sensitive to noise, 28 s DTV (previously used for the host interface) The removal of TXDAT­ means that the DAI interface is no longer usable. The DAI interface was designed to be used with media types that do not require DC isolation between the MAU and the DTE. Media which do not require DC isolation can be implemented more simply using the DAI interface, rather than the AUI interface. In most designs this is not a problem because most media requires DC isolation (10BASE-T 10BASE-T, 10BASE2 10BASE2, 10BASE5 10BASE5) and will use the AUI port. About the only media which does not require DC isolation is 10BASE-F 10BASE-F. SRD The SRD pin is an output pin used by the MACE device to transfer a receive data stream to external address detection logic. It is part of the EADI interface. This pin is used to help interface the MACE device to an external CAM device. Use of an external CAM is typically required when an application will operate in promiscuous mode and will need perfect filtering (i.e., the internal hash filter will not suffice). Example applications for this sort of operation are bridges and routers. Lack of perfect filtering in these applications forces the CPU to be more involved in filtering and thus either slows the forwarding rates achieved or forces the use of a more powerful CPU. DTV The DTV pin is part of the host interface to the MACE device. It is used to indicate that a read or write cycle to the MACE device was successful. If DTV is not asserted at the end of a cycle, the data transfer was not successful. Basically, this will happen on a write to a full transmit FIFO or a read from an empty receive Am79C940 Am79C940 FIFO. In general, there are ways to ensure that a transfer is always valid; so this pin is not required in many designs. For instance, the TDTREQ and RDTREQ pins can be used to monitor the state of the FIFOs to ensure that data transfer only occurs at the correct times. RXPOL RXPOL is typically used to drive an LED indicating the polarity of receive frames. This function is not necessary for correct operation of the Ethernet and serves strictly as a status indication to a user. The status of the receive polarity is still available through the PHYCC register. Am79C940 Am79C940 29 FUNCTIONAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip embodies the Media Access Control (MAC) and Physical Signaling (PLS) sub-layers of the 802.3 Standard. The MACE device provides the IEEE defined Attachment Unit Interface (AUI) for coupling to remote Media Attachment Units (MAUs) or on-board transceivers. The MACE device also provides a Digital Attachment I n t e r f a c e ( D A I ) , b y -p a s s i n g t h e d i f f e r e n t i a l AUI interface. The system interface provides a fundamental data conduit to and from an 802.3 network. The MACE device in conjunction with a user defined DMA engine, provides an 802.3 interface tailored to a specific application. In addition, the MACE device can be combined with similarly architected peripheral devices and a multi-channel DMA controller, thereby providing the system with access to multiple peripheral devices with a single master interface to memory. Network Interfaces The MACE device can be connected to an 802.3 network using any one of the AUI, 10 BASE-T, DAI and GPSI network interfaces. The Attachment Unit Interface (AUI) provides an IEEE compliant differential interface to a remote MAU or an on-board transceiver. An integrated 10BASE-T 10BASE-T MAU provides a direct interface for twisted pair Ethernet networks. The DAI port can connect to local transceiver devices for 10BASE2 10BASE2, 10BASE-T 10BASE-T or 10BASE-F 10BASE-F connections. A General Purpose Serial Interface (GPSI) is supported, which effectively bypasses the integrated Manchester encoder/ decoder, and allows direct access to/from the integral 802.3 Media Access Controller (MAC) to provide support for external encoding/decoding schemes. The interface in use is determined by the PORTSEL [1-0] bits in the PLS Configuration Control register. The EADI port does not provide network connectivity, but allows an optional external circuit to assist in receive packet accept/reject. System Interface The MACE device is a slave register based peripheral. All transfers to and from the device, including data, are performed using simple memory or I/O read and write commands. Access to all registers, including the Transmit and Receive FIFOs, are performed with identical read or write timing. All information on the system interface is synchronous to the system clock (SCLK), which allows simple external logic to be designed to interrogate the device status and control the network data flow. The Receive and Transmit FIFOs can be read or written by driving the appropriate address lines and assert- 30 ing CS and R/W. A n alter nati ve FIFO ac cess mechanism allows the use of the FDS and the R/W lines, ignoring the address lines (ADD4-0). The state of the R/W line in conjunction with the FDS input determines whether the Receive FIFO is read (R/W high) or the Transmit FIFO written (R/W low). The MACE device system interface permits interleaved transmit and receive bus transfers, allowing the Transmit FIFO to be filled (primed) while a frame is being received from the network and/or read from the Receive FIFO. In receive operation, the MACE device asserts Receive Data Transfer Request (RDTREQ) when the FIFO contains adequate data. For the first indication of a new receive frame, 64 bytes must be received, assuming normal operation. Once the initial 64 byte threshold has been reached, RDTREQ assertion and de-assertion is dependent on the programming of the Receive FIFO Watermark (RCVFW bits in the BIU Configuration Control register). The RDTREQ can be programmed to activate when there are 16, 32 or 64 bytes of data available in the Receive FIFO. Enable Receive (ENRCV bit in MAC Configuration Control register) must be set to assert RDTREQ. If the Runt Packet Accept feature is invoked (RPA bit in User Test Register), RDTREQ will be asserted for receive frames of less than 64 bytes on the basis of internal and/or external address match only. When RPA is set, RDTREQ will be asserted when the entire frame has been received or when the initial 64 byte threshold has been exceeded. See the FIFO Sub-Systems section for further details. Note that the Receive FIFO may not contain 64 data bytes at the time RDTREQ is asserted, if the automatic pad stripping feature has been enabled (ASTRP RCV bit in the Receive Frame Control register) and a minimum length packet with pad is received. The MACE device will check for the minimum received length from the network, strip the pad characters, and pass only the data frame through the Receive FIFO. If the Low Latency Receive feature is enabled (LLRCV bit set in Receive Frame Control Register), RDTREQ will be asserted once a low watermark threshold has been reached (12 bytes plus some additional synchronization time). Note that the system interface will therefore be exposed to potential disruption of the receive frame due to a network condition (see the FIFO Sub-System description for additional details). In transmit operation, the MACE device asserts Transmit Data Transfer Request (TDTREQ) dependent on the programming of the Transmit FIFO Watermark (XMTFW bits in the BIU Configuration Control register). TDTREQ will be permanently asserted when the Transmit FIFO is empty. The TDTREQ can be programmed to activate when there are 16, 32 or 64 bytes of space available in the Transmit FIFO. Enable Transmit (ENXMT bit in MAC Configuration Control register) must be set to assert TDTREQ. Write cycles to the Am79C940 Am79C940 Transmit FIFO will not return DTV if ENXMT is disabled, and no data will be written. The MACE device will commence the preamble sequence once the Transmit Start Point (XMTSP bits in BIU Configuration Control register) threshold is reached in the Transmit FIFO. The Transmit FIFO data will not be overwritten until at least 512 data bits have been transmitted onto the network. If a collision occurs within the slot time (512 bit time) window, the MACE device will generate a jam sequence (a 32-bit all zeroes pattern) before ceasing the transmission. The Transmit FIFO will be reset to point at the start of the transmit data field, and the message will be retried after the random back-off interval has expired. DETAILED FUNCTIONS Block Level Description The following sections describe the major sub-blocks of and the external interfaces to the MACE device. Bus Interface Unit (BIU) The BIU performs the interface between the host or system bus and the Transmit and Receive FIFOs, as well as all chip control and status registers. The BIU can be configured to accept data presented in either little-endian or big indian format, minimizing the external logic required to access the MACE device internal FIFOs and registers. In addition, the BIU directly supports 8-bit transfers and incorporates features to simplify interfacing to 32-bit systems using external latches. Externally, the FIFOs appear as two independent registers located at individual addresses. The remainder of the internal registers occupy 30 additional consecutive addresses, and appear as 8-bits wide. BIU to FIFO Data Path The BIU operates assuming that the 16-bit data path to/from the internal FIFOs is configured as two independent byte paths, activated by the Byte Enable sig nals BE0 and BE1. BE0 and BE1 are only used during accesses to the 16-bit wide Transmit and Receive FIFOs. After hardware or software reset, the BSWP bit will be cleared. FIFO accesses to the MACE device will operate assuming an Intel 80x86 type memory convention (most significant byte of a word stored in the higher addressed byte). Word data transfers to/from the FIFOs over the DBUS15-0 DBUS15-0 lines will have the least significant byte located on DBUS7-0 (activated by BE0) and the most significant byte located on DBUS15-8 DBUS15-8 (activated by BE1). FIFO data can be read or written using either byte and/ or word operations. If byte operation is required, read/write transfers can be performed on either the upper or lower data bus by asserting the appropriate byte enable. For instance with BSWP = 0, reading from or writing to DBUS15-8 DBUS15-8 is accomplished by asserting BE1, and allows the data stream to be read from or written to the appropriate FIFO in byte order (byte 0, byte 1,.byte n). It is equally valid to read or write the data stream using DBUS7­0 and by asserting BE0. For BSWP = 1, reading from or writing to DBUS15-8 DBUS15-8 is accomplished by asserting BE0, and allows the byte stream to be transferred in byte order. When word operations are required, BSWP ensures that the byte ordering of the target memory is compatible with the 802.3 requirement to send/receive the data stream in byte ascending order. With BSWP = 0, the data transferred to/from the FIFO assumes that byte n will be on DBUS7-0 (activated by BE0) and byte n+1 will be on DBUS15-8 DBUS15-8 (activated by BE1). With BSWP = 1, the data transferred to/from the FIFO assumes that byte n will be presented on DBUS15-8 DBUS15-8 (activated by BE0), and byte n+1 will be on DBUS7-0 (activated by BE1). There are some additional special cases to the above generalized rules, which are as follows: (a) When performing byte read operations, both halves of the data bus are driven with identical data, effectively allowing the user to arbitrarily read from either the upper or lower data bus, when only one of the byte enables is activated. (b) When byte write operations are performed, the Transmit FIFO latency is affected. See the FIFO Sub-System section for additional details. (c) If a word read is performed on the last data byte of a receive frame (EOF is asserted), and the message contained an odd number of bytes but the host requested a word operation by asserting both BE0 and BE1, then the MACE device will present one valid and one non-valid byte on the data bus. The placement of valid data for the data byte is dependent on the target memory architecture. Regardless of BSWP, the single valid byte will be read from the BE0 memory bank. If BSWP = 0, BE0 corresponds to DBUS7-0; if BSWP = 1, BE0 corresponds to DBUS15-8 DBUS15-8. (d) If a byte read is performed when the last data byte is read for a receive frame (when the MACE device activates the EOF signal), then the same byte will be presented on both the upper and lower byte of the data bus, regardless of which byte enable was activated (as is the case for all byte read operations). (e) When writing the last byte in a transmit message to the Transmit FIFO, the portion of the data bus Am79C940 Am79C940 31 that the last byte is transferred over is irrelevant, providing the appropriate byte enable is used. For BSWP = 0, data can be presented on DBUS7-0 using BE0 or DBUS15-8 DBUS15-8 using BE1. For BSWP = 1, data can be presented on DBUS7-0 using BE1 or DBUS15-8 DBUS15-8 using BE0. Byte Alignment For Register Write Operations BE0 BE1 BSWP DBUS7-0 X X 0 Write Data X (f) When neither BE0 nor BE1 are asserted, no data transfer will take place. DTV will not be asserted. BE1 BSWP DBUS7-0 0 0 n n+1 0 1 0 n n 1 0 0 n n 1 1 0 X X 0 0 1 n+1 n 0 1 1 n n 1 0 1 n n 1 1 1 X X Write Data The MACE device has two independent FIFOs, with 128-bytes for receive and 136-bytes for transmit operations. The FIFO sub-system contains both the FIFOs, and the control logic to handle normal and exception related conditions. DBUS15-8 DBUS15-8 0 1 X FIFO Subsystem Byte Alignment For FIFO Read Operations BE0 X DBUS15-8 DBUS15-8 X The Transmit and Receive FIFOs interface on the network side with the serializer/de-serializer in the MAC engine. The BIU provides access between the FIFOs and the host system to enable the movement of data to and from the network. Internally, the FIFOs appear to the BIU as independent 16-bit wide registers. Bytes or words can be written to the Transmit FIFO (XMTFIFO), or read from the Receive FIFO (RCVFIFO). Byte and word transfers can be mixed in any order. The BIU will ensure correct byte ordering dependent on the target host system, as determined by the programming of the BSWP bit in the BIU Configuration Control register. Byte Alignment For FIFO Write Operations BE0 BE1 BSWP DBUS7-0 DBUS15-8 DBUS15-8 0 0 0 n n+1 0 1 0 n X 1 0 0 X n 1 1 0 X X 0 0 1 n+1 n 0 1 1 X n 1 0 1 n X The XMTFIFO and RCVFIFO have three different modes of operation. These are Normal (Default), Burst and Low Latency Receive. Default operation will be used after the hardware RESET pin or software SWRST bit have been activated. The remainder of this general description applies to all modes except where specific differences are noted. 1 1 1 X X Transmit FIFO-General Operation BIU to Control and Status Register Data Path All registers in the address range 2-31 are 8-bits wide. When a read cycle is executed on any of these registers, the MACE device will drive data on both bytes of the data bus, regardless of the programming of BSWP. When a write cycle is executed, the MACE device strobes in data based on the programming of BSWP as shown in the tables below. All accesses to addresses 2-31 are independent of the BE0 and BE1 pins. Byte Alignment For Register Read Operations BE0 X BE1 X BSWP 0 DBUS7-0 Read DBUS15-8 DBUS15-8 Read X X 1 Data Read Data Read Data Data 32 When writing bytes to the XMTFIFO, certain restrictions apply. These restrictions have a direct influence on the latency provided by the FIFO to the host system. When a byte is written to the FIFO location, the entire word location is used. The unused byte is marked as a hole in the XMTFIFO. These holes are skipped during the serialization process performed by the MAC engine, when the bytes are unloaded from the XMTFIFO. For instance, assume the Transmit FIFO Watermark (XMTFW) is set for 32 write cycles. If the host writes byte wide data to the XMTFIFO, after 36 write cycles there will be space left in the XMTFIFO for only 32 more write cycles. Therefore TDTREQ will de-assert even though only 36-bytes of data have been loaded into the XMTFIFO. Transmission will not commence until 64-bytes or the End-of-Frame are available in the XMFIFO, so transmission would not start, and Am79C940 Am79C940 TDTREQ would remain de-asserted. Hence for byte wide data transfers, the XMTFW should be programmed to the 8 or 16 write cycle limit, or the host should ensure that sufficient data will be written to the XMTFIFO after TDTREQ has been de-asserted (which is permitted), to guarantee that the transmission will commence. A third alternative is to program the Transmit Start Point (XMTSP) in the BIU Configuration Control register to below the 64-byte default; thereby imposing a lower latency to the host system requiring additional data to ensure the XMTFIFO does not underflow during the transmit process, versus using the default XMTSP value. Note that if 64 single byte writes are executed on the XMTFIFO, and the XMTSP is set to 64-bytes, the transmission will commence, and all 64-bytes of information will be accepted by the XMTFIFO. The number of write cycles that the host uses to write the packet into the Transmit FIFO will also directly influence the amount of space utilized by the transmit message. If the number of write cycles (n) required to transfer a packet to the Transmit FIFO is even, the number of bytes used in the Transmit FIFO will be 2*n. If the number of write cycles required to transfer a packet to the Transmit FIFO is odd, the number of bytes used in the Transmit FIFO will be 2*n + 2 because the End Of Frame indication in the XMTFIFO is always placed at the end of a 4-byte boundary. For example, a 32-byte message written as bytes (n = 32 cycles) will use 64-bytes of space in the Transmit FIFO (2*n = 64), whereas a 65-byte message written as 32 words and 1 byte (n = 33 cycles) would use 68-bytes (2*n + 2 = 68) . The Transmit FIFO has been sized appropriately to minimize the system interface overhead. However, consideration must be given to overall system design if byte writes are supported. In order to guarantee that sufficient space is present in the XMTFIFO to accept the number of write cycles programmed by the XMTFW (including an End Of Frame delimiter), TDTREQ may go inactive before the XMTSP threshold is reached when using the non burst mode (XMTBRST = 0). For instance, assume that the XMTFW is programmed to allow 32 write cycles (default), and XMTSP is programmed to require 64 bytes (default) before starting transmission. Assuming that the host bursts the transmit data in a 32 cycle block, writing a single byte anywhere within this block will mean that XMTSP will not have been reached. This would be a typical scenario if the transmit data buffer was not aligned to a word boundary. The MACE device will continue to assert TDTREQ since an additional 36 write cycles can still be executed. If the host starts a second burst, the XMTSP will be reached, and TDTREQ will deassert when less that 32 write cycle can be performed although the data written by the host will continue to be accepted. The host must be aware that additional space exists in the XMTFIFO although TDTREQ becomes inactive, and must continue to write data to ensure the XMTSP threshold is achieved. No transmit activity will commence until the XMTSP threshold is reached. Once 36 write cycles have been executed. Note that write cycles can be performed to the XMTFIFO even if the TDTREQ is inactive. When TDTREQ is asserted, it guarantees that a minimum amount of space exists, when TDTREQ is deasserted, it does not necessarily indicate that there is no space in the XMTFIFO. The DTV pin will indicate the successful acceptance of data by the Transmit FIFO. As another example, assume again that the XMTFW is programmed for 32 write cycles. If the host writes word wide data continuously to the XMTFIFO, the TDTREQ will deassert when 36 writes have executed on the XMTFIFO, at which point 72-bytes will have been written to the XMTFIFO, the 64-byte XMTSP will have been exceeded and the transmission of preamble will have commenced. TDTREQ will not re-assert until the transmission of the packet data has commenced and the possibility of losing data due to a collision within the slot time is removed (512 bits have been transmitted without a collision indication). Assuming that the host actually stopped writing data after the initial 72-bytes, there will be only 16-bytes of data remaining in the XMTFIFO (8-bytes of preamble/SFD plus 56-bytes of data have been transmitted), corresponding to 12.8 µs of latency before an XMTFIFO underrun occurs. This latency is considerably less than the maximum possible 57.6 µs the system may have assumed. If the host had continued with the block transfer until 64 write cycles had been performed, 128-bytes would have been written to the XMTFIFO, and 72-bytes of latency would remain (57.6 µ s) when TDTREQ was re-asserted. Transmit FIFO-Burst Operation The XMTFIFO burst mode, programmed by the XMTBRST bit in the FIFO Configuration Control register, modifies TDTREQ behavior. The assertion of TDTREQ is controlled by the programming of the XMTFW bits, such that when the specified number of write cycles can be guaranteed (8, 16 or 32), TDTREQ will be asserted. TDTREQ will be de-asserted when the XMT FIFO can only accept a single write cycle (one word write including an End Of Frame delimiter) allowing the external device to burst data into the XMTFIFO when TDTREQ is asserted, and stop when TDTREQ is deasserted. Receive FIFO-General Operation The Receive FIFO contains additional logic to ensure that sufficient data is present in the RCVFIFO to allow the specified number of bytes to be read, regardless of the ordering of byte/word read accesses. This has an Am79C940 Am79C940 33 impact on the perceived latency that the Receive FIFO provides to the host system. The description and table below outline the point at which RDTREQ will be asserted when the first duration of the packet has been received and when any subsequent transfer of the packet to the host system is required. No preamble/SFD bytes are loaded into the Receive FIFO. All references to bytes pass through the receive FIFO. These references are received after the preamble/SFD sequence. The first assertion of RDTREQ for a packet will occur after the longer of the following two conditions is met: s 64-bytes have been received (to assure runt packets and packets experiencing collision within the slot time will be rejected). s The RCVFW threshold is reached plus an additional 12 bytes. The additional 12 bytes are necessary to ensure that any permutation of byte/word read access is guaranteed. They are required for all threshold values, but in the case of the 16 and 32-byte thresholds, the requirement that the slot time criteria is met dominates. Any subsequent assertion of RDTREQ necessary to complete the transfer of the packet will occur after the RCVFW threshold is reached plus an additional 12 bytes. The table below also outlines the latency provided by the MACE device when the RDTREQ is asserted. Receive FIFO Watermarks, RDTREQ Assertion and Latency RCVFW [1-0] Bytes Required for First Assertion of RDTREQ Bytes of Latency After First Assertion of RDTREQ Bytes Required for Subsequent Assertion of RDTREQ Bytes of Latency After Subsequent Assertion of RDTREQ 00 64 64 28 100 01 64 64 44 84 10 76 52 76 52 11 XX XX XX XX Receive FIFO-Burst Operation The RCVFIFO also provides a burst mode capability, programmed by the RCVBRST bit in the FIFO Configuration Control register, to modify the operation of RDTREQ.The assertion of RDTREQ will occur according to the programming of the RCVFW bits. RDTREQ will be de-asserted when the RCVFIFO can only provide a single read cycle (one word read). This allows the external device to burst data from the RCVFIFO once RDTREQ is asser