Am79C961A 10BASE-T Am79C961 10BASE2 10BASE5 10BASE-F 144-TQFP Am79C960 IOCS16 - Datasheet Archive

 

PCnetTM-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA DISTINCTIVE CHARACTERISTICS s Single-chip Ethernet

 

Am79C961A Am79C961A PCnetTM-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA DISTINCTIVE CHARACTERISTICS s Single-chip Ethernet controller for the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) buses s Look Ahead Packet Processing (LAPP) allows protocol analysis to begin before end of receive frame s Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards s Supports 4 DMA channels on chip s Supports full duplex operation on the 10BASE-T 10BASE-T, AUI, and GPSI ports s Supports 16 boot PROM locations s Direct interface to the ISA or EISA bus s Pin compatible to Am79C961 Am79C961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller s Software compatible with AMD's Am7990 LANCE register and descriptor architecture s Low power, CMOS design with sleep mode allows reduced power consumption for critical battery powered applications s Individual 136-byte transmit and 128-byte receive FIFOs provide packet buffering for increased system latency, and support the following features: s Supports 16 I/O locations s Provides integrated Attachment Unit Interface (AUI) and 10BASE-T 10BASE-T transceiver with 2 modes of port selection: - Automatic selection of AUI or 10BASE-T 10BASE-T - Software selection of AUI or 10BASE-T 10BASE-T s Automatic Twisted Pair receive polarity detection and automatic correction of the receive polarity s Supports bus-master, programmed I/O, and shared-memory architectures to fit in any PC application s Supports edge and level-sensitive interrupts - Automatic retransmission with no FIFO reload s DMA Buffer Management Unit for reduced CPU intervention which allows higher throughput by by-passing the platform DMA - Automatic receive stripping and transmit padding (individually programmable) s JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test - Automatic runt packet rejection s Integrated Manchester Encoder/Decoder - Automatic deletion of received collision frames s Supports the following types of network interfaces: s Dynamic transmit FCS generation programmable on a frame-by-frame basis s Single +5 V power supply s Internal/external loopback capabilities s Supports 8K, 16K, 32K, and 64K Boot PROMs or Flash for diskless node applications s Supports Microsoft's Plug and Play System configuration for jumperless designs s Supports staggered AT bus drive for reduced noise and ground bounce s Integrated Magic PacketTM support for remote wake up of Green PCs s Supports 8 interrupts on chip - AUI to external 10BASE2 10BASE2, 10BASE5 10BASE5, 10BASE-T 10BASE-T or 10BASE-F 10BASE-F MAU - Internal 10BASE-T 10BASE-T transceiver with Smart Squelch to Twisted Pair medium s Supports LANCE General Purpose Serial Interface (GPSI) s 132-pin PQFP and 144-pin TQFP packages s Supports Shared Memory and PIO modes s Supports PCMCIA mode (144-TQFP 144-TQFP version only) s Support for operation in industrial temperature range (­40°C to +85°C) available in both packages Publication# 19364 Rev: D Amendment/0 Issue Date: March 2000 GENERAL DESCRIPTION The PCnet-ISA II controller, a single-chip Ethernet controller, is a highly integrated system solution for the PC-AT Industry Standard Architecture (ISA) architecture. It is designed to provide flexibility and compatibility with any existing PC application. This highly integrated VLSI device is specifically designed to reduce parts count and cost, and addresses applications where higher system throughput is desired. The PCnet-ISA II controller is fabricated with AMD's advanced low-power CMOS process to provide low standby current for power sensitive applications. The PCnet-ISA II controller can be configured into one of three different architecture modes to suit a particular PC application. In the Bus Master mode, all transfers are performed using the integrated DMA controller. This configuration enhances system performance by allowing the PCnet-ISA II controller to bypass the platform DMA controller and directly address the full 24-bit memory space. The implementation of Bus Master mode allows minimum parts count for the majority of PC applications. The PCnet-ISA II can also be configured as a Bus Slave with either a Shared Memory or Programmed I/O architecture for compatibility with low-end machines, such as PC/XTs that do not support Bus Masters, and high-end machines that require local packet buffering for increased system latency. The PCnet-ISA II controller is designed to directly interface with the ISA or EISA system bus. It contains an ISA Plug and Play bus interface unit, DMA Buffer Management Unit, 802.3 Media Access Control function, individual 136-byte transmit and 128-byte receive FIFOs, IEEE 802.3 defined Attachment Unit Interface (AUI), and a Twisted Pair Transceiver Media Attachment Unit. Full duplex network operation can be enabled on any of the device's network ports. The PCnet-ISA II controller is also register compatible with the LANCE (Am7990) Ethernet controller and PCnet-ISA (Am79C960 Am79C960). The DMA Buffer Management Unit supports the LANCE descriptor software model. External 2 remote boot and Ethernet physical address PROMs and Electrically Erasable Proms are also supported. This advanced Ethernet controller has the built-in capability of automatically selecting either the AUI port or the Twisted Pair transceiver. Only one interface is active at any one time. The individual 136-byte transmit and 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the embedded General Purpose Serial Interface (GPSI) allows direct access to/from the MAC. In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity and activity, or jabber status. The PCnet-ISA II controller also provides an External Address Detection InterfaceTM (EADITM) to allow external hardware address filtering in internetworking applications. For power sensitive applications where low stand-by current is desired, the device incorporates a sleep function to reduce over-all system power consumption, excellent for notebooks and Green PCs. In conjunction with this low power mode, the PCnet-ISA II controller also has integrated functions to support Magic Packet, an inexpensive technology that allows remote wake up of Green PCs. With the rise of embedded networking applications operating in harsh environments where temperatures may exceed the normal commercial temperature (0°C to +70°C) window, an industrial temperature (­40°C to +85°C) version is available in all two packages; 132-pin PQFP and 144-pin TQFP. The industrial temperature version of the PCnet-ISA II Ethernet controller is characterized across the industrial temperature range (­40°C to +85°C) within the published power supply specification (4.75 V to 5.25 V; i.e., ±5% VCC). Am79C961A Am79C961A BLOCK DIAGRAM: BUS MASTER MODE AEN DACK[3, 5­7] DRQ[3, 5­7] RCV FIFO IOCHRDY IOCS16 IOCS16 IOR IOW IRQ[3, 4, 5, 9, 10, 11, 12] MASTER MEMR ISA Bus Interface Unit 802.3 MAC Core CI+/­ Encoder/ Decoder (PLS) & AUI Port XMT FIFO MEMW DXCVR/EAR DI+/­ XTAL1 XTAL2 DO+/­ REF RXD+/­ RESET 10BASE-T 10BASE-T MAU SBHE BALE FIFO Control SD[0-15] LA[17-23] SA[0-19] SLEEP SHFBUSY EEDO EEDI EESK EECS IRQ15/APCS IRQ15/APCS Private Bus Control Buffer Management Unit TXD+/­ TXPD+/­ BPCS LED[0­3] PRDB[0­7] TDO JTAG Port Control EEPROM Interface Unit TMS TDI TCK DVDD[1-7] DVSS[1-13] AVDD[1-4] AVSS[1-2] 19364B-1 19364B-1 Am79C961A Am79C961A 3 TABLE OF CONTENTS Am79C961A Am79C961A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 BLOCK DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CONNECTION DIAGRAMS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PQFP 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 PIN DESIGNATIONS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PIN DESCRIPTION: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IEEE P996 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 BALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DACK 3, 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DRQ 3, 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IOCHRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IOCS16 IOCS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IRQ 3, 4, 5, 9, 10, 11, 12, 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 LA17-23 LA17-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 MASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 MEMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 MEMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 SA0-19 SA0-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 SBHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 SD0-15 SD0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 IRQ12/FlashWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 IRQ15/APCS IRQ15/APCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 BPCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 DXCVR/EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 LEDO-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 PRDB3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 PRDB2/EEDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 PRDB1/EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 PRDB0/EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 SHFBUSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 EECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 CONNECTION DIAGRAMS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PQFP 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 BLOCK DIAGRAM: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4 Am79C961A Am79C961A LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Listed by Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PIN DESCRIPTION: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IOCHRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IOCS16 IOCS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 IRQ3, 4, 5, 9, 10, 11, 12, 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 MEMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 MEMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 SA0-15 SA0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 SBHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 SD0-15 SD0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 APCS/IRQ15 APCS/IRQ15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 BPAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 BPCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 DXCVR/EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 LED0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PRAB0-15 PRAB0-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PRDB3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PRDB2/EEDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PRDB1/EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 PRDB0/EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SHFBUSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 EECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SMAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SROE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SRCS/IRQ12 SRCS/IRQ12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SRWE/WE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 PIN DESCRIPTION: NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DI+, DI­ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 RXD+, RXD­ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TXD+, TXD­ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TXP+, TXP­ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PIN DESCRIPTION: IEEE 1149.1 (JTAG) TEST ACCESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PIN DESCRIPTION: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AVDD1­4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Am79C961A Am79C961A 5 AVSS1­2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DVDD1­7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DVSS1­13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 TQFP 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . .35 Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . .36 Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 BLOCK DIAGRAM: PCMCIA MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Listed by Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PIN DESCRIPTION: PCMCIA MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 PCMCIA vs. ISA Pinout Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 PCMCIA Pin Specification Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 PCMCIA MODE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 PCMCIA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Serial EEPROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Flash Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Shared Memory vs. Programmed I/O Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 FLASH MEMORY MAP AND CARD REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Important Note About The EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Bus Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Auto-Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 ADDRESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 WRITE_DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 READ_DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Initiation Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Isolation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Hardware Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Software Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Plug and Play Card Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Plug and Play Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . .54 DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Important Note About The EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Basic EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 AMD Device Driver Compatible EEPROM Byte Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Plug and Play Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 PCnet­ISA II's Legacy Bit Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Plug & Play Register Locations Detailed Description (Refer to the Plug & Play Register Map above) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 6 Am79C961A Am79C961A Vendor Defined Byte (PnP 0xF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Checksum Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Use Without EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 External Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Optional IEEE Address PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 EISA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 1. Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 2. Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3. FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Buffer Management Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Descriptor Ring Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Transmit Descriptor Table Entry (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Receive Descriptor Table Entry (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Differential Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Twisted Pair Transceiver (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Full Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 EADI (External Address Detection Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Am79C961A Am79C961A 7 Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Access Operations (Software) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 I/O Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 IEEE Address Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Boot PROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Static RAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Bus Cycles (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Address PROM Cycles External PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Address PROM Cycles Using EEPROM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Ethernet Controller Register Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 MAGIC PACKET OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Magic Packet Mode Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Magic Packet Receive Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 PCNET-ISA II CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 RAP: Register Address Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 CSR0: PCnet-ISA II Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 CSR1: IADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 CSR2: IADR[23:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 CSR5: Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 CSR6: RCV/XMT Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 CSR8: Logical Address Filter, LADRF[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 CSR9: Logical Address Filter, LADRF[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 CSR10 CSR10: Logical Address Filter, LADRF[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 CSR11 CSR11: Logical Address Filter, LADRF[63:48] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 CSR12 CSR12: Physical Address Register, PADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 CSR13 CSR13: Physical Address Register, PADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 CSR14 CSR14: Physical Address Register, PADR[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 CSR15 CSR15: Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 CSR16 CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 CSR17 CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 CSR18-19 CSR18-19: Current Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 CSR20-21 CSR20-21: Current Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 CSR22-23 CSR22-23: Next Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR24-25 CSR24-25: Base Address of Receive Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR26-27 CSR26-27: Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR28-29 CSR28-29: Current Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR30-31 CSR30-31: Base Address of Transmit Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8 Am79C961A Am79C961A CSR32-33 CSR32-33: Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR34-35 CSR34-35: Current Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR36-37 CSR36-37: Next Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR38-39 CSR38-39: Next Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR40-41 CSR40-41: Current Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CSR42-43 CSR42-43: Current Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CSR44-45 CSR44-45: Next Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CSR46 CSR46: Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CSR47 CSR47: Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CSR48-49 CSR48-49: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CSR50-51 CSR50-51: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 CSR52-53 CSR52-53: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR54-55 CSR54-55: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR56-57 CSR56-57: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR58-59 CSR58-59: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR60-61 CSR60-61: Previous Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR62-63 CSR62-63: Previous Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR64-65 CSR64-65: Next Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR66-67 CSR66-67: Next Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 CSR70-71 CSR70-71: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 CSR72 CSR72: Receive Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 CSR74 CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 CSR76 CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 CSR78 CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 CSR80 CSR80: Burst and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 CSR82 CSR82: Bus Activity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 CSR84-85 CSR84-85: DMA Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 CSR86 CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 CSR88-89 CSR88-89: Chip ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 CSR92 CSR92: Ring Length Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 CSR94 CSR94: Transmit Time Domain Reflectometry Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 CSR96-97 CSR96-97: Bus Interface Scratch Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 CSR98-99 CSR98-99: Bus Interface Scratch Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 CSR104-105 CSR104-105: SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 CSR108-109 CSR108-109: Buffer Management Scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 CSR112 CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 CSR114 CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 CSR124 CSR124: Buffer Management Unit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 ISACSR0: Master Mode Read Active/SRAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 ISACSR1: Master Mode Write Active/SRAM Address Pointer . . . . . . . . . . . . . . . . . . . . . . . .114 ISACSR2: Miscellaneous Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 ISACSR3: EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 ISACSR4: LED0 Status (Link Integrity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 ISACSR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 ISACSR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ISACSR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 ISACSR8: Software Configuration Register (Read-Only Register) . . . . . . . . . . . . . . . . . . . . .120 ISACSR9: Miscellaneous Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 RMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 RMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 RMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Am79C961A Am79C961A 9 RMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 TMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 TMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 TMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 TMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Ethernet Controller Registers (Accessed via RDP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 ISACSR-ISA Bus Configuration Registers (Accessed via IDP Port) . . . . . . . . . . . . . . . . . .128 SYSTEM APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Compatibility Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Optional Address PROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Boot PROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Static RAM Interface (for Shared Memory Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 10BASE-T 10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 SWITCHING CHARACTERISTICS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 SWITCHING CHARACTERISTICS: BUS MASTER MODE-FLASH READ CYCLE . . . . . . . . . . 140 SWITCHING CHARACTERISTICS: BUS MASTER MODE-FLASH WRITE CYCLE . . . . . . . . . .140 SWITCHING CHARACTERISTICS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . 141 SWITCHING CHARACTERISTICS: SHARED MEMORY MODE-FLASH READ CYCLE . . . . . .144 SWITCHING CHARACTERISTICS: SHARED MEMORY MODE-FLASH WRITE CYCLE . . . . . .144 SWITCHING CHARACTERISTICS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . .145 SWITCHING CHARACTERISTICS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 SWITCHING CHARACTERISTICS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 SWITCHING CHARACTERISTICS: 10BASE-T 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . .148 SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 SWITCHING WAVEFORMS: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 SWITCHING WAVEFORMS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 SWITCHING WAVEFORMS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 SWITCHING WAVEFORMS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .173 SWITCHING WAVEFORMS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 SWITCHING WAVEFORMS: 10BASE-T 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 PQB132 PQB132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 PQB132 PQB132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 PCnet-ISA II Compatible Media Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . .183 PCNET-ISA II COMPATIBLE 10BASE-T 10BASE-T FILTERS AND TRANSFORMERS . . . . . . . . . . . . . . . . .183 PCNET-ISA II COMPATIBLE AUI ISOLATION TRANSFORMERS . . . . . . . . . . . . . . . . . . . . . . . . .183 PCNET-ISA II COMPATIBLE DC/DC CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 MANUFACTURER CONTACT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 10 Am79C961A Am79C961A Layout Recommendations for Reducing Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 DECOUPLING LOW-PASS R/C FILTER DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Digital Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Analog Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 AVSS1 and AVDD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 AVSS2 and AVDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 AVSS2 and AVDD2/AVDD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 Sample Plug and Play Configuration Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 SAMPLE CONFIGURATION FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Alternative Method for Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 Introduction of the Look-Ahead Packet Processing (LAPP) Concept . . . . . . . . . .191 Outline of the LAPP Flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 SETUP: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 FLOW: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 LAPP Enable Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 LAPP Enable Rules for Parsing of Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 Some Characteristics of the XXC56 XXC56 Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . .201 SWITCHING CHARACTERISTICS OF A TYPICAL XXC56 XXC56 SERIAL EEPROM INTERFACE . . . .201 INSTRUCTION SET FOR THE XXC56 XXC56 SERIES OF EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . .202 Am79C961A Am79C961A PCnet-ISA II Silicon Errata Report . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 AM79C961A AM79C961A REV FD SILICON STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Am79C961A Am79C961A 11 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C961A AM79C961A K C \W ALTERNATE PACKAGING OPTION \W=Trimmed and Formed (PQB132 PQB132) OPTIONAL PROCESSING Blank=Standard Processing TEMPERATURE RANGE C=Commercial (0°C to +70°C) I =Industrial (­40°C to +85°C) PACKAGE TYPE (per Prod. Nomenclature/16-038) K=132-pin Plastic Quad Flat Pack (PQR132 PQR132) V=144-pin Thin Quad Flat Package (PQT144 PQT144) SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am79C961A Am79C961A PCnet-ISA II Jumperless Single-Chip Ethernet Controller for ISA Valid Combinations Valid Combinations KC, KC\W AM79C961A AM79C961A VC, VC\W Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. KI, KI\W AM79C961A AM79C961A VI, VI\W 12 Am79C961A Am79C961A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 DVSS3 MASTER DRQ7 DRQ6 DRQ5 DVSS10 DVSS10 DACK7 DACK6 DACK5 LA17 LA18 LA19 LA20 DVSS4 LA21 LA22 LA23 SBHE DVDD3 SA0 SA1 SA2 DVSS5 SA3 SA4 SA5 SA6 SA7 SA8 SA9 DVSS6 SA10 SA11 DVDD4 SA12 SA13 SA14 SA15 DVSS7 SA16 SA17 SA18 SA19 AEN IOCHRDY MEMW MEMR DVSS11 DVSS11 IRQ15/APCS IRQ15/APCS IRQ12/FLASHWE IRQ12/FLASHWE IRQ11 IRQ11 DVDD5 IRQ10 IRQ10 IOCS16 IOCS16 BALE IRQ3 IRQ4 IRQ5 REF DVSS12 DVSS12 DRQ3 DACK3 IOR IOW IRQ9 RESET 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 DVDD2 TCK TMS TDO TDI EECS BPCS SHFBUSY PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 DVSS2 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 DXCVR/EAR AVDD2 CI+ CI­ DI+ DI­ AVDD1 DO+ DO­ AVSS1 CONNECTION DIAGRAMS: BUS MASTER MODE PQFP 132 Am79C961AKC Am79C961AKC Am79C961A Am79C961A 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXPD+ TXD­ TXPD­ AVDD4 RXD+ RXD­ DVSS13 DVSS13 SD15 SD7 SD14 SD6 DVSS9 SD13 SD5 SD12 SD4 DVDD7 SD11 SD3 SD10 SD2 DVSS8 SD9 SD1 SD8 SD0 SLEEP DVDD6 19364B-2 19364B-2 13 PIN DESIGNATIONS: BUS MASTER MODE Listed by Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 DVSS3 34 DVDD4 67 DVDD6 100 AVSS1 2 MASTER 35 SA12 68 SLEEP 101 DO­ 3 DRQ7 36 SA13 69 SD0 102 DO+ 4 DRQ6 37 SA14 70 SD8 103 AVDD1 5 DRQ5 38 SA15 71 SD1 104 DI­ 6 DVSS10 DVSS10 39 DVSS7 72 SD9 105 DI+ 7 DACK7 40 SA16 73 DVSS8 106 CI­ 8 DACK6 41 SA17 74 SD2 107 CI+ 9 DACK5 42 SA18 75 SD10 108 AVDD2 10 LA17 43 SA19 76 SD3 109 DXCVR/EAR 11 LA18 44 AEN 77 SD11 110 LED3 12 LA19 45 IOCHRDY 78 DVDD7 111 LED2 13 LA20 46 MEMW 79 SD4 112 DVSS1 14 DVSS4 47 MEMR 80 SD12 113 LED1 15 LA21 48 DVSS11 DVSS11 81 SD5 114 LED0 16 LA22 49 IRQ15/APCS IRQ15/APCS 82 SD13 115 DVDD1 17 LA23 50 IRQ12/FlashWE 83 DVSS9 116 PRDB7 18 SBHE 51 IRQ11 IRQ11 84 SD6 117 PRDB6 19 DVDD3 52 DVDD5 85 SD14 118 PRDB5 20 SA0 53 IRQ10 IRQ10 86 SD7 119 PRDB4 21 SA1 54 IOCS16 IOCS16 87 SD15 120 DVSS2 22 SA2 55 BALE 88 DVSS13 DVSS13 121 PRDB3 23 DVSS5 56 IRQ3 89 RXD­ 122 PRDB2/EEDO 24 SA3 57 IRQ4 90 RXD+ 123 PRDB1/EEDI 25 SA4 58 IRQ5 91 AVDD4 124 PRDB0/EESK 26 SA5 59 REF 92 TXPD­ 125 SHFBUSY 27 SA6 60 DVSS12 DVSS12 93 TXD­ 126 BPCS 28 SA7 61 DRQ3 94 TXPD+ 127 EECS 29 SA8 62 DACK3 95 TXD+ 128 TDI 30 SA9 63 IOR 96 AVDD3 129 TDO 31 DVSS6 64 IOW 97 XTAL1 130 TMS 32 SA10 65 IRQ9 98 AVSS2 131 TCK 33 SA11 66 RESET 99 XTAL2 132 DVDD2 14 Am79C961A Am79C961A PIN DESIGNATIONS: BUS MASTER MODE Listed by Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. AEN 44 DVSS12 DVSS12 60 LED2 111 SA6 27 AVDD1 103 DVSS13 DVSS13 88 LED3 110 SA7 28 AVDD2 108 DVSS2 120 MASTER 2 SA8 29 AVDD3 96 DVSS3 1 MEMR 47 SA9 30 AVDD4 91 DVSS4 14 MEMW 46 SBHE 18 AVSS1 100 DVSS5 23 PRDB0/EESK 124 SD0 69 AVSS2 98 DVSS6 31 PRDB1/EEDI 123 SD1 71 BALE 55 DVSS7 39 PRDB2/EEDO 122 SD10 75 BPCS 126 DVSS8 73 PRDB3 121 SD11 77 CI­ 106 DVSS9 83 PRDB4 119 SD12 80 CI+ 107 DXCVR/EAR 109 PRDB5 118 SD13 82 DACK3 62 EECS 127 PRDB6 117 SD14 85 DACK5 9 IOCHRDY 45 PRDB7 116 SD15 87 DACK6 8 IOCS16 IOCS16 54 REF 59 SD2 74 DACK7 7 IOR 63 RESET 66 SD3 76 DI­ 104 IOW 64 RXD­ 89 SD4 79 DI+ 105 IRQ10 IRQ10 53 RXD+ 90 SD5 81 DO­ 101 IRQ11 IRQ11 51 SA0 20 SD6 84 DO+ 102 IRQ12/FlashWE 50 SA1 21 SD7 86 DRQ3 61 IRQ15/APCS IRQ15/APCS 49 SA10 32 SD8 70 DRQ5 5 IRQ3 56 SA11 33 SD9 72 DRQ6 4 IRQ4 57 SA12 35 SHFBUSY 125 DRQ7 3 IRQ5 58 SA13 36 SLEEP 68 DVDD1 115 IRQ9 65 SA14 37 TCK 131 DVDD2 132 LA17 10 SA15 38 TDI 128 DVDD3 19 LA18 11 SA16 40 TDO 129 DVDD4 34 LA19 12 SA17 41 TMS 130 DVDD5 52 LA20 13 SA18 42 TXD­ 93 DVDD6 67 LA21 15 SA19 43 TXD+ 95 DVDD7 78 LA22 16 SA2 22 TXPD­ 92 DVSS1 112 LA23 17 SA3 24 TXPD+ 94 DVSS10 DVSS10 6 LED0 114 SA4 25 XTAL1 97 DVSS11 DVSS11 48 LED1 113 SA5 26 XTAL2 99 Am79C961A Am79C961A 15 PIN DESIGNATIONS: BUS MASTER MODE Listed by Group Pin Name Pin Function I/O Driver ISA Bus Interface AEN Address Enable I BALE Bus Address Latch Enable I DACK[3, 5­7] DMA Acknowledge I DRQ[3, 5­7] DMA Request I/O TS3 IOCHRDY I/O Channel Ready I/O OD3 IOCS16 IOCS16 I/O Chip Select 16 O OD3 IOR I/O Read Select I IOW I/O Write Select I IRQ[3, 4, 5, 9, 10, 11, 12, 15] Interrupt Request O LA[17-23] Unlatched Address Bus I/O TS3 MASTER Master Transfer in Progress O OD3 MEMR Memory Read Select O TS3 MEMW Memory Write Select O TS3 REF Memory Refresh Active I RESET System Reset I SA[0 ­19] System Address Bus I/O TS3 SBHE System Byte High Enable I/O TS3 SD[0 ­15] System Data Bus I/O TS3 O TS1 O TS1 I/O TS1 O TS2 O TS2 O TS2 O TS2 I/O TS1 TS3/OD3 Board Interfaces IRQ15/APCS IRQ15/APCS IRQ15 IRQ15 or Address PROM Chip Select BPCS Boot PROM Chip Select DXCVR/EAR Disable Transceiver LED0 LED0/LNKST LED1 LED1/SFBD/RCVACT LED2 LED2/SRD/RXDATPOL LED3 LED3/SRDCLK/XMTACT PRDB[3­7] PROM Data Bus SLEEP Sleep Mode XTAL1 Crystal Input XTAL2 Crystal Output SHFBUSY Read access from EEPROM in process PRDB(0)/EESK Serial Shift Clock PRDB(1)/EEDI Serial Shift Data In PRDB(2)/EEDO Serial Shift Data Out EECS EEPROM Chip Select 16 I I Am79C961A Am79C961A O I/O I/O I/O O PIN DESIGNATIONS: BUS MASTER MODE (continued) Listed by Group Pin Name Pin Function I/O Collision Inputs Driver I Attachment Unit Interface (AUI) CI± DI± Receive Data I DO± Transmit Data O 10BASE-T 10BASE-T Receive Data I 10BASE-T 10BASE-T Transmit Data O 10BASE-T 10BASE-T Predistortion Control O Twisted Pair Transceiver Interface (10BASE-T 10BASE-T) RXD± TXD± TXPD± IEEE 1149.1 Test Access Port Interface (JTAG) TCK Test Clock I TDI Test Data Input I TDO Test Data Output O TMS Test Mode Select I TS2 Power Supplies AVDD Analog Power [1-4] AVSS Analog Ground [1-2] DVDD Digital Power [1-7] DVSS Digital Ground [1-13] Output Driver Types Name Type IOL (mA) IOH (mA) pF TS1 Tri-State 4 ­1 50 TS2 Tri-State 12 ­4 50 TS3 Tri-State 24 ­3 120 OD3 Open Drain 24 ­3 120 Am79C961A Am79C961A 17 PIN DESCRIPTION: BUS MASTER MODE These pins are part of the bus master mode. In order to understand the pin descriptions, definition of some terms from a draft of IEEE P996 are included. IEEE P996 Terminology Alternate Master: Any device that can take control of the bus through assertion of the MASTER signal. It has the ability to generate addresses and bus control signals in order to perform bus operations. All Alternate Masters must be 16 bit devices and drive SBHE. Bus Ownership: The Current Master possesses bus ownership and can assert any bus control, address and data lines. Current Master: The Permanent Master, Temporary Master or Alternate Master which currently has ownership of the bus. between back-to-back DMA requests. See the Back-to-Back DMA Requests section for details. Because of the operation of the Plug and Play registers, the DMA Channels on the PCnet-ISA II must be attached to the specific DRQ and DACK signals on the PC/AT bus as indicated by the pin names. IOCHRDY I/O Channel Ready Input/Output When the PCnet-ISA II controller is being accessed, IOCHRDY HIGH indicates that valid data exists on the data bus for reads and that data has been latched for writes. When the PCnet-ISA II controller is the Current Master on the ISA bus, it extends the bus cycle as long as IOCHRDY is LOW. IOCS16 IOCS16 I/O Chip Select 16 Output Permanent Master: Each P996 bus will have a device known as the Permanent Master that provides certain signals and bus control functions as described in Section 3.5 (of the IEEE P996 spec.), "Permanent Master". The Permanent Master function can reside on a Bus Adapter or on the backplane itself. When an I/O read or write operation is performed, the PCnet-ISA II controller will drive the IOCS16 IOCS16 pin LOW to indicate that the chip supports a 16-bit operation at this address. (If the motherboard does not receive this signal, then the motherboard will convert a 16-bit access to two 8-bit accesses). Temporary Master: A device that is capable of generating a DMA request to obtain control of the bus and directly asserting only the memory and I/O strobes during bus transfer. Addresses are generated by the DMA device on the Permanent Master. The PCnet-ISA II controller follows the IEEE P996 specification that recommends this function be implemented as a pure decode of SA0-9 and AEN, with no dependency on IOR, or IOW; however, some PC/AT clone systems are not compatible with this approach. For this reason, the PCnet-ISA II controller is recommended to be configured to run 8-bit I/O on all machines. Since data is moved by memory cycles there is virtually no performance loss incurred by running 8-bit I/O and compatibility problems are virtually eliminated. The PCnet-ISA II controller can be configured to run 8-bit-only I/O by clearing Bit 0 in Plug and Play register F0. ISA Interface AEN Address Enable Input This signal must be driven LOW when the bus performs an I/O access to the device. BALE IOR Used to latch the LA20­23 address lines. I/O Read DACK 3, 5-7 DMA Acknowledge Input Asserted LOW when the Permanent Master acknowledges a DMA request. When DACK is asserted the PCnet-ISA II controller becomes the Current Master by asserting the MASTER signal. I/O Write Input/Output When the PCnet-ISA II controller needs to perform a DMA transfer, it asserts DRQ. The Permanent Master acknowledges DRQ with the assertion of DACK. When the PCnet-ISA II does not need the bus it desserts DRQ. The PCnet-ISA II provides for fair bus bandwidth sharing between two bus mastering devices on the ISA bus through an adaptive delay which is inserted 18 IOR is driven LOW by the host to indicate that an Input/ Output Read operation is taking place. IOR is only valid if the AEN signal is LOW and the external address matches the PCnet-ISA II controller's predefined I/O address location. If valid, IOR indicates that a slave read operation is to be performed. IOW DRQ 3, 5-7 DMA Request Input Input IOW is driven LOW by the host to indicate that an Input/ Output Write operation is taking place. IOW is only valid if AEN signal is LOW and the external address matches the PCnet-ISA II controller's predefined I/O address location. If valid, IOW indicates that a slave write operation is to be performed. Am79C961A Am79C961A IRQ 3, 4, 5, 9, 10, 11, 12, 15 Interrupt Request (DRQ), the Ethernet controller asserts the MASTER signal to indicate to the Permanent Master that the PCnet-ISA II controller is becoming the Current Master. Output An attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR, RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT. All status flags have a mask bit which allows for suppression of IRQ asser tion. These flags have the following meaning: MEMR Memory Read Input/Output MEMR goes LOW to perform a memory read operation. MEMW Memory Write Input/Output MEMW goes LOW to perfor m a memor y wr ite operation. BABL Babble RCVCCO Receive Collision Count Overflow JAB Jabber REF MISS Missed Frame MERR Memory Error MPCO Missed Packet Count Overflow RINT Receive Interrupt IDON Initialization Done TXDATSTRT Transmit Start Memory Refresh Input When REF is asserted, a memory refresh is active. The PCnet-ISA II controller uses this signal to mask inadvertent DMA Acknowledge assertion during memory refresh periods. If DACK is asserted when REF is active, DACK assertion is ignored. REF is monitored to eliminate a bus arbitration problem observed on some ISA platforms. Because of the operation of the Plug and Play registers, the interrupts on the PCnet-ISA II must be attached to specific IRQ signals on the PC/AT bus. LA17-23 LA17-23 Unlatched Address Bus Input/Output The unlatched address bus is driven by the PCnet-ISA II controller during bus master cycle. The functions of these unlatched address pins will change when GPSI mode is invoked. The following table shows the pin configuration in GPSI mode. Please refer to the section on General Purpose Serial Interface for detailed information on accessing this mode. Pin Number Pin Function in Bus Master Mode Pin Function in GPSI Mode 10 LA17 RXDAT 11 LA18 SRDCLK 12 LA19 RXCRS 13 LA20 CLSN 15 LA21 STDCLK 16 LA22 TXEN 17 LA23 TXDAT RESET Reset Input When RESET is asserted HIGH the PCnet-ISA II controller performs an internal system reset. RESET must be held for a minimum of 10 XTAL1 periods before being deasserted. While in a reset state, the PCnet-ISA II controller will tristate or deassert all outputs to predefined reset levels. The PCnet-ISA II controller resets itself upon power-up. SA0-19 SA0-19 System Address Bus Input/Output This bus contains address information, which is stable during a bus operation, regardless of the source. SA17-19 SA17-19 contain the same values as the unlatched address LA17-19 LA17-19. When the PCnet-ISA II controller is the Current Master, SA0-19 SA0-19 will be driven actively. When the PCnet-ISA II controller is not the Current Master, the SA0-19 SA0-19 lines are continuously monitored to determine if an address match exists for I/O slave transfers or Boot PROM accesses. SBHE System Byte High Enable Input/Output This signal indicates the high byte of the system data bus is to be used. SBHE is driven by the PCnet-ISA II controller when performing bus mastering operations. MASTER Master Mode Input/Output This signal indicates that the PCnet-ISA II controller has become the Current Master of the ISA bus. After the PCnet-ISA II controller has received a DMA Acknowledge (DACK) in response to a DMA Request SD0-15 SD0-15 System Data Bus Input/Output These pins are used to transfer data to and from the PCnet-ISA II controller to system resources via the ISA data bus. SD0-15 SD0-15 is driven by the PCnet-ISA II control- Am79C961A Am79C961A 19 ler when performing bus master writes and slave read operations. Likewise, the data on SD0-15 SD0-15 is latched by the PCnet-ISA II controller when performing bus master reads and slave write operations. Board Interface IRQ12/FlashWE Flash Write Enable Output Optional interface to the Flash memory boot PROM Write Enable. IRQ15/APCS IRQ15/APCS Address PROM Chip Select Output When programmed as APCS in Plug and Play Register F0, this signal is asserted when the external Address PROM is read. When an I/O read operation is performed on the first 16 bytes in the PCnet-ISA II controller's I/O space, APCS is asserted. The outputs of the external Address PROM drive the PROM Data Bus. The PCnet-ISA II controller buffers the contents of the PROM data bus and drives them on the lower eight bits of the System Data Bus. If EADI mode is selected, this pin becomes the EAR input. The incoming frame will be checked against the internally active address detection mechanisms and the result of this check will be OR'd with the value on the EAR pin. The EAR pin is defined as REJECT. (See the EADI section for details regarding the function and timing of this signal). LEDO-3 LED Drivers Output These pins sink 12 mA each for driving LEDs. Their meaning is software configurable (see section The ISA Bus Configuration Registers) and they are active LOW. When EADI mode is selected, the pins named LED1, LED2, and LED3 change in function while LED0 continues to indicate 10BASE-T 10BASE-T Link Status. LED 1 Boot PROM Chip Select Output This signal is asserted when the Boot PROM is read. If SA0-19 SA0-19 lines match a predefined address block and MEMR is active and REF inactive, the BPCS signal will be asserted. The outputs of the external Boot PROM drive the PROM Data Bus. The PCnet-ISA II controller buffers the contents of the PROM data bus and drives them on the lower eight bits of the System Data Bus. DXCVR/EAR 3 SRDCLK Private Data Bus Input/Output This is the data bus for the Boot PROM and the Address PROM. PRDB2/EEDO Private data bus bit 2/Data Out Input/Output A multifunction pin which serves as PRDB2 of the private data bus and, when ISACSR3 bit 4 is set, changes to become DATA OUT from the EEPROM. PRDB1/EEDI Input/Output This pin can be used to disable external transceiver circuitry attached to the AUI interface when the internal 10BASE-T 10BASE-T port is active. The polarity of this pin is set by the DXCVRP bit (PnP register 0xF0, bit 5). When DXCVRP is cleared (default), the DXCVR pin is driven HIGH when the Twisted Pair port is active or SLEEP mode has been entered and driven LOW when the AUI port is active. When DXCVRP is set, the DXCVR pin is driven LOW when the Twisted Pair port is active or SLEEP mode has been entered and driven HIGH when the AUI port is active. 20 SRD PRDB3-7 BPCS Disable Transceiver/ External Address Reject SF/BD 2 When programmed to IRQ15 IRQ15 (default), this pin has the same function as IRQ 3, 4, 5, 9, 10, 11, or 12. EADI Function Private data bus bit 1/Data In Input/Output A multifunction pin which serves as PRDB1 of the private data bus and, when ISACSR3 bit 4 is set, changes to become DATA In to the EEPROM. PRDB0/EESK Private data bus bit 0/ Serial Clock Input/Output A multifunction pin which serves as PRDB0 of the private data bus and, when ISACSR3 bit 4 is set, changes to become Serial Clock to the EEPROM. Am79C961A Am79C961A SHFBUSY Shift Busy Input/Output This pin indicates that a read from the external EEPROM is in progress. It is active only when data is being shifted out of the EEPROM due to a hardware RESET or assertion of the EE_LOAD bit (ISACSR3, bit 14). If this pin is left unconnected or pulled low with a pull-down resistor, an EEPROM checksum error is forced. Normally, this pin should be connected to VCC through a 10K pull-up resistor. EECS EEPROM CHIP SELECT Output This signal is asserted when read or write accesses are being performed to the EEPROM. It is controlled by ISACSR3. It is driven at Reset during EEPROM Read. SLEEP Sleep Input When SLEEP pin is asserted (active LOW), the PCnet-ISA II controller performs an internal system reset and proceeds into a power savings mode. All outputs will be placed in their normal reset condition. All PCnet-ISA II controller inputs will be ignored except for the SLEEP pin itself. Deassertion of SLEEP results in the device waking up. The system must delay the starting of the network controller by 0.5 seconds to allow internal analog circuits to stabilize. XTAL1 Crystal Connection Input The internal clock generator uses a 20 MHz crystal that is attached to pins XTAL1 and XTAL2. Alternatively, an external 20 MHz CMOS-compatible clock signal can be used to drive this pin. Refer to the section on External Crystal Characteristics for more details. XTAL2 Crystal Connection Output The internal clock generator uses a 20 MHz crystal that is attached to pins XTAL1 and XTAL2. If an external clock is used, this pin should be left unconnected. Am79C961A Am79C961A 21 DVDD4 PRAB12 PRAB12 PRAB13 PRAB13 PRAB14 PRAB14 PRAB15 PRAB15 DVSS7 SA13 SA14 SA15 SRWE AEN IOCHRDY MEMW MEMR DVSS11 DVSS11 APCS/IRQ15 APCS/IRQ15 SRCS/IRQ12 SRCS/IRQ12 IRQ11 IRQ11 DVDD5 IRQ10 IRQ10 IOCS16 IOCS16 BPAM IRQ3 IRQ4 IRQ5 REF DVSS12 DVSS12 SROE SMAM IOR IOW IRQ9 RESET 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 DVDD2 TCK TMS TDO TDI EECS BPCS SHFBUSY PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 DVSS2 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 DXCVR/EAR AVDD2 CI+ CI­ DI+ DI­ AVDD1 DO+ DO­ AVSS1 CONNECTION DIAGRAMS: BUS SLAVE MODE PQFP 132 DVSS3 SMA SA0 SA1 SA2 DVSS10 DVSS10 SA3 SA4 SA5 SA6 SA7 SA8 SA9 DVSS4 SA10 SA11 SA12 SBHE DVDD3 PRAB0 PRAB1 PRAB2 DVSS5 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 DVSS6 PRAB10 PRAB10 PRAB11 PRAB11 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Am79C961AKC Am79C961AKC Am79C961A Am79C961A 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXPD+ TXD­ TXPD­ AVDD4 RXD+ RXD­ DVSS13 DVSS13 SD15 SD7 SD14 SD6 DVSS9 SD13 SD5 SD12 SD4 DVDD7 SD11 SD3 SD10 SD2 DVSS8 SD9 SD1 SD8 SD0 SLEEP DVDD6 19364B-3 19364B-3 BLOCK DIAGRAM: BUS SLAVE MODE AEN RCV FIFO IOCHRDY 802.3 MAC Core IOR IOW IRQ[3, 4, 5, 9, 10, 11, 12] IOCS16 IOCS16 MEMR DXCVR/EAR CI+/ISA Bus Interface Unit Encoder/ Decoder (PLS) & AUI Port XMT FIFO MEMW DI+/XTAL1 XTAL2 DO+/- REF RXD+/- RESET 10BASE-T 10BASE-T MAU SA[0-15] SBHE FIFO Control SD[0-15] Private Bus Control Buffer Management Unit SMA SLEEP BPAM SMAM SHFBUSY EEDO EEDI EESK EECS TXD+/TXPD+/- IRQ15/APCS IRQ15/APCS BPCS LED[0-3] PRAB[0-15] PRDB[0-7] SROE SRWE TDO JTAG Port Control EEPROM Interface Unit TMS TDI TCK DVDD[1-7] 19364B-4 19364B-4 DVSS[1-13] AVDD[1-4] AVSS[1-2] Am79C961A Am79C961A 23 PIN DESIGNATIONS: BUS SLAVE MODE Listed by Pin Number Pin # Name Pin # Name Pin # Name 1 DVSS3 45 IOCHRDY 89 RXD- 2 SMA 46 MEMW 90 RXD+ 3 SA0 47 MEMR 91 AVDD4 4 SA1 48 DVSS11 DVSS11 92 TXPD- 5 SA2 49 IRQ15 IRQ15 93 TXD- 6 DVSS10 DVSS10 50 IRQ12 IRQ12 94 TXPD+ 7 SA3 51 IRQ11 IRQ11 95 TXD+ 8 SA4 52 DVDD5 96 AVDD3 9 SA5 53 IRQ10 IRQ10 97 XTAL1 10 SA6 54 IOCS16 IOCS16 98 AVSS2 11 SA7 55 BPAM 99 XTAL2 12 SA8 56 IRQ3 100 AVSS1 13 SA9 57 IRQ4 101 DO- 14 DVSS4 58 IRQ5 102 DO+ 15 SA10 59 REF 103 AVDD1 16 SA11 60 DVSS12 DVSS12 104 DI- 17 SA12 61 SROE 105 DI+ 18 SBHE 62 SMAM 106 CI- 19 DVDD3 63 IOR 107 CI+ 20 PRAB0 64 IOW 108 AVDD2 21 PRAB1 65 IRQ9 109 DXCVR/EAR 22 PRAB2 66 RESET 110 LED3 23 DVSS5 67 DVDD6 111 LED2 24 PRAB3 68 SLEEP 112 DVSS1 25 PRAB4 69 SD0 113 LED1 26 PRAB5 70 SD8 114 LED0 27 PRAB6 71 SD1 115 DVDD1 28 PRAB7 72 SD9 116 PRDB7 29 PRAB8 73 DVSS8 117 PRDB6 30 PRAB9 74 SD2 118 PRDB5 31 DVSS6 75 SD10 119 PRDB4 32 PRAB10 PRAB10 76 SD3 120 DVSS2 33 PRAB11 PRAB11 77 SD11 121 PRDB3 34 78 DVDD7 122 PRDB2/EEDO PRAB12 PRAB12 79 SD4 123 PRDB1/EEDI 36 PRAB13 PRAB13 80 SD12 124 PRDB0/EESK 37 PRAB14 PRAB14 81 SD5 125 SHFBUSY 38 PRAB15 PRAB15 82 SD13 126 BPCS 39 DVSS7 83 DVSS9 127 EECS 40 SA13 84 SD6 128 TDI 41 SA14 85 SD14 129 TDO 42 SA15 86 SD7 130 TMS 43 SRWE 87 SD15 131 TCK 44 24 DVDD4 35 AEN 88 DVSS13 DVSS13 132 DVDD2 Am79C961A Am79C961A PIN DESIGNATIONS: BUS SLAVE MODE Listed by Pin Name Name Pin# Name Pin# Name Pin# AEN 44 IRQ15 IRQ15 49 SA13 40 AVDD1 103 IRQ3 56 SA14 41 AVDD2 108 IRQ4 57 SA15 42 AVDD3 96 IRQ5 58 SA2 5 AVDD4 91 IRQ9 65 SA3 7 AVSS1 100 LED0 114 SA4 8 AVSS2 98 LED1 113 SA5 9 BPAM 55 LED2 111 SA6 10 BPCS 126 LED3 110 SA7 11 CI- 106 MEMR 47 SA8 12 CI+ 107 MEMW 46 SA9 13 DI- 104 PRAB0 20 SBHE 18 DI+ 105 PRAB1 21 SD0 69 DO- 101 PRAB10 PRAB10 32 SD1 71 DO+ 102 PRAB11 PRAB11 33 SD10 75 DVDD1 115 PRAB12 PRAB12 35 SD11 77 DVDD2 132 PRAB13 PRAB13 36 SD12 80 DVDD3 19 PRAB14 PRAB14 37 SD13 82 DVDD4 34 PRAB15 PRAB15 38 SD14 85 DVDD5 52 PRAB2 22 SD15 87 DVDD6 67 PRAB3 24 SD2 74 DVDD7 78 PRAB4 25 SD3 76 DVSS1 112 PRAB5 26 SD4 79 DVSS10 DVSS10 6 PRAB6 27 SD5 81 DVSS11 DVSS11 48 PRAB7 28 SD6 84 DVSS12 DVSS12 60 PRAB8 29 SD7 86 DVSS13 DVSS13 88 PRAB9 30 SD8 70 DVSS2 120 PRDB0/DO 124 SD9 72 DVSS3 1 PRDB0/D1 123 SHFBUSY 125 DVSS4 14 PRDB0/SCLK 122 SLEEP 68 DVSS5 23 PRDB3 121 SMA 2 DVSS6 31 PRDB4 119 SMAM 62 DVSS7 39 PRDB5 118 SROE 61 DVSS8 73 PRDB6 117 SRWE 43 DVSS9 83 PRDB7 116 TCK 131 DXCVR/EAR 109 REF 59 TDI 128 EECS 127 RESET 66 TDO 129 IOCHRDY 45 RXD- 89 TMS 130 IOCS16 IOCS16 54 RXD+ 90 TXD- 93 IOR 63 SA0 3 TXD+ 95 IOW 64 SA1 4 TXPD- 92 IRQ10 IRQ10 53 SA10 15 TXPD+ 94 IRQ11 IRQ11 51 SA11 16 XTAL1 97 IRQ12 IRQ12 50 SA12 17 XTAL2 99 Am79C961A Am79C961A 25 PIN DESIGNATIONS: BUS SLAVE MODE Listed by Group Pin Name Pin Function I/O Driver ISA Bus Interface AEN Address Enable I IOCHRDY I/O Channel Ready O OD3 IOCS16 IOCS16 I/O Chip Select 16 O OD3 IOR I/O Read Select I IOW I/O Write Select I IRQ[3, 4, 5, 9, 10, 11, 12, 15] Interrupt Request O MEMR Memory Read Select I MEMW Memory Write Select I REF Memory Refresh Active I RESET System Reset I SA[0­15] System Address Bus I TS3/OD3 SBHE System Byte High Enable SD[0­15] System Data Bus I/O I TS3 IRQ15/APCS IRQ15/APCS IRQ15 IRQ15 or Address PROM Chip Select O TS1 BPCS Boot PROM Chip Select O TS1 BPAM Boot PROM Address Match I DXCVR/EAR Disable Transceiver I/O TS1 LED0 LED0/LNKST O TS2 LED1 LED1/SFBD/RCVACT O TS2 LED2 LED2/SRD/RXDATD01 LED2/SRD/RXDATD01 O TS2 LED3 LED3/SRDCLK/XMTACT O TS2 PRAB[0­15] PRivate Address Bus I/O TS3 PRDB[3­7] PRivate Data Bus I/O TS1 SLEEP Sleep Mode I SMA Slave Mode Architecture I SMAM Shared Memory Address Match I SROE Static RAM Output Enable O TS3 SRWE Static RAM Write Enable O TS1 XTAL1 Crystal Oscillator Input I XTAL2 Crystal Oscillator OUTPUT O Board Interfaces SHFBUSY Read access from EEPROM in process O PRDB(0)/EESK Serial Shift Clock I/O PRDB(1)/EEDI Serial Shift Data In I/O PRDB(2)/EEDO Serial Shift Data Out I/O EECS EEPROM Chip Select O 26 Am79C961A Am79C961A PIN DESIGNATIONS: BUS SLAVE MODE Listed by Group Pin Name Pin Function I/O Collision Inputs Driver I Attachment Unit Interface (AUI) CI± DI± Receive Data I DO± Transmit Data O 10BASE-T 10BASE-T Receive Data I 10BASE-T 10BASE-T Transmit Data O 10BASE-T 10BASE-T Predistortion Control O Twisted Pair Transceiver Interface (10BASE-T 10BASE-T) RXD± TXD± TXPD± IEEE 1149.1 Test Access Port Interface (JTAG) TCK Test Clock I TDI Test Data Input I TDO Test Data Output O TMS Test Mode Select I TS2 Power Supplies AVDD Analog Power [1-4] AVSS Analog Ground [1-2] DVDD Digital Power [1-7] DVSS Digital Ground [1-13] Output Driver Types Name Type IOL (mA) IOH (mA) pF TS1 Tri-State 4 ­1 50 TS2 Tri-State 12 ­4 50 TS3 Tri-State 24 ­3 120 OD3 Open Drain 24 ­3 120 Am79C961A Am79C961A 27 PIN DESCRIPTION: BUS SLAVE MODE ISA Interface AEN Address Enable Input This signal must be driven LOW when the bus performs an I/O access to the device. IOCHRDY IRQ3, 4, 5, 9, 10, 11, 12, 15 Interrupt Request Output An attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR, RINT, IDON or TXSTRT. All status flags have a mask bit which allows for suppression of IRQ assertion. These flags have the following meaning: BABL I/O Chip Select 16 Input/Output When an I/O read or write operation is performed, the PCnet-ISA II controller will drive this pin LOW to indicate that the chip supports a 16-bit operation at this address. (If the motherboard does not receive this signal, then the motherboard will convert a 16-bit access to two 8-bit accesses). The PCnet-ISA II controller follows the IEEE P996 specification that recommends this function be implemented as a pure decode of SA0-9 and AEN, with no dependency on IOR, or IOW; however, some PC/AT clone systems are not compatible with this approach. For this reason, the PCnet-ISA II controller is recommended to be configured to run 8-bit I/O on all machines. Since data is moved by memory cycles there is vir tually no performance loss incurred by running 8-bit I/O and compatibility problems are virtually eliminated. The PCnet-ISA II controller can be configured to run 8-bit-only I/ O by clearing Bit 0 in Plug and Play Register F0. IOR I/O Read Input To perform an Input/Output Read operation on the device IOR must be asserted. IOR is only valid if the AEN signal is LOW and the external address matches the PCnet-ISA II controller's predefined I/O address location. If valid, IOR indicates that a slave read operation is to be performed. IOW I/O Write Input To perform an Input/Output write operation on the device IOW must be asserted. IOW is only valid if AEN signal is LOW and the external address matches the PCnet-ISA II controller's predefined I/O address location. If valid, IOW indicates that a slave write operation is to be performed. 28 Receive Collision Count Overflow JAB Jabber MISS Missed Frame Memory Error MPCO IOCS16 IOCS16 RCVCCO MERR I/O Channel Ready Output When the PCnet-ISA II controller is being accessed, a HIGH on IOCHRDY indicates that valid data exists on the data bus for reads and that data has been latched for writes. Babble Missed Packet Count Overflow RINT Receive Interrupt IDON Initialization Done TXSTRT Transmit Start MEMR Memory Read Input ME M R go es L OW to pe rfo r m a me mo r y r ea d operation. MEMW Memory Write Input MEMW goes LOW to perform a memory write operation. REF Memory Refresh Input When REF is asserted, a memory refresh cycle is in progress. During a refresh cycle, MEMR assertion is ignored. RESET Reset Input When RESET is asserted HIGH, the PCnet-ISA II controller performs an internal system reset. RESET must be held for a minimum of 10 XTAL1 periods before being deasserted. While in a reset state, the PCnet-ISA II controller will tristate or deassert all outputs to predefined reset levels. The PCnet-ISA II controller resets itself upon power-up. SA0-15 SA0-15 System Address Bus Input This bus carries the address inputs from the system address bus. Address data is stable during command active cycle. Am79C961A Am79C961A SBHE DXCVR/EAR System Bus High Enable Input This signal indicates the HIGH byte of the system data bus is to be used. There is a weak pull-up resistor on this pin. If the PCnet-ISA II controller is installed in an 8-bit only system like the PC/XT, SBHE will always be HIGH and the PCnet-ISA II controller will perform only 8-bit operations. There must be at least one LOW going edge on this signal before the PCnet-ISA II controller will perform 16-bit operations. Disable Transceiver/ External Address Reject Input/Output This pin disables the transceiver. The DXCVR output is configured in the initialization sequence. A high level indicates the Twisted Pair Interface is active and the AUI is inactive, or SLEEP mode has been entered. A low