Am79213/Am79C203/031 CPD/P-109 IDC/16 IL00P VAB/41 - Datasheet Archive

 

Advanced Subscriber Line Interface Circuit (ASLIC TM) Device Advanced Subscriber Line Audio-Processing Circuit (ASLACTM) Device

 

Am79213/Am79C203/031 Am79213/Am79C203/031 Advanced Subscriber Line Interface Circuit (ASLIC TM) Device Advanced Subscriber Line Audio-Processing Circuit (ASLACTM) Device Technical Reference TABLE OF CONTENTS Linecard Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Operating the ASLIC/ASLAC Device Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ASLIC Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ASLAC Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ASLAC Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Overview of Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Two-Wire Impedance Matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Distortion Correction and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transhybrid Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Gain Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmit Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transmit PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Receive PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog Impedance Scaling Network (AISN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Speech Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC Feed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC Feed in the Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC Feed in the Standby, Tip Open, and Ring Open States . . . . . . . . . . . . . . . . . . . . . . . . . 23 Longitudinal Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ring Relay Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ring Relay Activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ring Relay Release. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Teletax Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12/16 kHz Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Line Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Detector Threshold Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ground-Key Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ground-Key Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ring-Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Line Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Go/NoGo Tests with Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 The Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ASLIC/ASLAC Devices Linecard Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 General Description of CSD Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# CPD/P-109 CPD/P-109 Rev: A Amendment: /0 Issue Date: January 1998 LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Voice Transmission Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Transmit PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PCM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Receive PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC Feed Control Block Diagram for Active and Disable States . . . . . . . . . . . . . 19 DC Feed Plot, VAB vs. ILOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage Current Characteristic for the North American Market . . . . . . . . . . . . . . 22 Line Current vs. Loop Resistance for the North American Market . . . . . . . . . . . 22 Standby, Tip Open, and Ring Open State Internal Configuration . . . . . . . . . . . . 23 Longitudinal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Metallic and Longitudinal Control Loop Block Diagram . . . . . . . . . . . . . . . . . . . 25 Current Zero Cross Detect Timing for Relay Opening . . . . . . . . . . . . . . . . . . . . 26 Metering Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12/16 kHz Metering Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Smooth Polarity Reverse Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Loop Supervision Architecture-ASLIC/ASLAC Devices . . . . . . . . . . . . . . . . . . . 31 Loopback Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Microprocessor Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ASLIC/ASLAC Typical Linecard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 LIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 2 Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Default States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 DC Feed Control Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 External Component Effects on DC Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VOFF Valid Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Programmable Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ASLAC Device Filter Gains for Line Test Modes . . . . . . . . . . . . . . . . . . . . . . . . 35 ASLAC Device Filter Gains for PCM Remote Line Tests . . . . . . . . . . . . . . . . . . 36 VOUT vs. PCM Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ST Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Metering Target Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Metering Threshold Voltages (Vt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Ring-Trip Threshold Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Presence of Ringing Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Loop Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 VAPP & RFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 N2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 VAS and VOFF Programmable Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Ground-Key & Switchhook Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ASLIC/ASLAC Devices Linecard Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 A-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference The Am79213/Am79C203/031 Am79213/Am79C203/031 Advanced Subscriber Line Interface chip set implements a universal telephone line interface function. This enables the design of a single, low cost, high performance, fully software programmable line interface card for multiple country applications world wide. All AC, DC, and signaling parameters are fully programmable via the microprocessor interface. Additionally, the ASLIC device and ASLAC device have integrated self test and line test capabilities to resolve faults to the line or line circuit. The integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective. The data sheet, PID 19770, is recommended to be used with this document. LINECARD BLOCK DIAGRAM Loop Voltage Sense Resistors Transmit Receive RFA SA Ring and Test Relays DC Feed Control Metering ASLIC Device Loop Voltage Monitor SB MPI Loop Current Monitor ASLAC Device BD B(Ring) RFB PCM Relay Driver Outputs Ring-Feed Resistor ASLIC Device Operating State MPI and PCM Backplane AD A(Tip) Relay Driver Inputs Ringer Supply Ringing-Current Sense Resistors Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 3 OPERATING THE ASLIC/ASLAC DEVICE PAIR ASLIC Device Table 1 defines the ASLIC device operating states set by ternary logic pins C1 and C2. The three states of the ternary input from the ASLAC device are VCC, ground, and 3-state or floating (FL). Table 1. Operating States C2 C1 Operating State VCC FL Disconnect - AD and BD at High-Z, Channel A and B power amplifiers shut down Open Disconnect VCC GND Ringing - RINGOUT activated Open Ringing GND GND Active feed, normal polarity B amplifier output Disconnect VCC VCC Ring Open - BD at High-Z, AD resistive feed through RTMG, both amplifiers shut down. AD pin Ring Open FL VCC Tip Open - AD at High-Z, BD current limited resistive feed through internal resistor, both amplifiers shut down. Open Tip Open FL FL Standby (High ohmic feed) - Loop supervision active, A and B amplifiers shut down Open Standby GND VCC Active feed, reverse polarity A amplifier output Disconnect GND FL Disable (Low power active feed state) Open Disconnect FL GND Standby (Not a valid state from the ASLAC device) Open Standby Pins I/O1, I/O2, and I/O3 can control relay driver outputs RY1OUT, RY2OUT, and RY3OUT. A logic Low on the relay control inputs causes the relay driver outputs to be pulled to battery ground. When a relay control input is left unconnected, the corresponding relay driver will be in the high impedance off state. Disconnect This state disconnects both A and B output amplifiers from the AD and BD outputs. The A and B amplifiers are shut down. Ringing RINGOUT, the ring relay driver is turned on and pulled to BGND. During the Ringing state, the A and B power amplifiers are turned off and their outputs placed in a high impedance state. Active Feed, Normal Polarity Normal polarity, active is usually enabled during a call. Both output amplifiers deliver the full power level determined by the DC Feed conditions set by the ASLAC device. The AD output of the ASLIC device is positive with respect to the BD output when current flows out of the RSN pin. Ring Open RTMG Connection Tip Open In this state, the Tip lead is opened and the BD pin is connected to QBAT through an internal resistor (typically 250 ). The current in the ring lead is limited by the ASLIC device to 40 mA typical. Standby The power amplifiers are turned off and the AD and BD outputs are driven by internal resistances connected to ground and QBAT, respectively. Line supervision remains active. A 30 mA typical current limit is provided on the tip lead to limit power dissipation under short loop conditions. In the Standby state, the ASLIC device is normal polarity. Active Feed, Reverse Polarity Same as normal polarity except the AD output of the ASLIC device is negative with respect to the BD output. Disable Current bias levels to the power amplifiers are lowered in this mode to reduce the on-hook ASLIC device power dissipation. Loop-current limit levels as determined by the ASLAC device are also reduced in the Disable state. On-hook transmission and loop supervision are possible in this state. In this state, the Ring lead is opened and the AD pin is switched to QBAT through the external thermal management resistor, RTMG. 4 Operating State in Thermal Shutdown Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference ASLIC Device Block Diagram A-Wire Output Amplifier AD SA RSN Input Amplifier RSN Loop-Current Sensing IDC IA Thermal Management Control VREF Transmit Amplifier + ­ + + IA IB IA + IB 600 ISUM 1/4 VTX 6 HPA VLONG VAB HPB BAL1 VHPA Thermal Shutdown + ­ VHPB ­0.5 + ­ SB Longitudinal Control Amplifier ­ + + VDC 1/20.67 VLBIAS ­6 B-Wire Output Amplifier VBAT BD Loop-Current Sensing IA IB + ­ To A-Wire Output Amplifier IA ­ IB 600 IDIF IB Thermal Management Control TMG ASLIC STATE CTL BUS RINGOUT RY1OUT RY2OUT C1 Ternary Decode C2 Relay Drivers C3 C4 RY3OUT C5 QBAT VCC GND Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference BGND 5 ASLAC Device Active State After a proper power-up sequence, the ASLAC device can operate in either the Active or Inactive state. The ASLAC device is forced into the Inactive state at powerup or by a hardware or software reset. In the Active state, the ASLAC device is able to transmit and receive PCM and analog information. This is the normal operating mode when a telephone call is in progress. The ASLAC device may be brought into the Active state by any one of three methods: 1) writing Activate (Command 6); 2) writing certain states in the SLIC State register bits, ST0, ST1, ST2 (Command 21); 3) by writing the TVD bit in Configuration Register 2. A logic High in the CS bit of the SLIC I/O and Chip Status register (Command 20) indicates the status. The ASLIC device Active state and DC Feed sections of the ASLAC device are controlled separately by the ST bits in the channel control register, MPI Command 21. Power-Up Sequence from VCC = 0 V The recommended power-up sequence is to apply: 1. Power supply grounds 2. VCC 3. VBAT 4. Signal connections 5. Hardware Reset The software initialization should then include: 1. Select MCLK frequency 2. Software Reset 3. Program filter coefficients 4. Activate Software initialization of the ASLAC device should always follow any power-up or hardware reset. Upon initial application of power, a minimum of 1 ms is needed before chip select may go Low and an MPI command initiated. If the power supply falls below a specified value, the device is reset and will require complete reprogramming with the above sequence. Please refer to the PI description for more details on this feature. 6 Inactive State Inactive state is enabled by sending Command 1 to the ASLAC device or when a VCC power interrupt occurs. No transmission or reception of voice data takes place, but the circuits that contain programmed information retain their data. Power is removed from all nonessential circuitry though the MPI remains active to receive new commands. Certain ASLIC device states and the TVD bit overrides an Inactivate command. The ASLIC device activate states are detailed at Command 21 and Command 22. If the SMODE bit is enabled, the TSA will remain powered up and will shift Signaling Register data out at the PCLK rate. The operation is identical to that in the Active state, except that the PCM data is indeterminate. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference ASLAC Device Block Diagram MCLK RING + TEST AX VIN DXA A/D RING + TEST AISN VOUT DXB * Signal Processing D/A AR Time Slot Assigner (TSA) & PCM Interface TSCA TSCB * DRA DRB* FS PCLK CS VM MicroProcessor Interface (MPI) Metering Generator with Level Control & Shaping DI/O INT RST DCLK IBAT IDC VLBIAS DC Feed Control C1 IAB C2 I/O1 Digital I/O IRTA IRTB I/O2 I/O3 * Loop Supervision I/O4* ISUM IDIF I and V Reference Generators VREF VCCD VCCA AGND IREF DGND Note: *Available on 44-pin device. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 7 Reset States Application of VCC on initial power up, a Low logic level on the RST pin, 16 DCLK cycles with CS Low, or a hardware reset command (# 3) resets the ASLAC device to the following default conditions. Table 2. Reset States Field Name ACT Field Description Force DSP active Value after Hardware Reset Hex after H/W Reset DSP inactive Transmit TS & PCM Register Value after Reset to Normal Conditions DSP inactive 00h PCM Transmit PCM highway A bus No effect TS Transmit time slot 0 No effect Receive TS & PCM Register 00h PCM Receive PCM highway A bus No effect TS Receive time slot 0 No effect Clock slot register 00h XE Transmit clock edge Negative edge No effect RCS Receive clock slot 0 No effect TCS Transmit clock slot 0 No effect Initial Signaling Register 04h HOOK Switchhook/ring trip On hook No effect GNK Ground key/start No ground No effect AST Anti-sat indicator Off No effect ICON Current limit indicator Off No effect TEMPA Thermal overload indicator Off No effect CFAIL Clock fail indicator On No effect RINGX Ringing absence test indicator Off No effect FAULT Power fault indicator Off No effect I/O 1-4 SLIC input/output register Input Input/Output Direction Register 00h PI Power interrupt Cleared Cleared CS Channel activity status Inactive Inactive D,C,B,A SLIC I/O direction All input No effect SLIC state register 00h POLNR Polarity, normal/reverse Normal polarity Normal polarity ST 0-2 SLIC state Standby Standby Special I/O Register 40h INTM Open drain No effect M2 Linear/Companded mode Companded No effect M1 8 Interrupt Drive mode General Purpose/ASLIC Device mode ASLIC Device mode No effect Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference Table 2. Reset States (continued) Field Name Field Description DC 1-2 C1-2 directions in GP mode C 1-2 Value after Hardware Reset Hex after H/W Reset Both input C1-2 data in GP Output mode Value after Reset to Normal Conditions No effect No effect Operating Functions Register 00h ABF Adaptive balance filter Off No effect A/µ A-law/µ-law A-law No effect EGR Default/programmed GR Use default Use prog. GR EGX Default/programmed GX Use default Use prog. GX EX Default/programmed X Use default Use prog. X ER Default/programmed R Use default Use prog. R EZ Default/programmed Z Use default Use prog. Z EB Default/programmed BFIR/IIR Use default Use prog. B CR1 Configuration Register 1 FLB Full digital loopback No loopback No loopback COX Cutoff transmit path No cutoff No cutoff TSLB Time slot loopback No loopback No loopback TON 1 kHz receive tone Tone off Tone off ALB Analog loopback No loopback No loopback RG 6 dB lower receive gain No loss No loss DHP Transmit high pass disable No disable No disable COR Cutoff receive path No cutoff No cutoff CR2 Configuration Register 2 TVD Test valid Complete Complete OKTON Tone OK Not done Not done OKTTX Metering OK Not done Not done OKRNG Ringing OK Not done Not done TM Test mode enable Disabled Disabled NOSL Teletax ramp Slow No effect CLSR Clear signaling register on READ Clear SR Clear SR RTSIG Real time data on INT Latched data on INT Latched data on INT CR3 Configuration Register 3 Reserved CR4 Configuration Register 4 ERTT Enable ring-trip threshold Use default Use prog RT thresh. EDPB Enable digital pre-balance Use default Use default DPB MTRF Metering frequency 12 kHz No effect MTRA 0-4 Metering amplitude 447 mVrms No effect 00h 80h 17h Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 9 Table 2. Reset States (continued) Field Name Field Description Value after Hardware Reset Hex after H/W Reset Value after Reset to Normal Conditions CR5 Configuration Register 5 IDC/16 IDC/16 Divide IDC by 16 Off Off SOREV Smooth polarity reverse Abrupt No effect TXTNO Teletax normal operation Tone No effect SBT 1 kHz sign bit toggle Off Off ZXR Zero cross relay operation Enabled No effect ARR Automatic ring relay release Automatic No effect CR6 Configuration Register 6 HOOK Mask switchhook/ring trip Mask No effect GNK Mask ground key/start Mask No effect AST Mask anti-sat indicator Mask No effect ICON Mask current limit indicator Mask No effect TEMPA Mask thermal overload indicator Mask No effect CFAIL Mask clock fail indicator Mask No effect RINGX Mask ringing absence test Mask No effect FAULT Mask power fault indicator Mask No effect CR7 Configuration Register 7 CMODE MCLK/PCLK mode Combined No effect SMODE PCM signaling mode No PCM signal No effect CSLE A-B Clock frequency select 8.192 MHz No effect MLIM 0-3 Metering limit 374 mVrms No effect RCN Revision code number ROM value 10 40h FFh ABh Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference Default States and Coefficients Within the ASLAC device, there are three types of registers referred to in different ways below. Registers that are initialized to an initial state have no designation. Registers that are permanently stored in ROM are designated by (DEF). Registers that are user programmed are designated by (Prog). Registers designated Prog and DEF are selectable at any time. Table 3. Default States Field Name Field Description Value after Hardware Reset Hex after H/W Reset Value after Reset to Normal Conditions GX Prog. transmit digital gain Indeterminate Indeterminate No effect GX:DEF Default transmit digital gain 1.9951172 A9F0h No effect GR Prog. receive digital gain Indeterminate Indeterminate No effect GR:DEF Default receive digital gain 0.5009766 A871h No effect Z Prog. impedance filter Indeterminate Indeterminate No effect Z:DEF Default impedance filter 0 0190h No effect 0 0190h No effect 0 0190h No effect 0 0190h No effect 0 0190h No effect 0 0190h No effect 1 01h No effect 0 0190h No effect BFIR Prog. balance FIR filter Indeterminate Indeterminate No effect BFIR:DEF Default balance FIR filter ­0.1015625 AABh No effect ­0.3906250 BA9h No effect ­0.296875 A2Ah No effect ­0.050781 AACh No effect 0.0009766 B87h No effect 0.0029297 297h No effect 0.0009766 B87h No effect 0.0019531 A87h No effect 0.0029297 2970h No effect X Prog. transmit filter Indeterminate Indeterminate No effect X:DEF Default transmit filter 1 0111h No effect " 0 0190h No effect " 0 0190h No effect " 0 0190h No effect Default transmit filter 1 0111h No effect " 0 0190h No effect " 0 0190h No effect X:DEF Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 11 Table 3. Default States (continued) Field Name Field Description Value after Hardware Reset Hex after H/W Reset Value after Reset to Normal Conditions R Prog. receive filter Indeterminate Indeterminate No effect R:DEF Default receive filter 0.9899902 32F0h No effect " 1 0111h No effect " 0 0190h No effect " 0 0190h No effect " 0 0190h No effect " 0 0190h No effect " 0 0190h No effect EPG Echo path gain Indeterminate Indeterminate No effect ELT Error level threshold Indeterminate Indeterminate No effect Adaptive B filter control Indeterminate DCR1 Decorrelation coefficient Indeterminate No effect DCR2 Decorrelation coefficient Indeterminate No effect LST Low-signal threshold Indeterminate No effect DPB Progr. digital pre-balance Indeterminate No effect DPB:DEF Default digital pre-balance 0 090h No effect RTT Prog. ring-trip threshold Indeterminate Indeterminate No effect RTT:DEF Default ring-trip threshold 10.5 mA 3Ch No effect BIIR Programmable B IIR filter Indeterminate Indeterminate No effect BIIR:DEF Default B IIR filter 0.9848633 DD01h No effect B5h No effect Loop-current limit ILA Current limit, Active 47.6 mA No effect ILD Current limit, Disable 21.2 mA No effect DC Feed parameters 08h No effect VAPP Apparent voltage 50.2 V No effect RFD Feed resistance 403 No effect Anti-sat value 88h No effect VAS Anti-sat offset voltage 14.4 V No effect VOFF Longitudinal offset voltage 8.4 V No effect N2 Anti-sat feed ratio 2 No effect Loop supervision threshold 56h No effect TGK 0-3 Ground-key threshold 7.23 mA No effect TSH 0-3 Off-hook threshold 10.06 mA No effect Debounce intervals GKNTDIS 12 Ground-key integration disable 23h Enabled Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference No effect No effect Table 3. Default States (continued) Field Name Field Description Value after Hardware Reset Hex after H/W Reset Value after Reset to Normal Conditions DSH 0-3 Debounce time, switchhook 8 ms No effect GKNT 0-1 Ground-key integration time 100 ms No effect AISN coefficient, analog gain 00h No effect AX Analog transmit gain 0 dB No effect AR Analog receive gain 0 dB No effect E-A AISN gain 0 No effect Upon initial application of power, a minimum of 1 ms is needed before the digital interface is ready to accept or transmit data. When power is initially applied or when a hardware reset (there are three methods) occurs, follow the sequence of commands as described in the ASLAC device operation section. A signal less than 100 ns should not cause a reset. To ensure proper reset, the minimum length of a reset pulse is 50 µs. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 13 SIGNAL PROCESSING Overview of Digital Filters Several of the blocks in the signal processing section are user programmable. These allow the user to optimize the performance of the ASLAC device for the system. Figure 1 shows ASLAC device signal processing and indicates the programmable blocks. The advantages of digital filters are: s High reliability s No drift with time or temperature s Unit-to-unit repeatability s Superior transmission performance Two-Wire Impedance Matching Two feedback paths on the ASLAC device modify the effective two-wire input impedance of the SLIC by providing programmable feedback from VIN to VOUT. The Analog Impedance Scaling Network (AISN) is a programmable analog gain of ­0.9375 to +0.9375 from VIN to VOUT. The Z filter is a programmable digital filter, also connecting VIN to VOUT. Distortion Correction and Equalization The ASLAC device contains programmable filters in the receive (R) and transmit (X) directions that may be programmed for line equalization and to correct any attenuation distortion introduced by the Z filter. 14 Transhybrid Balancing The ASLAC device programmable B filter is used to adjust transhybrid balance. The filter has a single pole IIR section (BIIR) and a 9-tap FIR section (BFIR), both operating at 16 kHz. The ASLAC device has an optional adaptive mode for the B filter, which may be used to achieve optimum performance. The Echo Path Gain (EPG) and Error Level Threshold (ELT) registers contain values that determine the adaptive mode performance. 1-tap Digital Prebalance (DPB) is available without enabling the B filter. Gain Adjustment The ASLAC device transmit path has two programmable gain blocks. Gain block AX is an analog gain of 0 dB or 6.02 dB, located immediately before the A/D converter. Gain block GX is a digital gain that is programmable to any gain from 0 dB to +12 dB, with a worst-case step size of 0.1 dB for gain settings below +10 dB, and a worst case step size of 0.3 dB for gain settings above +10 dB. The filters provide a net gain in the range of 0 dB to 18 dB. The ASLAC device receive path has two programmable loss blocks. Loss block GR is a digital loss that is programmable from 0 dB to 12 dB with a worst case step size of 0.1 dB. Loss block AR is an analog loss of 0 dB or 6.02 dB, located immediately after the D/A converter. This provides a net loss in the range of 0 dB to 18 dB. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference Figure 1. Voice Transmission Paths Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 15 VOUT VIN IAB Full Digital Loopback Enable TM TM AISN + RING AR AR = 0 dB or -6.02 dB AX = 0 dB or +6.02 dB AX DAC ADC VRING (UNFILTERED) RING RING HPF Z Programmable Block + Metering Detector Interpolator Decimator To DC Feed Control Section B-IIR + RG X B-FIR GR RFIR RIIR Receive Path cutoff LPR Adaptor Expander LPT Compressor & HP Ring Trip GX = 0 to +12 dB GX Ring-Trip Detector GR = 0 to -12 dB DPB + RG = 0 or -6.02 dB Interpolator Decimator Metering Level Control ASLAC DEVICE From De-Multiplexer Digital Loopback Enable To Multiplexer Transmit path cutoff and cutoff for digital loopback Transmit Signal Processing In the transmit path, the analog input signal (VIN) is digitized, filtered, and made available for output to the PCM highway in either linear or compressed (A-law/ µ-law) format. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The B, X, and GX blocks are user programmable digital filter sections with coefficients stored in the coefficient RAM, while AX is an analog amplifier that can be programmed for 0 dB or 6.02 dB gain. The filters use either user-programmed coefficients or default coefficients for processing data. The decimator reduces the high input sampling rate to 16 kHz for input to the B, GX, and X filters. The X filter is a 6-tap FIR section which is part of the frequency response correction network. The B filter operates on samples from the receive signal path in order to provide transhybrid balancing in the loop. The high-pass filter rejects low frequencies such as 50 or 60 Hz and may be disabled. A transmit cutoff mode is also provided. Transmit PCM Interface The transmit PCM interface receives an 8-bit compressed code (A-law/µ-law) or a 16-bit 2's complement linear code (13-bit dynamic range) from the digital transmit signal processor. The transmit PCM interface logic (Figure 2) controls the transmission of the data onto the PCM highway through the output port selection circuitry and the time and clock slot control block. The frame sync (FS) pulse identifies the beginning of a transmit frame and all channels (time slots) are referenced to it. The logic contains user programmable Transmit Time Slot and Transmit Clock Slot registers. From Transmit Signal Processor The Time Slot register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system. The Clock Slot register is 3 bits wide and may be programmed to offset the time slot assignment by 0 to 7 PCLK periods to eliminate any clock skew in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a nonzero remainder (R = fPCLK modulo 64 kHz, R > 0), and when the transmit clock slot is greater than R. In that case the R-bit fractional time slot after the last full time slot in the frame will contain random information and will have the TSC output turned on. For example, if the PCLK frequency is 1.544 MHz (R = 1) and the transmit clock slot is greater than 1, the 1-bit fractional time slot after the last full time slot in the frame will contain random information, and the TSC output will remain active during the fractional time slot. The data is transmitted in bytes with the most significant bit first. Figure 3 illustrates data flow on the PCM Highway. The PCM data may be user programmed for output onto either the DXA or DXB port. Correspondingly, either TSCA or TSCB (open drain) is Low during transmission. (DXB and TSCB are available only on the 44 pin version.) If the SMODE bit in CR7 is set to a logic 1, the information contained in the Signaling Register is transmitted onto the PCM Highway, every frame regardless of active/inactive status. The signaling data appears in the time slot following the programmed voice data. If time slot 127 is chosen, the signaling data will appear in the first time slot after frame sync. If Linear mode is selected while the SMODE bit is set to logic 1, linear data selection will override the SMODE selection and signaling data will not be sent out to the PCM highway. The data which accompanies the signaling register data will be indeterminate. DXA Output Register Port Selection TSCA DXB TSCB FS Time Slot Control Time & Clock Slot Register PCLK Figure 2. Transmit PCM Interface 16 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference From MPI FS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCLK DXA/B Three-State P7 P6 P5 P4 P3 P2 P1 P0 P7 P6 P5 P4 P3 P2 P1 P0 S7 S6 S5 S4 S3 S2 S1 S0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 L2 L1 L0 PCM Mode DXA/B Signaling Mode DXA/B Linear Mode Time slot "X" TSCA/B Time slot "X + 1" DRA/B P7 PCM and Signaling Modes DRA/B L15 P6 P5 P4 P3 P2 P1 L14 L13 L12 L11 L10 L9 L8 Three-State P0 L7 L6 L5 L4 L3 Linear Mode P = PCM Data S = Signaling Data L = Linear Data Figure 3. PCM Interface Timing Diagram Receive Signal Processing In the receive path, the linear or compressed (A-law or µ-law) digital signal is formatted, filtered, converted to analog, and passed to the VOUT pin. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The Z, R, and GR blocks are user-programmable filter sections with their coefficients stored in the coefficient RAM while AR is an analog amplifier that can be programmed for a 0 dB or 6.02 dB loss. A digital loss function, RG, can be programmed for a 0 dB or 6.02 dB loss. A receive cutoff mode is also provided. The filters use either user programmed coefficients or default coefficients for processing data. The low-pass filter band limits the signal. The R filter is a 1-tap IIR filter section operating at 8 kHz, followed by a 6-tap FIR section operating at a 16 kHz sampling rate and is part of the frequency response correction network. The analog impedance scaling network (AISN) is a user-programmable gain block providing feedback from VIN to VOUT to emulate different ZSLIC impedances from a single external ZSLIC impedance. The Z filter provides feedback from the transmit signal path to the receive path and is used to modify the effective input impedance to the system. The interpolator increases the sampling rate prior to D/A conversion. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 17 Receive PCM Interface The receive PCM interface logic (Figure 4) controls the reception of data bytes from the PCM highway. Compressed (A-law/µ-law) or 2's complement linear data is formatted and passed to the receive signal processor. The frame sync (FS) pulse identifies the beginning of a receive frame and all channels (time slots) are referenced to it. The logic contains user programmable Receive Time Slot and Receive Clock Slot registers. The Time Slot register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system. The Clock Slot register is 3 bits wide and may be programmed to offset the time slot assignment by 0 to 7 PCLK periods to eliminate any clock skews in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a nonzero remainder, R (R = fPLCK modulo 64 kHz, R > 0) and when the receive clock slot is greater than R. In that case, the last receive time slot in the frame will be not be usable. For example, if the PCLK frequency is 1.544 MHz (R = 1), the receive clock slot can be only 0 or 1 if the last time slot is to be used. The PCM data may be user programmed for input from either the DRA or DRB port. (DRB is available only on the 44 pin version.) Analog Impedance Scaling Network (AISN) The AISN is incorporated in the ASLAC device to scale the value of the external ZSLIC impedance. Scaling this external impedance with the AISN (along with the Z filter) allows matching of many different line conditions using a single impedance value. Linecards may be designed for many different specifications without any hardware changes. The AISN is a programmable gain that is connected across the ASLAC device input from VIN to VOUT. The gain can be varied from ­0.9375 to +0.9375 in 31 steps To Receive Signal Processor FS PCLK of 0.0625. The AISN gain is given by the following equation: h AISN 4 3 2 1 0 = 0.0625 [ ( A ² 2 + B ² 2 + C ² 2 + D ² 2 + E ² 2 ) ­ 16 ] The AISN gain is used to alter the input impedance of the ASLAC device and ASLIC device as shown in Figure 1. The input impedance into the ASLAC device from the ASLIC device is given by: 1 ­ G44 · ( h AISN ) ZIN = - · ZSL 1 ­ G 440 · ( h AISN ) Where G440 is the ASLIC device's echo gain into an open circuit and G44 is the ASLIC device's echo gain into a short circuit. There are two special cases to the formula for hAISN: 1. Value of ABCDE = 00000 will specify a gain of 0 (or cutoff). 2. A value of ABCDE = 10000 is a special case where the AISN circuitry is disabled and the VOUT amplifier is connected internally to VIN with a gain of 0 dB (equivalent to setting FLB bit in Configuration Register 1). This allows a Digital-to-Digital Loopback mode wherein a digital PCM input signal is completely processed through the receive section all the way to the VOUT amplifier, which is connected internally to VIN where it is processed through the transmit section and output as digital PCM data. Note that the data will not appear at VOUT in this case. VOUT is disabled. Speech Coding The A/D and D/A compression/expansion, if selected, follows either the A-law or the µ-law as they are defined in CCITT Rec. G.711. A-law or µ-law is programmed using MPI Command 25. Alternate bit inversion is performed as part of the A-law coding. Input Register Port Selection Time Slot Control Time Slot Registers Figure 4. Receive PCM Interface 18 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference DRA DRB From MPI DC FEED CONTROL DC Feed in the Active State Feed control for Active (normal or reverse polarity) and Disable states. ASLIC Device VREF 400 K CHP VDC + ­ RAB IAB VREF · VAB IDC 2K VAB RL K1 RSN IL00P IL00P ILOOP VLBIAS IDC VAPP CDC1 RFD VREF ILA, ILD DC Feed Controller VAS Digital Inputs from Control Interface N2 VLBIAS VOFF VREF To Longitudinal Control Loop ASLAC Device IREF IBAT RBAT2 RREF CB RBAT1 To ASLIC Device QBAT pin Figure 5. DC Feed Control Block Diagram for Active and Disable States VAB VAPP Anti-Sat Region KBAT * VBAT ­ VAS V2 Resistance-Feed Region (RFD) V1 Current-Limit Region ILOOP 0 ILIM (ILA, ILD) Figure 6. DC Feed Plot, VAB vs. ILOOP Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 19 Figure 5 shows the block diagram of the DC Feed control circuit. The DC Feed control parameters can be independently programmed by way of the MPI interface as indicated in Table 4. s VAPP, the apparent battery voltage s RFD, the DC Feed resistance s ILA, the loop-current limit level (ILIM) in the Active state s ILD, the loop-current limit level in the Disable state s VAS, the anti-sat offset voltage s N2, the anti-sat feed resistance factor V1 = VAPP ­ ILIM · RFD ; V2 = KBAT · QBAT ­ VAS; Where: RAB KBAT = -2.005 · · ( RBAT1 + RBAT2 ) As shown in Figure 6, V1 is the voltage at which the feed characteristic normally leaves the current limit region and enters the resistance feed region. If V1 is greater than V2, the anti-sat region is entered directly from the current limit region. If V1 is negative, there is no current limit region and the feed characteristics start out in the resistive feed region at VLOOP = 0. VBAT is the voltage applied to the QBAT and VBAT pins of the ASLIC device. In the Active state, ILIM = ILA; In the Disable state, ILIM = ILD The following equations define ILOOP: If VAB < V1 and V2: ILOOP = ILIM If V2 > V1: If V2 > VAB > V1: VAPP ­ VAB ILOOP = ILIM ­ VAB ­ V1 = -RFD RFD If VAB > V2: V1 + N2 · V2 VAB ILOOP = ILIM + - ­ - · ( N2 + 1 ) RFD RFD If V1 > V2: If V1 > VAB > V2: VAB ­ V2 ILOOP = ILIM ­ - · N2 RFD If VAB > V1: V1 + N2 · V2 VAB ILOOP = ILIM ­ - ­ - · ( N2 + 1 ) RFD RFD IDC and VDC (see Figure 5) for any of the above conditions is defined by the following equations: ILOOP IDC = - ; Where K1 is the four-wire (RSN pin) to two-wire (ILOOP) DC incremental current gain in the ASLIC device K1 VDC = VAB · ; Where is the two-wire (VAB) to VDC voltage gain in the ASLIC device The ASLIC/ASLAC devices have been designed to implement the feed equations assuming the following nominal values for ASLIC device parameters and external components: RREF, the current reference resistor from ASLAC device, IREF pin to ground: 7870 . RAB, the voltage-to-current conversion resistor between the ASLIC device, VDC pin and the ASLAC device, IAB pin: 35.7 k RBAT = RBAT1 + RBAT2, the battery voltage sense resistance connected between VBAT and the IBAT pin of the ASLAC device: 730 k K1, the ASLIC device four- to two-wire incremental DC current gain. 1 , the ASLIC device two- to four-wire DC voltage gain: = - = 0.0242 41.33 20 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference The nominal values of all programmable parameters are shown in the shaded areas of Table 4. Table 4. DC Feed Control Parameters Description Apparent voltage Control Variable Nominal Values Units 25.1 50.2 60.3 70.3 V KAPP 0.134 0.268 0.321 0.375 - 403 504 605 706 807 1009 1210 1614 W 0.069 0.087 0.104 0.122 0.139 0.174 0.208 0.278 - 5.3 7.4 10.6 12.7 15.9 21.2 26.5 31.8 mA VILIM 0.164 0.230 0.328 0.394 0.492 0.656 0.820 0.984 V IL_(mA) 33.9 37.1 42.3 47.6 52.9 63.5 mA VILIM Feed resistance VAPP(V) 1.050 1.148 1.312 1.476 1.640 1.968 V 6.2 8.2 10.3 12.3 14.4 16.5 18.5 20.6 V 0.033 0.044 0.055 0.066 0.077 0.088 0.099 0.110 V 2 3 5 9 RFD() KRFD Loop-current limits, Active and Disable states IL_(mA) Anti-sat offset voltage VAS(V) Anti-sat factor N2 KVAS - When external component and parameter values differ slightly from nominal, new DC Feed values can be calculated using the equations in Table 5. Table 5. External Component Effects on DC Feed VAPP RAB KAPP · -RREF · ILA, ILD K1 VILIM · -RREF RFD RAB KRFD · -K1 · VAS RAB KVAS · -RREF · Note: RAB and RREF are in . See Table 4 for values of KAPP, KRFD, KVAS, and VILIM. The values of proportionality constants KAPP, KRFD, VILIM, KVAS for any particular DC Feed program are located in Table 4 immediately below each shaded feed parameter value. Because the values of N2 do not depend upon external components, they do not have proportionality constants associated with them. The voltage appearing between the A and B legs when the loop is open can be calculated using the following equation: VAPP + N2 · ( KBAT · VBAT ­V AS ) N2 + 1 Figure 7 and Figure 8 show the performance that an ASLIC/ASLAC devices linecard will provide for the North American market using a ­51 V C.O. battery. The programmed parameters are: VABIL = 0 = - VAPP = 50.2 V, RFD = 403 , ILA = 47.6 mA, VAS = 10.3 V, N2 = 2, VOFF = 6.0 V The external component values are: RREF = 7.87 k, 1% RAB = 35.7 k, 1% RBAT1 = RBAT2 = 365 k, 1% Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 21 60 50 RLOOP = 1.9 k 40 VLOOP (Volts) 30 LSSGR Limits 20 10 0 10 20 30 40 50 60 70 80 90 100 ILOOP (mA) Figure 7. Voltage Current Characteristic for the North American Market 60 50 40 ILOOP (mA) 30 LSSGR Limits 20 10 0 500 1000 1500 2000 2500 3000 RLOOP () Figure 8. Line Current vs. Loop Resistance for the North American Market 22 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 3500 DC Feed in the Standby, Tip Open, and Ring Open States In the Standby and Tip Open states, the longitudinal control loop and both power amplifiers are turned off. Because the ASLIC device power amplifiers are turned off, voice transmission is not possible in the Standby, Tip Open, or Ring Open states. When in these states, the AD and BD outputs are driven by internal resistances connected to ground or QBAT to ensure line supervision remains active. Each internal resistance (see Feed Resistance in ASLIC device DC specs) is connected in series with constant current limit (30 mA on AD; 40 mA on BD) to limit ASLIC device power dissipation under short loop conditions. When the loop current is below the current limit, the ASLIC device appears as a constant voltage source in series with two of the internal resistances. Above the current limit, the ASLIC device acts as a constant current source of the appropriate value. Figure 9 shows the internal configuration of the ASLIC device in the Standby, Tip Open, and Ring Open states. In the Standby state, S1 and S2 are switched on and S3 is switched off. The ASLIC device delivers normal polarity (AD more positive than BD) current to the loop. In the Tip Open state, S1 and S3 are switched off and S2 is switched on. The ASLIC device provides a current limiter in series with the internal resistance to QBAT, through the 20 supervision sense resistor, to the BD output. In the Ring Open state, S1 and S2 are switched off and S3 is switched on. This allows loop current to be drawn from QBAT through the external thermal management resistor, RTMG. ASLIC QBAT 30 mA Current Limiter RTMG TMG C.O. BATTERY Feed Resistance S3 AD S1 BD S2 Feed Resistance 40 mA Current Limiter QBAT Figure 9. Standby, Tip Open, and Ring Open State Internal Configuration Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 23 Longitudinal Control Loop The purpose of the longitudinal control loop is to set the optimum two-wire, DC operating point of the ASLIC device. The DC operating point should be set so that enough headroom is allowed for signals to swing on the A and B legs of the line circuit. reference voltage will change, causing the operating point to move by the same amount. For long loops the operating point is fixed at approximately half of QBAT. In this case, the DC Feed is balanced and VA moves in the opposite direction from VB as the load is varied. In the case of short loops, where the longitudinal operating point is less than half of QBAT, programmable parameter VOFF determines the amount of headroom available as shown in Figure 10. In this case, the voltage at the A lead remains fixed and only the B lead responds to load variations. As long as the longitudinal control loop is within its operating range, VA will equal ­VOFF. This can be shown by the following derivation: The ASLIC device creates a longitudinal reference voltage by adding one half the line-to-line voltage to VOFF. The error amplifier compares this reference voltage to the actual longitudinal voltage and forces them to be equal by controlling the amount of longitudinal current delivered by the output amplifiers. If voltage VB changes (because of load variation, for example), the longitudinal VA + VB = ­ VOFF ­ VA + VB - - -2 2 2 2 VA + VB - = ­ VOFF ­ VA ­ VB -2 2 VA = -VOFF The level of VOFF is programmable to ensure that maximum signal swings can be accommodated by the ASLIC device. The range of VOFF is given in Table 6. Table 6. VOFF Valid Settings Control Variable VOFF Description Range Units Longitudinal offset voltage 6.0, 7.2, 8.4, 9.6, 10.8, 12, 13.2, 14.4 V BGND VOFF VA + ­ + VA ­ VB 2 VA+VB ­ 2 Longitudinal reference voltage + VB QBAT Note: Longitudinal reference voltage = ­ V OFF ­ VA ­ VB -2 Where: VOFF = 6 · VLBIAS Figure 10. Longitudinal Voltages 24 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference Figure 11 combines the functions of the metallic and longitudinal control loops into one block diagram. Also shown is the two-wire performance of the ASLIC/ASLAC devices system from short to long loops. 500 A +0.5 SA RSN GL = 28.6 µ ­ 200 K + CHP RL VAB VLONGREF = ­(VOFF + VAB/2) + ­ SB 500 VLONGREF IF |VLONGREF| < |VAB/2| VLONG = (VA + VB)/2 200 K B RDC DC ELSE VLONGREF = -VBAT/2 FEED CNTL GL = 28.6 µ IAB ­0.5 RAB VREF VREF ­ |VAB/41 VAB/41.33| VDC Volts QBAT VAB controlled by programmable DC Feed Control Block in the ASLAC device VB QBAT/2 VLONG VOFF VLONG Controlled by VLONGREF VA 0 RL Figure 11. Metallic and Longitudinal Control Loop Block Diagram Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 25 SIGNALING Ring Relay Operation The ring relay can be operated in the Synchronous or Asynchronous mode depending on the setting of the ZXR bit in CR5 (MPI Command 35 and Command 36). For synchronous ring relay operation, the ZXR bit is set to a logic 0. In this case, the ring relay is opened or closed at the appropriate voltage or current zero crossings of the ringing waveforms. Ring relay closure occurs at a zero crossing of the ringing voltage waveform relative to QBAT. To open the relay, the relay driver is turned off at a ringing-current zero crossing. During active ringing, a ring relay trigger pulse is generated every time the current ringing waveform crosses zero from either direction (See Figure 12). If the ringing signal disappears, the ring relay is allowed to operate asynchronously after waiting 63 ms. When a zero crossing is again detected, ring relay operation again becomes synchronized to zero cross. Synchronous relay operation can be disabled by setting the ZXR bit in CR5 (MPI Command 35 and Command 36) to a logic 1. In this case, the ring relay will always open or close asynchronously. Ringing Current Zero Crossing Pulses Zero cross relay operation 63 ms Asynchronous relay operation Zero cross relay operation Figure 12. Current Zero Cross Detect Timing for Relay Opening 26 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference Ring Relay Activate Ring relay closure can occur only when the ST2, ST1, and ST0 bits in the SLIC state register (MPI Command 21 and Command 22) have all been set to logic 1. This combination of STn bits forces the ternary code on the ASLIC device state control lines, C1 and C2, to the Ringing state. Ring Relay Release When the ARR (Auto ring relay release) bit in CR5 (MPI Command 35 and Command 36) is a logic 1, ring relay release occurs only when the bits in the ST field of the ASLIC device state register are programmed to anything other than the Ringing state, or in the case of a power-cross detect. When the ARR bit in CR5 is a logic 0, the ring relay will release automatically upon the occurrence of a ring-trip or a power-cross detect, and the ASLIC device will enter the Disable state until a new MPI command is issued that places the ASLIC device in a Nonringing state. The ring relay can still be released synchronously or asynchronously by writing any nonringing ASLIC device control code into the ST field of the ASLIC device state register within the ASLAC device. Teletax Signaling be sent during the Active (normal or reverse polarity) state. Teletax signals can be either 12/16 kHz metering bursts or polarity reversals, depending on the TXTNO bit in CR5. When the TXTNO bit is a logic 0, the ASLIC/ASLAC devices are set for 12/16 kHz teletax operation. When TXTNO is a logic 1, the teletax mode is polarity reversal. Both types of teletax signals must be turned on and off slowly enough to prevent noticeable interference with voice signals. Either 12/16 kHz or polrev teletax is initiated when ST2 = 0, ST1 = 1, and ST0 = 1 is written in the SLIC state register. 12/16 kHz Metering The ASLAC device supplies 12/16 kHz metering signals in the form of a voltage fed from the VM pin. The metering signal is generated internally using the sine, ramp, and gain DACs shown in Figure 13. The output on VM is the ramped sine wave shown in Figure 14. The gain DAC receives its analog reference waveform from the ramp DAC. The 5-bit output of the gain control block controls the gain DAC and sets the target metering signal level that should appear at the VM pin of the ASLAC device. The signal across a nominal 200 , two-wire metering load is approximately 6.67 times VM. Teletax signals are pulses that send call charge information to the subscriber equipment. These signals can 12/16 kHz Sine DAC MTRF 12/16 kHz Select Ramp DAC Gain DAC VM 8 5 Ramp Counter Gain Control 8 kHz Clock Up/Down (Meter On/Off) MLIM 5 Ramp Timing Control NOSL (CR2.2) 4 MTRA Threshold Detector Sample frequency = 128 kHz HPF AX VIN A/D To Voice DSP Figure 13. Metering Generators Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 27 12/16 kHz Shaped metering signal tr Metering enable pulse tf tp Figure 14. 12/16 kHz Metering Waveforms The metering signal that drives the ASLIC device appears at the ASLAC device VM pin as bursts of 12 kHz or 16 kHz sine waves. As shown in Figure 13, the signal at VM originates in a sine DAC whose output is proportional to the sine of its input count. In this manner, a low distortion sine wave can be generated as the frequency divider that drives the sine DAC counts through its range. The MTRF bit of CR4 (MPI Command 33 and Command 34) selects the division factor in the frequency divider block required to produce either 12 kHz or 16 kHz metering frequency. To reduce noise in the voice channel, the NOSL bit in CR2 can be set to a logic 0. In this case, the metering signal is ramped slowly on and off in response to the up/down signal that controls the ramp timing and gain control blocks. Ramping to and from full level lasts 20 ms and is accomplished in a maximum of 160 steps. If, while the metering is ramping up, the metering voltage component at VIN becomes higher than the metering voltage limit programmed by the MLIM field of CR7 (MPI Command 39 and Command 40), the ramp counter is halted before it reaches the full 160 counts. This action prevents the two-wire metering voltage from overdriving the ASLIC device in cases where the two-wire load is high impedance at the metering frequency. If immediate ramp up (< 5 ms) of the 12/16 kHz metering signal is desired, the NOSL bit in CR2 (MPI Command 29 and Command 30) can be set to a logic 1. 28 The high-pass filter (HPF) between VIN and the threshold detector is intended to remove voice frequency components. Because of this filter, the internal threshold voltage corresponds to a different signal level at VIN for 12 and 16 kHz signals. 12 kHz signals are attenuated by 1.23 dB relative to 16 kHz signals. This produces nominal thresholds referred to VIN (AX = 0dB) of 59 to 745 mVrms for 12 kHz and 68 to 862 mVrms for 16 kHz. A table of threshold voltages for all MLIM code combinations appears in the description for CR7 (MPI Command 39 and Command 40) located in the MPI command section of this specification. A table of VM voltage targets for all MTRA code combinations appears in the description for CR4 located in the MPI command (MPI Command 33 and Command 34) section of this specification. Polarity Reverse Polarity reversal places the ASLIC device into a condition where the AD pin is more negative than the BD pin. Setting the TXTNO bit in configuration register, CR5, to a logic 1 defines teletax signaling as a polarity reversal. Setting ST2 = 0, ST1 = 1, and ST0 = 1 in the SLIC state register will then cause a polarity reversal. Abrupt Polarity Reverse For abrupt polarity reverse (SOREV bit of CR5 = 1), the ASLAC device immediately reverses the direction of IDC and places the ASLIC device in the Polarity Reverse state by way of interface pins C1 and C2. The typical abrupt reversal time is about 5 ms. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference Smooth Polarity Reverse Smooth polarity reversal is required in certain administrations where it is used as a teletax signal and applied during normal voice conversation. In this application, the response of the DC control loop must be slowed so that noise from the polarity reversal is not objectionable. The typical smooth reversal time is about 64 ms. SLIC State Register ST = 010 When the SOREV bit is a logic 0, the current in the IDC pin ramps slowly between polarities in response to a polarity reversal initiated by writing the ST field of the ASLIC device state register with the appropriate code (ST2 = 0, ST1 = 1, and ST0 = 1). To prevent unwanted transients in the ASLIC device, the polarity reverse command is actually sent to the ASLIC device only after the current in IDC passes through zero while moving to the opposite polarity. POLREV NORM 64 ms 64 ms IN Current at ASLAC device, IDC pin ZERO OUT ASLIC device in normal polarity (A more positive than B) C2 = GND C1 = VCC ASLIC device in normal polarity (A more positive than B) ASLIC device in reverse polarity (B more positive than A) + VAB 0 ­ Figure 15. Smooth Polarity Reverse Waveforms Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 29 LINE SUPERVISION Off-Hook Detection The line supervision functions include off-hook, ground-key, fault, and ring-trip detection. Threshold levels for all of these functions are independently programmable through the microprocessor interface. Figure 16 shows the block diagram of the ASLAC device loop supervision function. A threshold detector compares ISUM to reference TSH. TSH is the off-hook threshold value previously programmed by the write loop supervision thresholds command (MPI Command 68 and Command 69). When ISUM becomes greater than TSH, an off hook is detected and, after debouncing, the HOOK bit of the signaling register is set to logic 1. To improve noise immunity, hysteresis of approximately 10% of the off-hook threshold current is included before debouncing. Because ISUM is an absolute value signal, metering signals at the two-wire output appear as rectified currents at ISUM. Metering pulses sent after an on-hook may cause ISUM to persist until the end of the metering pulse. Therefore, during the transmission of a metering pulse, the ASLAC device uses the current in IDC instead of ISUM to sense the supervisory loop current. ISUM and IDIF are provided by the ASLIC device. These are scaled-down versions of the sum and differences of the currents in the individual legs of the loop. Using these currents, the ASLAC device is able to perform switchhook, ground-key, and fault detection functions. Detector Threshold Ranges The ranges of programmed loop supervision parameters are summarized in Table 7 and programmed using MPI Commands 72­75. The programmable threshold levels shown in Table 7 are valid only when RREF = 7.87 k. Threshold levels for other values of RREF can be calculated using the following equation: 7.87 ( k ) TSH or TGK (mA) = - x threshold current RREF ( k ) (mA) from Table 7 Switchhook Debounce The debounce circuit eliminates false detection due to contact bounce during switchhook opens and closures. When the ASLAC device is not in Ringing state, the debounce timer takes its input from the loop or groundkey threshold detector. The debounce timer validates a detect after an interval during which no threshold detector transitions in either direction occur. The length of the debounce interval is programmable through MPI. If detection occurs before the interval ends, the timer is restarted from zero and again looks for an interval of no transitions. After debouncing, the result is placed into the HOOK bit (bit 7) of the signaling register. Loss of VBAT will disable the debounce circuit output and will prevent switchhook detect. Table 7. Programmable Threshold Levels Control Field Description Programmable thresholds (RREF = 7.87 k) Units TSH Off-hook threshold 1.3, 2.1, 3.14, 4.1, 6.3, 7.55, 10.06, 12.16, 15.2, 18.34, 20.3, 24.4 mA TGK Ground-key threshold 1.1, 1.9, 2.83, 3.8, 6.0, 7.23, 9.64, 11.6, 14.6, 17.6, 19.6, 23.7 mA DSH Debounce timer interval 0 to 15 in steps of 1 ms GKNT Ground-key integration time Integration disabled, 16 2/3, 50, 60, 100 ms 30 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference R S1B RGFD1 RING BUS T S1A Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference BD SB SA AD A LEG POWER AMP Sum/Difference IDIF CDIF VREF ISUM From A Leg, 20 Sense Resistor B LEG ASLIC Device POWER AMP 20 To TX AMP and DC Feed Control To Sum/Difference Block 20 ASLIC Device Note: S1 shown in nonringing position RFB RSR1 RSR2 RSB RSA RFA BGND IDIF ISUM IRTA virta-irtb VIN Ring Trip Ring Relay Control Logic Enable/Disable Operate on zero cross Ring Relay Control Ring-trip filter and 104 ms Threshold ComparaDebounce tor (Part of DSP) 13.5 ms Debounce Power-Cross Validation ST Field SLIC State Register Current Zero Cross Pulses pkFT FT Fault Detector TGK Fault Detector Ground-Key Threshold Detector Switchhook Threshold Detector 4 ms Debounce Integrator GKNT Integrator Debounce MUX Signaling Register Fault Bit Signaling Register GNDX Bit DSP Clock Frequencies: Voice Mode - 8 kHz Ringing State - 500 Hz TSH DSH Ring-trip and power-cross IRTB S1C functions (analog part) vRGFD1 > 50 V Voltage Zero Cross Pulses ASLAC Device Ringing Figure 16. Loop Supervision Architecture-ASLIC/ASLAC Devices 31 Signaling Register Hook Bit Ground-Key Detection A threshold detector compares IDIF to reference TGK. TGK is the ground-key threshold value previously programmed by the write loop supervision thresholds command (MPI Command 68 and Command 69). When IDIF becomes greater than TGK, a ground key is detected and, after integration to remove longitudinal AC disturbances, the GNK bit of the signaling register is set to logic 1. Operation of the ground-key integrator is discussed later in this specification. To improve noise immunity, hysteresis of approximately 10% of the ground-key threshold current is included before the ground-key integrator. Ground-Key Integrator The output of the ground-key threshold detector is fed to the ground-key integrator, which ensures the groundkey detector function will operate even in the presence of 60 Hz, 50 Hz, or 16 2/3 Hz longitudinal disturbances. To accomplish this, the integrator determines the average time that the detector output is on or off during an integral number of cycles of the longitudinal disturbance signal. Differences between average on and off times determine the actual detection status. The integration time can be programmed to 100 ms, 60 ms, 50 ms or 16 2/3 ms using the GKNT field in COP Command 9. The integrator is enabled or disabled using the GKNTDIS bit. The 100 ms integration time is used for both 50 Hz and 60 Hz currents. The 60 ms integration time is used for averaging both 50 Hz and 16 2/3 Hz currents, while the 50 ms time is used for 60 Hz currents. The 16 2/3 ms integration time is used to reduce ground-key response times to a minimum in the case of a remote ring lead seizure. After integration, the result is placed in the GNK bit (bit 6) of the signaling register. Because the sampling rate of the ground-key integrator is 8 kHz, aliasing is possible when high-frequency longitudinal disturbances occur. Therefore, an external filter capacitor between pin IDIF and VREF must be used to provide immunity to high-frequency noise. Ring-Trip Detection The ring-trip detection function is implemented as shown in Figure 16. The voltage drop across RGFD1 is proportional to the ringing current flowing in the loop. The voltages on either side of RGFD1 are sensed by ringing sense resistors RSR1 and RSR2 that feed the current difference circuit in the ASLAC device through pins IRTA and IRTB. As a result, the current flowing out of the current difference circuit is proportional to the ringing current flowing in the loop. This current is used in the ASLAC device for ring-trip, power-cross detect, and ring relay release functions. The ring-trip function provides optimum load and response performance by utilizing different techniques, depending on the length of the loop. For short loops (less than 1000 , when response time is critical), ring trip occurs when an off-hook condition that causes the line current to exceed 98 mA through RGFD1 (50 V with RGFD1 = 510 ) for longer than 13.5 ms. For long loops, the current through RGFD1 does not exceed 98 mA, therefore, a ring-trip filter and comparator arrangement combined with a 104 ms debouncer must be used as described below. Loss of VBAT will disable the 104 ms debounce output and prevent ring-trip detection. During ringing, the A/D input is switched from its normal connection to the ASLAC device VIN pin and connected to the output of the current differencing circuit. The A/D produces a 19-bit word which is then sampled every 2 ms (500 Hz sampling rate) by the low-pass, ring-trip filter implemented in the DSP. The ring-trip filter has a bandwidth of approximately 4 Hz and removes enough of the ringing ripple so a reliable ring trip can be detected by the threshold comparator. The ring-trip current threshold, against which the ring-trip filter output is compared, represents a DC voltage across RGFD1. Various current detection thresholds can be programmed by MPI Command 62 and Command 63. When an off hook occurs, the ringing waveform exhibits a shift in average DC content. When the average DC level is detected to be above the programmed ring-trip threshold, a debounce timer is initiated. If the ring-trip threshold is set such that the negative peaks do not fall below the threshold, the timer will end after 104 ms. The result of this sequence of events will set the hook bit and indicate the intention to open the ring relay. Assuming the auto ring relay release is enabled, the next current zero crossing will instruct the ring relay to open and enable the zero crossing hysteresis for power-cross protection. Exiting ring, either by programming or by ring trip, will cause the internal circuitry to reset all timers and enable switchhook detection. Once switchhook detection is enabled, the respective debounces for fault detection (15 ms first period and 4 ms thereafter) and switchhook detection (programmable from 1 to 15 ms) must be satisfied before any internal registers will change. If the receiving phone is taken off hook during the cadence, off hook will be detected by the normal off-hook detection circuitry. Specified ring-trip detection thresholds are relative to RGFD1 = 510 . The ring-trip filter in the DSP reduces the AC component to a point where the filtered output can be compared to threshold voltage and reliably determine whether a ring trip has occurred. The DSP implements a ring-trip filter with a pair of complex poles that provides the high level of filtering required for reliable ring-trip detection. This filter is described by the following transfer functions: a0 h z = H2 ( z ) · - 1 + a1 · z 32 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference ­1 + a2 · z ­2 Where: a0 = 0.00390625; a1 = ­1.9375; a2 = 0.941406; sampling rate = 500 Hz ­ k 1 H2 ( z ) = z · - where k = 0 .15 16 k When a ring trip occurs, a logic 1 is placed into the HOOK bit (bit 7) of the signaling register (MPI Command 14). Because the ring-trip current detection thresholds are sensed by the voltage developed across RGFD1, altering the value of RGFD1 will necessitate recalulating the ring-trip current thresholds. It is possible to scale RSR1 and RSR2 to offset this difference, however, the voltage and current zero crossing thresholds will also change. Before altering the values of RGFD1, RSR1, and RSR2, contact CPD linecard applications staff for more information. Power-Cross Detection During Ringing During the Ringing state, the ASLIC device and its surge protector are not connected to the line. When a 60 Hz power cross occurs, the normal ring-trip circuitry in the ASLAC device should detect it and immediately release the ring relay. For higher power-cross levels, the normal ring trip may not function because of signal overload of the A/D in the ASLAC device. Therefore, an independent method of detecting a power cross during ring trip is provided. This method is described below. During ringing, any current higher than 98 mA peak across RGFD1, the ring-feed resistor, is detected by the ASLAC device as a possible power-cross condition. The ASLAC device also observes the zero crossings of the voltage across RGFD1. If, for two cycles, a voltage greater than 50 V (98 mA · 510 ) is detected between two successive voltage zero crossings and the period of the zero crossings is between 13.5 ms and 24 ms (75 and 40 Hz), a power cross is confirmed and the ring relay releases. If a power cross occurs that does not exceed the 50 V limit, a ring trip will still happen because it is processed as if it were a normal ring trip. Line Fault Alarm The ASLAC device detects positive leg-to-battery faults by comparing the longitudinal sense current, IDIF, to a reference that represents a DC fault current of FT (see Figure 16). If the DC fault current exceeds FT from the most positive lead to QBAT, the FAULT bit in the signaling register is set to a logic 1 after the programmed ground-key integration time. To improve noise immunity, hysteresis of approximately 15% of the loop current is included. Ring-to-ground faults cannot be distinguished from a normal ground key. However, this type of fault can be recognized as a ground key that persists for an excessively long time. If the circuit configuration is changed from that on the schematic and the RSB sense resistor is exposed to the ringing voltage, a false fault bit may occur during ringing cadence when the ring off command is sent when zero crossing ring relay is enabled. This is because of the detection int he ASLIC device which is designed to force IDIF to ground when the voltage difference between the SA and SB pins is greater than 7.5 V. This condition would normally be met by the overvoltage protection firing on the two wire side. The ASLAC device will interpret the grounded IDIF as a fault current greater than 52 mA. When the resistors are outside the sense loop the fault detector in the ASLIC device will cause the IDIF voltage to oscillate at the ringing frequency. If a ringing off command is received when the IDIF voltage is low, a fault detection will occur if the zero crossing release is more than 4 ms away (the fault is debounced with a 4 ms counter). Power-Cross Alarm When either low-level or high-level power crosses occur, the ASLIC device and ASLAC device signal these events by setting the FAULT bit in the signaling register. After this bit is set, a relay can be operated that safely removes the linecard from service. When the junction temperature of the ASLIC device reaches approximately 160°C, the ASLIC device signals this condition to the ASLAC device by driving the VDC pin to a voltage specified in the ASLIC device DC Specifications table. In normal operation, the voltage at this pin should always be less than VREF. The VDC pin feeds the IAB pin of the ASLAC device through an external resistor, RAB. Low-level power crosses can occur that fail to activate any of the external thyristor protection devices. In this situation, the ASLIC/ASLAC devices must differentiate between unacceptable power-cross current levels and low-level longitudinal induction current levels that do not affect the operation of the linecard. To accomplish this, the ASLAC device sets the FAULT bit only when each longitudinal current peak becomes greater than pkFT for more than 4 ms. If the fault current drops below pkFT for more than 4 ms and the average longitudinal current is less than FT, the FAULT bit is reset to a logic 0. When an ASLIC device thermal overload condition is present, TEMPA (bit 3) in the signaling register (MPI Command 14) is set to a logic 1. Low-level power crosses on the B lead that fail to set the FAULT bit can be recognized as a persistent ground key indication by the GNDX bit in the signaling register. Alarms Thermal Overload Alarm The external thyristor device on the linecard provides protection when larger power line voltages appear at Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 33 the subscriber line interface and the protection relay cannot be activated fast enough to prevent destruction of the ASLIC device. When the thyristors trigger, the fault currents are diverted to ground. In this case, the fault condition can only be recognized as a persistent ground key. By the time the fault is recognized and the protection relay is activated, the external fuse resistors (see Figure 16) may have already been destroyed. To solve this problem, the voltages across RFA and RFB are directly sensed by the ASLIC device as the voltages between AD and SA and BD and SB respectively. When the voltage across either of the fuse resistors exceeds 7.5 V peak, the ASLIC device senses this and immediately forces the voltage at its IDIF pin to ground. The ASLAC device detects this condition on its own IDIF pin as a current equivalent to more than pkFT mA of longitudinal current and sets the FAULT bit in the signaling register to a logic 1. Clock Failure Alarm The clock failure alarm will detect four conditions: missing MCLK clock pulses, programmed MCLK frequency unmatched to applied frequency, internal phase locked loop not locked, and missing frame sync pulses. Incoming clock pulses on the MCLK pin are continuously counted from the beginning of one frame to the beginning of the next frame. There should be exactly 1024 clock cycles per frame for an 8.192 MHz clock, 512 clocks per frame for a 4.096 MHz clock, or 256 clocks for a 2.048 MHz clock. Any deviation from the expected clock count caused by clock or frame sync aberrations greater than ± 2 clock cycles will set bit 2 in the signaling register to a logic 1. Power Interrupt Alarm The ASLAC device senses the voltage present at VCC. If the power supply falls below a fixed threshold of approximately 1.5 V for a period greater than 2 µs, the PI bit is set in the SLIC I/O register (MPI Command 20). When this bit is set, the device is disabled and will require complete reprogramming. The PI bit in the ASLIC device I/O register will read back as a logic 1 to indicate that a power interruption has been detected. LINE STATUS INDICATORS Go/NoGo Tests with Test Load There are two types of Go/NoGo tests. One of these types monitors DC Loop conditions and the results are available on a continuous basis from the signaling register (MPI Command 14). The other type of Go/NoGo test is one that does not continuously monitor conditions in the ASLAC device but requires initial setup by software or firmware commands. These tests are controlled and monitored by bits 4 through 6 in configuration register 2. Results are valid 34 only after 63 ms when the measurement valid bit has been set by the ASLAC device. The following are descriptions of the Go/NoGo test bits available in the signaling (SIG) and CR2 registers. Loop Sense Bit (SIG, bit 7) Bit 7 in the signaling register is set to a logic 1 when the current through a test resistor is greater than or equal to the programmed off-hook threshold current (TSH). Ground Key Bit (SIG, bit 6) This bit in the signaling register indicates when abnormal longitudinal currents are present. These currents could result from a defective ASLIC device or high lineto-ground leakage levels. When these currents are greater than the programmed ground-key threshold current (TGK), bit 6 in the signaling register is set to a logic 1. Voltage Bit (SIG, bit 5) When the ASLIC device is operating in the Anti-Sat state, this bit is set to a logic 1. Current Bit (SIG, bit 4) When the ASLIC device is operating in the current limit region, this bit is set to a logic 1. Ringing Voltage Bit (CR2, bit 4) In this test, the ring relay is operated along with the test relay that connects a test resistor across the line. To start the test, the OKTTX and OKTON bits are reset, the OKRNG bit and the TVD bit (bit 7) are set. Then the OKRNG bit is set, and the TVD bit (bit 7) is reset. The ringing current through the test resistor is sensed and processed by the ASLAC device in the same manner as a ring trip. In this test, however, the ring-trip filter cutoff frequency is increased 16 times by clocking it at 8 kHz instead of 500 Hz. Because of this, the ring signal is unaffected as it goes through the ring-trip filter. Also, during this test, an attenuation of 1 or 16 times (depending upon the setting of bit 7, CR5) is inserted after the A/D to improve resolution for higher ringing currents. The ringing signal is then compared to the ring-threshold level set by the coefficients in MPI Command 60 and Command 61. After 63 ms, the ASLAC device sets the TVD bit and if the current is less than the programmed level, the OKRNG bit is reset. Otherwise the bit remains set. During this test, the transmit path PCM output is activated and the high-pass filter disabled. This allows monitoring of the AC and DC components of the ringing signal. To eliminate the effect of the DC component of the ringing signal, the high-pass filter in the DSP can be activated by clearing the DHP bit of CR1. Meter Voltage Bit (CR2, bit 5) This test uses the metering signal limit-threshold detector to compare the programmed value of MLIM with the metering echo level on VIN (see Figure 13). To start this test, the OKRNG and OKTON bits are reset, the OKTTX Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference bit and the TVD bits are set.Then the OKTTX bit is set, and the TVD bit reset. After 63 ms, the ASLAC device sets the TVD bit and if the metering echo has never exceeded the MLIM level, the OKTTX bit is reset; otherwise it remains set. If the metering signal is at such a low level that it never produces an echo larger than MLIM, it will not be detected. For test purposes, the metering signal can be increased to a level that guarantees detection. This can be done by programming the MTRA field in CR4. Pass Tone Bit (CR2, bit 6) To start the pass tone test, the TON bit in CR1 is set then OKRNG and OKTTX bits are reset, and OKTON and TVD are set. Then the OKTON bit is set and the TVD bit is reset. A 1 kHz, 0 dBm0 signal is generated by the DSP and applied to the receive digital input. The signal is routed through the receive DSP path in the ASLAC device and the ASLIC device to the test load. The pass tone echo is sent back through the ASLIC device and ASLAC device transmit path and measured at the B-filter summing point. If the B filter and ASLAC device gains are adjusted to exactly cancel the return echo under nominal conditions, no signal will be measured at the digital output. If the gains deviate in either direction from nominal values, an error signal appears at the digital output. This error signal is compared to an Error Level Threshold (ELT) programmed by MPI Command 58. After 63 ms, the ASLAC device sets the TVD bit and, if the signal exceeds the ELT, then the OKTON bit is reset. Otherwise, it remains set. (test valid) bit is set to a logic 0. The OKTTX, OKRNG, and OKTON bits in CR2 should be logic 0's. If zero crossings occur within 63 ms from the test start, the RINGX bit in the signaling register will be reset. When a zero crossing fails to appear within 63 ms, the RINGX bit is set, indicating that the ringing signal is no longer present. The only way to clear the RINGX bit after a test failure is to reset the ASLAC device or repair the fault and rerun the test. During normal ringing, the RINGX bit will be set to 0 initially and will go to a logic 1 if the ringing signal is lost. Line Test Modes To facilitate tests of the subscriber line, the TM bit in CR2 is set, which makes available special ASLAC device test states where signal levels proportional to DC loop voltage, VAB (current IAB into the ASLAC device is proportional to VAB), are converted to a digital code and sent toward the network by the PCM interface. The full-scale value corresponds to a DC loop voltage of 50 VDC. To use these test states, the following configuration adjustments must be made: 1. ASLIC/ASLAC devices to Standby using the ST bits (ST2 = ST1 = ST0 = 0) 2. Set the gain of the AISN to 0 and AX to 0 dB (00h in MPI Command 76) 3. Disable transmit high-pass filter (CR1.1 = 1) 4. Enable test mode (CR2.3 = 1) 5. Program the ASLAC device filter gains (shown in Table 8) using the command and coefficients indicated Ringing Present Bit (SIG, bit 1) In this test, the presence of ringing voltage is sensed by timing the occurrence of the voltage zero crossings of the ringing signal at IRTA, which senses the linecard side of the ring feed resistor. To start this test, the TVD 6. Set the ASLIC/ASLAC devices to the Active state (ST2 = 0; ST1 = 1; ST0 = 0). Table 8. ASLAC Device Filter Gains for Line Test Modes Filter gains MPI Command # Coefficients (in Hex unless otherwise noted) Z gain = 0 V/V 48 01 90 01 90 01 90 01 90 01 90 01 90 01 01 90 B gain = 0 V/V 50 09 00 90 09 00 90 09 00 90 09 00 90 09 00 01 90 GX gain = 0 dB 44 80 80 X gain = 0 dB 52 01 11 01 90 01 90 01 90 01 90 01 90 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 35 In some cases, equipment used for line evaluation are AC coupled or can only measure signals in the voice band. To accommodate this type of equipment, the SBT bit in CR5 has been provided which, when set, causes the measurement samples from the A/D output that are to be placed in the PCM channel to be first converted to AC or "chopped" by reversing the sign bit (bit 7) every 0.5 ms. Metallic Leakage Measurement Metallic (line-to-line) leakage resistance can be measured with greater accuracy using the following steps: 1. Set a loop current of 0.625 mA. This is accomplished by using MPI Command 66 to set ILA = 10.1 mA and setting the IDC/16 IDC/16 bit in CR5 to a logic 1. 2. With the TM bit in CR2 set to a logic 1, the metallic leakage resistance is obtained using the following equation: VAB Rleak = -0.625 + ASLIC Metallic Offset Current ( mA ) Remote Line Tests through the PCM Channel The current in the two-wire loop is K1 times the current into the RSN node of the ASLIC device. The current at the RSN node of the ASLIC device can be controlled by the VOUT pin of the ASLAC device through RRX. The full-scale output voltage of the VOUT pin is VREF ±1.25 V. The maximum current which can be controlled by this method is given by: 1.25V ILOOP = - · K1 + ASLIC Metallic Offset Current ( mA ) RRX By sending different values of A-law or µ-law codes, currents between 0 and ILOOP of each polarity may be sent. It would be necessary to reverse the polarity of the ASLIC/ASLAC devices for proper operation of negative currents. In order for VOUT to have exclusive control of the RSN node, the following configuration adjustments must be made: 1. Inactivate the ASLAC device 2. Set the gain of the AISN to 0 and AR to 0 dB (00h in MPI Command 76 and Command 77) 3. Program the current limit (ILA or ILD) to 5 mA in MPI Command 66 and Command 67 4. Set the IDC/16 IDC/16 bit in CR 5 5. Program the following ASLAC device filter gains using the commands and coefficients indicated 6. Set the ASLIC device to the Active state using the ST bits, (ST2 = 0; ST1 = 1; ST0 = 0) Table 9. ASLAC Device Filter Gains for PCM Remote Line Tests Filter gains MPI Command # Coefficients (in hex unless otherwise noted) Z gain = 0 V/V 48 01 90 01 90 01 90 01 90 01 90 01 90 01 01 90 B gain = 0 V/V 50 09 00 90 09 00 90 09 00 90 09 00 90 09 00 01 90 GX gain = 0 dB 44 80 80 X gain = 0 dB 52 01 11 01 90 01 90 01 90 01 90 01 90 GR gain = 0 dB 46 01 11 R gain = 0 dB 54 80 01 80 01 80 80 80 80 80 80 80 80 80 80 RG gain = 0 dB 27 CR1, bit 2 = logic 0 After these steps are performed, the current in the loop will be directly proportional to the voltage on the VOUT pin of the ASLAC device, which is controlled by the PCM channel codes. This relationship will hold as long as the loop impedance is low enough to allow the voltage across the loop to be lower than the anti-sat point. The DC voltage on the remote line can then be monitored by setting the TM bit in CR2. This encodes the voltage on the transmit PCM channel. 36 Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference Table 10. VOUT vs. PCM Coding Coding Law A-law (zero) A-law (max/min) µ-law (zero) µ-law (max/min) PCM code VOUT (V) 01010101 2.1 (VREF) 00101010/10101010 0.904/3.3 01111111 2.1 (VREF) 00000000/10000000 0.904/3.3 Leakage Current Tests Quick tests for leakage levels that are greater than predetermined threshold levels are available by placing the ASLIC device in various states and comparing the metallic and longitudinal current levels (ISUM and IDIF) against threshold levels programmed by the TSH and TGK fields in MPI Command 72 and Command 73. Note that this test can only compare leakage currents and not resistances. To measure resistance, a more precise measurement technique is described in the metallic leakage measurements section. To test metallic leakage current, the ASLIC device is placed in the Standby state and the desired leakage current threshold programmed using the TSH field. This current threshold represents a metallic leakage resistance threshold calculated by dividing the battery voltage by the programmed TSH current. When the leakage current is greater than the TSH current, the HOOK bit in the signaling register will be set, which means the metallic leakage resistance is less than the threshold resistance. Ring-to-ground and tip-to-ground leakages are tested by placing the ASLIC device in the Tip Open or Ring Open state respectively and programming the TGK field for the desired leakage current threshold. As in the metallic leakage case, the programmed resistance thresh- old is found by dividing the battery voltage by the programmed TGK current. When the leakage current is greater than the TGK current, the GNK bit in the signaling register will be set. Loopback Modes The ASLAC device provides digital loopback paths as shown in Figure 17. The TS Loopback mode (TSLB) internally feeds the selected receive PCM data to the selected transmit PCM channel, however, it does not affect the status of transmit cutoff while the transmit signal processor is opened. The receive and transmitter processor paths may be opened by setting the COR and COX bits in CR1 to logic 1. The Time Slot Loopback mode is invoked by setting the TSLB bit in CR1 to a logic 1. In TSA Loopback mode, PCM data has 2 frame sync. delays. Linear data has only one frame sync delay. The PCM Hiways (A or B) are selected by MPI Commands 8, 9, 10, and 11. A Full Loopback mode (FLB) is also provided, which disconnects the ASLAC device from the ASLIC device and routes the receive data through the D/A converter, through the A/D converter, and back to the transmit output. The Full Loopback mode is invoked by setting the FLB bit in CR1 to a logic 1 or by programming the AISN coefficient to 10000. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 37 Transmit Path Cutoff VIN ADC Analog Loopback Mode ALB = 1 Full AISN Loopback Mode FLB = 1 DAC Transmit Signal Processing Decimator Interpolator VOUT DX DXA DXB PCM HIWAY SEL MPI: 8, 9 Z Time Slot Loopback Mode TSLB = 1 B Receive Signal Processing Switches shown in normal voice transmission position DRA DR Receive Path Cutoff DRB PCM HIWAY SEL MPI: 10, 11 Figure 17. Loopback Paths The ASLAC device MPI consists of serial data input and output (DI/O), data clock (DCLK), and a chip select CS (Figure 18). The serial input consists of 8-bit command words which may be followed with additional bytes of input data or may be followed by the ASLAC device sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. The ASLAC device's MPI will not accept a command or data byte of less than 8 bits; if more than 8 bits are sent during CS Low, the last 8 bits will be interpreted as the command or data byte. All data bytes are read or written one at a time, with CS going High for at least the minimum off period before the next byte is read or written. All commands that require additional input data to the device must have the input data as the next n words written into the device. All commands that are followed 38 by output data will cause the device to output data for the next n transitions of CS going Low. The ASLAC device will not accept any input commands until all the data has been shifted out. Unused bits in the data bytes are read out as zeros. An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the High state between accesses, the DCLK may run continuously with no change to the internal control data. Using this method, the same DCLK may be run to a number of ASLAC devices and the individual CS lines will select the appropriate device to access. It should be noted that the DCLK can stay in the High state indefinitely with no loss of internal control information regardless of any transitions on the CS lines. If CS is held Low for 16 DCLK cycles, a hardware reset is executed. Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference CS CS Off Period 1 2 3 4 5 6 7 8 1 2 3 DCLK Three-State DOUT DIN Figure 18. Microprocessor Interface Timing Diagram Am79213/Am79C203/031 Am79213/Am79C203/031 Technical Reference 39 Table 11. MPI Commands C# Hex D7 D6 D5 D4 D3 D2 D1 D0 1. 00 0 0 0 0 0 0 0 0 Inactivate 2. 02 0 0 0 0 0 0 1 0 Software reset to normal 3. 04 0 0 0 0 0 1 0 0 Hardware reset 4. 06 0 0 0 0 0 1 1 0 No operation 6. 0E 0 0 0 0 1 1 1 0 Activate 8. 40 0 1 0 0 0 0 0 0 Write TX time slot and PCM highway 9. 41 0 1 0 0 0 0 0 1 Read TX time slot and PCM highway 10. 42 0 1 0 0 0 0 1 0 Write RX time slot and PCM highway 11. 43 0 1 0 0 0 0 1 1 Read RX time slot and PCM highway 12. 44 0 1 0 0 0 1 0 0 Write RX and TX clock slot selection 13. 45 0 1 0 0 0 1 0 1 Read RX and TX clock slot selection 14. 4F 0 1 0 0 1 1 1 1 Read signaling register 17. 52 0 1 0 1 0 0 1 0 Write Input/Output register 18. 53 0 1 0 1 0 0 1 1 Read Input/Output register 19. 54 0 1 0 1 0 1 0 0 Write Input/Output register direction 20. 55 0 1 0 1 0 1 0 1 Read I/O direction, power interrupt & channel status 21. 56 0 1 0 1 0 1 1 0 Write SLIC state register 22. 57 0 1 0 1 0 1 1 1 Read SLIC state register 23. 5C 0 1 0 1 1 1 0 0 Write special I/O register 24. 5D 0 1 0 1 1 1 0 1 Read special I/O register 25. 60 0 1 1 0 0 0 0 0 Write operating functions 26. 61 0 1 1 0 0 0 0 1 Read operating functions 27. 62 0 1 1 0 0 0 1 0 Write configuration register 1 (CR1) 28. 63 0 1 1 0 0 0 1 1 Read configuration register 1 (CR1) 29. 64 0 1 1 0 0 1 0 0 Write configuration register 2