Am79212/Am79C202 CPD/P-110 IDC/16 IL00P VAB/41 - Datasheet Archive

 

Advanced Subscriber Line Interface Circuit (ASLIC TM) Device Advanced Subscriber Line Audio-Processing Circuit (ASLACTM) Device

 

Am79212/Am79C202 Am79212/Am79C202 Advanced Subscriber Line Interface Circuit (ASLIC TM) Device Advanced Subscriber Line Audio-Processing Circuit (ASLACTM) Device Technical Reference TABLE OF CONTENTS Linecard Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Operating the ASLIC/ASLAC Devices Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ASLIC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ASLIC Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ASLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ASLAC Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Default States and Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Overview of Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Distortion Correction and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transhybrid Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Gain Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog Impedance Scaling Network (AISN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Speech Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC Feed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC Feed in the Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC Feed in the Standby, Tip Open, and Ring Open States . . . . . . . . . . . . . . . . . . . . . . . . . 21 Longitudinal Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ring Relay Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ring Relay Activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ring Relay Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Teletax Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12/16 kHz Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Line Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Detector Threshold Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ground-Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ground-Key Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ring-Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Line Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Go/NoGo Tests with Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General Control Interface (GCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 GCI General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ASLAC Device GCI Format and Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 The SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 The Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# CPD/P-110 CPD/P-110 Rev: A Amendment: /0 Issue Date: January 1998 TOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Summary of Monitor Channel COP Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Detailed Descriptions of Monitor Channel COP Commands . . . . . . . . . . . . . . . . . . . . 58 ASLIC/ASLAC Devices Linecard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 General Description of CSD Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 CRC Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 C Program for CRC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 2 Voice Transmission Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC Feed Control Block Diagram for Active and Disable States . . . . . . . . . . . . . 17 DC Feed Plot, VAB vs. ILOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage Current Characteristic for the North American Market . . . . . . . . . . . . . 20 Line Current vs. Loop Resistance for the North American Market . . . . . . . . . . . 20 Standby, Tip Open, and Ring Open State Internal Configuration . . . . . . . . . . . 21 Longitudinal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Metallic and Longitudinal Control Loop Block Diagram . . . . . . . . . . . . . . . . . . . 23 Zero Cross Detect Timing for Relay Opening . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Metering Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12/16 kHz Metering Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Smooth Polarity Reverse Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Loop Supervision Architecture-ASLIC/ASLAC Devices . . . . . . . . . . . . . . . . . . . 29 Loopback Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Time Slot Control and GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Multiplexed GCI Time Slot Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Security Procedure for C/I Downstream Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Maximum Speed Monitor Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Monitor Transmitter State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Monitor Receiver State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Signaling Register Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ASLIC/ASLAC Typical Linecard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Am79212/Am79C202 Am79212/Am79C202 Technical Reference LIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 ASLIC Device Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SC Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Monitor Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 COP Commands (Coefficient Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC Feed Control Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 External Component Effects on DC Feed Parameters . . . . . . . . . . . . . . . . . . . 19 Longitudinal Control Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programmable Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ASLAC Device Filter Gains for Line Test Modes . . . . . . . . . . . . . . . . . . . . . . . . 33 ASLAC Device Filter Gains for PCM Remote Line Tests . . . . . . . . . . . . . . . . . . 34 VOUT vs. PCM Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Loopback Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Channel Assignment Codes (Timeslot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ASLIC/ASLAC Devices Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Class of Monitor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ASLAC Device DSP Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Loop Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 VAPP & RFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 N2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 VAS & VOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Off-Hook and Ground-Key Threshold Current . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Presence of Ringing Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ASLIC/ASLAC Devices Linecard Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Am79212/Am79C202 Am79212/Am79C202 Technical Reference 3 The Am79212/Am79C202 Am79212/Am79C202 Advanced Subscriber Line Interface chip set implements a universal telephone line interface function. This enables the design of a single, low-cost, high-performance, fully-software-programmable line interface card for multiple country applications world wide. All AC, DC, and Signaling parameters are fully programmable via the General Control Interface (GCI). Additionally, the ASLIC device and ASLAC device have integrated self test and line test capabilities to resolve faults to the line or line circuit. The integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective. This document is meant to be used with the data sheet, PID 19780. LINECARD BLOCK DIAGRAM Loop Voltage Sense Resistors Transmit Receive Ring and Test Relays AD DC Feed Control Metering SA ASLIC Device Loop Voltage Monitor SB Loop Current Monitor BD B(Ring) ASLAC Device RFB Relay Driver Outputs ASLIC Device Operating State Ring-Feed Resistor Relay Driver Inputs Ringer Supply Ringing-Current Sense Resistors 4 Am79212/Am79C202 Am79212/Am79C202 Technical Reference GCI Backplane RFA A(Tip) OPERATING THE ASLIC/ASLAC DEVICES PAIR ASLIC Device Table 1 defines the ASLIC device operating states set by ternary logic pins C1 and C2. The three states of the ternary input from the ASLAC device are VCC, ground (GND), and 3-state or floating (FL). Table 1. ASLIC Device Operating States C2 C1 Operating State VCC FL Disconnect ­ AD and BD at High-Z, Channel A and B power amplifiers shut down Open Disconnect VCC GND Ringing ­ RINGOUT activated Open Ringing GND GND Active feed, normal polarity B amplifier output Disconnect VCC VCC Ring Open ­ BD at High-Z, AD resistive feed through RTMG, both amplifiers shut down AD pin Ring Open FL VCC Tip Open ­ AD at High-Z, BD current limited resistive feed through internal resistor, both amplifiers shut down Open Tip Open FL FL Standby (High ohmic feed) ­ Loop supervision active, A and B amplifiers shut down Open Standby GND VCC Active feed, Reverse polarity A amplifier output Disconnect GND FL Disable (low-power active feed state) Open Disconnect FL GND Standby (Not a valid state from the ASLAC device) Open Standby Pins C3, C4, and C5 control relay driver outputs RY1OUT, RY2OUT, and RY3OUT. A logic High on the relay control inputs causes the relay driver outputs to be pulled to battery ground. When a relay control input is left unconnected, the corresponding relay driver will be in the high-impedance off state. RTMG Connection Operating State in Thermal Shutdown Tip Open In this state, the tip lead is opened and the ring lead is connected to VBAT through an internal resistor (typically 250 ). The current in the ring lead is limited by the ASLIC device to 40 mA (typical). Standby Disconnect This state disconnects both A and B output amplifiers from the AD and BD outputs. The A and B amplifiers are shut down. Ringing RINGOUT, the ring relay driver, is turned on and pulled to BGND. During the Ringing state, the A and B power amplifiers are turned off and their outputs placed in a high-impedance state. Active Feed, Normal Polarity A normal polarity active is usually enabled during a call. Both output amplifiers deliver the full power level determined by the DC Feed conditions set by the ASLAC device. The AD output of the ASLIC device is positive with respect to the BD output when current flows out of the RSN pin. Ring Open In this state, the ring lead is opened and the tip lead is switched to VBAT through the external thermal management resistor, RTMG. The power amplifiers are turned off and the AD and BD outputs are driven by internal 250 (typical) resistors connected to ground and VBAT respectively. Line supervision remains active. Current limiters are provided on each line to limit power dissipation under short loop conditions. In the Standby state, the ASLIC device is in normal polarity. Active Feed, Reverse Polarity Reverse polarity is the same as normal polarity except the AD output of the ASLIC device is negative with respect to the BD output. Disable Current bias levels to the power amplifiers are lowered in this mode to reduce the on-hook ASLIC device power dissipation. Loop-current limit levels as determined by the ASLAC device are also reduced in the Disable state. On-hook transmission and loop supervision are possible in this state. Am79212/Am79C202 Am79212/Am79C202 Technical Reference 5 ASLIC Device Block Diagram A-Wire Output Amplifier AD RSN Input Amplifier RSN Loop-Current Sensing IDC IA VREF Thermal Management Control SA Transmit Amplifier + ­ IA + IB 600 + IA IB ISUM + 1/4 VTX 6 HPA BAL2 12 VLONG VAB HPB BAL1 VHPA Thermal Shutdown + ­ VHPB Longitudinal Control Amplifier ­0.5 + ­ + + ­ SB VDC 1/20.67 VLBIAS ­6 B-Wire Output Amplifier VBAT BD + ­ IA IB Loop-Current Sensing To A-Wire Output Amplifier IA ­ IB 600 IDIF IB Thermal Management Control TMG ASLIC Device STATE CTL BUS RINGOUT RY1OUT RY2OUT C1 Ternary Decode C2 C3 C4 Relay Drivers C5 RY3OUT VBAT 6 VCC Am79212/Am79C202 Am79212/Am79C202 Technical Reference GND BGND ASLAC Device Active State After a proper power-up sequence, the ASLAC device can operate in either the Active or Inactive state. The ASLAC device is forced into the Inactive state at powerup or by a hardware or software reset. 2. VCC In the Active state, the ASLAC device is able to transmit and receive PCM and analog information. This is the normal operating mode when a telephone call is in progress. The ASLAC device may be brought into the Active state by any one of three methods: 1) writing Activate (CR1.7); 2) writing certain states in the C/I register bits, ST0, ST1, ST2; or 3) by writing the TVD bit in configuration register #2. The ASLIC device Active state and DC Feed sections of the ASLAC device are controlled separately by the ST bits in the C/I channel. 3. VBAT Inactive State Power-Up Sequence from VCC = 0 V The recommended power-up sequence is to apply: 1. Power supply grounds 4. Signal connections 5. Hardware Reset The software initialization should then include: 1. Software Reset 2. Program filter coefficients 3. Activate Software initialization of the ASLAC device should always follow any power-up or hardware reset. Inactive state is enabled by placing a logic 0 in the ACT bit of configuration register 1. No transmission or reception of voice data takes place, but the circuits that contain programmed information retain their data. Power is removed from all nonessential circuitry though the GCI interface remains active to receive new commands. Certain ASLIC device states and the TVD bit override an Inactivate command. The ASLIC device activate states are detailed at CR1. Upon initial application of power, a minimum of 1 ms is needed before any C/I command is initiated. If the power supply falls below a specified value, the device is reset and will require complete reprogramming with the above sequence. Please refer to the PI description for more details on this feature. Am79212/Am79C202 Am79212/Am79C202 Technical Reference 7 ASLAC Device Block Diagram RING + TEST AX VIN ­1 VINM VOUT DU A/D RING + TEST Signal Processing AISN AR MUX/ DEMUX D/A DD FS VM Metering Generator with Level Control & Shaping DCL Time Slot Assigner S0 S1 S2 RST IBAT IDC VLBIAS DC Feed Control C1 C2 IAB I/O1 Digital I/O IRTA IRTB I/O2 I1 Loop Supervision O1 ISUM IDIF I and V Reference Generators VREF VCCD 8 VCCA AGND Am79212/Am79C202 Am79212/Am79C202 Technical Reference IREF DGND Reset States Application of VCC on initial power up, a logic High level on the RST pin, or software command setting bit 4 in the SOP command register resets the ASLAC device to the default conditions as shown in Table 2 and Table 3. Table 2. SC Reset State Field Name Field Description Value after Hardware Reset Hex after H/W Reset C/I Downstream ST 0­2 ASLIC/ASLAC devices state Standby/Inactive I/O1 User Input/Output Input data I/O2 User Input/Output Input data O1 User Output Output data C/I Upstream Hook On/Off-hook status On-hook GNK Ground key status Loop open SLCX Signaling register Output I/O1 User Input/Output Input data on pin I/O2 User Input/Output Input data on pin I1 User Input 0 Input data Table 3. Monitor Reset State Field Name Field Description Value after Hardware Reset Hex after H/W Reset TOP Commands (Transfer Operation) CIC Channel ID Signaling register HOOK Switchhook/ring trip On-hook GNK Ground key/start No ground AST Anti-sat. indicator Off ICON Current-limit indicator Off TEMPA Thermal overload indicator Off CFAIL Clock fail indicator Off RINGX Ringing absence test indicator Off FAULT Power fault indicator Off Internal checksum SOP Commands (Status Operation) / Configuration Registers POLNR Polarity, normal/reverse Normal polarity RST Reset 0 LSEL1-0 Length of data 0 Am79212/Am79C202 Am79212/Am79C202 Technical Reference 9 Table 3. Monitor Reset State (continued) Field Name Field Description Value after Hardware Reset Configuration register 1 Hex after H/W Reset 04h ACT Activate/inactivate Inactive COX Cutoff transmit path No cutoff LB Loopback enable TON 1 kHz receive tone RG 6 dB lower receive gain DHP Transmit high pass disable COR Cutoff receive path No loopback Tone off Loss inserted No disable No cutoff Configuration register 2 80h TVD Test valid Complete OKTON Tone OK Not done OKTTX Metering OK Not done OKRNG Ringing OK Not done TM Test mode enable Disabled NOSL Teletax ramp Smooth DI/O1; DI/O2 I/O port direction Input Configuration register 3 00h ABF Adaptive balance filter Off A/µ A-law/µ-law EGR Default/programmed GR Use default EGX Default/programmed GX Use default EX Default/programmed X Use default ER Default/programmed R Use default EZ Default/programmed Z Use default EB Default/programmed BFIR/IIR Use default A-law Configuration register 4 00h RTD Enable ring trip threshold Use default DPB Enable digital pre-balance Use default MTRF Metering frequency 12 kHz MTRA 0-4 Metering amplitude 61 mVrms Configuration register 5 00h IDC/16 IDC/16 Divide IDC by 16 SOREV Smooth polarity reverse Smooth TXTNO Teletax normal operation 12/16 kHz 10 Unity Am79212/Am79C202 Am79212/Am79C202 Technical Reference Table 3. Monitor Reset State (continued) Field Name Field Description Value after Hardware Reset SBT 1 kHz sign bit toggle ZXR Zero cross relay operation ARR Auto. ring relay release Automatic DLB Digital Loopback mode Hex after H/W Reset Off DD to DU Enabled Configuration register 6 00h HOOK Mask switchhook/ring trip Not masked GNK Mask ground key/start Not masked AST Mask anti-sat. indicator Not masked ICON Mask current-limit indicator Not masked TEMPA Mask thermal overload indicator Not masked CFAIL Mask clock fail indicator Not masked RINGX Mask ringing absence test Not masked FAULT Mask power fault indicator Not masked Configuration register 7 PI Power interrupt MLIM 0-3 Metering limit 0Fh PI not occurred 745 mVrms Am79212/Am79C202 Am79212/Am79C202 Technical Reference 11 Upon initial application of power, a minimum of 1 ms is needed before the digital interface is ready to accept or transmit data. The ASLAC device should then be programmed with the desired filter coefficients, feed, supervision, and all other required parameters to ensure correct operation. Default States and Coefficients Within the ASLAC device there are two types of registers referred to in different ways below. Registers that are permanently stored in ROM are designated by (DEF). Registers that are user programmed are designated by (Prog.). Registers that are designated by Prog and DEF are selectable at any time. Table 4. COP Commands (Coefficient Operation) Field Name Field Description Value after Hardware Reset Current limit Hex after H/W Reset 65h ILA Current limit, Active 26.5 mA ILD Current Limit, Disable 21.2 mA DC feed parameters 08h VAPP Apparent voltage 50.2 V RFD Feed resistance 403 Anti-saturation value 88h VAS Anti-sat offset voltage 14.4 V VOFF Longitudinal offset voltage 8.4 V N2 Anti-sat feed ratio 2 Loop supervision threshold 56h TGK 0-3 Ground key threshold 7.23 mA TSH 0-3 Off-hook threshold 10.06 mA Debounce intervals 23h GKNTDIS Ground key integration disable Enabled DSH 0-3 Debounce time, switchhook 8 ms GKNT 0-1 Ground key integration time 100 ms Analog gains 20h AX Analog transmit gain 0 dB AR Analog receive gain 0 dB E-A AISN gain ELT 0 00h Error level threshold Indeterminate Indeterminate GX Prog. transmit digital gain Indeterminate Indeterminate GX:DEF Default transmit digital gain 1.0000 0190h GR Prog. receive digital gain Indeterminate Indeterminate GR:DEF Default receive digital gain 1.0000 0111h Z Prog. impedance filter Indeterminate Indeterminate Z:DEF Default impedance filter 0 0190h 0 0190h 0 0190h 0 0190h 0 0190h 12 Am79212/Am79C202 Am79212/Am79C202 Technical Reference Table 4. COP Commands (Coefficient Operation) (continued) Field Name Field Description 090h 090h 090h 090h 090h 0 090h 0 090h 0 090h 0 Default B IIR filter 0 0 BIIR:DEF Indeterminate 0 Programmable B IIR filter Indeterminate 0 BIIR 0190h 0 Default balance FIR filter 01h 0 BFIR:DEF 0190h 1 Prog. balance FIR filter Hex after H/W Reset 0 BFIR Value after Hardware Reset 090h Indeterminate Indeterminate 0 0190h Adaptive B filter control Indeterminate DCR1 Decorrelation coef. Indeterminate DCR2 Decorrelation coef. Indeterminate LST Low signal threshold Indeterminate LST: DEF Default low signal threshold DPB Progr. digital pre-balance Indeterminate DPB:DEF Default digital pre-balance 0 090h X Prog. transmit filter Indeterminate Indeterminate X:DEF Default transmit filter 1 0111h " 0 0190h " 0 0190h " 0 0190h " 0 0190h " 0 0190h Indeterminate Indeterminate 0 090h R2 Prog. receive filter R2:DEF Default receive filter 1 0111h " 0 0190h " 0 0190h " 0 0190h " 0 0190h " 0 0190h Indeterminate Indeterminate R1 Prog. receive filter R1:DEF Default receive filter 0.00 2E01h EPG Prog. echo path gain Indeterminate Indeterminate Am79212/Am79C202 Am79212/Am79C202 Technical Reference 13 Table 4. COP Commands (Coefficient Operation) (continued) Field Name Field Description Value after Hardware Reset Hex after H/W Reset EPG:DEF Default echo path gain Indeterminate 1009h RTT Ring trip threshold Indeterminate Indeterminate RTT:DEF Default ring trip threshold 10.5 mA 3Ch Upon initial application of power, a minimum of 1 ms is needed before the digital interface is ready to accept or transmit data. When power is initially applied or when a hardware reset (there are two methods) occurs, follow the sequence of commands as described in the ASLAC device operation section. Distortion Correction and Equalization The ASLAC device contains programmable filters in the receive (R) and transmit (X) directions that may be programmed for line equalization and to correct any attenuation distortion caused by the Z filter. Transhybrid Balancing The advantages of digital filters are: The ASLAC device programmable B filter is used to adjust transhybrid balance. The filter has a single pole IIR section (BIIR) and an 8-tap FIR section (BFIR), both operating at 16 kHz. The ASLAC device has an optional Adaptive state for the B filter which may be used to achieve optimum performance. The Echo Path Gain (EPG) and Error Level Threshold (ELT) registers contain values that determine the Adaptive state performance. 1-tap Digital Pre-Balance (DPB) is available without enabling the B filter. s High reliability; Gain Adjustment s No drift with time or temperature; The ASLAC device transmit path has two programmable gain blocks. Gain block AX is an analog gain of 0 dB or 6.02 dB, located immediately before the A/D converter. Gain block GX is a digital gain that is programmable to any gain from 0 dB to +12 dB with a worstcase step size of 0.1 dB for gain settings below +10 dB, and a worst-case step size of 0.3 dB for gain settings above +10 dB. The filters provide a net gain in the range of 0 dB to 18 dB. SIGNAL PROCESSING Overview of Digital Filters Several of the blocks in the signal processing section are user programmable. These allow the user to optimize the performance of the ASLAC device for the system. Figure 1 shows ASLAC device signal processing and indicates the programmable blocks. s Unit-to-unit repeatability; s Superior transmission performance. Two-Wire Impedance Matching Two feedback paths on the ASLAC device modify the effective two-wire input impedance of the SLIC by providing programmable feedback from VIN to VOUT. The Analog Impedance Scaling Network (AISN) is a programmable analog gain of ­0.9375 to +0.9375 from VIN to VOUT. The Z filter is a programmable digital filter, also connecting VIN to VOUT. 14 The ASLAC device receive path has two programmable loss blocks. Loss block GR is a digital loss that is programmable from 0 dB to 12 dB with a worst-case step size of 0.1 dB. Loss block AR is an analog loss of 0 dB or 6.02 dB, located immediately after the D/A converter. This provides a net loss in the range of 0 dB to 18 dB. Am79212/Am79C202 Am79212/Am79C202 Technical Reference Figure 1. Voice Transmission Paths Am79212/Am79C202 Am79212/Am79C202 Technical Reference 15 VOUT VIN IAB Full Digital Loopback Enable TM TM AISN + RING AR AR = 0 dB or -6.02 dB AX = 0 dB or +6.02 dB AX DAC ADC VRING (UNFILTERED) RING RING HPF Z Programmable Block + Metering Detector Interpolator Decimator To DC Feed Control Section B-IIR + RG X LPT Compressor & HP Ring Trip B-FIR RIIR Expander Receive Path cutoff and cutoff for digital loopback GR RFIR LPR Adaptor GX = 0 to +12 dB GX Ring-Trip Detector GR = 0 to -12 dB DPB + RG = 0 or -6.02 dB Interpolator Decimator Metering Level Control ASLAC From De-Multiplexer Digital Loopback Enable To Multiplexer Transmit Path Cutoff Transmit Signal Processing In the transmit path, the analog input signal (VIN) is digitized, filtered, and made available for output to the GCI in either A-law or µ-law compressed format. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The B, X, and GX blocks are user programmable digital filter sections with coefficients stored in the coefficient RAM while AX is an analog amplifier that can be programmed for 0 dB or 6.02 dB gain. The filters use either user-programmed coefficients or default coefficients for processing data. The decimator reduces the high input sampling rate to 16 kHz for input to the B, GX, and X filters. The X filter is a 6-tap FIR section which is part of the frequency response correction network. The B filter operates on samples from the receive signal path in order to provide transhybrid balancing in the loop. The high-pass filter rejects low frequencies such as 50 or 60 Hz and may be disabled. A transmit cutoff mode is also provided. Receive Signal Processing In the receive path, the compressed A-law or µ-law digital signal is formatted, filtered, converted to analog, and passed to the VOUT pin. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The Z, R, and GR blocks are user-programmable filter sections with their coefficients stored in the coefficient RAM while AR is an analog amplifier which can be programmed for a 0 dB or 6.02 dB loss. A digital loss function, RG, can be programmed for a 0 dB or 6.02 dB loss. A receive cutoff mode is also provided. The filters use either user-programmed coefficients or default coefficients for processing data. The low-pass filter band limits the signal. The R filter is a 1-tap IIR filter section operating at 8 kHz, followed by a 6-tap FIR section operating at a 16 kHz sampling rate and is part of the frequency response correction network. The analog impedance scaling network (AISN) is a user-programmable gain block providing feedback from VIN to VOUT to emulate different ZSLIC impedances from a single external ZSLIC impedance. The Z filter provides feedback from the transmit signal path to the receive path and is used to modify the effective input impedance to the system. The interpolator increases the sampling rate prior to D/A conversion. Analog Impedance Scaling Network (AISN) The AISN is incorporated in the ASLAC device to scale the value of the external ZSLIC impedance. Scaling this external impedance with the AISN (along with the Z filter) allows matching of many different line conditions using a single impedance value. Linecards may be designed for many different specifications without any hardware changes. The AISN is a programmable gain that is connected across the ASLAC device input from VIN to VOUT. The gain can be varied from ­0.9375 to +0.9375 in 31 steps of 0.0625. The AISN gain is given by the following equation: 4 3 2 1 0 h AISN = 0.0625 [ ( A · 2 + B · 2 + C · 2 + D · 2 + E · 2 ) ­ 16 ] The AISN gain is used to alter the input impedance of the ASLAC device and ASLIC device and its location in the signal processing is shown in Figure 1. The input impedance into the ASLAC device from the ASLIC device is given by: 1 ­ G44 · h AISN ZIN = - · ZSL 1 ­ G 440 · h AISN Where G440 is the ASLIC device's echo gain into an open circuit and G44 is the ASLIC device's echo gain into a short circuit. There are two special cases to the formula for hAISN: 1. Value of ABCDE = 00000 will specify a gain of 0 (or cutoff), and 2. A value of ABCDE = 10000 is a special case where the AISN circuitry is disabled and the VOUT amplifier is connected internally to VIN with a gain of 0 dB (equivalent to setting FLB bit in Configuration Register 1), and 3. This allows a Digital-to-Digital Loopback mode wherein a digital PCM input signal is completely processed through the receive section all the way to the VOUT pin. The signal is then connected internally to VIN where it is processed through the transmit section and output as digital PCM data. Speech Coding The A/D and D/A compression/expansion, if selected, follows either the A-law or the µ-law as they are defined in CCITT Rec. G.711. A-law or µ-law is programmed using CR3.6. Alternate bit inversion is performed as part of the A-law coding. 16 Am79212/Am79C202 Am79212/Am79C202 Technical Reference DC FEED CONTROL DC Feed in the Active State Feed control for Active (normal or reverse polarity) and Disable states. ASLIC Device + VREF ­ VDC RAB IAB VREF | * VAB| 400 K CHP IDC VAB RL RFD RSN IL00P IL00P VLBIAS ILOOP VAPP CDC1 2K K1 IDC VREF ILA, ILD DC Feed Controller VAS Digital Inputs from Control Interface N2 VLBIAS VOFF VREF To Longitudinal Control Loop ASLAC Device IREF IBAT RBAT2 RBAT1 RREF CB To ASLIC Device VBAT pin Figure 2. DC Feed Control Block Diagram for Active and Disable States VAB VAPP Anti-Sat Region KBAT * VBAT ­ VAS V2 Resistance Feed Region (RFD) V1 Current Limit Region ILOOP 0 ILIM (ILA, ILD) Figure 3. DC Feed Plot, VAB vs. ILOOP Am79212/Am79C202 Am79212/Am79C202 Technical Reference 17 Figure 2 shows the block diagram of the DC Feed control circuit. The DC Feed control parameters can be independently programmed by way of the C/I interface as indicated in Table 5. s VAPP, the apparent battery voltage s RFD, the DC Feed resistance s ILA, the loop-current limit level (ILIM) in Active state s ILD, the loop-current limit level in Disable state s VAS, the anti-saturation offset voltage s N2, the anti-sat feed resistance factor V1 = VAPP ­ ILIM · RFD; RAB V2 = KBAT · VBAT ­ VAS; Where: KBAT = -2.005 · · ( RBAT1 + RBAT2 ) As shown in Figure 3, V1 is the voltage at which the feed characteristic normally leaves the current-limit region and enters the resistance-feed region. If V1 is greater than V2, the anti-sat region is entered directly from the currentlimit region. If V1 is negative, there is no current-limit region and the feed characteristics start out in the resistivefeed region at VLOOP = 0. VBAT is the voltage applied to the VBAT pin of the ASLIC device In the Active state, ILIM = ILA; In the Disable state, ILIM = ILD The following equations define ILOOP: If VAB < V1 and V2: ILOOP = ILIM If V2 > V1: If V2 > VAB > V1: VAB ­ V 1 VAPP ­ VAB ILOOP = ILIM ­ - = -RFD RFD If VAB > V2: V1 + N2 · V2 VAB ILOOP = ILIM + - ­ - · ( N2 + 1 ) RFD RFD If V1 > V2: If V1 > VAB > V2: VAB ­ V2 ILOOP = ILIM ­ - · N2 RFD If VAB > V1: V1 + N2 · V2 VAB ILOOP = ILIM ­ - ­ - · ( N2 + 1 ) RFD RFD IDC and VDC (see Figure 2) for any of the above conditions is defined by the following equations: ILOOP IDC = - ; Where K1 is the four-wire (RSN pin) to two-wire (ILOOP) DC incremental current gain in the ASLIC device. K1 VDC = VAB · ; Where is the two-wire (VAB) to VDC voltage gain in the ASLIC device. The ASLIC/ASLAC devices have been designed to implement the feed equations assuming the following nominal values for ASLIC device parameters and external components: RREF, the current reference resistor from the ASLAC device, IREF pin to ground: 7870 . RAB, the voltage-to-current conversion resistor between the ASLIC device, VDC pin, and the ASLAC device, IAB pin: 35.7 k. RBAT = RBAT1 + RBAT2, the battery voltage sense resistance connected between VBAT and the IBAT pin of the ASLAC device: 730 k. K1, the ASLIC device four- to two-wire incremental DC current gain. 1 , the ASLIC device two- to four-wire DC voltage gain: = - = 0.0242 . 41.33 18 Am79212/Am79C202 Am79212/Am79C202 Technical Reference The nominal values of all programmable parameters are shown in the shaded areas of Table 5. Table 5. DC Feed Control Parameters Description Apparent voltage Control Variable Nominal Values Units 25.1 50.2 60.3 70.3 V KAPP Feed resistance VAPP(V) 0.134 0.268 0.321 0.375 - 403 504 605 706 807 1009 1210 1614 0.069 0.087 0.104 0.122 0.139 0.174 0.208 0.278 - 5.3 7.4 10.6 12.7 15.9 21.2 26.5 31.8 mA 0.820 0.984 V RFD() KRFD Loop-current limits, IL_(mA) Active and Disable VILIM 0.164 0.230 0.328 0.394 0.492 0.656 states IL_(mA) 33.9 37.1 42.3 47.6 52.9 63.5 mA VILIM 1.050 1.148 1.312 1.476 1.640 1.968 V 6.2 8.2 10.3 12.3 14.4 16.5 18.5 20.6 V 0.033 0.044 0.055 0.066 0.077 0.088 0.099 0.110 V 2 3 5 9 Anti-sat offset VAS(V) voltage KVAS Anti-sat factor N2 - When external component and parameter values differ slightly from nominal, new DC Feed values can be calculated using the equations in Table 6. Table 6. External Component Effects on DC Feed Parameters VAPP RAB KAPP · -RREF · ILA, ILD K1 VILIM · -RREF RFD RAB KRFD · -K1 · VAS RAB KVAS · -RREF · Note: RAB and RREF are in . See Table 5 for values of KAPP, KRFD, KVAS, and VILIM. The values of proportionality constants KAPP, KRFD, VILIM, KVAS for any particular DC Feed program are located in Table 5 immediately below each shaded feed parameter value. Because the values of N2 do not depend upon external components, they do not have proportionality constants associated with them. The voltage appearing between the A and B legs when the loop is open can be calculated using the following equation: VAPP + N2 · ( KBAT · VBAT ­ V AS ) VAB IL = 0 = -N2 + 1 Figure 4 and Figure 5 show the performance that an ASLIC/ASLAC devices linecard will provide for the North American market using a ­51 V C.O. battery. The programmed parameters are: VAPP = 50.2 V, RFD = 403 , ILA = 47.6 mA, VAS = 10.3 V, N2 = 2, VOFF = 6.0 V The external component values are: RREF = 7.87 k, 1% RAB = 35.7 k, 1% RBAT1 = RBAT2 = 365 k, 1% Am79212/Am79C202 Am79212/Am79C202 Technical Reference 19 60 50 RLOOP = 1.9 k 40 VLOOP (Volts) 30 LSSGR Limits 20 10 0 10 20 30 40 50 70 60 80 90 100 ILOOP (mA) Figure 4. Voltage Current Characteristic for the North American Market 60 50 40 ILOOP (mA) 30 LSSGR Limits 20 10 0 500 1000 1500 2000 2500 3000 RLOOP () Figure 5. Line Current vs. Loop Resistance for the North American Market 20 Am79212/Am79C202 Am79212/Am79C202 Technical Reference 3500 DC Feed in the Standby, Tip Open, and Ring Open States In the Standby and Tip Open states, the longitudinal control loop and both power amplifiers are turned off. Because the ASLIC device power amplifiers are turned off, voice transmission is not possible in the Standby, Tip Open, or Ring Open states. When in these states, the AD and BD outputs are driven by internal resistances connected to ground or VBAT to ensure line supervision remains active. Each internal resistance (see Feed Resistance in ASLIC device DC specs) is connected in series with constant current limit (30 mA on AD; 40 mA on BD) to limit ASLIC device power dissipation under short loop conditions. When the loop current is below the current limit, the ASLIC device appears as a constant voltage source in series with two of the internal resistances. Above the current limit, the ASLIC device acts as a con- stant current source of the appropriate value. Figure 6 shows the internal configuration of the ASLIC device in the Standby, Tip Open, and Ring Open states. In the Standby state, S1 and S2 are switched on and S3 is switched off. The ASLIC device delivers normal polarity (AD more positive than BD) current to the loop. In the Tip Open state, S1 and S3 are switched off and S2 is switched on. The ASLIC device provides a current limiter in series with the internal resistance to VBAT, through the 20 supervision sense resistor, to the BD output. In the Ring Open state, S1 and S2 are switched off and S3 is switched on. This allows loop current to be drawn from VBAT through the external thermal management resistor, RTMG. ASLIC Device VBAT 30 mA Current Limiter RTMG TMG C.O. BATTERY Feed Resistance S3 AD S1 BD S2 Feed Resistance 40 mA Current Limiter VBAT Figure 6. Standby, Tip Open, and Ring Open State Internal Configuration Am79212/Am79C202 Am79212/Am79C202 Technical Reference 21 Longitudinal Control Loop The purpose of the longitudinal control loop is to set the optimum two-wire, DC operating point of the ASLIC device. The DC operating point should be set so that enough headroom is allowed for signals to swing on the A and B legs of the line circuit. longitudinal reference voltage will change, causing the operating point to move by the same amount. For long loops, the operating point is fixed at approximately half of VBAT. In this case, the DC Feed is balanced and VA moves in the opposite direction from VB as the load is varied. In the case of short loops, where the longitudinal operating point is less than half of VBAT, programmable parameter VOFF determines the amount of headroom available as shown in Figure 7. In this case, the voltage at the A lead remains fixed and only the B lead responds to load variations. As long as the longitudinal control loop is within its operating range, VA will equal ­VOFF. This can be shown by the following derivation: The ASLIC device creates a longitudinal reference voltage by adding one half of the line-to-line voltage to VOFF. The error amplifier compares this reference voltage to the actual longitudinal voltage and forces them to be equal by controlling the amount of longitudinal current delivered by the output amplifiers. If voltage VB changes (because of load variation, for example), the VA + VB = ­ VOFF ­ VA + VB - - -2 2 2 2 VA + VB - = ­ VOFF ­ VA ­ VB -2 2 VA = ­ VOFF The level of VOFF is programmable to ensure that maximum signal swings can be accommodated by the ASLIC device. The range of VOFF is given in Table 7. Table 7. Longitudinal Control Parameters Control Variable Description Range Units VOFF Longitudinal offset voltage 6, 7.2, 8.4, 9.6, 10.8, 12, 13.2, 14.4 V BGND + VOFF VA ­ + VA ­ VB 2 VA + VB ­ 2 Longitudinal reference voltage + VB VBAT Note: Longitudinal reference voltage = ­ V OFF ­ VA ­ VB -2 Where: VOFF = 6 · VLBIAS Figure 7. Longitudinal Voltages 22 Am79212/Am79C202 Am79212/Am79C202 Technical Reference Figure 8 combines the functions of the metallic and longitudinal control loops into one block diagram. Also shown is the two-wire performance of the ASLIC/ASLAC devices system from short to long loops . 500 A +0.5 SA RSN GL = 28.6 µ ­ 200 K CHP RL VLONGREF VLONG = (VA + VB)/2 200 K B RDC + VAB VLONGREF = ­(VOFF + VAB/2) + ­ SB 500 DC FEED CNTL IF |VLONGREF| > |VAB/2| VLONGREF - VBAT/2 GL = 28.6 µ IAB ­0.5 RAB VREF VREF ­ |VAB/41 VAB/41.33| VDC Volts QBAT VAB controlled by programmable DC Feed Control Block in the ASLAC device VB QBAT/2 VLONG VOFF VLONG controlled by VLONGREF VA RL 0 Figure 8. Metallic and Longitudinal Control Loop Block Diagram Am79212/Am79C202 Am79212/Am79C202 Technical Reference 23 SIGNALING Ring Relay Operation The ring relay can be operated in the Synchronous or Asynchronous state depending on the setting of the ZXR bit in CR5. For synchronous ring relay operation, the ZXR bit is set to a logic 0. In this case, the ring relay is opened or closed at the appropriate voltage or current zero crossings of the ringing waveforms. Ring relay closure occurs at a zero crossing of the ringing voltage waveform relative to VBAT. To open the relay, the relay driver is turned off at a ringing-current zero crossing. During active ringing, a ring relay trigger pulse is generated every time the current ringing waveform crosses zero from either direction (see Figure 9). If the ringing signal disappears, the ring relay is allowed to operate asynchronously after waiting 63 ms. When a zero crossing is again detected, ring relay operation again becomes synchronized to zero cross. Synchronous relay operation can be disabled by setting the ZXR bit in CR5 (MPI Command 35 and Command 36) to a logic 1. In this case, the ring relay will always open or close asynchronously. Ringing Current Zero Crossing Pulses Zero cross relay operation 63 ms Asynchronous relay operation Figure 9. Zero Cross Detect Timing for Relay Opening 24 Am79212/Am79C202 Am79212/Am79C202 Technical Reference Zero cross relay operation Ring Relay Activate Teletax Signaling Ring relay closure can occur only when the ST2, ST1, and ST0 bits in the C/I channel have all been set to logic 1. This combination of STn bits forces the ternary code on the ASLIC device state control lines, C1 and C2, to the ringing state. Teletax signals are pulses that send call charge information to the subscriber equipment. These signals can be sent during the Active (normal or reverse polarity) state. Teletax signals can be either 12/16 kHz metering bursts or polarity reversals, depending on the TXTNO bit in CR5. Ring Relay Release When the ARR (Auto Ring Relay Release) bit in CR5 is a logic 1, ring relay release occurs only when the bits in the ST field of the ASLIC device state register are programmed to anything other than the Ringing state, or in the case of a power-cross detect. When the ARR bit in CR5 is a logic 0, the ring relay will release automatically upon the occurrence of a ring-trip or a power-cross detect, and the ASLIC device will enter the Disable state until a new C/I command is issued that places the ASLIC device in a nonringing state. The ring relay can still be released synchronously or asynchronously by writing any nonringing ASLIC device control code into the ST field of the ASLIC device state register within the ASLAC device. When the TXTNO bit is a logic 0, the ASLIC/ASLAC devices are set for 12/16 kHz teletax operation. When TXTNO is a logic 1, the Teletax mode is polarity reversal. Both types of teletax signals must be turned on and off slowly enough to prevent noticeable interference with voice signals. Either 12/16 kHz or polrev teletax is initiated when ST2 = 0, ST1 = 1 and ST0 = 1 is written in the SLIC state register. 12/16 kHz Metering The ASLAC device supplies 12/16 kHz metering signals in the form of a voltage fed from the VM pin. The metering signal is generated internally using the Sine, Ramp, and Gain DAC's shown in Figure 10. The output on VM is the ramped sine wave shown in Figure 11. The Gain DAC receives its analog reference waveform from the Ramp DAC. The 5-bit output of the Gain control block controls the Gain DAC and sets the target metering signal level that should appear at the VM pin of the ASLAC device. The signal across a nominal 200 , two-wire metering load is approximately 6.67 times VM. 12/16 kHz Sine DAC MTRF 12/16 kHz Select Ramp DAC Gain DAC VM 8 5 Ramp Counter Gain Control 8 kHz Clock Ramp Timing Control NOSL (CR2.2) Up/Down (Meter On/Off) 4 MLIM AX VIN Threshold Detector 5 MTRA Sample frequency = 128 kHz HPF A/D To Voice DSP Figure 10. Metering Generators Am79212/Am79C202 Am79212/Am79C202 Technical Reference 25 12/16 kHz Shaped metering signal tr Metering enable pulse tf tp Figure 11. 12/16 kHz Metering Waveforms The metering signal that drives the ASLIC device appears at the ASLAC device VM pin as bursts of 12 kHz or 16 kHz sine waves. As shown in Figure 10, the signal at VM originates in a sine DAC whose output is proportional to the sine of its input count. In this manner, a low distortion sine wave can be generated as the frequency divider that drives the sine DAC counts through its range. A table of VM voltage targets for all MTRA code combinations appears in the description for CR4 located in the SOP command section of this specification. The MTRF bit of (CR4.5) selects the division factor in the frequency divider block required to produce either 12 kHz or 16 kHz metering frequency. Setting the TXTNO bit in configuration register CR5 to a logic 1 defines teletax signaling as a polarity reversal. Setting ST2 = 0, ST1 = 1, and ST0 = 1 in the SLIC state register will then cause a polarity reversal. To reduce noise in the voice channel, the NOSL bit in CR2 can be set to a logic 0. In this case, the metering signal is ramped slowly on and off in response to the up/ down signal that controls the ramp timing and gain control blocks. Ramping to and from full level lasts 20 ms and is accomplished in a maximum of 160 steps. If, while the metering is ramping up, the metering voltage component at VIN becomes higher than the metering voltage limit programmed by the MLIM field of CR7, the ramp counter is halted before it reaches the full 160 counts. This action prevents the two-wire metering voltage from overdriving the ASLIC device in cases where the twowire load is high impedance at the metering frequency. If immediate ramp up (< 5 ms) of the 12/16 kHz metering signal is desired, the NOSL bit in CR2 can be set to a logic 1. The high-pass filter (HPF) between VIN and the threshold detector is intended to remove voice frequency components. Because of this filter, the internal threshold voltage corresponds to a different signal level at VIN for 12 kHz and 16 kHz signals. 12 kHz signals are attenuated by 1.23 dB relative to 16 kHz signals. This produces nominal thresholds referred to VIN (AX = 0 dB) of 59 to 745 mVrms for 12 kHz and 68 to 862 mVrms for 16 kHz. Polarity Reverse Polarity reversal places the ASLIC device into a condition where the AD pin is more negative than the BD pin. Abrupt Polarity Reverse For abrupt polarity reverse (SOREV bit of CR5.6 = 1), the ASLAC device immediately reverses the direction of IDC and places the ASLIC device in the Polarity Reverse state by way of interface pins C1 and C2. The typical abrupt reversal time is about 5 ms. Smooth Polarity Reverse Smooth polarity reversal is required in certain administrations where it is used as a teletax signal and applied during normal voice conversation. In this application, the response of the DC control loop must be slowed so that noise from the polarity reversal is not objectionable. The typical smooth reversal time is about 64 ms. When the SOREV bit is a logic 0, the current in the IDC pin ramps slowly between polarities in response to a polarity reversal initiated by writing the ST field of the ASLIC device state register with the appropriate code (ST2 = 0, ST1 = 1, and ST0 = 1). To prevent unwanted transients in the ASLIC device, the polarity reverse command is actually sent to the ASLIC device only after the current in IDC passes through zero while moving to the opposite polarity. A table of threshold voltages for all MLIM code combinations appears in the description for CR7 located in the SOP command section of this specification. 26 Am79212/Am79C202 Am79212/Am79C202 Technical Reference SLIC State Register ST = 010 POLREV NORM 64 ms 64 ms IN Current at ASLAC device, IDC pin ZERO OUT ASLIC device in normal polarity (A more positive than B) C2 = GND C1 = VCC ASLIC device in normal polarity (A more positive than B) ASLIC device in reverse polarity (B more positive than A) + VAB 0 ­ Figure 12. Smooth Polarity Reverse Waveforms Am79212/Am79C202 Am79212/Am79C202 Technical Reference 27 LINE SUPERVISION The line supervision functions include off-hook, groundkey, fault, and ring-trip detection. Threshold levels for all of these functions are independently programmable through the microprocessor interface. Figure 13 shows the block diagram of the ASLAC device loop supervision function. ISUM and IDIF are provided by the ASLIC device. These are scaled-down versions of the sum and differences of the currents in the individual legs of the loop. Using these currents, the ASLAC device is able to perform switchhook, ground-key, and fault detection functions. Detector Threshold Ranges The ranges of programmed loop supervision parameters are summarized in Table 8 and programmed using COP commands. The programmable threshold levels shown in Table 8 are valid only when RREF = 7.87 k. Threshold levels for other values of RREF can be calculated using the following equation: 7.87 ( k ) TSH or TGK (mA) = - x threshold curNEW RREF ( k ) rent (mA) from Table 8 Off-Hook Detection A threshold detector compares ISUM to reference TSH. TSH is the off-hook threshold value previously programmed by the write loop supervision thresholds command (COP command 7). When ISUM becomes greater than TSH, an off hook is detected and, after debouncing, the HOOK bit of the signaling register is set to logic 1. To improve noise immunity, hysteresis of approximately 10% of the off-hook threshold current is included before debouncing. Because ISUM is an absolute value signal, metering signals at the two-wire output appear as rectified currents at ISUM. Metering pulses sent after an onhook may cause ISUM to persist until the end of the metering pulse. Therefore, during the transmission of a metering pulse, the ASLAC device uses the current in IDC instead of ISUM to sense the supervisory loop current. Switchhook Debounce The debounce circuit eliminates false detection due to contact bounce during hook switch opens and closures. When the ASLAC device is not in the Ringing state, the debounce timer takes its input from the loop or groundkey threshold detector. The debounce timer validates a detect after an interval during which no threshold detector transitions in either direction occur. The length of the debounce interval is programmable through MPI. If detection occurs before the interval ends, the timer is restarted from zero and again looks for an interval of no transitions. After debouncing, the result is placed into the HOOK bits of the upstream C/I channel and signaling register. Loss of VBAT will disable the debounce circuit output and will prevent switchhook detect. Table 8. Programmable Threshold Levels Control Field Description Programmable Thresholds (RREF = 7.87 k) TSH Off-hook threshold 1.3, 2.1, 3.14, 4.1, 6.3, 7.55, 10.06, 12.16, 15.2, 18.34, 20.3, 24.4 TGK Ground-key threshold 1.1, 1.9, 2.83, 3.8, 6.0, 7.23, 9.64, 11.6, 14.6, 17.6, 19.6, 23.7 DSH Debounce timer interval 0 to 15 in steps of 1 GKNT Ground-key integration time Integration disabled, 16 2/3, 50, 60, 100 Units mA ms 28 Am79212/Am79C202 Am79212/Am79C202 Technical Reference R S1B RGFD1 RING BUS T S1A RFB Am79212/Am79C202 Am79212/Am79C202 Technical Reference BD SB SA AD A LEG POWER AMP Sum/Difference IDIF CDIF VREF ISUM From A Leg, 20 Sense Resistor ASLIC Device B LEG POWER AMP 20 To TX AMP and DC Feed Control To Sum/Difference Block 20 ASLIC Device Note: S1 shown in nonringing position RSR1 RSR2 RSB RSA RFA BGND IDIF ISUM IRTA IRTB virta-irtb VIN Ring-Trip and powercross Ring Trip Ring Relay Control Logic Enable/Disable Operate on zero cross Ring Relay Control pkFT FT Fault Detector TGK Fault Detector Ground-Key Threshold Detector Switchhook Threshold Detector 4 ms Debounce Integrator GKNT Integrator Debounce MUX Signaling Register Fault Bit DU C/I Channel GNDX Bit DSP Clock Frequencies: Voice Mode - 8 kHz Ringing State - 500 Hz DSH Ring-Trip filter and 104 ms Threshold Comparator (Part of DSP) Debounce 13.5 ms Debounce Power-Cross Validation ST Field DD C/I Channel Current Zero Cross Pulses TSH S1C vRGFD1 > 50 V Voltage Zero Cross Pulses ASLAC Device Ringing Figure 13. Loop Supervision Architecture-ASLIC/ASLAC Devices 29 DU C/I Channel Hook Bit Ground-Key Detection A threshold detector compares IDIF to reference TGK. TGK is the ground-key threshold value previously programmed by the write loop supervision thresholds command (Command 7). When IDIF becomes greater than TGK, a ground key is detected and, after integration to remove longitudinal AC disturbances, the GNK bit of the signaling register is set to logic 1. Operation of the ground-key integrator is discussed later in this specification. To improve noise immunity, hysteresis of approximately 10% of the ground-key threshold current is included before the ground-key integrator. Ground-Key Integrator The output of the ground-key threshold detector is fed to the ground-key integrator that ensures the groundkey detector function will operate even in the presence of 60 Hz, 50 Hz, or 16 2/3 Hz longitudinal disturbances. To accomplish this, the integrator determines the average time that the detector output is on or off during an integral number of cycles of the longitudinal disturbance signal. Differences between average on and off times determine the actual detection status. The integration time can be programmed to 100 ms, 60 ms, 50 ms or 16 2/3 ms using the GKNT field in COP Command 9. The integrator is enabled or disabled using the GKNTDIS bit. The 100 ms integration time is used for both 50 Hz and 60 Hz currents. The 60 ms integration time is used for averaging both 50 Hz and 16 2/3 Hz currents while the 50 ms time is used for 60 Hz currents. The 16 2/3 ms integration time is used to reduce ground-key response times to a minimum in the case of a remote ring lead seizure. After integration, the result is placed in the GNK bit of the upstream C/I channel and in bit 6 of the signaling register. Because the sampling rate of the ground-key integrator is 8 kHz, aliasing is possible when high-frequency longitudinal disturbances occur. Therefore, an external filter capacitor between pins IDIF and VREF must be used to provide immunity to high-frequency noise. Ring-Trip Detection The ring-trip detection function is implemented as shown in Figure 13. The voltage drop across RGFD1 is proportional to the ringing current flowing in the loop. The voltages on either side of RGFD1 are sensed by ringing sense resistors RSR1 and RSR2 that feed the current difference circuit in the ASLAC device through pins IRTA and IRTB. As a result, the current flowing out of the current difference circuit is proportional to the ringing current flowing in the loop. This current is used in the ASLAC device for ring-trip, power-cross detect, and ring relay release functions. The ring-trip function provides optimum load and response performance by utilizing different techniques depending on the length of the loop. For short loops 30 (less than 1000 , when response time is critical), ring trip occurs when an off-hook condition which causes the voltage across RGFD1 to exceed 50 V for longer than 13.5 ms. For long loops, the current through RGFD1 does not exceed 50 V, therefore, a ring-trip filter and comparator arrangement combined with a 104 ms debouncer must be used as described below. Loss of VBAT will disable the 104 ms debounce output and prevent ring-trip detection. During ringing, the A/D input is switched from its normal connection to the ASLAC device VIN pin and connected to the output of the current differencing circuit. The A/D produces a 19-bit word which is then sampled every 2 ms (500 Hz sampling rate) by the low-pass, ringtrip filter implemented in the DSP. The ring-trip filter has a bandwidth of approximately 4 Hz and removes enough of the ringing ripple so a reliable ring trip can be detected by the threshold comparator. The ring-trip current threshold, against which the ring-trip filter output is compared, represents a DC voltage across RGFD1. Various current detection thresholds can be programmed. The default ring-trip threshold represents a DC voltage across RGFD1 equal to 5.357 V. When RGFD1 equals 510 W, this is equivalent to a loop-current threshold of 10.505 mADC. When an off hook occurs, the ringing waveform exhibits a shift in average DC content. When the average DC level is detected to be above the programmed ring-trip threshold, a debounce timer is initiated. If the ring-trip threshold is set such that the negative peaks do not fall below the threshold, the timer will end after 104 ms. The result of this sequence of events will set the hook bit and indicate the intention to open the ring relay. Assuming the Auto Ring Relay Release is enabled, the next current zero crossing will instruct the ring relay to open and enable the zero crossing hysteresis for power-cross protection. Exiting Ring, either by programming or by ring trip, will cause the internal circuitry to reset all timers and enable switchhook detection. Once switchhook detection is enabled, the respective debounces for fault detection (15 ms first period and 4 ms thereafter) and switchhook detection (programmable from 1 to 15 ms) must be satisfied before any internal registers will change. If the receiving phone is taken off hook during the cadence, off hook will be detected by the normal off-hook detection circuitry. Specified ring-trip detection thresholds are relative to RGFD1 = 510 . The ring-trip filter in the DSP reduces the AC component to a point where the filtered output can be compared to threshold voltage and reliably determine whether a ring trip has occurred. The DSP implements a ring-trip filter with a pair of complex poles that provides the high level of filtering required for reliable ring-trip detection. This filter is described by the following transfer functions: a0 h ( z ) = H2 ( z ) · -1+a ­1 + a ­2 1·z 2·z Am79212/Am79C202 Am79212/Am79C202 Technical Reference Where: a0 = 0.00390625; a1 = ­1.9375; a2 = 0.941406; Sampling rate = 500 Hz ­ k 1 H2 ( z ) = z · - where K = 0 .15 16 k When a ring trip occurs, a logic 1 is placed into the HOOK bit (bit 7) of the upstream C/I channel and bit 7 of the signaling register. Because the ring-trip current detection thresholds are sensed by the voltage developed across RGFD1, altering the value of RGFD1 will necessitate recalculating the ring-trip current thresholds. It is possible to scale RSR1 and RSR2 to offset this difference, however, the voltage and current zero crossing thresholds will also change. Before altering the values of RGFD1, RSR1, and RSR2, contact CPD Linecard applications staff for more information. Power-Cross Detection During Ringing During the Ringing state, the ASLIC device and it's surge protector are not connected to the line. When a 60 Hz power cross occurs, the normal ring-trip circuitry in the ASLAC device should detect it and immediately release the ring relay. For higher power-cross levels, the normal ring trip may not function because of signal overload of the A/D in the ASLAC device. Therefore, an independent method of detecting a power cross during ring trip is provided. This method is described below. During ringing, any voltage higher than 50 V peak across RGFD1, the ring-feed resistor, is detected by the ASLAC device as a possible power-cross condition. The ASLAC device also observes the zero crossings of the voltage across RGFD1. If, for two cycles, a voltage greater than 50 V is detected between two successive voltage zero crossings and the period of the zero crossings is between 13.5 ms and 24 ms (75 and 40 Hz), a power cross is confirmed and the ring relay releases. If a power cross occurs that does not exceed the 50 V limit, a ring trip will still happen because it is processed as if it were a normal ring trip. Alarms Thermal Overload Alarm When the junction temperature of the ASLIC device reaches approximately 160°C, the ASLIC device signals this condition to the ASLAC device by driving the VDC pin to a voltage specified in the ASLIC device DC Specifications table. In normal operation, the voltage at this pin should always be less than VREF. The VDC pin feeds the IAB pin of the ASLAC device through an external resistor, RAB. When an ASLIC device thermal overload condition is present, TEMPA (bit #3) in the signaling register is set to a logic 1. Line Fault Alarm The ASLAC device detects positive leg-to-battery faults by comparing the longitudinal sense current, IDIF, to a reference that represents a DC fault current of FT (see Figure 13). If the DC fault current exceeds FT from the most positive lead to VBAT, the FAULT bit in the signaling register is set to a logic 1 after the programmed groundkey integration time. To improve noise immunity, hysteresis of approximately 15% of the loop current is included. Ring-to-ground faults cannot be distinguished from a normal ground key. However, this type of fault can be recognized as a ground key that persists for an excessively long time. Power-Cross Alarm When either low-level or high-level power crosses occur, the ASLIC device and ASLAC device signal these events by setting the FAULT bit in the signaling register. After this bit is set, a relay can be operated that safely removes the linecard from service. Low-level power crosses can occur that fail to activate any of the external thyristor protection devices. In this situation, the ASLIC/ASLAC devices must differentiate between unacceptable power-cross current levels and low-level longitudinal induction current levels that do not affect the operation of the linecard. To accomplish this, the ASLAC device sets the FAULT bit only when each longitudinal current peak becomes greater than pkFT for more than 4 ms. If the fault current drops below pkFT for more than 4 ms and the average longitudinal current is less than FT, the FAULT bit is reset to a logic 0. Low-level power crosses on the B lead that fail to set the FAULT bit can be recognized as a persistent ground key indication by the GNDX bit in the C/I channel. The external thyristor device on the linecard provides protection when larger power line voltages appear at the subscriber line interface and the protection relay cannot be activated fast enough to prevent destruction of the ASLIC device. When the thyristors trigger, the fault currents are diverted to ground. In this case, the fault condition can only be recognized as a persistent ground key. By the time the fault is recognized and the protection relay activated, the external fuse resistors (see Figure 13) may have already been destroyed. To solve this problem, the voltages across RFA and RFB are directly sensed by the ASLIC device as the voltages between AD and SA, and BD and SB respectively. When the voltage across either of the fuse resistors exceeds 7.5 V peak, the ASLIC device senses this and immediately forces the voltage at its IDIF pin to ground. The ASLAC device detects this condition on its own IDIF pin as a current equivalent to more than pkFT mA of longitudinal current and sets the FAULT bit in the signaling register to a logic 1. Am79212/Am79C202 Am79212/Am79C202 Technical Reference 31 Clock Failure Alarm Ringing Voltage Bit (CR2, Bit 4) Incoming clock pulses on the DCL pin are continuously counted from the beginning of one frame to the beginning of the next frame. There should be exactly 512 clocks per frame for a 4.096 MHz clock or 256 clocks for a 2.048 MHz clock. Any deviation from the expected clock count caused by clock or frame sync aberrations will set bit 2 in the signaling register to a logic 1. In this test, the ring relay is operated along with the test relay that connects a test resistor across the line. To start the test, the OKTTX and OKTON bits are reset, the OKRNG bit is set, and the TVD bit (bit 7) is reset. The ringing current through the test resistor is sensed and processed by the ASLAC device in the same manner as a ring trip. In this test, however, the ring-trip filter cut-off frequency is increased 16 times by clocking it at 8 kHz instead of 500 Hz. Because of this, the ring signal is unaffected as it goes through the ring-trip filter. Also during this test, an attenuation of 1 or 16 times (depending upon the setting of bit 7, CR5) is inserted after the A/D to improve resolution for higher ringing currents. The ringing signal is then compared to the ring threshold level set by the coefficients in COP command 37. After 63 ms, the ASLAC device sets the TVD bit and if the current is less than the programmed level, the OKRNG bit is reset. Otherwise the bit remains set. Power Interrupt Alarm The ASLAC device senses the voltage present at VCC. If the power supply falls below a fixed threshold of approximately 1.5 V for a period greater than 2 µs, the PI bit is set in CR7. When this bit is set, the device is disabled and will require complete reprogramming. The PI bit in the ASLIC device I/O register will read back as a logic 1 to indicate that a power interruption has been detected. LINE STATUS INDICATORS Go/NoGo Tests with Test Load There are two types of Go/NoGo tests. One of these types monitors DC LOOP conditions and the results are available on a continuous basis from the signaling register bits 0­3. The other type of Go/NoGo test is one that does not continuously monitor conditions in the ASLAC device but requires initial setup by software or firmware commands. These tests are controlled and monitored by bits 4 through 6 in configuration register 2. Results are valid only after 63 ms when the measurement valid bit has been set by the ASLAC device. During this test, the transmit path PCM output is activated and the high-pass filter disabled. This allows monitoring of the AC and DC components of the ringing signal. To eliminate the effect of the DC component of the ringing signal, the high-pass filter in the DSP can be activated by clearing the DHP bit of CR1. Meter Voltage Bit (CR2, Bit 5) Bit 7 in the signaling register is set to a logic 1 when the current through a test resistor is greater than or equal to the programmed off-hook threshold current (TSH). This test uses the metering signal limit threshold detector to compare the programmed value of MLIM with the metering echo level on VIN (see Figure 10). To start this test, the OKRNG and OKTON bits are reset, the OKTTX bit is set, and the TVD bit reset. After 63 ms, the ASLAC device sets the TVD bit and if the metering echo has never exceeded the MLIM level, the OKTTX bit is reset; otherwise it remains set. If the metering signal is at such a low level that it never produces an echo larger than MLIM, it will not be detected. For test purposes, the metering signal can be increased to a level that guarantees detection. This can be done by programming the MTRA field in CR4. Ground Key Bit (SIG, Bit 6) Pass Tone Bit (CR2, Bit 6) This bit in the signaling register indicates when abnormal longitudinal currents are present. These currents could result from a defective ASLIC device or high lineto-ground leakage levels. When these currents are greater than the programmed ground-key threshold current (TGK), bit 6 in the signaling register is set to a logic 1. To start the pass tone test, the OKRNG and OKTTX bits are reset and the TON bit in CR1 is set at the same time. The OKTON bit is set and the TVD bit reset. A 1 kHz, 0 dBm0 signal is generated by the DSP and applied to the receive digital input. The signal is routed through the receive DSP path in the ASLAC device and the ASLIC device to the test load. The pass tone echo is sent back through the ASLIC device and ASLAC device transmit path and measured at the B-filter summing point. If the B filter and ASLAC device gains are adjusted to exactly cancel the return echo under nominal conditions, no signal will be measured at the digital output. If the gains deviate in either direction from nominal values, an error signal appears at the digital output. This error signal is compared to an Error Level Threshold The following are descriptions of the Go/NoGo test bits available in the signaling (SIG) and CR2 registers. Loop Sense Bit (SIG, Bit 7) Voltage Bit (SIG, Bit 5) When the ASLIC device is operating in the Anti-Sat state, this bit is set to a logic 1. Current Bit (SIG, Bit 4) When the ASLIC device is operating in the current-limit region, this bit is set to a logic 1. 32 Am79212/Am79C202 Am79212/Am79C202 Technical Reference (ELT) programmed by COP command 13. After 63 ms, the ASLAC device sets the TVD bit and, if the signal exceeds the ELT, then the OKTON bit is reset; otherwise, it remains set. Ringing Present Bit (SIG, Bit 1) In this test, the presence of ringing voltage is sensed by timing the occurrence of the voltage zero crossings of the ringing signal at IRTA, which senses the linecard side of the ring feed resistor. To start this test, the TVD (test valid) bit is set to a logic 0. The OKTTX, OKRNG, and OKTON bits in CR2 should be logic 0's. If zero crossings occur within 63 ms from the test start, the RINGX bit in the signaling register will be reset. When a zero crossing fails to appear within 63 ms, the RINGX bit is set, indicating that the ringing signal is no longer present. The only way to clear the RINGX bit after a test failure is to reset the ASLAC device or repair the fault and rerun the test. During normal ringing, the RINGX bit will be set to 0 initially and will go to a logic 1 if the ringing signal is lost. Line Test Modes To facilitate tests of the subscriber line, the TM bit in CR2 is set, which makes available special ASLAC device test states where signal levels proportional to DC loop voltage, VAB (current IAB into the ASLAC device is proportional to VAB) are converted to a digital code and sent toward the network by the GCI, B1 channel. The full-scale value corresponds to a DC loop voltage of 50 VDC. To use these test states, the following configuration adjustments must be made: 1. ASLIC/ASLAC devices to Standby using the ST bits in the downstream C/I channel (ST2 = ST1 = ST0 = 0) 2. Set the gain of the AISN to 0 and AX to 0 dB (COP command 11 = 00h) 3. Disable transmit high-pass filter (CR1.1 =1) 4. Enable Test mode (CR2.3 = 1) 5. Program the ASLAC device filter gains (shown in Table 9) using the command and coefficients indicated 6. Set the ASLIC/ASLAC devices to the Active state (ST2 = 0; ST1 = 1; ST0 = 0). Table 9. ASLAC Device Filter Gains for Line Test Modes Filter Gains COP Command # Coefficients (in Hex unless otherwise noted) Z gain = 0 V/V 19, 21 01 90 01 90 01 90 01 90 01 90 01 90 01 01 90 B gain = 0 V/V 23, 25 09 00 90 09 00 90 09 00 90 09 00 90 09 00 01 90 GX gain = 0 dB 15 80 80 X gain = 0 dB 29 01 11 01 90 01 90 01 90 01 90 01 90 Am79212/Am79C202 Am79212/Am79C202 Technical Reference 33 In some cases, equipment used for line evaluation are AC coupled or can only measure signals in the voice band. To accommodate this type of equipment, the SBT bit in CR5 has been provided that, when set, causes the measurement samples from the A/D output that are to be placed in the PCM channel to be first converted to AC or "chopped" by reversing the sign bit (bit 7) every 0.5 ms. Metallic Leakage Measurement Metallic (line-to-line) leakage resistance can be measured with greater accuracy using the following steps: 1. Set a loop current of 0.625 mA. This is accomplished by using COP command 1 to set ILA = 10.1 mA and setting the IDC/16 IDC/16 bit in CR5.7 to a logic 1. 2. With the TM bit in CR2 set to a logic 1, the metallic leakage resistance is obtained using the following equation: VAB Rleak = -0.625 + ASLIC Metallic Offset Current ( mA ) Remote Line Tests through the PCM Channel The current in the two-wire loop is K1 times the current into the RSN node of the ASLIC device. The current at the RSN node of the ASLIC device can be controlled by the VOUT pin of the ASLAC device through RRX. The full-scale output voltage of the VOUT pin is VREF ±1.25 V. The maximum current which can be controlled by this method is given by: 1.25V ILOOP = - · K1 + ASLIC Metallic Offset Current ( mA ) RRX By sending different values of A-law or µ-law codes, currents between 0 and ILOOP of each polarity may be sent. It would be necessary to reverse the polarity of the ASLIC/ASLAC devices for proper operation of negative currents. In order for VOUT to have exclusive control of the RSN node, the following configuration adjustments must be made: 1. Inactivate the ASLAC device 2. Set the gain of the AISN to 0 and AR to 0 dB (COP command 11 = 00h) 3. Program the current limit (ILA or ILD) to 5 mA (COP command 1 = 00h) 4. Set the IDC/16 IDC/16 bit in CR5.7 5. Program the ASLAC device filter gains (shown in Table 10) using the commands and coefficients indicated 6. Set the ASLIC device to Active state using the ST bits, (ST2 = 0; ST1 = 1; ST0 = 0) Table 10. ASLAC Device Filter Gains for PCM Remote Line Tests Filter Gains MPI Command # Coefficients (in Hex unless otherwise noted) Z gain = 0 V/V 48 01 90 01 90 01 90 01 90 01 90 01 90 01 01 90 B gain = 0 V/V 50 09 00 90 09 00 90 09 00 90 09 00 90 09 00 01 90 GX gain = 0 dB 44 80 80 X gain = 0 dB 52 01 11 01 90 01 90 01 90 01 90 01 90 GR gain = 0 dB 46 01 11 R gain = 0 dB 54 80 01 80 01 80 80 80 80 80 80 80 80 80 80 RG gain = 0 dB 27 CR1, bit 2 = logic 0 After these steps are performed, the current in the loop will be directly proportional to the voltage on the VOUT pin of the ASLAC device which is controlled by the PCM channel codes. This relationship will hold as long as the loop impedance is low enough to allow the voltage across the loop to be lower than the anti-saturation point. The DC voltage on the remote line can then be monitored by setting the TM bit in CR2. This encodes the voltage on the transmit PCM channel. 34 Am79212/Am79C202 Am79212/Am79C202 Technical Reference Table 11. VOUT vs. PCM Coding Coding Law PCM Code 01010101 µ-law (max/min) 2.1 (VREF) 00000000/10000000 µ-law (zero) 0.904/3.3 01111111 A-law (max/min) 2.1 (VREF) 00101010/10101010 A-law (zero) VOUT (V) 0.904/3.3 Leakage Current Tests Quick tests for leakage levels that are greater than predetermined threshold levels are available by placing the ASLIC device in various states and comparing the metallic and longitudinal current levels (ISUM and IDIF) against threshold levels programmed by the TSH and TGK fields in COP command 7. Note that this test can only compare leakage currents and not resistances. To measure resistance, a more precise measurement technique is described in the metallic leakage measurements section. To test metallic leakage current, the ASLIC device is placed in the Standby state and the desired leakage current threshold programmed using the TSH field. This current threshold represents a metallic leakage resistance threshold calculated by dividing the battery voltage by the programmed TSH current. When the leakage current is greater than the TSH current, the HOOK bit in the signalling register will be set, which means the metallic leakage resistance is less than the threshold resistance. Ring-to-ground and tip-to-ground leakages are tested by placing the ASLIC device in the Tip Open or Ring Open state respectively and programming the TGK field Loopback Modes The ASLAC device provides a digital loopback path as shown in Figure 14. The Digital Loopback mode internally feeds the downstream B1 channel in the DD path to the upstream B1 channel in the DU path, while the transmit and receive signal processors are opened. The Digital Loopback mode is invoked by setting the LB bit in CR1 to a logic 1 and the DLB bit in CR5 to a logic 0. Automatic DD - DU loopback is provided according to Table 12. A Full Digital Loopback mode that disconnects the ASLAC device from the ASLIC device and routes the downstream signal through the D/A converter and back upstream through the A/D converter is also provided. The Full Digital Loopback mode is invoked by setting the LB bit in CR1 to a logic 1 and the DLB bit in CR5 to a logic 1. Transmit Path Cutoff VIN ADC Transmit Signal Processing Decimator AISN Full Loopback Mode LB = 1 DLB = 1 Z DAC VOUT for the desired leakage current threshold. As in the metallic leakage case, the programmed resistance threshold is found by dividing the battery voltage by the programmed TGK current. When the leakage current is greater than the TGK current, the GNK bit in the upstream C/I channel will be set. Interpolator B DU Digital Loopback Mode LB = 1 DLB = 0 Receive Signal Processing Switches shown in normal, voice transmission position DD Receive Path Cutoff Figure 14. Loopback Paths Am79212/Am79C202 Am79212/Am79C202 Technical Reference 35 During Digital (DD - DU) Loopback mode, when CR5.0 = 0 and CR1.5 = 1, loopback behaves according to Table 12. Table 12. Loopback Behavior ASLAC Device State ACT = 0 (CR1.7 = 0) (Default) ACT = 1 (CR1.7 = 1) Standby Loopback Control via CR1 and CR5 Disconnect Loopback Control via CR1 and CR5 Ring open Loopback Control via CR1 and CR5 Tip open Loopback Control via CR1 and CR5 Disable Loopback Control via CR1 and CR5 Ringing Control via CR1 and CR5 Control via CR1 and CR5 Active Control via CR1 and CR5 Control via CR1 and CR5 Active, Teletax Control via CR1 and CR5 Control via CR1 and CR5 GENERAL CONTROL INTERFACE (GCI) GCI General Description The ASLAC device uses the General Control Interface (GCI) protocol where voice and control data are combined into one serial bit stream. The ASLAC device sends upstream data out of the DU pin and receives downstream data from the DD pin. Clocking and frame sync are input to the DCL and FS pins, respectively. Also, input to the multiplexer is a Status and Control (SC) byte containing subscriber line status information and a Monitor byte containing processor status information. Up to eight line circuit channel assignments are provided by strapping the S0, S1, and S2 channel selection pins on the ASLAC device to GND or VCC, as shown in Table 13. Table 13. Channel Assignment Codes (Timeslot) S2 S1 S0 Channel # GND GND GND 0 GND GND VCC 1 GND VCC GND 2 GND VCC VCC 3 VCC GND GND 4 VCC GND VCC 5 VCC VCC GND 6 VCC VCC VCC 7 In the time slot control block (shown in Figure 15), the Frame Sync (FS) pulse identifies the beginning of a transmit frame and all GCI channels are referenced to it. The channel slot number is read from the external channel identification pins, S0, S1, and S2. Voice, C/I, and monitor data are sent to the transmit multiplexer where they are combined and serially shifted out of the DU pin during the selected time slot. The receive side uses the same channel control block information to demultiplex the incoming GCI data stream into separate voice, C/I, and monitor data bytes. Normal GCI protocol allows for two voice bytes per channel; B1 and B2 (see Figure 15). The ASLAC device is designed to transmit and receive voice data in the B1 channel. The ASLAC device supports an eight-slot GCI bus. The external clock applied to the DCL pin can be either 2.048 MHz or 4.096 MHz. To ensure that internal clocking is 2.048 MHz for both of these DCL-clock rates, the ASLAC device counts the number of DCL-clock pulses per frame to determine the external clock rate. 36 Am79212/Am79C202 Am79212/Am79C202 Technical Reference Voice Data for B1 Byte C/I Data Upstream Multiplexer DU Monitor Data S0 S1 S2 DCL Time Slot Control FS B1 Byte Voice Data C/I Data Downstream Demultiplexer DD Monitor Data Figure 15. Time Slot Control and GCI Interface ASLAC DEVICE GCI FORMAT AND COMMAND STRUCTURE The GCI interface provides communication of both control and voice data between the GCI highway and subscriber line circuits over a single pair of pins on the ASLAC device. A complete GCI frame is sent upstream on the DU pin and received downstream on the DD pin every 125 µs. Each frame consists of eight, 4-byte time slots that contain voice and control information. The overall structure of the GCI frame is shown in Figure 16. The 4-byte GCI time slot contains the following: s Two bytes, B1 and B2, reserved for voice data. The B1 channel is used for voice data. The B2 channel is unused. s One monitor (M) byte for reading and writing control data and DSP coefficients to the ASLAC device. s One signaling and control (SC) byte containing a 6-bit Command/Indicate (C/I) field for control information and a 2-bit field with Monitor Receive and Monitor Transmit (MR and MX) bits for handshaking functions. All principal signaling information is carried on the C/I channel. The ASLAC device utilizes the full C/I channel capacity of the GCI bus. Am79212/Am79C202 Am79212/Am79C202 Technical Reference 37 FS 0-3 DU, DD 4-7 8-11 12-15 16-19 CHN0 CHN1 CHN2 CHN3 CHN4 20-23 24-27 CHN6 CHN5 8 8 8 B2 M SC 0 1 2 CHN7 8 B1 28-31 3 6 1 1 C/I MR MX Figure 16. Multiplexed GCI Time Slot Structure The SC Channel The upstream and downstream SC channels are continuously sending loop supervision and control data every frame to and from the ASLAC device in the C/I field. This allows the upstream processor to have immediate access to the subscriber-line loop status. The MR and MX bits are used for handshaking during data exchange on the monitor channel. 38 Am79212/Am79C202 Am79212/Am79C202 Technical Reference Downstream C/I Channel The coding of the downstream C/I channel is shown in the following diagram. The bits are received by the ASLAC device with the most significant bits first. MSB LSB 7 6 5 4 3 2 1 0 ST2 ST1 ST0 I/O1 I/O2 O1 MR MX || ST2, ST1, ST0: These bits, together with the TXTNO bit (CR5.5) and POLNR (bit 5) in the SOP command, determine the operating state of the ASLIC/ASLAC devices according to Table 14. Table 14. ASLIC/ASLAC Devices Operating States TXTNO POLNR ST2 ST1 ST0 ASLIC Device State* ASLAC Device State X X 0 0 X X 1 0 0 Standby Inactive * 0 Ring Open Inactive * X X 1 X X 0 1 0 Disconnect Inactive * 0 1 Tip Open Inactive * X X X X 1 0 1 Disable Inactive * 1 1 1 Ringing Activated 0 0 0 1 0 Active Activated 0 0 0 1 1 Active Activated 12/16 kHz Teletax 0 1 0 1 0 Active, RP Activated 0 1 0 1 1 Active, RP Activated 12/16 kHz Teletax 1 0 0 1 0 Active Activated 1 0 0 1 1 Active, RP Activated Polrev Teletax 1 1 0 1 0 Active, RP Activated 1 1 0 1 1 Active Activated Polrev Teletax Notes: X = Don't Care * The state of the ASLIC device is set by the ternary code on the C1 and C2 pins controlled by the ASLAC device. See the Operating States section for details on the ASLIC device states. * The Inactive state can be overridden by the ACT bit (CR1.7). 1. During the ASLIC device Active state, the ASLIC device is in normal polarity unless otherwise noted. 2. Reverse polarity, RP, (Tip ­, Ring +) is possible only during ASLIC device Active state. I/O1/2: Logical state of the programmable input/output pins if programmed as an output pin. 1 = The corresponding pin at the ASLAC device digital interface is driven High. 0 = The corresponding pin at the ASLAC device digital interface is driven Low. O1: Logical state of output pin O1. 1 = The corresponding pin at the ASLAC device digital interface is driven High. 0 = The corresponding pin at the ASLAC device digital interface is driven Low. Am79212/Am79C202 Am79212/Am79C202 Technical Reference 39 Figure 17 shows a flowchart that describes the transmission protocol for the downstream channel, which provides a high level of security for the C/I channel data exchange. When the received pattern of C/I bits 6 through 1 is different from the pattern currently in the C/I input register, the new pattern is loaded into a secondary C/I register and a latch is set. When the next pattern is received (in the following cycle) while the latch is set, the following rules apply: 1. If the received pattern corresponds to the pattern in the secondary register, then the new pattern is loaded into the C/I register and the latch is reset. 2. If the received pattern is different from the pattern in the secondary register and different from the pattern currently in the C/I register, the newly received pattern is loaded into the secondary C/I register and the latch remains set. 3. If the received pattern is the same as the pattern currently in the C/I register, then the C/I register is unchanged and the latch is reset. Receive New C/I Code Yes =I? No I: C/I Register Contents Store in S S: C/I Secondary Register Contents Receive New C/I Code Yes Load C/I Register with New Code =S? No =I? Yes No Figure 17. Security Procedure for C/I Downstream Byte 40 Am79212/Am79C202 Am79212/Am79C202 Technical Reference Upstream C/I Channel The SC channel, which includes the six C/I channel bits, is transmitted upstream every frame. The bit definitions in upstream C/I channel are shown in the following diagram. These bits are transmitted by the ASLAC device (most significant bit first). MSB LSB 7 6 5 4 3 2 1 0 Hook GNK SLCX I/O1 I/O2 I1 MR MX || Upstream Bit Definitions of C/I field: HOOK: Indication of loop condition. 1 = Subscriber is off-hook 0 = Subscriber is on-hook GNK: Indication if a ground connection is taking place. 1 = Ground connection 0 = No ground connection SLCX: Summary output of the signaling register (see TOP command). 1 = One or more of the unmasked bits in the signaling register has toggled. 0 = None of the unmasked bits in the signaling register has toggled. I/O1; I/O2: Logical state of the programmable input/output pins (read back of output level if programmed as an output pin). 1 = The corresponding pin at the ASLAC device digital interface is High. 0 = The corresponding pin at the ASLAC device digital interface is Low. I1: Logical state of the non-programmable input pin. 1 = The corresponding pin at the ASLAC device digital interface is High. 0 = The corresponding pin at the ASLAC device digital interface is Low. The Monitor Channel The monitor channel (see Figure 16) is used to load ASLAC device internal device registers, to read the status of the device and the contents of the internal registers, and to provide supplementary signaling. Information is transferred on the monitor channel using the MR and MX bits of the fourth (SC) octet to provide a reliable method of data exchange between the DU and DD devices. The monitor byte is the third byte in the 4-byte frame sent and received every 125 µs over the DU or DD pins. A monitor command consists of one or more command bytes on DD that may be followed with additional bytes of input data or may be followed by the ASLAC device sending out bytes of data over the DU pin. Am79212/Am79C202 Am79212/Am79C202 Technical Reference 41 Monitor Channel Protocol 1st Byte 2nd Byte 3rd Byte MX Transmitter EOM MX MR Receiver MR ACK 1st Byte ACK 2nd Byte ACK 3rd Byte 125 µs Figure 18. Maximum Speed Monitor Handshake Timing s When an MX and MR pair bit is inactive (High) for two or more consecutive frames, an idle state on the monitor channel and the end of message (EOM) is indicated. s As shown in Figure 18, a transmission is initiated by the transition of the transmitter MX bit from the Inactive state to the Active state. The transition coincides with the beginning of the first byte sent on the monitor channel. The receiver acknowledges the first byte by setting the MR bit to active and keeping it active for at least one more frame. s The same byte is sent continuously in each of the succeeding frames until either a new byte is transmitted, or the end of the message or an abort occurs. s Any false MX or MR bit received by the receiver or transmitter leads to a request for abort or an abort, respectively. s The same data must be received in two consecutive frames in order to be accepted by the receiver. 42 s A bus collision resolution mechanism is implemented in the transmitter. Before a device can send a monitor channel message, it must detect the idle condition (MR and MX both High). During the transmission of the first byte, the ASLAC device senses if the expected transmitted bit is that which is detected on the interface bus. If any bit comparison fails, transmission of more bits is immediately stopped. s Any abort command leads to a reset of any pending commands in the ASLAC device. The device remains in the previous configu