Am49PDL127BH/ Am49PDL129BH Am49PDL127BH/Am49PDL129BH PDL129 - Datasheet Archive

 

Am49PDL129BH Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced

 

Am49PDL127BH/ Am49PDL127BH/ Am49PDL129BH Am49PDL129BH Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 30452 Revision A Amendment +3 Issue Date December 16, 2003 THIS PAGE LEFT INTENTIONALLY BLANK. ADVANCE INFORMATION Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS MCP Features Both top and bottom boot blocks in one device Power supply voltage of 2.7 to 3.3 volt Manufactured on 0.13 µm process technology High performance 20-year data retention at 125°C - Access time as fast as 65 ns initial / 25 ns page Minimum 1 million erase cycle guarantee per sector Package PERFORMANCE CHARACTERISTICS - 73-Ball FBGA Operating Temperature High Performance - ­40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES 128 Mbit Page Mode device - Page size of 8 words: Fast page read access from random locations within the page Dual Chip Enable inputs (PDL129 PDL129 only) - Two CE# inputs control selection of each half of the memory space Single power supply operation - Full Voltage range: 2.7 to 3.3 volt read, erase, and program operations for battery-powered applications Simultaneous Read/Write Operation - Data can be continuously read from one bank while executing erase/program functions in another bank - Zero latency switching from write to read operations FlexBank Architecture - 4 separate banks, with up to two simultaneous operations per device - Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) - Bank B: 48 Mbit (32 Kw x 96) - Bank C: 48 Mbit (32 Kw x 96) - Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) - Page access times as fast as 25 ns - Random access times as fast as 65 ns Power consumption (typical values at 10 MHz) - 45 mA active read current - 25 mA program/erase current - 1 µA typical standby mode current SOFTWARE FEATURES Software command-set compatible with JEDEC 42.4 standard - Backward compatible with Am29F and Am29LV families CFI (Common Flash Interface) complaint - Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume - Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command - Reduces overall programming time when issuing multiple program command sequences SecSiTM (Secured Silicon) Sector region - Up to 128 words accessible through a command sequence - Up to 64 factory-locked words - Up to 64 customer-lockable words This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 30452 Rev: A Amendment +3 Issue Date: December 16, 2003 Refer to AMD's Website (www.amd.com) for the latest information. A D V A N C E I N F O R M A T I O N HARDWARE FEATURES pSRAM FEATURES Ready/Busy# pin (RY/BY#) Power dissipation - Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) - Hardware method to reset the device to reading array data WP#/ACC (Write Protect/Acceleration) input - At VIL, hardware level protection for the first and last two 4K word sectors. - At VIH, allows removal of sector protection - At VHH, provides accelerated programming in a factory setting - Operating: 40 mA maximum - Standby: 70 µA maximum - Deep power-down standby: 5 µA CE1s# and CE2ps Chip Select Power down features using CE1s# and CE2ps Data retention supply voltage: 2.7 to 3.3 volt Byte data control: LB#s (DQ7­DQ0), UB#s (DQ15­DQ8) 8-word page mode access Persistent Sector Protection - A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector - Sectors can be locked and unlocked in-system at VCC level Password Sector Protection - A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password 2 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION The Am29PDL127H/Am29PDL129H Am29PDL127H/Am29PDL129H are 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory devices organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0 DQ15-DQ0. The devices can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The devices offer fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the devices have separate chip enable (CE#f1, CE#f2), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit memory space. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: PDL127 PDL127 Configuration Chip Enable Control Bank Sectors A CE#f1 16 Mbit (4 Kw x 8 and 32 Kw x 31) B 48 Mbit (32 Kw x 96) C 48 Mbit (32 Kw x 96) D 16 Mbit (4 Kw x 8 and 32 Kw x 31) PDL129H PDL129H Configuration Chip Enable Control Bank CE#f1 CE#f2 Sectors A 16 Mbit (4 Kw x 8 and 32 Kw x 31) B 48 Mbit (32 Kw x 96) C 48 Mbit (32 Kw x 96) D 16 Mbit (4 Kw x 8 and 32 Kw x 31) Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.3 V) for both read and write functions. Internally gener- December 16, 2003 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 3 A D V A N C E I N F O R M A T I O N TABLE OF CONTENTS PDL127 PDL127 Configuration . 3 PDL129H PDL129H Configuration . 3 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagram­PDL129 PDL129 . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions . 7 Connection Diagram­PDL127 PDL127 . . . . . . . . . . . . . . . . 8 Special Package Handling Instructions . 8 Look Ahead Ballout Diagram . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12 MCP Device Bus Operations . . . . . . . . . . . . . . . . 13 Requirements for Reading Array Data . 15 Random Read (Non-Page Read) . 15 Page Mode Read . 15 Table 2. Page Select .15 Write Pulse "Glitch" Protection . 42 Logical Inhibit . 42 Power-Up Write Inhibit . 42 Common Flash Memory Interface (CFI) . . . . . . . 42 Command Definitions . . . . . . . . . . . . . . . . . . . . . 46 Reading Array Data . 46 Reset Command . 46 Autoselect Command Sequence . 46 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence . 47 Word Program Command Sequence . 47 Unlock Bypass Command Sequence . 47 Figure 5. Program Operation . 48 Chip Erase Command Sequence . 48 Sector Erase Command Sequence . 48 Simultaneous Operation . 15 Figure 6. Erase Operation. 49 Table 3. Bank Select (PDL129H PDL129H) .15 Table 4. Bank Select (PDL127H PDL127H) .15 Erase Suspend/Erase Resume Commands . 49 Password Program Command . 49 Password Verify Command . 50 Password Protection Mode Locking Bit Program Command . 50 Persistent Sector Protection Mode Locking Bit Program Command . 50 SecSi Sector Protection Bit Program Command . 50 PPB Lock Bit Set Command . 50 DYB Write Command . 50 Password Unlock Command . 50 PPB Program Command . 51 All PPB Erase Command . 51 DYB Write Command . 51 PPB Lock Bit Set Command . 51 PPB Status Command . 51 PPB Lock Bit Status Command . 51 Sector Protection Status Command . 51 Command Definitions Tables . 52 Writing Commands/Command Sequences . 16 Accelerated Program Operation . 16 Autoselect Functions . 16 Standby Mode . 16 Automatic Sleep Mode . 16 RESET#: Hardware Reset Pin . 17 Output Disable Mode . 17 Table 5. Am29PDL127H Am29PDL127H Sector Architecture .18 Table 6. Am29PDL129H Am29PDL129H Sector Architecture .25 Table 7. SecSiTM Sector Addresses .32 Table 8. Am29PDL127H Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection .33 Table 9. Am29PDL129H Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection .34 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 35 Persistent Sector Protection . 35 Persistent Protection Bit (PPB) . 35 Persistent Protection Bit Lock (PPB Lock) . 35 Dynamic Protection Bit (DYB) . 35 Table 10. Sector Protection Schemes .36 Persistent Sector Protection Mode Locking Bit . 36 Password Protection Mode . 36 Password and Password Mode Locking Bit . 37 64-bit Password . 37 Write Protect (WP#) . 37 Persistent Protection Bit Lock . 37 High Voltage Sector Protection . 38 Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms . 39 Temporary Sector Unprotect . 40 Figure 2. Temporary Sector Unprotect Operation. 40 SecSiTM (Secured Silicon) Sector Flash Memory Region . 40 Factory-Locked Area (64 words) . 40 Customer-Lockable Area (64 words) . 40 Figure 3. PDL127H/129H PDL127H/129H SecSi Sector Protection Algorithm. 41 SecSi Sector Protection Bits . 41 Figure 4. SecSi Sector Protect Verify. 42 Hardware Data Protection . 42 Low VCC Write Inhibit . 42 4 Table 15. Memory Array Command Definitions . 52 Table 16. Sector Protection Command Definitions . 53 Write Operation Status . . . . . . . . . . . . . . . . . . . . 54 DQ7: Data# Polling . 54 Figure 7. Data# Polling Algorithm . 54 RY/BY#: Ready/Busy# . 55 DQ6: Toggle Bit I . 55 Figure 8. Toggle Bit Algorithm. 55 DQ2: Toggle Bit II . 56 Reading Toggle Bits DQ6/DQ2 . 56 DQ5: Exceeded Timing Limits . 56 DQ3: Sector Erase Timer . 56 Table 17. Write Operation Status . 57 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 58 Figure 9. Maximum Negative Overshoot Waveform . 58 Figure 10. Maximum Positive Overshoot Waveform. 58 ESD Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 59 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 11. Test Setup. 61 Figure 12. Input Waveforms and Measurement Levels . 61 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 62 CE#1ps Timing . 62 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N Figure 13. Timing Diagram for Alternating Between Pseudo SRAM and Flash. 62 Flash AC Characteristics . . . . . . . . . . . . . . . . . . . 63 Read-Only Operations ­ Am29PDL127H Am29PDL127H . 63 Read-Only Operations ­ Am29PDL129H Am29PDL129H . 63 Figure 14. Read Operation Timings . 64 Figure 15. Page Read Operation Timings. 64 Hardware Reset (RESET#) . 65 Figure 16. Reset Timings . 65 Erase and Program Operations . 66 Figure 17. Program Operation Timings. 67 Figure 18. Accelerated Program Timing Diagram. 67 Figure 19. Chip/Sector Erase Operation Timings . 68 Figure 20. Back-to-back Read/Write Cycle Timings . 69 Figure 21. Data# Polling Timings (During Embedded Algorithms). 69 Figure 22. Toggle Bit Timings (During Embedded Algorithms). 70 Figure 23. DQ2 vs. DQ6. 70 Temporary Sector Unprotect . 71 Figure 24. Temporary Sector Unprotect Timing Diagram . 71 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram . 72 Alternate CE#f1 Controlled Erase and Program Operations . 73 Figure 26. Flash Alternate CE#f1 Controlled Write (Erase/Program) Operation Timings. 74 Read Cycle . 75 Figure 27. Pseudo SRAM Read Cycle. 75 Figure 28. Page Read Timing . 76 Write Cycle . 77 Figure 29. Pseudo SRAM Write Cycle-WE# Control . 77 Figure 30. Pseudo SRAM Write Cycle-CE1#s Control . 78 Figure 31. Pseudo SRAM Write Cycle- UB#s and LB#s Control. 79 Erase And Programming Performance . . . . . . . Latchup Characteristics . . . . . . . . . . . . . . . . . . . . Package Pin Capacitance. . . . . . . . . . . . . . . . . . . Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . pSRAM Power on and Deep Power Down . . . . . 80 80 80 80 81 81 Figure 32. Deep Power-down Timing. 81 Figure 33. Power-on Timing. 81 pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 82 Figure 34. Read Address Skew . 82 Figure 35. Write Address Skew. 82 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 83 TLA073-73-Ball Fine-Pitch Grid Array 8 x 11.6 mm . 83 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 84 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 75 December 16, 2003 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 5 A D V A N C E I N F O R M A T I O N PRODUCT SELECTOR GUIDE Part Number Speed Option Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH Flash Memory Standard Voltage Range: VCC = 2.7­3.3 V Pseudo SRAM 66 85 66 85 Max Access Time, ns 65 85 70 85 Page Access Time, ns 25 30 30 35 CE#f1 Access, ns 65 85 70 85 OE# Access, ns 25 30 25 30 MCP BLOCK DIAGRAM A21 to A0 (A22 PDL127 PDL127 only) (A22) A21 to A0 RY/BY# 128 MBit Flash Memory WP#/ACC RESET# CE#f1 CE#f2 (PDL129 PDL129 only) DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A20 to A0 LB#s UB#s WE# OE# CE1#ps CE2ps 6 32 MBit Pseudo SRAM DQ15 to DQ0 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAM­PDL129 PDL129 73-Ball FBGA Top View A1 A10 NC NC B1 B5 B6 B10 NC NC NC NC C5 Pseudo SRAM Only Flash Only C1 C3 C4 C6 C7 C8 NC A7 LB# WP#/ACC WE# A8 A11 D2 D3 D4 D7 D8 D9 A3 A6 UB# A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RY/BY# A20 A9 A13 A21 F1 F2 F3 F4 F7 F8 F9 F10 NC A1 A4 A17 A10 A14 CE#f2 NC G1 G2 G3 G4 G7 G8 G9 G10 NC A0 VSS DQ1 DQ6 NC A16 NC H2 H3 H4 H5 H6 H7 H8 H9 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 NC J2 J3 J4 J5 J6 J7 J8 J9 CE#1ps DQ0 DQ10 VCCf VCCps DQ12 DQ7 VSS K3 K4 K5 K6 K7 K8 DQ8 DQ2 DQ11 NC DQ5 DQ14 L1 L5 L6 L10 NC NC NC NC D5 D6 RESET# CE2ps Shared M1 M10 NC NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is December 16, 2003 exposed to temperatures above 150°C for prolonged periods of time. Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 7 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAM­PDL127 PDL127 73-Ball FBGA Top View A1 A10 NC NC B1 B5 B6 B10 NC NC NC NC C5 Flash Only C1 C3 C4 C6 C7 C8 NC A7 LB# WP#/ACC WE# A8 A11 D2 D3 D4 D7 D8 D9 A3 A6 UB# A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RY/BY# A20 A9 A13 A21 F1 F2 F3 F4 F7 F8 F9 F10 NC A1 A4 A17 A10 A14 A22 NC G1 G2 G3 G4 G7 G8 G9 G10 NC A0 VSS DQ1 DQ6 NC A16 NC H2 H3 H4 H5 H6 H7 H8 H9 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 NC J2 J3 J4 J5 J6 J7 J8 J9 CE#1ps DQ0 DQ10 VCCf VCCps DQ12 DQ7 VSS K3 K4 K5 K6 K7 K8 DQ8 DQ2 DQ11 NC DQ5 DQ14 L1 L5 L6 L10 NC NC NC NC D5 D6 RESET# CE2ps Shared M1 M10 NC NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data 8 Pseudo SRAM Only integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N PIN DESCRIPTION LOGIC SYMBOL A20­A0 = 21 Address Inputs (Common) A21 = Address Inputs (Flash) A22 = Address Input (PDL127 PDL127 only) (Flash) A21 DQ15­DQ0 = 16 Data Inputs/Outputs (Common) A22 (PDL127 PDL127 Only) CE#f1 = Chip Enable 1 (Flash) CE#f1 CE#f2 = Chip Enable 2 (Flash) (PDL 129 only) CE#f2 (PDL129 PDL129 Only) CE#1ps = Chip Enable 1 (pSRAM) CE2ps = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) WE# RY/BY# = Ready/Busy Output and open drain. When RY/BY# = VIH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. WP#/ACC UB#s OE# RESET# UB#s LB#s = Device Ground (Common) NC RY/BY# = pSRAM Power Supply VSS CE2ps = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs CE#1ps = Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V, program and erase operations are accelerated. VCCf DQ15­DQ0 = Hardware Reset Pin, Active Low WP#/ACC 16 = Lower Byte Control (pSRAM) RESET# A20­A0 = Upper Byte Control (pSRAM) LB#s 21 = Pin Not Connected Internally December 16, 2003 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 9 A D V A N C E I N F O R M A T I O N LOOK AHEAD BALLOUT DIAGRAM A1 A2 A9 A10 NC NC NC NC B1 B2 B9 B10 NC NC NC LEGEND NC C2 C3 C4 C5 C6 C7 C8 C9 AVD# VSS CLK CE#f2 VCC RST# CLK RY/BY# D2 D3 D4 D5 D6 D7 D8 D9 WP# A7 LB# ACC or WP#/ACC WE# A8 A11 CE#1 E2 E3 E4 E5 E6 E7 E8 E9 A3 A6 UB# RESET# CE2 A19 A12 A15 F2 F3 F4 F5 F6 F7 F8 F9 A2 A5 A18 RY/BY# A20 A9 A13 A21 G2 G3 G4 G5 G6 G7 G8 G9 A1 A4 A17 CE#1 A23 A10 A14 A22 H2 H3 H4 H5 H6 H7 H8 H9 A0 VSS DQ1 VCC CE2 DQ6 A24 A16 J2 J3 J4 J5 J6 J7 J8 J9 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 CREs or VCCf K2 K3 K4 K5 K6 K7 K8 K9 CE1# DQ0 DQ10 VCCf VCC DQ12 DQ7 VSS L2 L3 L4 L5 L6 L7 L8 L9 NC DQ8 DQ2 DQ11 A25 or VCCQ DQ5 M2 M3 M4 M5 M6 M7 M8 M9 IRQ/A27 IRQ/A27 A26 NC VCC/VCCQ CE#2 VCCQ VCCQ Data Storage NC 1st RAM 2nd RAM FASL Standard MCP Packages 7.0 x 9.0 mm 8.0 x 10.0 mm 8.0 x 11.6 mm 9.0 x 12.0 mm DQ14 LOCK or WP#/ACC N1 N2 N9 N10 NC NC NC NC P1 P2 P9 P10 NC NC NC NC Note: The future ballouts shown in this diagram represent possible future products with densities up to 4 Gbits of Flash plus 4 Gbits of SRAM. Device combinations include NOR Flash plus SRAM, NOR Flash plus pSRAM, and NOR Flash plus pSRAM plus data storage. Contact a sales representative for device specifications, planned production, and availability before designing in any future product. 10 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N To provide customers with a migration path to higher densities, as well as the option of stacking more die in o ne pa cka ge, th e pre ce ding diagram s how s a look-ahead ballout that supports: NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and PSRAM densities up to 4 Gigabits NOR Flash and PSRAM and DATA STORAGE densities up to 4 Gigabits December 16, 2003 The signal locations of the resultant MCP device are shown in the diagram. Note that for different densities, the actual package outline may vary. However, any ballout in any MCP will be a subset of the ballout diagram shown. In some cases, there may be outrigger balls in locations outside the grid shown. Do not connect these outrigger balls to any signal. For further information regarding the look-ahead ballout, contact the appropriate AMD or Fujitsu sales office. Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 11 A D V A N C E I N F O R M A T I O N ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49PDL12 Am49PDL12 7 B H 66 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (­40°C to +85°C) SPEED OPTION See "Product Selector Guide" on page 5. PROCESS TECHNOLOGY H = 0.13 µm PSEUDO SRAM DEVICE DENSITY B = 32 Mbits CONTROL PINS 7 = 1 CE Flash 9 = 2 CE Flash AMD DEVICE NUMBER/DESCRIPTION Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) Pseudo Static RAM with Page Mode Valid Combinations Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Order Number Package Marking T, S M490000028 M490000028 Am49PDL127BH85I Am49PDL127BH85I T, S M490000029 M490000029 Am49PDL129BH66I Am49PDL129BH66I T, S M490000030 M490000030 Am49PDL129BH85I Am49PDL129BH85I 12 Am49PDL127BH66I Am49PDL127BH66I T, S M490000031 M490000031 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information December 16, 2003 needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 13 A D V A N C E Table 1. Write to Active Flash Device Bus Operations CE#f2 CE#f1 (PDL129 PDL129 CE#1ps CE2ps OE# WE# Active only) Operation (Notes 1, 2) Read from Active Flash I N F O R M A T I O N (Note 7) (Note 8) (Note 7) (Note 8) L (H) H (L) L (H) H (L) H H H L H H H L Addr. LB#s UB#s WP#/ (Note (Note RESET# ACC 3) 3) (Note 4) DQ7­ DQ0 DQ15­ DQ8 L H AIN X X H L/H DOUT DOUT H L AIN X X H (Note 4) DIN DIN Standby VCC ± 0.3 V H H X X X X X VCC ± 0.3 V H High-Z High-Z Deep Power-down Standby VCC ± 0.3 V H L X X X X X VCC ± 0.3 V H High-Z High-Z L H H H X X X H H X X X H L/H High-Z High-Z X X X X X L L/H High-Z High-Z L SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X H L SADD, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X X X X X X VID (Note 6) DIN High-Z L L DOUT DOUT L H AIN H L H X High-Z DOUT L H DOUT High-Z L L DIN DIN H L High-Z DIN L H DIN High-Z Output Disable (Note 9) L (H) Flash Hardware (Note 7) Reset (Note 8) H (L) H Sector Unprotect (Notes 5, 9) Temporary Sector Unprotect (Note 9) (Note 8) H (L) (Note 7) X (Note 8) Read from pSRAM Write to pSRAM L (H) H H H H L H H L H H (Note 7) H H H (L) H H L (H) L H (Note 7) Sector Protect (Notes 6, 10) H H X L L H L H H X L AIN H X Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5­12.5 V, VHH = 9.0 ± 0.5 V, X = Don't Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f1 or 2 = VIL, CE#1ps = VIL and CE2ps = VIH at the same time. 3. Don't care or open LB#s or UB#s. 4. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. 7. Data will be retained in pSRAM. 8. Data will be lost in pSRAM. 9. Both CE#f1 inputs may be held low for this operation. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. 14 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appropriate CE#f1/CE#f2 (PDL129 PDL129 only) pins to VIL. CE#f1 and CE#f2 are the power control and for PDL129 PDL129 select the lower (CE#f1) or upper (CE#f2) halves of the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. page mode accesses are obtained by keeping A22­A3 (A21­A3 for PDL129 PDL129) constant and changing A2 to A0 to select the specific word within that page. Table 2. Word Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE#f1 to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC­tOE time). A2 A1 A0 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the Flash AC Characteristics table for timing specifications and to Figure 14 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. 1 1 1 Simultaneous Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), The bank can be selected by bank addresses (A22­A20) (A21­A20 for PDL129 PDL129) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 3. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits A22­A3 (A21­A3 for PDL129 PDL129) select an 8-word page, and address bits A2­A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor fall within that page) are t PACC. When CE#f1 and CE#f2 (PDL129 PDL129 only) are deasserted (CE#f1=CE#f2=VIH), the reassertion of CE#f1 or CE#f2 (PDL129 PDL129 only) for subsequent access has access time of t ACC or t CE . Here again, CE#f1/CE#f2 (PDL129 PDL129 only) selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast December 16, 2003 Page Select Bank Select (PDL129H PDL129H) Bank CE#f1 CE#f2 A21­A20 Bank A 0 1 00, 01, 10 Bank B 0 1 11 Bank C 1 0 00 Bank D 1 0 01, 10, 11 Table 4. Bank Select (PDL127H PDL127H) Bank A22­A20 Bank A 000 Bank B 001, 010, 011 Bank C 100, 101, 110 Bank D 111 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 15 A D V A N C E I N F O R M A T I O N Writing Commands/Command Sequences Autoselect Functions To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f1 or CE#f2 (PDL 129 only) to VIL, and OE# to VIH. If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15­DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Command Sequence sections for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" refers to the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The Flash AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result. 16 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f1, CE#f2 (PDL129 PDL129 only) and RESET# pins are all held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE#f1, CE#f2 (PDL129 PDL129 only), and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 150 ns. The automatic sleep mode is independent of the CE#f1/CE#f2 (PDL129 PDL129 only), WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash December 16, 2003 memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 17 A D V A N C E Table 5. Am29PDL127H Am29PDL127H Sector Architecture Sector Size (Kwords) Address Range (x16) 00000000000 4 000000h­000FFFh 00000000001 4 001000h­001FFFh SA2 00000000010 4 002000h­002FFFh SA3 00000000011 4 003000h­003FFFh SA4 00000000100 4 004000h­004FFFh SA5 00000000101 4 005000h­005FFFh SA6 00000000110 4 006000h­006FFFh SA7 00000000111 4 007000h­007FFFh SA8 00000001XXX 00000001XXX 32 008000h­00FFFFh SA9 00000010XXX 00000010XXX 32 010000h­017FFFh SA10 00000011XXX 00000011XXX 32 018000h­01FFFFh SA11 00000100XXX 00000100XXX 32 020000h­027FFFh SA12 00000101XXX 00000101XXX 32 028000h­02FFFFh SA13 00000110XXX 00000110XXX 32 030000h­037FFFh SA14 00000111XXX 00000111XXX 32 038000h­03FFFFh SA15 00001000XXX 00001000XXX 32 040000h­047FFFh SA16 00001001XXX 00001001XXX 32 048000h­04FFFFh SA17 00001010XXX 00001010XXX 32 050000h­057FFFh SA18 00001011XXX 00001011XXX 32 058000h­05FFFFh SA19 00001100XXX 00001100XXX 32 060000h­067FFFh SA20 00001101XXX 00001101XXX 32 068000h­06FFFFh SA21 00001110XXX 00001110XXX 32 070000h­077FFFh SA22 00001111XXX 00001111XXX 32 078000h­07FFFFh SA23 00010000XXX 00010000XXX 32 080000h­087FFFh SA24 00010001XXX 00010001XXX 32 088000h­08FFFFh SA25 00010010XXX 00010010XXX 32 090000h­097FFFh SA26 00010011XXX 00010011XXX 32 098000h­09FFFFh SA27 00010100XXX 00010100XXX 32 0A0000h­0A7FFFh SA28 00010101XXX 00010101XXX 32 0A8000h­0AFFFFh SA29 00010110XXX 00010110XXX 32 0B0000h­0B7FFFh SA30 00010111XXX 00010111XXX 32 0B8000h­0BFFFFh SA31 00011000XXX 00011000XXX 32 0C0000h­0C7FFFh SA32 00011001XXX 00011001XXX 32 0C8000h­0CFFFFh SA33 00011010XXX 00011010XXX 32 0D0000h­0D7FFFh SA34 00011011XXX 00011011XXX 32 0D8000h­0DFFFFh SA35 00011100XXX 00011100XXX 32 0E0000h­0E7FFFh SA36 00011101XXX 00011101XXX 32 0E8000h­0EFFFFh SA37 00011110XXX 00011110XXX 32 0F0000h­0F7FFFh SA38 18 Sector Address (A22-A12 A22-A12) SA1 Bank Sector SA0 Bank A Bank I N F O R M A T I O N 00011111XXX 00011111XXX 32 0F8000h­0FFFFFh Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E Table 5. I N F O R M A T I O N Am29PDL127H Am29PDL127H Sector Architecture (Continued) 100000h­107FFFh 00100001XXX 00100001XXX 32 108000h­10FFFFh 00100010XXX 00100010XXX 32 110000h­117FFFh SA42 00100011XXX 00100011XXX 32 118000h­11FFFFh SA43 00100100XXX 00100100XXX 32 120000h­127FFFh SA44 00100101XXX 00100101XXX 32 128000h­12FFFFh SA45 00100110XXX 00100110XXX 32 130000h­137FFFh SA46 00100111XXX 00100111XXX 32 138000h­13FFFFh SA47 00101000XXX 00101000XXX 32 140000h­147FFFh SA48 00101001XXX 00101001XXX 32 148000h­14FFFFh SA49 00101010XXX 00101010XXX 32 150000h­157FFFh SA50 00101011XXX 00101011XXX 32 158000h­15FFFFh SA51 00101100XXX 00101100XXX 32 160000h­167FFFh SA52 00101101XXX 00101101XXX 32 168000h­16FFFFh SA53 00101110XXX 00101110XXX 32 170000h­177FFFh SA54 00101111XXX 00101111XXX 32 178000h­17FFFFh SA55 00110000XXX 00110000XXX 32 180000h­187FFFh SA56 00110001XXX 00110001XXX 32 188000h­18FFFFh SA57 00110010XXX 00110010XXX 32 190000h­197FFFh SA58 00110011XXX 00110011XXX 32 198000h­19FFFFh SA59 00110100XXX 00110100XXX 32 1A0000h­1A7FFFh SA60 00110101XXX 00110101XXX 32 1A8000h­1AFFFFh SA61 00110110XXX 00110110XXX 32 1B0000h­1B7FFFh SA62 00110111XXX 00110111XXX 32 1B8000h­1BFFFFh SA63 00111000XXX 00111000XXX 32 1C0000h­1C7FFFh SA64 00111001XXX 00111001XXX 32 1C8000h­1CFFFFh SA65 00111010XXX 00111010XXX 32 1D0000h­1D7FFFh SA66 00111011XXX 00111011XXX 32 1D8000h­1DFFFFh SA67 00111100XXX 00111100XXX 32 1E0000h­1E7FFFh SA68 00111101XXX 00111101XXX 32 1E8000h­1EFFFFh SA69 00111110XXX 00111110XXX 32 1F0000h­1F7FFFh SA70 00111111XXX 00111111XXX 32 1F8000h­1FFFFFh SA71 01000000XXX 01000000XXX 32 200000h­207FFFh SA72 01000001XXX 01000001XXX 32 208000h­20FFFFh SA73 01000010XXX 01000010XXX 32 210000h­217FFFh SA74 01000011XXX 01000011XXX 32 218000h­21FFFFh SA75 01000100XXX 01000100XXX 32 220000h­227FFFh SA76 01000101XXX 01000101XXX 32 228000h­22FFFFh SA77 01000110XXX 01000110XXX 32 230000h­237FFFh SA78 December 16, 2003 32 SA41 Bank 00100000XXX 00100000XXX SA40 Bank B SA39 01000111XXX 01000111XXX 32 238000h­23FFFFh Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 19 A D V A N C E Table 5. I N F O R M A T I O N Am29PDL127H Am29PDL127H Sector Architecture (Continued) 240000h­247FFFh 01001001XXX 01001001XXX 32 248000h­24FFFFh 01001010XXX 01001010XXX 32 250000h­257FFFh SA82 01001011XXX 01001011XXX 32 258000h­25FFFFh SA83 01001100XXX 01001100XXX 32 260000h­267FFFh SA84 01001101XXX 01001101XXX 32 268000h­26FFFFh SA85 01001110XXX 01001110XXX 32 270000h­277FFFh SA86 01001111XXX 01001111XXX 32 278000h­27FFFFh SA87 01010000XXX 01010000XXX 32 280000h­287FFFh SA88 01010001XXX 01010001XXX 32 288000h­28FFFFh SA89 01010010XXX 01010010XXX 32 290000h­297FFFh SA90 01010011XXX 01010011XXX 32 298000h­29FFFFh SA91 01010100XXX 01010100XXX 32 2A0000h­2A7FFFh SA92 01010101XXX 01010101XXX 32 2A8000h­2AFFFFh SA93 01010110XXX 01010110XXX 32 2B0000h­2B7FFFh SA94 01010111XXX 01010111XXX 32 2B8000h­2BFFFFh SA95 01011000XXX 01011000XXX 32 2C0000h­2C7FFFh SA96 01011001XXX 01011001XXX 32 2C8000h­2CFFFFh SA97 01011010XXX 01011010XXX 32 2D0000h­2D7FFFh SA98 01011011XXX 01011011XXX 32 2D8000h­2DFFFFh SA99 01011100XXX 01011100XXX 32 2E0000h­2E7FFFh SA100 SA100 01011101XXX 01011101XXX 32 2E8000h­2EFFFFh SA101 SA101 01011110XXX 01011110XXX 32 2F0000h­2F7FFFh SA102 SA102 01011111XXX 01011111XXX 32 2F8000h­2FFFFFh SA103 SA103 01100000XXX 01100000XXX 32 300000h­307FFFh SA104 SA104 01100001XXX 01100001XXX 32 308000h­30FFFFh SA105 SA105 01100010XXX 01100010XXX 32 310000h­317FFFh SA106 SA106 01100011XXX 01100011XXX 32 318000h­31FFFFh SA107 SA107 01100100XXX 01100100XXX 32 320000h­327FFFh SA108 SA108 01100101XXX 01100101XXX 32 328000h­32FFFFh SA109 SA109 01100110XXX 01100110XXX 32 330000h­337FFFh SA110 SA110 01100111XXX 01100111XXX 32 338000h­33FFFFh SA111 SA111 01101000XXX 01101000XXX 32 340000h­347FFFh SA112 SA112 01101001XXX 01101001XXX 32 348000h­34FFFFh SA113 SA113 01101010XXX 01101010XXX 32 350000h­357FFFh SA114 SA114 01101011XXX 01101011XXX 32 358000h­35FFFFh SA115 SA115 01101100XXX 01101100XXX 32 360000h­367FFFh SA116 SA116 01101101XXX 01101101XXX 32 368000h­36FFFFh SA117 SA117 01101110XXX 01101110XXX 32 370000h­377FFFh SA118 SA118 20 32 SA81 Bank 01001000XXX 01001000XXX SA80 Bank B SA79 01101111XXX 01101111XXX 32 378000h­37FFFFh Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E Table 5. I N F O R M A T I O N Am29PDL127H Am29PDL127H Sector Architecture (Continued) 01110001XXX 01110001XXX 32 388000h­38FFFFh 01110010XXX 01110010XXX 32 390000h­397FFFh 01110011XXX 01110011XXX 32 398000h­39FFFFh SA123 SA123 01110100XXX 01110100XXX 32 3A0000h­3A7FFFh SA124 SA124 01110101XXX 01110101XXX 32 3A8000h­3AFFFFh SA125 SA125 01110110XXX 01110110XXX 32 3B0000h­3B7FFFh SA126 SA126 01110111XXX 01110111XXX 32 3B8000h­3BFFFFh SA127 SA127 01111000XXX 01111000XXX 32 3C0000h­3C7FFFh SA128 SA128 01111001XXX 01111001XXX 32 3C8000h­3CFFFFh SA129 SA129 01111010XXX 01111010XXX 32 3D0000h­3D7FFFh SA130 SA130 01111011XXX 01111011XXX 32 3D8000h­3DFFFFh SA131 SA131 01111100XXX 01111100XXX 32 3E0000h­3E7FFFh SA132 SA132 01111101XXX 01111101XXX 32 3E8000h­3EFFFFh SA133 SA133 01111110XXX 01111110XXX 32 3F0000h­3F7FFFh SA134 SA134 01111111XXX 01111111XXX 32 3F8000h­3FFFFFh SA135 SA135 10000000XXX 10000000XXX 32 400000h­407FFFh SA136 SA136 10000001XXX 10000001XXX 32 408000h­40FFFFh SA137 SA137 10000010XXX 10000010XXX 32 410000h­417FFFh SA138 SA138 10000011XXX 10000011XXX 32 418000h­41FFFFh SA139 SA139 10000100XXX 10000100XXX 32 420000h­427FFFh SA140 SA140 10000101XXX 10000101XXX 32 428000h­42FFFFh SA141 SA141 10000110XXX 10000110XXX 32 430000h­437FFFh SA142 SA142 10000111XXX 10000111XXX 32 438000h­43FFFFh SA143 SA143 10001000XXX 10001000XXX 32 440000h­447FFFh SA144 SA144 10001001XXX 10001001XXX 32 448000h­44FFFFh SA145 SA145 10001010XXX 10001010XXX 32 450000h­457FFFh SA146 SA146 10001011XXX 10001011XXX 32 458000h­45FFFFh SA147 SA147 10001100XXX 10001100XXX 32 460000h­467FFFh SA148 SA148 10001101XXX 10001101XXX 32 468000h­46FFFFh SA149 SA149 10001110XXX 10001110XXX 32 470000h­477FFFh SA150 SA150 10001111XXX 10001111XXX 32 478000h­47FFFFh SA151 SA151 10010000XXX 10010000XXX 32 480000h­487FFFh SA152 SA152 10010001XXX 10010001XXX 32 488000h­48FFFFh SA153 SA153 10010010XXX 10010010XXX 32 490000h­497FFFh SA154 SA154 10010011XXX 10010011XXX 32 498000h­49FFFFh SA155 SA155 10010100XXX 10010100XXX 32 4A0000h­4A7FFFh SA156 SA156 10010101XXX 10010101XXX 32 4A8000h­4AFFFFh SA157 SA157 10010110XXX 10010110XXX 32 4B0000h­4B7FFFh SA158 SA158 Bank C 380000h­387FFFh SA122 SA122 December 16, 2003 32 SA121 SA121 Bank 01110000XXX 01110000XXX SA120 SA120 Bank B SA119 SA119 10010111XXX 10010111XXX 32 4B8000h­4BFFFFh Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 21 A D V A N C E Table 5. I N F O R M A T I O N Am29PDL127H Am29PDL127H Sector Architecture (Continued) SA159 SA159 10011000XXX 10011000XXX 32 4C0000h­4C7FFFh SA160 SA160 10011001XXX 10011001XXX 32 4C8000h­4CFFFFh SA161 SA161 10011010XXX 10011010XXX 32 4D0000h­4D7FFFh SA162 SA162 10011011XXX 10011011XXX 32 4D8000h­4DFFFFh SA163 SA163 10011100XXX 10011100XXX 32 4E0000h­4E7FFFh 10011101XXX 10011101XXX 32 4E8000h­4EFFFFh SA165 SA165 10011110XXX 10011110XXX 32 4F0000h­4F7FFFh SA166 SA166 10011111XXX 10011111XXX 32 4F8000h­4FFFFFh SA167 SA167 10100000XXX 10100000XXX 32 500000h­507FFFh SA168 SA168 10100001XXX 10100001XXX 32 508000h­50FFFFh SA169 SA169 10100010XXX 10100010XXX 32 510000h­517FFFh SA170 SA170 10100011XXX 10100011XXX 32 518000h­51FFFFh SA171 SA171 10100100XXX 10100100XXX 32 520000h­527FFFh SA172 SA172 10100101XXX 10100101XXX 32 528000h­52FFFFh SA173 SA173 10100110XXX 10100110XXX 32 530000h­537FFFh SA174 SA174 10100111XXX 10100111XXX 32 538000h­53FFFFh SA175 SA175 10101000XXX 10101000XXX 32 540000h­547FFFh SA176 SA176 10101001XXX 10101001XXX 32 548000h­54FFFFh SA177 SA177 10101010XXX 10101010XXX 32 550000h­557FFFh SA178 SA178 10101011XXX 10101011XXX 32 558000h­15FFFFh SA179 SA179 10101100XXX 10101100XXX 32 560000h­567FFFh SA180 SA180 10101101XXX 10101101XXX 32 568000h­56FFFFh SA181 SA181 10101110XXX 10101110XXX 32 570000h­577FFFh SA182 SA182 10101111XXX 10101111XXX 32 578000h­57FFFFh SA183 SA183 10110000XXX 10110000XXX 32 580000h­587FFFh SA184 SA184 10110001XXX 10110001XXX 32 588000h­58FFFFh SA185 SA185 10110010XXX 10110010XXX 32 590000h­597FFFh SA186 SA186 10110011XXX 10110011XXX 32 598000h­59FFFFh SA187 SA187 10110100XXX 10110100XXX 32 5A0000h­5A7FFFh SA188 SA188 10110101XXX 10110101XXX 32 5A8000h­5AFFFFh SA189 SA189 Bank C SA164 SA164 10110110XXX 10110110XXX 32 5B0000h­5B7FFFh SA190 SA190 5B8000h­5BFFFFh 32 5C0000h­5C7FFFh 10111001XXX 10111001XXX 32 5C8000h­5CFFFFh SA193 SA193 10111010XXX 10111010XXX 32 5D0000h­5D7FFFh SA194 SA194 10111011XXX 10111011XXX 32 5D8000h­5DFFFFh SA195 SA195 10111100XXX 10111100XXX 32 5E0000h­5E7FFFh SA196 SA196 10111101XXX 10111101XXX 32 5E8000h­5EFFFFh SA197 SA197 10111110XXX 10111110XXX 32 5F0000h­5F7FFFh SA198 SA198 22 32 10111000XXX 10111000XXX SA192 SA192 Bank 10110111XXX 10110111XXX SA191 SA191 10111111XXX 10111111XXX 32 5F8000h­5FFFFFh Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E Table 5. I N F O R M A T I O N Am29PDL127H Am29PDL127H Sector Architecture (Continued) 32 600000h­607FFFh 11000001XXX 11000001XXX 32 608000h­60FFFFh SA201 SA201 11000010XXX 11000010XXX 32 610000h­617FFFh SA202 SA202 11000011XXX 11000011XXX 32 618000h­61FFFFh SA203 SA203 11000100XXX 11000100XXX 32 620000h­627FFFh SA204 SA204 11000101XXX 11000101XXX 32 628000h­62FFFFh SA205 SA205 11000110XXX 11000110XXX 32 630000h­637FFFh SA206 SA206 11000111XXX 11000111XXX 32 638000h­63FFFFh SA207 SA207 11001000XXX 11001000XXX 32 640000h­647FFFh SA208 SA208 11001001XXX 11001001XXX 32 648000h­64FFFFh SA209 SA209 11001010XXX 11001010XXX 32 650000h­657FFFh SA210 SA210 11001011XXX 11001011XXX 32 658000h­65FFFFh SA211 SA211 11001100XXX 11001100XXX 32 660000h­667FFFh SA212 SA212 11001101XXX 11001101XXX 32 668000h­66FFFFh SA213 SA213 11001110XXX 11001110XXX 32 670000h­677FFFh SA214 SA214 11001111XXX 11001111XXX 32 678000h­67FFFFh SA215 SA215 11010000XXX 11010000XXX 32 680000h­687FFFh SA216 SA216 11010001XXX 11010001XXX 32 688000h­68FFFFh SA217 SA217 11010010XXX 11010010XXX 32 690000h­697FFFh SA218 SA218 11010011XXX 11010011XXX 32 698000h­69FFFFh SA219 SA219 11010100XXX 11010100XXX 32 6A0000h­6A7FFFh SA220 SA220 11010101XXX 11010101XXX 32 6A8000h­6AFFFFh SA221 SA221 11010110XXX 11010110XXX 32 6B0000h­6B7FFFh SA222 SA222 11010111XXX 11010111XXX 32 6B8000h­6BFFFFh SA223 SA223 11011000XXX 11011000XXX 32 6C0000h­6C7FFFh SA224 SA224 11011001XXX 11011001XXX 32 6C8000h­6CFFFFh SA225 SA225 11011010XXX 11011010XXX 32 6D0000h­6D7FFFh SA226 SA226 11011011XXX 11011011XXX 32 6D8000h­6DFFFFh SA227 SA227 11011100XXX 11011100XXX 32 6E0000h­6E7FFFh SA228 SA228 11011101XXX 11011101XXX 32 6E8000h­6EFFFFh SA229 SA229 11011110XXX 11011110XXX 32 6F0000h­6F7FFFh SA230 SA230 December 16, 2003 11000000XXX 11000000XXX SA200 SA200 Bank C SA199 SA199 11011111XXX 11011111XXX 32 6F8000h­6FFFFFh Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 23 A D V A N C E Table 5. Am29PDL127H Am29PDL127H Sector Architecture (Continued) Sector Sector Address (A22-A12 A22-A12) Sector Size (Kwords) Address Range (x16) SA231 SA231 11100000XXX 11100000XXX 32 700000h­707FFFh SA232 SA232 11100001XXX 11100001XXX 32 708000h­70FFFFh SA233 SA233 11100010XXX 11100010XXX 32 710000h­717FFFh SA234 SA234 11100011XXX 11100011XXX 32 718000h­71FFFFh SA235 SA235 11100100XXX 11100100XXX 32 720000h­727FFFh SA236 SA236 11100101XXX 11100101XXX 32 728000h­72FFFFh SA237 SA237 11100110XXX 11100110XXX 32 730000h­737FFFh SA238 SA238 11100111XXX 11100111XXX 32 738000h­73FFFFh SA239 SA239 11101000XXX 11101000XXX 32 740000h­747FFFh SA240 SA240 11101001XXX 11101001XXX 32 748000h­74FFFFh SA241 SA241 11101010XXX 11101010XXX 32 750000h­757FFFh SA242 SA242 11101011XXX 11101011XXX 32 758000h­75FFFFh SA243 SA243 11101100XXX 11101100XXX 32 760000h­767FFFh SA244 SA244 11101101XXX 11101101XXX 32 768000h­76FFFFh SA245 SA245 11101110XXX 11101110XXX 32 770000h­777FFFh SA246 SA246 11101111XXX 11101111XXX 32 778000h­77FFFFh SA247 SA247 11110000XXX 11110000XXX 32 780000h­787FFFh SA248 SA248 11110001XXX 11110001XXX 32 788000h­78FFFFh SA249 SA249 11110010XXX 11110010XXX 32 790000h­797FFFh SA250 SA250 11110011XXX 11110011XXX 32 798000h­79FFFFh SA251 SA251 11110100XXX 11110100XXX 32 7A0000h­7A7FFFh SA252 SA252 11110101XXX 11110101XXX 32 7A8000h­7AFFFFh SA253 SA253 11110110XXX 11110110XXX 32 7B0000h­7B7FFFh SA254 SA254 11110111XXX 11110111XXX 32 7B8000h­7BFFFFh SA255 SA255 11111000XXX 11111000XXX 32 7C0000h­7C7FFFh SA256 SA256 11111001XXX 11111001XXX 32 7C8000h­7CFFFFh SA257 SA257 11111010XXX 11111010XXX 32 7D0000h­7D7FFFh SA258 SA258 11111011XXX 11111011XXX 32 7D8000h­7DFFFFh SA259 SA259 Bank D Bank I N F O R M A T I O N 11111100XXX 11111100XXX 32 7E0000h­7E7FFFh SA260 SA260 32 7E8000h­7EFFFFh 11111110XXX 11111110XXX 32 7F0000h­7F7FFFh SA262 SA262 11111111000 4 7F8000h­7F8FFFh SA263 SA263 11111111001 4 7F9000h­7F9FFFh SA264 SA264 11111111010 4 7FA000h­7FAFFFh SA265 SA265 11111111011 4 7FB000h­7FBFFFh SA266 SA266 11111111100 4 7FC000h­7FCFFFh SA267 SA267 11111111101 4 7FD000h­7FDFFFh SA268 SA268 11111111110 4 7FE000h­7FEFFFh SA269 SA269 24 11111101XXX 11111101XXX SA261 SA261 11111111111 4 7FF000h­7FFFFFh Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture CE#f2 Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) 0 1 0000000000 4 000000h­000FFFh 0 1 0000000001 4 001000h­001FFFh SA2 0 1 0000000010 4 002000h­002FFFh SA3 0 1 0000000011 4 003000h­003FFFh SA4 0 1 0000000100 4 004000h­004FFFh SA5 0 1 0000000001 4 005000h­005FFFh SA6 0 1 0000000010 4 006000h­006FFFh SA7 0 1 0000000011 4 007000h­007FFFh SA8 0 1 0000001XXX 0000001XXX 32 008000h­00FFFFh SA9 0 1 0000010XXX 0000010XXX 32 010000h­017FFFh SA10 0 1 0000011XXX 0000011XXX 32 018000h­01FFFFh SA11 0 1 0000100XXX 0000100XXX 32 020000h­027FFFh SA12 0 1 0000101XXX 0000101XXX 32 028000h­02FFFFh SA13 0 1 0000110XXX 0000110XXX 32 030000h­037FFFh SA14 0 1 0000111XXX 0000111XXX 32 038000h­03FFFFh SA15 0 1 0001000XXX 0001000XXX 32 040000h­047FFFh SA16 0 1 0001001XXX 0001001XXX 32 048000h­04FFFFh SA17 0 1 0001010XXX 0001010XXX 32 050000h­057FFFh SA18 0 1 0001011XXX 0001011XXX 32 058000h­05FFFFh SA19 0 1 0001100XXX 0001100XXX 32 060000h­067FFFh SA20 0 1 0001101XXX 0001101XXX 32 068000h­06FFFFh SA21 0 1 0001110XXX 0001110XXX 32 070000h­077FFFh SA22 0 1 0001111XXX 0001111XXX 32 078000h­07FFFFh SA23 0 1 0010000XXX 0010000XXX 32 080000h­087FFFh SA24 0 1 0010001XXX 0010001XXX 32 088000h­08FFFFh SA25 0 1 0010010XXX 0010010XXX 32 090000h­097FFFh SA26 0 1 0010011XXX 0010011XXX 32 098000h­09FFFFh SA27 0 1 0010100XXX 0010100XXX 32 0A0000h­0A7FFFh SA28 0 1 0010101XXX 0010101XXX 32 0A8000h­0AFFFFh SA29 0 1 0010110XXX 0010110XXX 32 0B0000h­0B7FFFh SA30 0 1 0010111XXX 0010111XXX 32 0B8000h­0BFFFFh SA31 0 1 0011000XXX 0011000XXX 32 0C0000h­0C7FFFh SA32 0 1 0011001XXX 0011001XXX 32 0C8000h­0CFFFFh SA33 0 1 0011010XXX 0011010XXX 32 0D0000h­0D7FFFh SA34 0 1 0011011XXX 0011011XXX 32 0D8000h­0DFFFFh SA35 0 1 0011100XXX 0011100XXX 32 0E0000h­0E7FFFh SA36 0 1 0011101XXX 0011101XXX 32 0E8000h­0EFFFFh SA37 0 1 0011110XXX 0011110XXX 32 0F0000h­0F7FFFh SA38 Bank A CE#f1 SA1 Bank Sector SA0 Bank 0 1 0011111XXX 0011111XXX 32 0F8000h­0FFFFFh Sector CE#f1 CE#f2 Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) December 16, 2003 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 25 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture (Continued) 0100000XXX 0100000XXX 32 100000h­107FFFh 0 1 0100001XXX 0100001XXX 32 108000h­10FFFFh 0 1 0100010XXX 0100010XXX 32 110000h­117FFFh SA42 0 1 0100011XXX 0100011XXX 32 118000h­11FFFFh SA43 0 1 0100100XXX 0100100XXX 32 120000h­127FFFh SA44 0 1 0100101XXX 0100101XXX 32 128000h­12FFFFh SA45 0 1 0100110XXX 0100110XXX 32 130000h­137FFFh SA46 0 1 0100111XXX 0100111XXX 32 138000h­13FFFFh SA47 0 1 0101000XXX 0101000XXX 32 140000h­147FFFh SA48 0 1 0101001XXX 0101001XXX 32 148000h­14FFFFh SA49 0 1 0101010XXX 0101010XXX 32 150000h­157FFFh SA50 0 1 0101011XXX 0101011XXX 32 158000h­15FFFFh SA51 0 1 0101100XXX 0101100XXX 32 160000h­167FFFh SA52 0 1 0101101XXX 0101101XXX 32 168000h­16FFFFh SA53 0 1 0101110XXX 0101110XXX 32 170000h­177FFFh SA54 0 1 0101111XXX 0101111XXX 32 178000h­17FFFFh SA55 0 1 0110000XXX 0110000XXX 32 180000h­187FFFh SA56 0 1 0110001XXX 0110001XXX 32 188000h­18FFFFh SA57 0 1 0110010XXX 0110010XXX 32 190000h­197FFFh SA58 0 1 0110011XXX 0110011XXX 32 198000h­19FFFFh SA59 0 1 0110100XXX 0110100XXX 32 1A0000h­1A7FFFh SA60 0 1 0110101XXX 0110101XXX 32 1A8000h­1AFFFFh SA61 0 1 0110110XXX 0110110XXX 32 1B0000h­1B7FFFh SA62 0 1 0110111XXX 0110111XXX 32 1B8000h­1BFFFFh SA63 0 1 0111000XXX 0111000XXX 32 1C0000h­1C7FFFh SA64 0 1 0111001XXX 0111001XXX 32 1C8000h­1CFFFFh SA65 0 1 0111010XXX 0111010XXX 32 1D0000h­1D7FFFh SA66 0 1 0111011XXX 0111011XXX 32 1D8000h­1DFFFFh SA67 0 1 0111100XXX 0111100XXX 32 1E0000h­1E7FFFh SA68 0 1 0111101XXX 0111101XXX 32 1E8000h­1EFFFFh SA69 0 1 0111110XXX 0111110XXX 32 1F0000h­1F7FFFh SA70 0 1 0111111XXX 0111111XXX 32 1F8000h­1FFFFFh SA71 0 1 1000000XXX 1000000XXX 32 200000h­207FFFh SA72 0 1 1000001XXX 1000001XXX 32 208000h­20FFFFh SA73 0 1 1000010XXX 1000010XXX 32 210000h­217FFFh SA74 0 1 1000011XXX 1000011XXX 32 218000h­21FFFFh SA75 0 1 1000100XXX 1000100XXX 32 220000h­227FFFh SA76 0 1 1000101XXX 1000101XXX 32 228000h­22FFFFh SA77 0 1 1000110XXX 1000110XXX 32 230000h­237FFFh SA78 26 1 SA41 Bank 0 SA40 Bank B SA39 0 1 1000111XXX 1000111XXX 32 238000h­23FFFFh CE#f2 Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) Sector CE#f1 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture (Continued) 1 1001000XXX 1001000XXX 32 240000h­247FFFh 0 1 1001001XXX 1001001XXX 32 248000h­24FFFFh SA81 0 1 1001010XXX 1001010XXX 32 250000h­257FFFh SA82 0 1 1001011XXX 1001011XXX 32 258000h­25FFFFh SA83 0 1 1001100XXX 1001100XXX 32 260000h­267FFFh SA84 0 1 1001101XXX 1001101XXX 32 268000h­26FFFFh SA85 0 1 1001110XXX 1001110XXX 32 270000h­277FFFh SA86 0 1 1001111XXX 1001111XXX 32 278000h­27FFFFh SA87 0 1 1010000XXX 1010000XXX 32 280000h­287FFFh SA88 0 1 1010001XXX 1010001XXX 32 288000h­28FFFFh SA89 0 1 1010010XXX 1010010XXX 32 290000h­297FFFh SA90 0 1 1010011XXX 1010011XXX 32 298000h­29FFFFh SA91 0 1 1010100XXX 1010100XXX 32 2A0000h­2A7FFFh SA92 0 1 1010101XXX 1010101XXX 32 2A8000h­2AFFFFh SA93 0 1 1010110XXX 1010110XXX 32 2B0000h­2B7FFFh SA94 0 1 1010111XXX 1010111XXX 32 2B8000h­2BFFFFh SA95 0 1 1011000XXX 1011000XXX 32 2C0000h­2C7FFFh SA96 0 1 1011001XXX 1011001XXX 32 2C8000h­2CFFFFh SA97 0 1 1011010XXX 1011010XXX 32 2D0000h­2D7FFFh SA98 0 1 1011011XXX 1011011XXX 32 2D8000h­2DFFFFh SA99 0 1 1011100XXX 1011100XXX 32 2E0000h­2E7FFFh SA100 SA100 0 1 1011101XXX 1011101XXX 32 2E8000h­2EFFFFh SA101 SA101 0 1 1011110XXX 1011110XXX 32 2F0000h­2F7FFFh SA102 SA102 0 1 1011111XXX 1011111XXX 32 2F8000h­2FFFFFh SA103 SA103 0 1 1100000XXX 1100000XXX 32 300000h­307FFFh SA104 SA104 0 1 1100001XXX 1100001XXX 32 308000h­30FFFFh SA105 SA105 0 1 1100010XXX 1100010XXX 32 310000h­317FFFh SA106 SA106 0 1 1100011XXX 1100011XXX 32 318000h­31FFFFh SA107 SA107 0 1 1100100XXX 1100100XXX 32 320000h­327FFFh SA108 SA108 0 1 1100101XXX 1100101XXX 32 328000h­32FFFFh SA109 SA109 0 1 1100110XXX 1100110XXX 32 330000h­337FFFh SA110 SA110 0 1 1100111XXX 1100111XXX 32 338000h­33FFFFh SA111 SA111 0 1 1101000XXX 1101000XXX 32 340000h­347FFFh SA112 SA112 0 1 1101001XXX 1101001XXX 32 348000h­34FFFFh SA113 SA113 0 1 1101010XXX 1101010XXX 32 350000h­357FFFh SA114 SA114 0 1 1101011XXX 1101011XXX 32 358000h­35FFFFh SA115 SA115 0 1 1101100XXX 1101100XXX 32 360000h­367FFFh SA116 SA116 0 1 1101101XXX 1101101XXX 32 368000h­36FFFFh SA117 SA117 0 1 1101110XXX 1101110XXX 32 370000h­377FFFh SA118 SA118 Bank 0 SA80 Bank B SA79 0 1 1101111XXX 1101111XXX 32 378000h­37FFFFh CE#f2 Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) Sector December 16, 2003 CE#f1 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 27 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture (Continued) 1 1110000XXX 1110000XXX 32 380000h­387FFFh 0 1 1110001XXX 1110001XXX 32 388000h­38FFFFh SA121 SA121 0 1 1110010XXX 1110010XXX 32 390000h­397FFFh SA122 SA122 0 1 1110011XXX 1110011XXX 32 398000h­39FFFFh SA123 SA123 0 1 1110100XXX 1110100XXX 32 3A0000h­3A7FFFh SA124 SA124 0 1 1110101XXX 1110101XXX 32 3A8000h­3AFFFFh SA125 SA125 0 1 1110110XXX 1110110XXX 32 3B0000h­3B7FFFh SA126 SA126 0 1 1110111XXX 1110111XXX 32 3B8000h­3BFFFFh SA127 SA127 0 1 1111000XXX 1111000XXX 32 3C0000h­3C7FFFh SA128 SA128 0 1 1111001XXX 1111001XXX 32 3C8000h­3CFFFFh SA129 SA129 0 1 1111010XXX 1111010XXX 32 3D0000h­3D7FFFh SA130 SA130 0 1 1111011XXX 1111011XXX 32 3D8000h­3DFFFFh SA131 SA131 0 1 1111100XXX 1111100XXX 32 3E0000h­3E7FFFh SA132 SA132 0 1 1111101XXX 1111101XXX 32 3E8000h­3EFFFFh SA133 SA133 0 1 1111110XXX 1111110XXX 32 3F0000h­3F7FFFh SA134 SA134 28 0 SA120 SA120 Bank B SA119 SA119 0 1 1111111XXX 1111111XXX 32 3F8000h­3FFFFFh Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture (Continued) 0 0000000XXX 0000000XXX 32 000000h­007FFFh 1 0 0000001XXX 0000001XXX 32 008000h­00FFFFh SA137 SA137 1 0 0000010XXX 0000010XXX 32 010000h­017FFFh SA138 SA138 1 0 0000011XXX 0000011XXX 32 018000h­01FFFFh SA139 SA139 1 0 0000100XXX 0000100XXX 32 020000h­027FFFh SA140 SA140 1 0 0000101XXX 0000101XXX 32 028000h­02FFFFh SA141 SA141 1 0 0000110XXX 0000110XXX 32 030000h­037FFFh SA142 SA142 1 0 0000111XXX 0000111XXX 32 038000h­03FFFFh SA143 SA143 1 0 0001000XXX 0001000XXX 32 040000h­047FFFh SA144 SA144 1 0 0001001XXX 0001001XXX 32 048000h­04FFFFh SA145 SA145 1 0 0001010XXX 0001010XXX 32 050000h­057FFFh SA146 SA146 1 0 0001011XXX 0001011XXX 32 058000h­05FFFFh SA147 SA147 1 0 0001100XXX 0001100XXX 32 060000h­067FFFh SA148 SA148 1 0 0001101XXX 0001101XXX 32 068000h­06FFFFh SA149 SA149 1 0 0001110XXX 0001110XXX 32 070000h­077FFFh SA150 SA150 1 0 0001111XXX 0001111XXX 32 078000h­07FFFFh SA151 SA151 1 0 0010000XXX 0010000XXX 32 080000h­087FFFh SA152 SA152 1 0 0010001XXX 0010001XXX 32 088000h­08FFFFh SA153 SA153 1 0 0010010XXX 0010010XXX 32 090000h­097FFFh SA154 SA154 1 0 0010011XXX 0010011XXX 32 098000h­09FFFFh SA155 SA155 1 0 0010100XXX 0010100XXX 32 0A0000h­0A7FFFh SA156 SA156 1 0 0010101XXX 0010101XXX 32 0A8000h­0AFFFFh SA157 SA157 1 0 0010110XXX 0010110XXX 32 0B0000h­0B7FFFh SA158 SA158 Bank 1 SA136 SA136 Bank C SA135 SA135 1 0 0010111XXX 0010111XXX 32 0B8000h­0BFFFFh Sector CE#f1 CE#f2 Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) December 16, 2003 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 29 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture (Continued) 0011000XXX 0011000XXX 32 0C0000h­0C7FFFh 1 0 0011001XXX 0011001XXX 32 0C8000h­0CFFFFh 1 0 0011010XXX 0011010XXX 32 0D0000h­0D7FFFh SA162 SA162 1 0 0011011XXX 0011011XXX 32 0D8000h­0DFFFFh SA163 SA163 1 0 0011100XXX 0011100XXX 32 0E0000h­0E7FFFh SA164 SA164 1 0 0011101XXX 0011101XXX 32 0E8000h­0EFFFFh SA165 SA165 1 0 0011110XXX 0011110XXX 32 0F0000h­0F7FFFh SA166 SA166 1 0 0011111XXX 0011111XXX 32 0F8000h­0FFFFFh SA167 SA167 1 0 0100000XXX 0100000XXX 32 100000h­107FFFh SA168 SA168 1 0 0100001XXX 0100001XXX 32 108000h­10FFFFh SA169 SA169 1 0 0100010XXX 0100010XXX 32 110000h­117FFFh SA170 SA170 1 0 0100011XXX 0100011XXX 32 118000h­11FFFFh SA171 SA171 1 0 0100100XXX 0100100XXX 32 120000h­127FFFh SA172 SA172 1 0 0100101XXX 0100101XXX 32 128000h­12FFFFh SA173 SA173 1 0 0100110XXX 0100110XXX 32 130000h­137FFFh SA174 SA174 1 0 0100111XXX 0100111XXX 32 138000h­13FFFFh SA175 SA175 1 0 0101000XXX 0101000XXX 32 140000h­147FFFh SA176 SA176 1 0 0101001XXX 0101001XXX 32 148000h­14FFFFh SA177 SA177 1 0 0101010XXX 0101010XXX 32 150000h­157FFFh SA178 SA178 1 0 0101011XXX 0101011XXX 32 158000h­15FFFFh SA179 SA179 1 0 0101100XXX 0101100XXX 32 160000h­167FFFh SA180 SA180 1 0 0101101XXX 0101101XXX 32 168000h­16FFFFh SA181 SA181 1 0 0101110XXX 0101110XXX 32 170000h­177FFFh SA182 SA182 1 0 0101111XXX 0101111XXX 32 178000h­17FFFFh SA183 SA183 1 0 0110000XXX 0110000XXX 32 180000h­187FFFh SA184 SA184 1 0 0110001XXX 0110001XXX 32 188000h­18FFFFh SA185 SA185 1 0 0110010XXX 0110010XXX 32 190000h­197FFFh SA186 SA186 1 0 0110011XXX 0110011XXX 32 198000h­19FFFFh SA187 SA187 1 0 0110100XXX 0110100XXX 32 1A0000h­1A7FFFh SA188 SA188 1 0 0110101XXX 0110101XXX 32 1A8000h­1AFFFFh SA189 SA189 1 0 0110110XXX 0110110XXX 32 1B0000h­1B7FFFh SA190 SA190 1 0 0110111XXX 0110111XXX 32 1B8000h­1BFFFFh SA191 SA191 1 0 0111000XXX 0111000XXX 32 1C0000h­1C7FFFh SA192 SA192 1 0 0111001XXX 0111001XXX 32 1C8000h­1CFFFFh SA193 SA193 1 0 0111010XXX 0111010XXX 32 1D0000h­1D7FFFh SA194 SA194 1 0 0111011XXX 0111011XXX 32 1D8000h­1DFFFFh SA195 SA195 1 0 0111100XXX 0111100XXX 32 1E0000h­1E7FFFh SA196 SA196 1 0 0111101XXX 0111101XXX 32 1E8000h­1EFFFFh SA197 SA197 1 0 0111110XXX 0111110XXX 32 1F0000h­1F7FFFh SA198 SA198 30 0 SA161 SA161 Bank 1 SA160 SA160 Bank C (continued) SA159 SA159 1 0 0111111XXX 0111111XXX 32 1F8000h­1FFFFFh CE#f2 Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) Sector CE#f1 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture (Continued) 0 1000000XXX 1000000XXX 32 200000h­207FFFh 1 0 1000001XXX 1000001XXX 32 208000h­20FFFFh SA201 SA201 1 0 1000010XXX 1000010XXX 32 210000h­217FFFh SA202 SA202 1 0 1000011XXX 1000011XXX 32 218000h­21FFFFh SA203 SA203 1 0 1000100XXX 1000100XXX 32 220000h­227FFFh SA204 SA204 1 0 1000101XXX 1000101XXX 32 228000h­22FFFFh SA205 SA205 1 0 1000110XXX 1000110XXX 32 230000h­237FFFh SA206 SA206 1 0 1000111XXX 1000111XXX 32 238000h­23FFFFh SA207 SA207 1 0 1001000XXX 1001000XXX 32 240000h­247FFFh SA208 SA208 1 0 1001001XXX 1001001XXX 32 248000h­24FFFFh SA209 SA209 1 0 1001010XXX 1001010XXX 32 250000h­257FFFh SA210 SA210 1 0 1001011XXX 1001011XXX 32 258000h­25FFFFh SA211 SA211 1 0 1001100XXX 1001100XXX 32 260000h­267FFFh SA212 SA212 1 0 1001101XXX 1001101XXX 32 268000h­26FFFFh SA213 SA213 1 0 1001110XXX 1001110XXX 32 270000h­277FFFh SA214 SA214 1 0 1001111XXX 1001111XXX 32 278000h­27FFFFh SA215 SA215 1 0 1010000XXX 1010000XXX 32 280000h­287FFFh SA216 SA216 1 0 1010001XXX 1010001XXX 32 288000h­28FFFFh SA217 SA217 1 0 1010010XXX 1010010XXX 32 290000h­297FFFh SA218 SA218 1 0 1010011XXX 1010011XXX 32 298000h­29FFFFh SA219 SA219 1 0 1010100XXX 1010100XXX 32 2A0000h­2A7FFFh SA220 SA220 1 0 1010101XXX 1010101XXX 32 2A8000h­2AFFFFh SA221 SA221 1 0 1010110XXX 1010110XXX 32 2B0000h­2B7FFFh SA222 SA222 1 0 1010111XXX 1010111XXX 32 2B8000h­2BFFFFh SA223 SA223 1 0 1011000XXX 1011000XXX 32 2C0000h­2C7FFFh SA224 SA224 1 0 1011001XXX 1011001XXX 32 2C8000h­2CFFFFh SA225 SA225 1 0 1011010XXX 1011010XXX 32 2D0000h­2D7FFFh SA226 SA226 1 0 1011011XXX 1011011XXX 32 2D8000h­2DFFFFh SA227 SA227 1 0 1011100XXX 1011100XXX 32 2E0000h­2E7FFFh SA228 SA228 1 0 1011101XXX 1011101XXX 32 2E8000h­2EFFFFh SA229 SA229 1 0 1011110XXX 1011110XXX 32 2F0000h­2F7FFFh SA230 SA230 Bank 1 SA200 SA200 Bank C (continued) SA199 SA199 1 0 1011111XXX 1011111XXX 32 2F8000h­2FFFFFh CE#f2 Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) Sector December 16, 2003 CE#f1 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 31 A D V A N C E Table 6. I N F O R M A T I O N Am29PDL129H Am29PDL129H Sector Architecture (Continued) 1 0 1100000XXX 1100000XXX 32 300000h­307FFFh SA232 SA232 1 0 1100001XXX 1100001XXX 32 308000h­30FFFFh SA233 SA233 1 0 1100010XXX 1100010XXX 32 310000h­317FFFh SA234 SA234 1 0 1100011XXX 1100011XXX 32 318000h­31FFFFh SA235 SA235 1 0 1100100XXX 1100100XXX 32 320000h­327FFFh SA236 SA236 1 0 1100101XXX 1100101XXX 32 328000h­32FFFFh SA237 SA237 1 0 1100110XXX 1100110XXX 32 330000h­337FFFh SA238 SA238 1 0 1100111XXX 1100111XXX 32 338000h­33FFFFh SA239 SA239 1 0 1101000XXX 1101000XXX 32 340000h­347FFFh SA240 SA240 1 0 1101001XXX 1101001XXX 32 348000h­34FFFFh SA241 SA241 1 0 1101010XXX 1101010XXX 32 350000h­357FFFh SA242 SA242 1 0 1101011XXX 1101011XXX 32 358000h­35FFFFh SA243 SA243 1 0 1101100XXX 1101100XXX 32 360000h­367FFFh SA244 SA244 1 0 1101101XXX 1101101XXX 32 368000h­36FFFFh SA245 SA245 1 0 1101110XXX 1101110XXX 32 370000h­377FFFh SA246 SA246 1 0 1101111XXX 1101111XXX 32 378000h­37FFFFh SA247 SA247 1 0 1110000XXX 1110000XXX 32 380000h­387FFFh SA248 SA248 1 0 1110001XXX 1110001XXX 32 388000h­38FFFFh SA249 SA249 1 0 1110010XXX 1110010XXX 32 390000h­397FFFh SA250 SA250 1 0 1110011XXX 1110011XXX 32 398000h­39FFFFh SA251 SA251 1 0 1110100XXX 1110100XXX 32 3A0000h­3A7FFFh SA252 SA252 1 0 1110101XXX 1110101XXX 32 3A8000h­3AFFFFh SA253 SA253 1 0 1110110XXX 1110110XXX 32 3B0000h­3B7FFFh SA254 SA254 1 0 1110111XXX 1110111XXX 32 3B8000h­3BFFFFh SA255 SA255 1 0 1111000XXX 1111000XXX 32 3C0000h­3C7FFFh SA256 SA256 1 0 1111001XXX 1111001XXX 32 3C8000h­3CFFFFh SA257 SA257 1 0 1111010XXX 1111010XXX 32 3D0000h­3D7FFFh SA258 SA258 1 0 1111011XXX 1111011XXX 32 3D8000h­3DFFFFh SA259 SA259 1 0 1111100XXX 1111100XXX 32 3E0000h­3E7FFFh SA260 SA260 1 0 1111101XXX 1111101XXX 32 3E8000h­3EFFFFh SA261 SA261 1 0 1111110XXX 1111110XXX 32 3F0000h­3F7FFFh SA262 SA262 1 0 1111111000 32 3F8000h­3F8FFFh SA263 SA263 1 0 1111111001 4 3F9000h­3F9FFFh SA264 SA264 1 0 1111111010 4 3FA000h­3FAFFFh SA265 SA265 1 0 1111111011 4 3FB000h­3FBFFFh SA266 SA266 1 0 1111111100 4 3FC000h­3FCFFFh SA267 SA267 1 0 1111111101 4 3FD000h­3FDFFFh SA268 SA268 1 0 1111111110 4 3FE000h­3FEFFFh SA269 SA269 Bank D SA231 SA231 1 0 1111111111 4 3FF000h­3FFFFFh Table 7. SecSiTM Sector Addresses SecSi Sector Area 32 Sector Size Address Range Factory-Locked Area 64 words SecSi Sector Area Sector Size Address Range Customer-Lockable Area 64 words 000040h-00007Fh 000000h-00003Fh Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N Table 8. Am29PDL127H Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A22-A12 A22-A12 SA135 SA135­SA138 SA138 100000XXXXX 100000XXXXX 128 (4x32) Kwords SA139 SA139­SA142 SA142 100001XXXXX 100001XXXXX 128 (4x32) Kwords Sector/ Sector Block Size SA143 SA143­SA146 SA146 100010XXXXX 100010XXXXX 128 (4x32) Kwords SA147 SA147­SA150 SA150 100011XXXXX 100011XXXXX 128 (4x32) Kwords SA0 00000000000 4 Kwords SA151 SA151­SA154 SA154 100100XXXXX 100100XXXXX 128 (4x32) Kwords SA1 00000000001 4 Kwords SA155 SA155­SA158 SA158 100101XXXXX 100101XXXXX 128 (4x32) Kwords SA2 00000000010 4 Kwords SA159 SA159­SA162 SA162 100110XXXXX 100110XXXXX 128 (4x32) Kwords SA3 00000000011 4 Kwords SA163 SA163­SA166 SA166 100111XXXXX 100111XXXXX 128 (4x32) Kwords SA4 00000000100 4 Kwords SA167 SA167­SA170 SA170 101000XXXXX 101000XXXXX 128 (4x32) Kwords SA5 00000000101 4 Kwords SA171 SA171­SA174 SA174 101001XXXXX 101001XXXXX 128 (4x32) Kwords SA6 00000000110 4 Kwords SA175 SA175­SA178 SA178 101010XXXXX 101010XXXXX 128 (4x32) Kwords SA7 00000000111 4 Kwords SA179 SA179­SA182 SA182 101011XXXXX 101011XXXXX 128 (4x32) Kwords SA183 SA183­SA186 SA186 101100XXXXX 101100XXXXX 128 (4x32) Kwords SA8­SA10 00000001XXX 00000001XXX 00000010XXX 00000010XXX 00000011XXX 00000011XXX 96 (3x32) Kwords SA187 SA187­SA190 SA190 101101XXXXX 101101XXXXX 128 (4x32) Kwords SA11­SA14 000001XXXXX 000001XXXXX 128 (4x32) Kwords SA191 SA191­SA194 SA194 101110XXXXX 101110XXXXX 128 (4x32) Kwords SA15­SA18 000010XXXXX 000010XXXXX 128 (4x32) Kwords SA195 SA195­SA198 SA198 101111XXXXX 101111XXXXX 128 (4x32) Kwords SA19­SA22 000011XXXXX 000011XXXXX 128 (4x32) Kwords SA199 SA199­SA202 SA202 110000XXXXX 110000XXXXX 128 (4x32) Kwords SA23­SA26 000100XXXXX 000100XXXXX 128 (4x32) Kwords SA203 SA203­SA206 SA206 110001XXXXX 110001XXXXX 128 (4x32) Kwords SA27­SA30 000101XXXXX 000101XXXXX 128 (4x32) Kwords SA207 SA207­SA210 SA210 110010XXXXX 110010XXXXX 128 (4x32) Kwords SA31­SA34 000110XXXXX 000110XXXXX 128 (4x32) Kwords SA211 SA211­SA214 SA214 110011XXXXX 110011XXXXX 128 (4x32) Kwords SA35­SA38 000111XXXXX 000111XXXXX 128 (4x32) Kwords SA215 SA215­SA218 SA218 110100XXXXX 110100XXXXX 128 (4x32) Kwords SA39­SA42 001000XXXXX 001000XXXXX 128 (4x32) Kwords SA219 SA219­SA222 SA222 110101XXXXX 110101XXXXX 128 (4x32) Kwords SA43­SA46 001001XXXXX 001001XXXXX 128 (4x32) Kwords SA223 SA223­SA226 SA226 110110XXXXX 110110XXXXX 128 (4x32) Kwords SA47­SA50 001010XXXXX 001010XXXXX 128 (4x32) Kwords SA227 SA227­SA230 SA230 110111XXXXX 110111XXXXX 128 (4x32) Kwords SA51­SA54 001011XXXXX 001011XXXXX 128 (4x32) Kwords SA231 SA231­SA234 SA234 111000XXXXX 111000XXXXX 128 (4x32) Kwords SA55­SA58 001100XXXXX 001100XXXXX 128 (4x32) Kwords SA235 SA235­SA238 SA238 111001XXXXX 111001XXXXX 128 (4x32) Kwords SA59­SA62 001101XXXXX 001101XXXXX 128 (4x32) Kwords SA239 SA239­SA242 SA242 111010XXXXX 111010XXXXX 128 (4x32) Kwords SA63­SA66 001110XXXXX 001110XXXXX 128 (4x32) Kwords SA243 SA243­SA246 SA246 111011XXXXX 111011XXXXX 128 (4x32) Kwords SA67­SA70 001111XXXXX 001111XXXXX 128 (4x32) Kwords SA247 SA247­SA250 SA250 111100XXXXX 111100XXXXX 128 (4x32) Kwords SA71­SA74 010000XXXXX 010000XXXXX 128 (4x32) Kwords SA251 SA251­SA254 SA254 111101XXXXX 111101XXXXX 128 (4x32) Kwords SA75­SA78 010001XXXXX 010001XXXXX 128 (4x32) Kwords SA255 SA255­SA258 SA258 111110XXXXX 111110XXXXX 128 (4x32) Kwords SA79­SA82 010010XXXXX 010010XXXXX 128 (4x32) Kwords SA259 SA259­SA261 SA261 96 (3x32) Kwords SA83­SA86 010011XXXXX 010011XXXXX 128 (4x32) Kwords 11111100XXX 11111100XXX 11111101XXX 11111101XXX 11111110XXX 11111110XXX SA87­SA90 010100XXXXX 010100XXXXX 128 (4x32) Kwords SA262 SA262 11111111000 4 Kwords SA91­SA94 010101XXXXX 010101XXXXX 128 (4x32) Kwords SA263 SA263 11111111001 4 Kwords SA95­SA98 010110XXXXX 010110XXXXX 128 (4x32) Kwords SA264 SA264 11111111010 4 Kwords SA99­SA102 SA102 010111XXXXX 010111XXXXX 128 (4x32) Kwords SA265 SA265 11111111011 4 Kwords SA103 SA103­SA106 SA106 011000XXXXX 011000XXXXX 128 (4x32) Kwords SA266 SA266 11111111100 4 Kwords SA107 SA107­SA110 SA110 011001XXXXX 011001XXXXX 128 (4x32) Kwords SA267 SA267 11111111101 4 Kwords SA111 SA111­SA114 SA114 011010XXXXX 011010XXXXX 128 (4x32) Kwords SA268 SA268 11111111110 4 Kwords SA115 SA115­SA118 SA118 011011XXXXX 011011XXXXX 128 (4x32) Kwords SA269 SA269 11111111111 4 Kwords SA119 SA119­SA122 SA122 011100XXXXX 011100XXXXX 128 (4x32) Kwords SA123 SA123­SA126 SA126 011101XXXXX 011101XXXXX 128 (4x32) Kwords SA127 SA127­SA130 SA130 011110XXXXX 011110XXXXX 128 (4x32) Kwords Sector A22-A12 A22-A12 Sector/ Sector Block Size SA131 SA131­SA134 SA134 011111XXXXX 011111XXXXX 128 (4x32) Kwords December 16, 2003 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 33 A D V A N C E I N F O R M A T I O N Sector Sector CE#f1 CE#f2 A21­A12 Sector/ Sector Block Size SA0 0 1 0000000000 4 Kwords SA1 0 1 0000000001 4 Kwords SA2 0 1 0000000010 4 Kwords SA3 0 1 0000000011 4 Kwords SA4 0 1 0000000100 4 Kwords SA5 0 1 0000000101 4 Kwords SA6 0 1 0000000110 4 Kwords SA7 0 1 0000000111 4 Kwords SA8­SA10 0 1 0000001XXX 0000001XXX 0000010XXX 0000010XXX 0000011XXX 0000011XXX 96 (3x32) Kwords CE#f2 A21­A12 Sector/ Sector Block Size SA127 SA127­SA130 SA130 0 1 11110XXXXX 11110XXXXX 128 (4x32) Kwords SA131 SA131­SA134 SA134 0 1 11111XXXXX 11111XXXXX 128 (4x32) Kwords SA135 SA135­SA138 SA138 1 0 00000XXXXX 00000XXXXX 128 (4x32) Kwords SA139 SA139­SA142 SA142 1 0 00001XXXXX 00001XXXXX 128 (4x32) Kwords SA143 SA143­SA146 SA146 1 0 00010XXXXX 00010XXXXX 128 (4x32) Kwords SA147 SA147­SA150 SA150 1 0 00011XXXXX 00011XXXXX 128 (4x32) Kwords SA151 SA151­SA154 SA154 1 0 00100XXXXX 00100XXXXX 128 (4x32) Kwords SA155 SA155­SA158 SA158 1 0 00101XXXXX 00101XXXXX 128 (4x32) Kwords SA159 SA159­SA162 SA162 1 0 00110XXXXX 00110XXXXX 128 (4x32) Kwords SA163 SA163­SA166 SA166 1 0 00111XXXXX 00111XXXXX 128 (4x32) Kwords SA167 SA167­SA170 SA170 1 0 01000XXXXX 01000XXXXX 128 (4x32) Kwords SA171 SA171­SA174 SA174 1 0 01001XXXXX 01001XXXXX 128 (4x32) Kwords SA175 SA175­SA178 SA178 1 0 01010XXXXX 01010XXXXX 128 (4x32) Kwords SA179 SA179­SA182 SA182 Table 9. Am29PDL129H Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE#f1 1 0 01011XXXXX 01011XXXXX 128 (4x32) Kwords SA11­SA14 0 1 00001XXXXX 00001XXXXX 128 (4x32) Kwords SA183 SA183­SA186 SA186 1 0 01100XXXXX 01100XXXXX 128 (4x32) Kwords SA15­SA18 0 1 00010XXXXX 00010XXXXX 128 (4x32) Kwords SA187 SA187­SA190 SA190 1 0 01101XXXXX 01101XXXXX 128 (4x32) Kwords SA19­SA22 0 1 00011XXXXX 00011XXXXX 128 (4x32) Kwords SA191 SA191­SA194 SA194 1 0 01110XXXXX 01110XXXXX 128 (4x32) Kwords SA23­SA26 0 1 00100XXXXX 00100XXXXX 128 (4x32) Kwords SA195 SA195­SA198 SA198 1 0 01111XXXXX 01111XXXXX 128 (4x32) Kwords SA27­SA30 0 1 00101XXXXX 00101XXXXX 128 (4x32) Kwords SA199 SA199­SA202 SA202 1 0 10000XXXXX 10000XXXXX 128 (4x32) Kwords SA31­SA34 0 1 00110XXXXX 00110XXXXX 128 (4x32) Kwords SA203 SA203­SA206 SA206 1 0 10001XXXXX 10001XXXXX 128 (4x32) Kwords SA35­SA38 0 1 00111XXXXX 00111XXXXX 128 (4x32) Kwords SA207 SA207­SA210 SA210 1 0 10010XXXXX 10010XXXXX 128 (4x32) Kwords SA39­SA42 0 1 01000XXXXX 01000XXXXX 128 (4x32) Kwords SA211 SA211­SA214 SA214 1 0 10011XXXXX 10011XXXXX 128 (4x32) Kwords SA43­SA46 0 1 01001XXXXX 01001XXXXX 128 (4x32) Kwords SA215 SA215­SA218 SA218 1 0 10100XXXXX 10100XXXXX 128 (4x32) Kwords SA47­SA50 0 1 01010XXXXX 01010XXXXX 128 (4x32) Kwords SA219 SA219­SA222 SA222 1 0 10101XXXXX 10101XXXXX 128 (4x32) Kwords SA51­SA54 0 1 01011XXXXX 01011XXXXX 128 (4x32) Kwords SA223 SA223­SA226 SA226 1 0 10110XXXXX 10110XXXXX 128 (4x32) Kwords SA55­SA58 0 1 01100XXXXX 01100XXXXX 128 (4x32) Kwords SA227 SA227­SA230 SA230 1 0 10111XXXXX 10111XXXXX 128 (4x32) Kwords SA59­SA62 0 1 01101XXXXX 01101XXXXX 128 (4x32) Kwords SA231 SA231­SA234 SA234 1 0 11000XXXXX 11000XXXXX 128 (4x32) Kwords SA63­SA66 0 1 01110XXXXX 01110XXXXX 128 (4x32) Kwords SA235 SA235­SA238 SA238 1 0 11001XXXXX 11001XXXXX 128 (4x32) Kwords SA67­SA70 0 1 01111XXXXX 01111XXXXX 128 (4x32) Kwords SA239 SA239­SA242 SA242 1 0 11010XXXXX 11010XXXXX 128 (4x32) Kwords SA71­SA74 0 1 10000XXXXX 10000XXXXX 128 (4x32) Kwords SA243 SA243­SA246 SA246 1 0 11011XXXXX 11011XXXXX 128 (4x32) Kwords SA75­SA78 0 1 10001XXXXX 10001XXXXX 128 (4x32) Kwords SA247 SA247­SA250 SA250 1 0 11100XXXXX 11100XXXXX 128 (4x32) Kwords SA79­SA82 0 1 10010XXXXX 10010XXXXX 128 (4x32) Kwords SA251 SA251­SA254 SA254 1 0 11101XXXXX 11101XXXXX 128 (4x32) Kwords SA83­SA86 0 1 10011XXXXX 10011XXXXX 128 (4x32) Kwords SA255 SA255­SA258 SA258 1 0 11110XXXXX 11110XXXXX 128 (4x32) Kwords SA87­SA90 0 1 10100XXXXX 10100XXXXX 128 (4x32) Kwords SA91­SA94 0 1 10101XXXXX 10101XXXXX 128 (4x32) Kwords 96 (3x32) Kwords SA95­SA98 0 1 10110XXXXX 10110XXXXX 128 (4x32) Kwords SA99­SA102 SA102 0 1 10111XXXXX 10111XXXXX 128 (4x32) Kwords SA103 SA103­SA106 SA106 0 1 11000XXXXX 11000XXXXX 128 (4x32) Kwords SA107 SA107­SA110 SA110 0 1 11001XXXXX 11001XXXXX 128 (4x32) Kwords SA111 SA111­SA114 SA114 0 1 11010XXXXX 11010XXXXX 128 (4x32) Kwords SA115 SA115­SA118 SA118 0 1 11011XXXXX 11011XXXXX 128 (4x32) Kwords SA119 SA119­SA122 SA122 0 1 11100XXXXX 11100XXXXX 128 (4x32) Kwords SA123 SA123­SA126 SA126 0 1 11101XXXXX 11101XXXXX 128 (4x32) Kwords 34 SA259 SA259­SA261 SA261 1 0 1111100XXX 1111100XXX 1111101XXX 1111101XXX 1111110XXX 1111110XXX SA262 SA262 1 0 1111111000 4 Kwords SA263 SA263 1 0 1111111001 4 Kwords SA264 SA264 1 0 1111111010 4 Kwords SA265 SA265 1 0 1111111011 4 Kwords SA266 SA266 1 0 1111111100 4 Kwords SA267 SA267 1 0 1111111101 4 Kwords SA268 SA268 1 0 1111111110 4 Kwords SA269 SA269 1 0 1111111111 4 Kwords Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N SECTOR PROTECTION The Am29PDL127H/Am29PDL129H Am29PDL127H/Am29PDL129H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Dynamically Locked-The sector is protected and can be changed by a simple command. Persistent Sector Protection To achieve these states, three types of "bits" are used: A command sector protection method that replaces the old 12 V controlled protection method. Persistent Protection Bit (PPB) Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. The WP# Hardware Protection feature is always available, regardless of which of the other two methods are chosen. Selecting a Sector Protection Mode The device defaults to the Persistent Sector Protection mode. However, to prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode, it is recommended that either of two one-time programmable non-volatile bits that permanently define which sector protection method be set before the device is first programmed. The Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. The Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Command Sequence for details. Persistent Sector Protection The Persistent Sector Protection method replaces the 12 V controlled protection method in previous AMD flash devices. This new method provides three different sector protection states: Persistently Locked-The sector is protected and cannot be changed. December 16, 2003 Unlocked-The sector is unprotected and can be changed by a simple command. A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state ­ meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH 35 A D V A N C E I N F O R M A T I O N not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. Table 10. Sector Protection Schemes DYB PPB PPB Lock 0 0 0 Unprotected-PPB and DYB are changeable 0 0 1 Unprotected-PPB not changeable, DYB is changeable 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Sector State Protected-PPB and DYB are changeable Protected-PPB not changeable, DYB is changeable Table 10 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a g i v e n s e c t o r c a n b e ve r i f i e d b y w r i t i n g a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differ- 36 Am49PDL127BH/Am49PDL129BH Am49PDL127BH/Am49PDL129BH December 16, 2003 A D V A N C E I N F O R M A T I O N ences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objective