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PRELIMINARY Am29PDL129H Am29PDL129H 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control and Dual Chip Enable Inputs DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES 128 Mbit Page Mode device - Page size of 8 words: Fast page read access from random locations within the page Dual Chip Enable inputs - Two CE# inputs control selection of each half of the memory space Single power supply operation - Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications Simultaneous Read/Write Operation - Data can be continuously read from one bank while executing erase/program functions in another bank - Zero latency switching from write to read operations - 4 separate banks, with up to two simultaneous operations per device - Bank 1A: 48 Mbit (32 Kw x 96) - Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31) - Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) - Bank 2B: 48 Mbit (32 Kw x 96) Enhanced VersatileI/O SOFTWARE FEATURES Software command-set compatible with JEDEC 42.4 standard - Backward compatible with Am29F and Am29LV families CFI (Common Flash Interface) complaint - Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume - Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command FlexBank Architecture TM - 55 mA active read current - 25 mA program/erase current - 1 µA typical standby mode current (VIO) Control - Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin - VIO options at 1.8 V and 3 V I/O SecSiTM (Secured Silicon) Sector region - Up to 128 words accessible through a command sequence - Up to 64 factory-locked words - Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 0.13 µm process technology 20-year data retention at 125°C Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS High Performance - Page access times as fast as 20 ns - Random access times as fast as 55 ns Power consumption (typical values at 10 MHz) - Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) - Hardware method to reset the device to reading array data WP#/ACC (Write Protect/Acceleration) input - At VIL, hardware level protection for the first and last two 4K word sectors. - At VIH, allows removal of sector protection - At VHH, provides accelerated programming in a factory setting Persistent Sector Protection - A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector - Sectors can be locked and unlocked in-system at VCC level Password Sector Protection - A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password Package options - 80-ball Fine-pitch BGA - Multi Chip Packages (MCP) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26842 Rev: B Amendment/+1 Issue Date: August 8, 2003 P R E L I M I N A R Y GENERAL DESCRIPTION The Am29PDL129H Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The device is offered in a 64-ball Fortified BGA package, an 80-ball Fine-pitch BGA package, and various multi-chip packages. The word-wide data (x16) appears on DQ15-DQ0 DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 85 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE1#, CE2#), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit memory space. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Chip Enable Configuration CE1# Control CE2# Control Bank 1A 48 Mbit (32 Kw x 96) Bank 2A 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 1B 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 2B 48 Mbit (32 Kw x 96) Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V or 2.7 V to 3.3 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. 2 The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Simultaneous Operation Block Diagram . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10 Command Definitions. . . . . . . . . . . . . . . . . . . . . . 34 Reading Array Data . 34 Reset Command . 34 Autoselect Command Sequence . 34 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence . 34 Word Program Command Sequence . 35 Unlock Bypass Command Sequence . 35 Table 1. Am29PDL129H Am29PDL129H Device Bus Operations .10 Figure 3. Program Operation . 36 Requirements for Reading Array Data . 10 Random Read (Non-Page Read) . 10 Page Mode Read . 10 Chip Erase Command Sequence . 36 Sector Erase Command Sequence . 36 Table 2. Page Select .11 Erase Suspend/Erase Resume Commands . 37 Password Program Command . 37 Password Verify Command . 38 Password Protection Mode Locking Bit Program Command . 38 Persistent Sector Protection Mode Locking Bit Program Command . 38 SecSi Sector Protection Bit Program Command . 38 PPB Lock Bit Set Command . 38 DYB Write Command . 38 Password Unlock Command . 39 PPB Program Command . 39 All PPB Erase Command . 39 DYB Write Command . 39 PPB Lock Bit Set Command . 39 PPB Status Command . 39 PPB Lock Bit Status Command . 39 Sector Protection Status Command . 39 Simultaneous Operation . 11 Table 3. Bank Select .11 Writing Commands/Command Sequences . 11 Accelerated Program Operation . 11 Autoselect Functions . 11 Automatic Sleep Mode . 12 RESET#: Hardware Reset Pin . 12 Output Disable Mode . 12 Table 4. Am29PDL129H Am29PDL129H Sector Architecture .13 Table 5. SecSiTM Sector Addresses .21 Table 6. Autoselect Codes (High Voltage Method) .22 Table 7. Am29PDL129H Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE1# Control .23 Table 8. Am29PDL129H Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE2# Control .23 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 24 Persistent Sector Protection . 24 Persistent Protection Bit (PPB) . 24 Persistent Protection Bit Lock (PPB Lock) . 24 Dynamic Protection Bit (DYB) . 24 Table 9. Sector Protection Schemes .25 Persistent Sector Protection Mode Locking Bit . 25 Password Protection Mode . 25 Password and Password Mode Locking Bit . 26 64-bit Password . 26 Write Protect (WP#) . 26 Persistent Protection Bit Lock . 26 High Voltage Sector Protection . 27 Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms . 28 Temporary Sector Unprotect . 29 Figure 2. Temporary Sector Unprotect Operation. 29 SecSiTM (Secured Silicon) Sector Flash Memory Region . 29 Factory-Locked Area (64 words) . 29 Customer-Lockable Area (64 words) . 29 SecSi Sector Protection Bits . 30 Hardware Data Protection . 30 Low VCC Write Inhibit . 30 Write Pulse "Glitch" Protection . 30 Logical Inhibit . 30 Power-Up Write Inhibit . 30 Common Flash Memory Interface (CFI) . . . . . . . 30 August 8, 2003 Figure 4. Erase Operation. 37 Table 14. Memory Array Command Definitions . 40 Table 15. Sector Protection Command Definitions . 41 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 42 DQ7: Data# Polling . 42 Figure 5. Data# Polling Algorithm . 42 DQ6: Toggle Bit I . 43 Figure 6. Toggle Bit Algorithm. 43 DQ2: Toggle Bit II . 44 Reading Toggle Bits DQ6/DQ2 . 44 DQ5: Exceeded Timing Limits . 44 DQ3: Sector Erase Timer . 44 Table 16. Write Operation Status . 45 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 46 Figure 7. Maximum Negative Overshoot Waveform . 46 Figure 8. Maximum Positive Overshoot Waveform. 46 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 9. Test Setup, VIO = 2.7 ­ 3.6 V . 48 Figure 10. Input Waveforms and Measurement Levels . 48 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 49 CE1#/CE2# Timing . 49 Figure 11. Timing Diagram for Alternating Between CE1# and CE2# Control. 49 Read-Only Operations . 49 Figure 12. Read Operation Timings . 50 Figure 13. Page Read Operation Timings. 50 Hardware Reset (RESET#) . 51 Figure 14. Reset Timings . 51 Erase and Program Operations . 52 Am29PDL129H Am29PDL129H 3 P R E L I M I N A R Y Figure 15. Program Operation Timings. 53 Figure 16. Accelerated Program Timing Diagram. 53 Figure 17. Chip/Sector Erase Operation Timings . 54 Figure 18. Back-to-back Read/Write Cycle Timings . 55 Figure 19. Data# Polling Timings (During Embedded Algorithms). 55 Figure 20. Toggle Bit Timings (During Embedded Algorithms). 56 Figure 21. DQ2 vs. DQ6. 56 Temporary Sector Unprotect . 57 Figure 22. Temporary Sector Unprotect Timing Diagram . 57 Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram 58 Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings. 60 Erase And Programming Performance. . . . . . . . 61 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 61 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 61 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 VBB080-80-Ball Fine-pitch Ball Grid Array 11.5 x 9 mm package . 62 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63 Alternate CE# Controlled Erase and Program Operations . 59 4 Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y PRODUCT SELECTOR GUIDE Part Number Am29PDL129H Am29PDL129H VCC, VIO = 2.7­3.3 V Speed Option 53* VCC, VIO = 2.7­3.6 V 63 83 VCC = 2.7­3.6 V, VIO = 1.65­1.95 V 68 Max Access Time, ns (tACC) 88 55 65 65 85 20 25 30 30 Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) *Contact factory for availability BLOCK DIAGRAM DQ15­DQ0 RY/BY# (See Note) VCC VSS Sector Switches VIO RESET# Input/Output Buffers Erase Voltage Generator WE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE1# CE2# OE# Y-Decoder A21­A3 Y-Gating Timer Address Latch VCC Detector Data Latch X-Decoder Cell Matrix A2­A0 Note:RY/BY# is an open drain output. August 8, 2003 Am29PDL129H Am29PDL129H 5 P R E L I M I N A R Y SIMULTANEOUS OPERATION BLOCK DIAGRAM VCC VSS OE# CE1#=L CE2#=H Mux Bank 1A Bank 1B X-Decoder A21­A0 RESET# WE# CE1# CE2# WP#/ACC STATE CONTROL & COMMAND REGISTER Status DQ15­DQ0 Control Mux DQ15­DQ0 CE1#=H CE2#=L X-Decoder Bank 2A Address Bank 2A X-Decoder Bank 2B Address Y-gate A21­A0 DQ0­DQ15 A21­A0 DQ15­DQ0 Bank 1B Address DQ15­DQ0 RY/BY# DQ15­DQ0 A21­A0 X-Decoder Y-gate Bank 1A Address A21­A0 Bank 2B Mux 6 Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y CONNECTION DIAGRAMS 80-Ball Fine-pitch BGA Top View, Balls Facing Down A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 L8 M8 NC NC NC NC NC VIO VSS NC NC NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 NC NC A13 A12 A14 A15 A16 NC DQ15 VSS NC NC C6 D6 E6 F6 G6 H6 J6 K6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 C5 D5 E5 F5 G5 H5 J5 K5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 C4 D4 E4 F4 G4 H4 J4 K4 A18 A20 DQ2 DQ10 DQ11 DQ3 RY/BY# WP#/ACC C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 NC NC A3 A4 A2 A1 A0 CE1# OE# VSS NC NC A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 NC NC NC NC NC NC NC VIO CE2# NC NC NC August 8, 2003 Am29PDL129H Am29PDL129H 7 P R E L I M I N A R Y PIN DESCRIPTION A21­A0 = the device is either executing an embedded algorithm or the device is executing a hardware reset operation. 22-bit address bus for 2 x 64 Mb device. A9 supports 12 V autoselect inputs. WP#/ACC 16-bit data inputs/outputs/float CE1#, CE2# = = = = = Pin Not Connected Internally RY/BY# = Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, VCC = Chip Power Supply (2.7 V to 3.6 V and 2.7 V to 3.3 V) RESET# = Hardware Reset Pin Device Ground NC Input/Output Buffer Power Supply (1.65 V to 1.95 V or 2.7 V to 3.6 V) Write Enable VSS = Output Enable Input WE# Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V, program and erase operations are accelerated. Chip Enable Inputs. CE1# controls the 64 Mb in Banks 1A and 1B. CE2# controls the 64 Mb in Banks 2A and 2B. OE# = VIO DQ15­DQ0 = LOGIC SYMBOL 22 A21­A0 16 DQ15­DQ0 CE1# CE2# OE# WE# WP#/ACC RESET# RY/BY# VIO (VCCQ) 8 Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29PDL129 Am29PDL129 H 53 VK I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (­40°C to +85°C) PACKAGE TYPE VK = 80-Ball Fine-pitch Ball Grid Array 0.8 mm pitch, 11.5 x 9 mm package (VBB080 VBB080) SPEED OPTION See Product Selector Guide and Valid Combinations PROCESS TECHNOLOGY H = 0.13 µm DEVICE NUMBER/DESCRIPTION Am29PDL129H Am29PDL129H 128 Megabit (8 M x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Dual Chip Enable Inputs Valid Combinations Valid Combinations for BGA Packages Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Order Number Am29PDL129H53 Am29PDL129H53 PD129H53V PD129H53V Am29PDL129H63 Am29PDL129H63 PD129H63V PD129H63V Am29PDL129H68 Am29PDL129H68 VKI PD129H68V PD129H68V Am29PDL129H83 Am29PDL129H83 PD129H83V PD129H83V Am29PDL129H88 Am29PDL129H88 PD129H88V PD129H88V 1. August 8, 2003 I Speed (ns) VIO Range 55 Package Marking 2.7­3.3 V 65 85 2.7­3.6 V 1.65­1.95 V 2.7­3.6 V 1.65­1.95 V For the Am29PDL129H Am29PDL129H, the last digit of the speed grade specifies the VIO range of the device. Speed grades ending in 3 (e.g., 53, 63) indicate a 3 Volt VIO range. Speed grades ending in 8 (e.g., 68, 88) indicate a 1.8 Volt VIO range. Am29PDL129H Am29PDL129H 9 P R E L I M I N A R Y DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. Operation register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am29PDL129H Am29PDL129H Device Bus Operations L WP#/ACC Addresses (A21­A0) DQ15­ DQ0 H H X AIN DOUT L H X (Note 2) AIN DIN L L RESET# H H WE# H CE2# OE# L CE1# H Read Write H L VIO± 0.3 V VIO ± 0.3 V X X VIO ± 0.3 V X X High-Z Output Disable L L H H H X X High-Z Reset X X X X L X X High-Z Temporary Sector Unprotect (High Voltage) X X X X VID X AIN DIN Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5­12.5 V, VHH = 8.5­9.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High Voltage Sector Protection section. 2. WP#/ACC must be high when writing to sectors SA1-133 SA1-133, SA1-134 SA1-134, SA2-0, or SA2-1. Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appropriate CE1#/CE2# pins to VIL. CE1# and CE2# are the power control and select the lower (CE1#) or upper (CE2#) halves of the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Characteristics table for timing specifications and to Figure 12 for the timing diagram. ICC1 in 10 the DC Characteristics table represents the active current specification for reading array data. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC­tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits A21­A3 select an 8-word page, and address bits A2­A0 select a specific work within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor fall within that page) are t PACC . When CE1# and CE2# are deasserted (CE1#=CE2#=VIH), the reassertion of CE1# or CE2# for subsequent access has access time of tACC or tCE. Here again, CE1#/CE2# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A21­A3 constant and changing A2 to A0 to select the specific word within that page. Table 2. Page Select Word A2 A1 A0 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 sectors of memory), the system must drive WE# and CE1# or CE2# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" refers to the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. Bank CE1# CE2# A21­A20 If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result. Bank 1A 0 1 00, 01, 10 Autoselect Functions Bank 1B 0 1 11 Bank 2A 1 0 00 Bank 2B 1 0 01, 10, 11 Simultaneous Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), The bank can be selected by bank addresses (A21­A20) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 3. Bank Select Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing August 8, 2003 If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15­DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Am29PDL129H Am29PDL129H 11 P R E L I M I N A R Y Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE1#, CE2# and RESET# pins are all held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE1#, CE2#, and RESET# are held at VIH, but not within V IO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 150 ns. The automatic sleep mode is independent of the WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RE- 12 SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Table 4. Am29PDL129H Am29PDL129H Sector Architecture Sector CE1# CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) SA1-0 0 1 0000000XXX 0000000XXX 32 000000h­007FFFh SA1-1 0 1 0000001XXX 0000001XXX 32 008000h­00FFFFh SA1-2 0 1 0000010XXX 0000010XXX 32 010000h­017FFFh SA1-3 0 1 0000011XXX 0000011XXX 32 018000h­01FFFFh SA1-4 0 1 0000100XXX 0000100XXX 32 020000h­027FFFh SA1-5 0 1 0000101XXX 0000101XXX 32 028000h­02FFFFh SA1-6 0 1 0000110XXX 0000110XXX 32 030000h­037FFFh SA1-7 0 1 0000111XXX 0000111XXX 32 038000h­03FFFFh SA1-8 0 1 0001000XXX 0001000XXX 32 040000h­047FFFh SA1-9 0 1 0001001XXX 0001001XXX 32 048000h­04FFFFh SA1-10 SA1-10 0 1 0001010XXX 0001010XXX 32 050000h­057FFFh SA1-11 SA1-11 0 1 0001011XXX 0001011XXX 32 058000h­05FFFFh SA1-12 SA1-12 0 1 0001100XXX 0001100XXX 32 060000h­067FFFh SA1-13 SA1-13 0 1 0001101XXX 0001101XXX 32 068000h­06FFFFh SA1-14 SA1-14 0 1 0001110XXX 0001110XXX 32 070000h­077FFFh SA1-15 SA1-15 0 1 0001111XXX 0001111XXX 32 078000h­07FFFFh SA1-16 SA1-16 0 1 0010000XXX 0010000XXX 32 080000h­087FFFh SA1-17 SA1-17 0 1 0010001XXX 0010001XXX 32 088000h­08FFFFh SA1-18 SA1-18 0 1 0010010XXX 0010010XXX 32 090000h­097FFFh SA1-19 SA1-19 0 1 0010011XXX 0010011XXX 32 098000h­09FFFFh SA1-20 SA1-20 0 1 0010100XXX 0010100XXX 32 0A0000h­0A7FFFh SA1-21 SA1-21 0 1 0010101XXX 0010101XXX 32 0A8000h­0AFFFFh SA1-22 SA1-22 0 1 0010110XXX 0010110XXX 32 0B0000h­0B7FFFh SA1-23 SA1-23 0 1 0010111XXX 0010111XXX 32 0B8000h­0BFFFFh SA1-24 SA1-24 0 1 0011000XXX 0011000XXX 32 0C0000h­0C7FFFh SA1-25 SA1-25 0 1 0011001XXX 0011001XXX 32 0C8000h­0CFFFFh SA1-26 SA1-26 0 1 0011010XXX 0011010XXX 32 0D0000h­0D7FFFh SA1-27 SA1-27 0 1 0011011XXX 0011011XXX 32 0D8000h­0DFFFFh SA1-28 SA1-28 0 1 0011100XXX 0011100XXX 32 0E0000h­0E7FFFh SA1-29 SA1-29 0 1 0011101XXX 0011101XXX 32 0E8000h­0EFFFFh SA1-30 SA1-30 0 1 0011110XXX 0011110XXX 32 0F0000h­0F7FFFh SA1-31 SA1-31 0 1 0011111XXX 0011111XXX 32 0F8000h­0FFFFFh SA1-32 SA1-32 0 1 0100000XXX 0100000XXX 32 100000h­107FFFh SA1-33 SA1-33 0 1 0100001XXX 0100001XXX 32 108000h­10FFFFh SA1-34 SA1-34 0 1 0100010XXX 0100010XXX 32 110000h­117FFFh SA1-35 SA1-35 0 1 0100011XXX 0100011XXX 32 118000h­11FFFFh SA1-36 SA1-36 0 1 0100100XXX 0100100XXX 32 120000h­127FFFh SA1-37 SA1-37 0 1 0100101XXX 0100101XXX 32 128000h­12FFFFh Bank 1A Bank August 8, 2003 Am29PDL129H Am29PDL129H 13 P R E L I M I N A R Y Table 4. Am29PDL129H Am29PDL129H Sector Architecture Sector CE1# CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) SA1-38 SA1-38 0 1 0100110XXX 0100110XXX 32 130000h­137FFFh SA1-39 SA1-39 0 1 0100111XXX 0100111XXX 32 138000h­13FFFFh SA1-40 SA1-40 0 1 0101000XXX 0101000XXX 32 140000h­147FFFh SA1-41 SA1-41 0 1 0101001XXX 0101001XXX 32 148000h­14FFFFh SA1-42 SA1-42 0 1 0101010XXX 0101010XXX 32 150000h­157FFFh SA1-43 SA1-43 0 1 0101011XXX 0101011XXX 32 158000h­15FFFFh SA1-44 SA1-44 0 1 0101100XXX 0101100XXX 32 160000h­167FFFh SA1-45 SA1-45 0 1 0101101XXX 0101101XXX 32 168000h­16FFFFh SA1-46 SA1-46 Bank 0 1 0101110XXX 0101110XXX 32 170000h­177FFFh Address Range (x16) 1 0101111XXX 0101111XXX 32 178000h­17FFFFh 0 1 0110000XXX 0110000XXX 32 180000h­187FFFh SA1-49 SA1-49 0 1 0110001XXX 0110001XXX 32 188000h­18FFFFh SA1-50 SA1-50 0 1 0110010XXX 0110010XXX 32 190000h­197FFFh SA1-51 SA1-51 0 1 0110011XXX 0110011XXX 32 198000h­19FFFFh SA1-52 SA1-52 0 1 0110100XXX 0110100XXX 32 1A0000h­1A7FFFh SA1-53 SA1-53 0 1 0110101XXX 0110101XXX 32 1A8000h­1AFFFFh SA1-54 SA1-54 0 1 0110110XXX 0110110XXX 32 1B0000h­1B7FFFh SA1-55 SA1-55 0 1 0110111XXX 0110111XXX 32 1B8000h­1BFFFFh SA1-56 SA1-56 0 1 0111000XXX 0111000XXX 32 1C0000h­1C7FFFh SA1-57 SA1-57 0 1 0111001XXX 0111001XXX 32 1C8000h­1CFFFFh SA1-58 SA1-58 0 1 0111010XXX 0111010XXX 32 1D0000h­1D7FFFh SA1-59 SA1-59 0 1 0111011XXX 0111011XXX 32 1D8000h­1DFFFFh SA1-60 SA1-60 0 1 0111100XXX 0111100XXX 32 1E0000h­1E7FFFh SA1-61 SA1-61 0 1 0111101XXX 0111101XXX 32 1E8000h­1EFFFFh SA1-62 SA1-62 0 1 0111110XXX 0111110XXX 32 1F0000h­1F7FFFh SA1-63 SA1-63 0 1 0111111XXX 0111111XXX 32 1F8000h­1FFFFFh SA1-64 SA1-64 0 1 1000000XXX 1000000XXX 32 200000h­207FFFh SA1-65 SA1-65 0 1 1000001XXX 1000001XXX 32 208000h­20FFFFh SA1-66 SA1-66 0 1 1000010XXX 1000010XXX 32 210000h­217FFFh SA1-67 SA1-67 0 1 1000011XXX 1000011XXX 32 218000h­21FFFFh SA1-68 SA1-68 0 1 1000100XXX 1000100XXX 32 220000h­227FFFh SA1-69 SA1-69 0 1 1000101XXX 1000101XXX 32 228000h­22FFFFh SA1-70 SA1-70 0 1 1000110XXX 1000110XXX 32 230000h­237FFFh SA1-71 SA1-71 0 1 1000111XXX 1000111XXX 32 238000h­23FFFFh SA1-72 SA1-72 0 1 1001000XXX 1001000XXX 32 240000h­247FFFh SA1-73 SA1-73 0 1 1001001XXX 1001001XXX 32 248000h­24FFFFh SA1-74 SA1-74 0 1 1001010XXX 1001010XXX 32 250000h­257FFFh SA1-75 SA1-75 0 1 1001011XXX 1001011XXX 32 258000h­25FFFFh SA1-76 SA1-76 0 1 1001100XXX 1001100XXX 32 260000h­267FFFh SA1-77 SA1-77 14 0 SA1-48 SA1-48 Bank 1A SA1-47 SA1-47 0 1 1001101XXX 1001101XXX 32 268000h­26FFFFh Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Table 4. Am29PDL129H Am29PDL129H Sector Architecture CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) 0 1 1001110XXX 1001110XXX 32 270000h­277FFFh 0 1 1001111XXX 1001111XXX 32 278000h­27FFFFh SA1-80 SA1-80 0 1 1010000XXX 1010000XXX 32 280000h­287FFFh SA1-81 SA1-81 0 1 1010001XXX 1010001XXX 32 288000h­28FFFFh SA1-82 SA1-82 0 1 1010010XXX 1010010XXX 32 290000h­297FFFh SA1-83 SA1-83 0 1 1010011XXX 1010011XXX 32 298000h­29FFFFh SA1-84 SA1-84 0 1 1010100XXX 1010100XXX 32 2A0000h­2A7FFFh SA1-85 SA1-85 0 1 1010101XXX 1010101XXX 32 2A8000h­2AFFFFh SA1-86 SA1-86 0 1 1010110XXX 1010110XXX 32 2B0000h­2B7FFFh SA1-87 SA1-87 0 1 1010111XXX 1010111XXX 32 2B8000h­2BFFFFh SA1-88 SA1-88 0 1 1011000XXX 1011000XXX 32 2C0000h­2C7FFFh SA1-89 SA1-89 0 1 1011001XXX 1011001XXX 32 2C8000h­2CFFFFh SA1-90 SA1-90 0 1 1011010XXX 1011010XXX 32 2D0000h­2D7FFFh SA1-91 SA1-91 0 1 1011011XXX 1011011XXX 32 2D8000h­2DFFFFh SA1-92 SA1-92 0 1 1011100XXX 1011100XXX 32 2E0000h­2E7FFFh SA1-93 SA1-93 0 1 1011101XXX 1011101XXX 32 2E8000h­2EFFFFh SA1-94 SA1-94 0 1 1011110XXX 1011110XXX 32 2F0000h­2F7FFFh SA1-95 SA1-95 Bank 1A CE1# SA1-79 SA1-79 August 8, 2003 Sector SA1-78 SA1-78 Bank 0 1 1011111XXX 1011111XXX 32 2F8000h­2FFFFFh Am29PDL129H Am29PDL129H Address Range (x16) 15 P R E L I M I N A R Y Table 4. Am29PDL129H Am29PDL129H Sector Architecture CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) 0 1 1100000XXX 1100000XXX 32 300000h­307FFFh 0 1 1100001XXX 1100001XXX 32 308000h­30FFFFh SA1-98 SA1-98 0 1 1100010XXX 1100010XXX 32 310000h­317FFFh SA1-99 SA1-99 0 1 1100011XXX 1100011XXX 32 318000h­31FFFFh SA1-100 SA1-100 0 1 1100100XXX 1100100XXX 32 320000h­327FFFh SA1-101 SA1-101 0 1 1100101XXX 1100101XXX 32 328000h­32FFFFh SA1-102 SA1-102 0 1 1100110XXX 1100110XXX 32 330000h­337FFFh SA1-103 SA1-103 0 1 1100111XXX 1100111XXX 32 338000h­33FFFFh SA1-104 SA1-104 0 1 1101000XXX 1101000XXX 32 340000h­347FFFh SA1-105 SA1-105 0 1 1101001XXX 1101001XXX 32 348000h­34FFFFh SA1-106 SA1-106 0 1 1101010XXX 1101010XXX 32 350000h­357FFFh SA1-107 SA1-107 0 1 1101011XXX 1101011XXX 32 358000h­35FFFFh SA1-108 SA1-108 0 1 1101100XXX 1101100XXX 32 360000h­367FFFh SA1-109 SA1-109 0 1 1101101XXX 1101101XXX 32 368000h­36FFFFh SA1-110 SA1-110 0 1 1101110XXX 1101110XXX 32 370000h­377FFFh SA1-111 SA1-111 0 1 1101111XXX 1101111XXX 32 378000h­37FFFFh SA1-112 SA1-112 0 1 1110000XXX 1110000XXX 32 380000h­387FFFh SA1-113 SA1-113 0 1 1110001XXX 1110001XXX 32 388000h­38FFFFh SA1-114 SA1-114 0 1 1110010XXX 1110010XXX 32 390000h­397FFFh SA1-115 SA1-115 0 1 1110011XXX 1110011XXX 32 398000h­39FFFFh SA1-116 SA1-116 0 1 1110100XXX 1110100XXX 32 3A0000h­3A7FFFh SA1-117 SA1-117 0 1 1110101XXX 1110101XXX 32 3A8000h­3AFFFFh SA1-118 SA1-118 0 1 1110110XXX 1110110XXX 32 3B0000h­3B7FFFh SA1-119 SA1-119 0 1 1110111XXX 1110111XXX 32 3B8000h­3BFFFFh SA1-120 SA1-120 0 1 1111000XXX 1111000XXX 32 3C0000h­3C7FFFh SA1-121 SA1-121 0 1 1111001XXX 1111001XXX 32 3C8000h­3CFFFFh SA1-122 SA1-122 0 1 1111010XXX 1111010XXX 32 3D0000h­3D7FFFh SA1-123 SA1-123 0 1 1111011XXX 1111011XXX 32 3D8000h­3DFFFFh SA1-124 SA1-124 0 1 1111100XXX 1111100XXX 32 3E0000h­3E7FFFh SA1-125 SA1-125 0 1 1111101XXX 1111101XXX 32 3E8000h­3EFFFFh SA1-126 SA1-126 0 1 1111110XXX 1111110XXX 32 3F0000h­3F7FFFh SA1-127 SA1-127 0 1 1111111000 4 3F8000h­3F8FFFh SA1-128 SA1-128 0 1 1111111001 4 3F9000h­3F9FFFh SA1-129 SA1-129 0 1 1111111010 4 3FA000h­3FAFFFh SA1-130 SA1-130 0 1 1111111011 4 3FB000h­3FBFFFh SA1-131 SA1-131 0 1 1111111100 4 3FC000h­3FCFFFh SA1-132 SA1-132 0 1 1111111101 4 3FD000h­3FDFFFh SA1-133 SA1-133 0 1 1111111110 4 3FE000h­3FEFFFh SA1-134 SA1-134 Bank 1B CE1# SA1-97 SA1-97 16 Sector SA1-96 SA1-96 Bank 0 1 1111111111 4 3FF000h­3FFFFFh Am29PDL129H Am29PDL129H Address Range (x16) August 8, 2003 P R E L I M I N A R Y Table 4. Am29PDL129H Am29PDL129H Sector Architecture Sector CE1# CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) SA2-0 1 0 0000000000 4 000000h­000FFFh SA2-1 1 0 0000000001 4 001000h­001FFFh SA2-2 1 0 0000000010 4 002000h­002FFFh SA2-3 1 0 0000000011 4 003000h­003FFFh SA2-4 1 0 0000000100 4 004000h­004FFFh SA2-5 1 0 0000000101 4 005000h­005FFFh SA2-6 1 0 0000000110 4 006000h­006FFFh SA2-7 1 0 0000000111 4 007000h­007FFFh SA2-8 Bank 1 0 0000001XXX 0000001XXX 32 008000h­00FFFFh 1 0 0000010XXX 0000010XXX 32 010000h­017FFFh 1 0 0000011XXX 0000011XXX 32 018000h­01FFFFh SA2-11 SA2-11 1 0 0000100XXX 0000100XXX 32 020000h­027FFFh SA2-12 SA2-12 1 0 0000101XXX 0000101XXX 32 028000h­02FFFFh SA2-13 SA2-13 1 0 0000110XXX 0000110XXX 32 030000h­037FFFh SA2-14 SA2-14 1 0 0000111XXX 0000111XXX 32 038000h­03FFFFh SA2-15 SA2-15 1 0 0001000XXX 0001000XXX 32 040000h­047FFFh SA2-16 SA2-16 1 0 0001001XXX 0001001XXX 32 048000h­04FFFFh SA2-17 SA2-17 1 0 0001010XXX 0001010XXX 32 050000h­057FFFh SA2-18 SA2-18 1 0 0001011XXX 0001011XXX 32 058000h­05FFFFh SA2-19 SA2-19 1 0 0001100XXX 0001100XXX 32 060000h­067FFFh SA2-20 SA2-20 1 0 0001101XXX 0001101XXX 32 068000h­06FFFFh SA2-21 SA2-21 1 0 0001110XXX 0001110XXX 32 070000h­077FFFh SA2-22 SA2-22 1 0 0001111XXX 0001111XXX 32 078000h­07FFFFh SA2-23 SA2-23 1 0 0010000XXX 0010000XXX 32 080000h­087FFFh SA2-24 SA2-24 1 0 0010001XXX 0010001XXX 32 088000h­08FFFFh SA2-25 SA2-25 Bank 2A SA2-9 SA2-10 SA2-10 1 0 0010010XXX 0010010XXX 32 090000h­097FFFh SA2-26 SA2-26 0 0010011XXX 0010011XXX 32 098000h­09FFFFh 1 0 0010100XXX 0010100XXX 32 0A0000h­0A7FFFh SA2-28 SA2-28 1 0 0010101XXX 0010101XXX 32 0A8000h­0AFFFFh SA2-29 SA2-29 1 0 0010110XXX 0010110XXX 32 0B0000h­0B7FFFh SA2-30 SA2-30 1 0 0010111XXX 0010111XXX 32 0B8000h­0BFFFFh SA2-31 SA2-31 1 0 0011000XXX 0011000XXX 32 0C0000h­0C7FFFh SA2-32 SA2-32 1 0 0011001XXX 0011001XXX 32 0C8000h­0CFFFFh SA2-33 SA2-33 1 0 0011010XXX 0011010XXX 32 0D0000h­0D7FFFh SA2-34 SA2-34 1 0 0011011XXX 0011011XXX 32 0D8000h­0DFFFFh SA2-35 SA2-35 1 0 0011100XXX 0011100XXX 32 0E0000h­0E7FFFh SA2-36 SA2-36 1 0 0011101XXX 0011101XXX 32 0E8000h­0EFFFFh SA2-37 SA2-37 1 0 0011110XXX 0011110XXX 32 0F0000h­0F7FFFh SA2-38 SA2-38 August 8, 2003 1 SA2-27 SA2-27 1 0 0011111XXX 0011111XXX 32 0F8000h­0FFFFFh Am29PDL129H Am29PDL129H 17 P R E L I M I N A R Y Table 4. Am29PDL129H Am29PDL129H Sector Architecture CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) 1 0 0100000XXX 0100000XXX 32 100000h­107FFFh 1 0 0100001XXX 0100001XXX 32 108000h­10FFFFh SA2-41 SA2-41 1 0 0100010XXX 0100010XXX 32 110000h­117FFFh SA2-42 SA2-42 1 0 0100011XXX 0100011XXX 32 118000h­11FFFFh SA2-43 SA2-43 1 0 0100100XXX 0100100XXX 32 120000h­127FFFh SA2-44 SA2-44 1 0 0100101XXX 0100101XXX 32 128000h­12FFFFh SA2-45 SA2-45 1 0 0100110XXX 0100110XXX 32 130000h­137FFFh SA2-46 SA2-46 1 0 0100111XXX 0100111XXX 32 138000h­13FFFFh SA2-47 SA2-47 1 0 0101000XXX 0101000XXX 32 140000h­147FFFh SA2-48 SA2-48 1 0 0101001XXX 0101001XXX 32 148000h­14FFFFh SA2-49 SA2-49 1 0 0101010XXX 0101010XXX 32 150000h­157FFFh SA2-50 SA2-50 1 0 0101011XXX 0101011XXX 32 158000h­15FFFFh SA2-51 SA2-51 1 0 0101100XXX 0101100XXX 32 160000h­167FFFh SA2-52 SA2-52 1 0 0101101XXX 0101101XXX 32 168000h­16FFFFh SA2-53 SA2-53 1 0 0101110XXX 0101110XXX 32 170000h­177FFFh SA2-54 SA2-54 1 0 0101111XXX 0101111XXX 32 178000h­17FFFFh SA2-55 SA2-55 1 0 0110000XXX 0110000XXX 32 180000h­187FFFh SA2-56 SA2-56 1 0 0110001XXX 0110001XXX 32 188000h­18FFFFh SA2-57 SA2-57 1 0 0110010XXX 0110010XXX 32 190000h­197FFFh SA2-58 SA2-58 1 0 0110011XXX 0110011XXX 32 198000h­19FFFFh SA2-59 SA2-59 1 0 0110100XXX 0110100XXX 32 1A0000h­1A7FFFh SA2-60 SA2-60 1 0 0110101XXX 0110101XXX 32 1A8000h­1AFFFFh SA2-61 SA2-61 1 0 0110110XXX 0110110XXX 32 1B0000h­1B7FFFh SA2-62 SA2-62 1 0 0110111XXX 0110111XXX 32 1B8000h­1BFFFFh SA2-63 SA2-63 1 0 0111000XXX 0111000XXX 32 1C0000h­1C7FFFh SA2-64 SA2-64 1 0 0111001XXX 0111001XXX 32 1C8000h­1CFFFFh SA2-65 SA2-65 1 0 0111010XXX 0111010XXX 32 1D0000h­1D7FFFh SA2-66 SA2-66 1 0 0111011XXX 0111011XXX 32 1D8000h­1DFFFFh SA2-67 SA2-67 1 0 0111100XXX 0111100XXX 32 1E0000h­1E7FFFh SA2-68 SA2-68 1 0 0111101XXX 0111101XXX 32 1E8000h­1EFFFFh SA2-69 SA2-69 1 0 0111110XXX 0111110XXX 32 1F0000h­1F7FFFh SA2-70 SA2-70 1 0 0111111XXX 0111111XXX 32 1F8000h­1FFFFFh SA2-71 SA2-71 1 0 1000000XXX 1000000XXX 32 200000h­207FFFh SA2-72 SA2-72 1 0 1000001XXX 1000001XXX 32 208000h­20FFFFh SA2-73 SA2-73 1 0 1000010XXX 1000010XXX 32 210000h­217FFFh SA2-74 SA2-74 1 0 1000011XXX 1000011XXX 32 218000h­21FFFFh SA2-75 SA2-75 1 0 1000100XXX 1000100XXX 32 220000h­227FFFh SA2-76 SA2-76 1 0 1000101XXX 1000101XXX 32 228000h­22FFFFh SA2-77 SA2-77 1 0 1000110XXX 1000110XXX 32 230000h­237FFFh SA2-78 SA2-78 Bank 2B CE1# SA2-40 SA2-40 18 Sector SA2-39 SA2-39 Bank 1 0 1000111XXX 1000111XXX 32 238000h­23FFFFh Am29PDL129H Am29PDL129H Address Range (x16) August 8, 2003 P R E L I M I N A R Y Table 4. Am29PDL129H Am29PDL129H Sector Architecture Sector CE1# CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) SA2-79 SA2-79 1 0 1001000XXX 1001000XXX 32 240000h­247FFFh SA2-80 SA2-80 1 0 1001001XXX 1001001XXX 32 248000h­24FFFFh SA2-81 SA2-81 1 0 1001010XXX 1001010XXX 32 250000h­257FFFh SA2-82 SA2-82 1 0 1001011XXX 1001011XXX 32 258000h­25FFFFh SA2-83 SA2-83 1 0 1001100XXX 1001100XXX 32 260000h­267FFFh SA2-84 SA2-84 1 0 1001101XXX 1001101XXX 32 268000h­26FFFFh SA2-85 SA2-85 1 0 1001110XXX 1001110XXX 32 270000h­277FFFh SA2-86 SA2-86 1 0 1001111XXX 1001111XXX 32 278000h­27FFFFh SA2-87 SA2-87 1 0 1010000XXX 1010000XXX 32 280000h­287FFFh SA2-88 SA2-88 1 0 1010001XXX 1010001XXX 32 288000h­28FFFFh SA2-89 SA2-89 1 0 1010010XXX 1010010XXX 32 290000h­297FFFh SA2-90 SA2-90 1 0 1010011XXX 1010011XXX 32 298000h­29FFFFh SA2-91 SA2-91 1 0 1010100XXX 1010100XXX 32 2A0000h­2A7FFFh SA2-92 SA2-92 1 0 1010101XXX 1010101XXX 32 2A8000h­2AFFFFh SA2-93 SA2-93 1 0 1010110XXX 1010110XXX 32 2B0000h­2B7FFFh SA2-94 SA2-94 1 0 1010111XXX 1010111XXX 32 2B8000h­2BFFFFh SA2-95 SA2-95 1 0 1011000XXX 1011000XXX 32 2C0000h­2C7FFFh SA2-96 SA2-96 1 0 1011001XXX 1011001XXX 32 2C8000h­2CFFFFh SA2-97 SA2-97 1 0 1011010XXX 1011010XXX 32 2D0000h­2D7FFFh SA2-98 SA2-98 1 0 1011011XXX 1011011XXX 32 2D8000h­2DFFFFh SA2-99 SA2-99 1 0 1011100XXX 1011100XXX 32 2E0000h­2E7FFFh SA2-100 SA2-100 1 0 1011101XXX 1011101XXX 32 2E8000h­2EFFFFh SA2-101 SA2-101 1 0 1011110XXX 1011110XXX 32 2F0000h­2F7FFFh SA2-102 SA2-102 1 0 1011111XXX 1011111XXX 32 2F8000h­2FFFFFh SA2-103 SA2-103 1 0 1100000XXX 1100000XXX 32 300000h­307FFFh SA2-104 SA2-104 1 0 1100001XXX 1100001XXX 32 308000h­30FFFFh SA2-105 SA2-105 1 0 1100010XXX 1100010XXX 32 310000h­317FFFh SA2-106 SA2-106 1 0 1100011XXX 1100011XXX 32 318000h­31FFFFh SA2-107 SA2-107 1 0 1100100XXX 1100100XXX 32 320000h­327FFFh SA2-108 SA2-108 1 0 1100101XXX 1100101XXX 32 328000h­32FFFFh SA2-109 SA2-109 1 0 1100110XXX 1100110XXX 32 330000h­337FFFh SA2-110 SA2-110 1 0 1100111XXX 1100111XXX 32 338000h­33FFFFh SA2-111 SA2-111 1 0 1101000XXX 1101000XXX 32 340000h­347FFFh SA2-112 SA2-112 1 0 1101001XXX 1101001XXX 32 348000h­34FFFFh SA2-113 SA2-113 1 0 1101010XXX 1101010XXX 32 350000h­357FFFh SA2-114 SA2-114 1 0 1101011XXX 1101011XXX 32 358000h­35FFFFh SA2-115 SA2-115 1 0 1101100XXX 1101100XXX 32 360000h­367FFFh SA2-116 SA2-116 1 0 1101101XXX 1101101XXX 32 368000h­36FFFFh SA2-117 SA2-117 1 0 1101110XXX 1101110XXX 32 370000h­377FFFh SA2-118 SA2-118 1 0 1101111XXX 1101111XXX 32 378000h­37FFFFh Bank 2B Bank August 8, 2003 Am29PDL129H Am29PDL129H Address Range (x16) 19 P R E L I M I N A R Y Table 4. Bank Sector CE1# Am29PDL129H Am29PDL129H Sector Architecture CE2# Sector Address (A21-A12 A21-A12) Sector Size (Kwords) Address Range (x16) 0 1110000XXX 1110000XXX 32 380000h­387FFFh 0 1110001XXX 1110001XXX 32 388000h­38FFFFh 1 0 1110010XXX 1110010XXX 32 390000h­397FFFh SA2-122 SA2-122 1 0 1110011XXX 1110011XXX 32 398000h­39FFFFh SA2-123 SA2-123 1 0 1110100XXX 1110100XXX 32 3A0000h­3A7FFFh SA2-124 SA2-124 1 0 1110101XXX 1110101XXX 32 3A8000h­3AFFFFh SA2-125 SA2-125 1 0 1110110XXX 1110110XXX 32 3B0000h­3B7FFFh SA2-126 SA2-126 1 0 1110111XXX 1110111XXX 32 3B8000h­3BFFFFh SA2-127 SA2-127 1 0 1111000XXX 1111000XXX 32 3C0000h­3C7FFFh SA2-128 SA2-128 1 0 1111001XXX 1111001XXX 32 3C8000h­3CFFFFh SA2-129 SA2-129 1 0 1111010XXX 1111010XXX 32 3D0000h­3D7FFFh SA2-130 SA2-130 1 0 1111011XXX 1111011XXX 32 3D8000h­3DFFFFh SA2-131 SA2-131 1 0 1111100XXX 1111100XXX 32 3E0000h­3E7FFFh SA2-132 SA2-132 1 0 1111101XXX 1111101XXX 32 3E8000h­3EFFFFh SA2-133 SA2-133 1 0 1111110XXX 1111110XXX 32 3F0000h­3F7FFFh SA2-134 SA2-134 20 1 1 SA2-121 SA2-121 Bank 2B SA2-119 SA2-119 SA2-120 SA2-120 1 0 1111111XXX 1111111XXX 32 3F8000h­3FFFFFh Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Table 5. SecSiTM Sector Addresses Sector Size Am29PDL129H Am29PDL129H Address Range 128 words 000000h­00007Fh Factory-Locked Area 64 words 000000h-00003Fh Customer-Lockable Area 64 words 000040h-00007Fh Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7­DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programm ing algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 6. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see August 8, 2003 Table 4). Table 6 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7­DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 14. Note that if a Bank Address (BA) on address bits A21 and A20 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 14. This method does not require V ID . Refer to the Autoselect Command Sequence section for more information. Am29PDL129H Am29PDL129H 21 P R E L I M I N A R Y Table 6. Description Manufacturer ID: AMD Device ID Read Cycle 1 Read Cycle 3 Sector Protection Verification SecSi Indicator Bit (DQ7, DQ6) A8 A7 A6 A5 to A4 A3 A2 A1 A0 DQ15 to DQ0 H X X VID X L L X L L L L 0001h L L H 227Eh H H H L 2221h H H H 2200h H H A9 L L A10 H H A21 to A12 H L WE# L CE2# OE# L CE1# L L H H L L H H L L H H L L Read Cycle 2 Autoselect Codes (High Voltage Method) H L H X X VID X L L L L SA X VID X L L L L L H L 0001h (protected), 0000h (unprotected) L H H H X X VID X X L X L L H H 00C0h (factory and customer locked), 0080h (factory locked) L Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences 22 Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Table 7. Am29PDL129H Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE1# Control Table 8. Am29PDL129H Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE2# Control Sector Group A21-12 A21-12 Sector/Sector Block Size Sector Group A21-12 A21-12 Sector/Sector Block Size SA1-0­SA1-3 00000XXXXX 00000XXXXX 128 (4x32) Kwords SA2-0 0000000000 4 Kwords SA1-4­SA1-7 00001XXXXX 00001XXXXX 128 (4x32) Kwords SA2-1 0000000001 4 Kwords SA1-8­SA1-11 SA1-11 00010XXXXX 00010XXXXX 128 (4x32) Kwords SA2-2 0000000010 4 Kwords SA1-12 SA1-12­SA1-15 SA1-15 00011XXXXX 00011XXXXX 128 (4x32) Kwords SA2-3 0000000011 4 Kwords SA1-16 SA1-16­SA1-19 SA1-19 00100XXXXX 00100XXXXX 128 (4x32) Kwords SA2-4 0000000100 4 Kwords SA1-20 SA1-20­SA1-23 SA1-23 00101XXXXX 00101XXXXX 128 (4x32) Kwords SA2-5 0000000101 4 Kwords SA1-24 SA1-24­SA1-27 SA1-27 00110XXXXX 00110XXXXX 128 (4x32) Kwords SA2-6 0000000110 4 Kwords SA1-28 SA1-28­SA1-31 SA1-31 00111XXXXX 00111XXXXX 128 (4x32) Kwords SA2-7 0000000111 4 Kwords SA1-32 SA1-32­SA1-35 SA1-35 01000XXXXX 01000XXXXX 128 (4x32) Kwords SA2-8 0000001XXX 0000001XXX 32 Kwords SA1-36 SA1-36­SA1-39 SA1-39 01001XXXXX 01001XXXXX 128 (4x32) Kwords SA2-9 0000010XXX 0000010XXX 32 Kwords SA1-40 SA1-40­SA1-43 SA1-43 01010XXXXX 01010XXXXX 128 (4x32) Kwords SA2-10 SA2-10 0000011XXX 0000011XXX 32 Kwords SA1-44 SA1-44­SA1-47 SA1-47 01011XXXXX 01011XXXXX 128 (4x32) Kwords SA2-11 SA2-11 - SA2-14 SA2-14 00001XXXXX 00001XXXXX 128 (4x32) Kwords SA1-48 SA1-48­SA1-51 SA1-51 01100XXXXX 01100XXXXX 128 (4x32) Kwords SA2-15 SA2-15 - SA2-18 SA2-18 00010XXXXX 00010XXXXX 128 (4x32) Kwords SA1-52 SA1-52­SA1-55 SA1-55 01101XXXXX 01101XXXXX 128 (4x32) Kwords SA2-19 SA2-19 - SA2-22 SA2-22 00011XXXXX 00011XXXXX 128 (4x32) Kwords SA1-56 SA1-56­SA1-59 SA1-59 01110XXXXX 01110XXXXX 128 (4x32) Kwords SA2-23 SA2-23 - SA2-26 SA2-26 00100XXXXX 00100XXXXX 128 (4x32) Kwords SA1-60 SA1-60­SA1-63 SA1-63 01111XXXXX 01111XXXXX 128 (4x32) Kwords SA2-27 SA2-27 - SA2-30 SA2-30 00101XXXXX 00101XXXXX 128 (4x32) Kwords SA1-64 SA1-64­SA1-67 SA1-67 10000XXXXX 10000XXXXX 128 (4x32) Kwords SA2-31 SA2-31 - SA2-34 SA2-34 00110XXXXX 00110XXXXX 128 (4x32) Kwords SA1-68 SA1-68­SA1-71 SA1-71 10001XXXXX 10001XXXXX 128 (4x32) Kwords SA2-35 SA2-35 - SA2-38 SA2-38 00111XXXXX 00111XXXXX 128 (4x32) Kwords SA1-72 SA1-72­SA1-75 SA1-75 10010XXXXX 10010XXXXX 128 (4x32) Kwords SA2-39 SA2-39 - SA2-42 SA2-42 01000XXXXX 01000XXXXX 128 (4x32) Kwords SA1-76 SA1-76­SA1-79 SA1-79 10011XXXXX 10011XXXXX 128 (4x32) Kwords SA2-43 SA2-43 - SA2-46 SA2-46 01001XXXXX 01001XXXXX 128 (4x32) Kwords SA1-80 SA1-80­SA1-83 SA1-83 10100XXXXX 10100XXXXX 128 (4x32) Kwords SA2-47 SA2-47 - SA2-50 SA2-50 01010XXXXX 01010XXXXX 128 (4x32) Kwords SA1-84 SA1-84­SA1-87 SA1-87 10101XXXXX 10101XXXXX 128 (4x32) Kwords SA2-51 SA2-51 - SA2-54 SA2-54 01011XXXXX 01011XXXXX 128 (4x32) Kwords SA1-88 SA1-88­SA1-91 SA1-91 10110XXXXX 10110XXXXX 128 (4x32) Kwords SA2-55 SA2-55 - SA2-58 SA2-58 01100XXXXX 01100XXXXX 128 (4x32) Kwords SA1-92 SA1-92­SA1-95 SA1-95 10111XXXXX 10111XXXXX 128 (4x32) Kwords SA2-59 SA2-59 - SA2-62 SA2-62 01101XXXXX 01101XXXXX 128 (4x32) Kwords SA1-96 SA1-96­SA1-99 SA1-99 11000XXXXX 11000XXXXX 128 (4x32) Kwords SA2-63 SA2-63 - SA2-66 SA2-66 01110XXXXX 01110XXXXX 128 (4x32) Kwords SA1-100 SA1-100­SA1-103 SA1-103 11001XXXXX 11001XXXXX 128 (4x32) Kwords SA2-67 SA2-67 - SA2-70 SA2-70 01111XXXXX 01111XXXXX 128 (4x32) Kwords SA1-104 SA1-104­SA1-107 SA1-107 11010XXXXX 11010XXXXX 128 (4x32) Kwords SA2-71 SA2-71 - SA2-74 SA2-74 10000XXXXX 10000XXXXX 128 (4x32) Kwords SA1-108 SA1-108­SA1-111 SA1-111 11011XXXXX 11011XXXXX 128 (4x32) Kwords SA2-75 SA2-75 - SA2-78 SA2-78 10001XXXXX 10001XXXXX 128 (4x32) Kwords SA1-112 SA1-112­SA1-115 SA1-115 11100XXXXX 11100XXXXX 128 (4x32) Kwords SA2-79 SA2-79 - SA2-82 SA2-82 10010XXXXX 10010XXXXX 128 (4x32) Kwords SA1-116 SA1-116­SA1-119 SA1-119 11101XXXXX 11101XXXXX 128 (4x32) Kwords SA2-83 SA2-83 - SA2-86 SA2-86 10011XXXXX 10011XXXXX 128 (4x32) Kwords SA1-120 SA1-120­SA1-123 SA1-123 11110XXXXX 11110XXXXX 128 (4x32) Kwords SA2-87 SA2-87 - SA2-90 SA2-90 10100XXXXX 10100XXXXX 128 (4x32) Kwords SA1-124 SA1-124 1111100XXX 1111100XXX 32 Kwords SA2-91 SA2-91 - SA2-94 SA2-94 10101XXXXX 10101XXXXX 128 (4x32) Kwords SA1-125 SA1-125 1111101XXX 1111101XXX 32 Kwords SA2-95 SA2-95 - SA2-98 SA2-98 10110XXXXX 10110XXXXX 128 (4x32) Kwords SA1-126 SA1-126 1111110XXX 1111110XXX 32 Kwords SA2-99 SA2-99 - SA2-102 SA2-102 10111XXXXX 10111XXXXX 128 (4x32) Kwords SA1-127 SA1-127 1111111000 4 Kwords SA2-103 SA2-103 - SA2-106 SA2-106 11000XXXXX 11000XXXXX 128 (4x32) Kwords SA1-128 SA1-128 1111111001 4 Kwords SA2-107 SA2-107 - SA2-110 SA2-110 11001XXXXX 11001XXXXX 128 (4x32) Kwords SA1-129 SA1-129 1111111010 4 Kwords SA2-111 SA2-111 - SA2-114 SA2-114 11010XXXXX 11010XXXXX 128 (4x32) Kwords SA1-130 SA1-130 1111111011 4 Kwords SA2-115 SA2-115 - SA2-118 SA2-118 11011XXXXX 11011XXXXX 128 (4x32) Kwords SA1-131 SA1-131 1111111100 4 Kwords SA2-119 SA2-119 - SA2-122 SA2-122 11100XXXXX 11100XXXXX 128 (4x32) Kwords SA1-132 SA1-132 1111111101 4 Kwords SA2-123 SA2-123 - SA2-126 SA2-126 11101XXXXX 11101XXXXX 128 (4x32) Kwords SA1-133 SA1-133 1111111110 4 Kwords SA2-127 SA2-127 - SA2-130 SA2-130 11110XXXXX 11110XXXXX 128 (4x32) Kwords SA1-134 SA1-134 1111111111 4 Kwords SA2-131 SA2-131 - SA2-134 SA2-134 11111XXXXX 11111XXXXX 128 (4x32) Kwords August 8, 2003 Am29PDL129H Am29PDL129H 23 P R E L I M I N A R Y SECTOR PROTECTION The Am29PDL129H Am29PDL129H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: flash devices. This new method provides three different sector protection states: Persistent Sector Protection Persistently Locked-The sector is protected and cannot be changed. A command sector protection method that replaces the old 12 V controlled protection method. Dynamically Locked-The sector is protected and can be changed by a simple command. Password Sector Protection Unlocked-The sector is unprotected and can be changed by a simple command. A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors SA1-133 SA1-133, SA1-134 SA1-134, SA2-0 and SA2-1. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. Persistent Sector Protection The Persistent Sector Protection method replaces the 12 V controlled protection method in previous AMD 24 To achieve these states, three types of "bits" are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state ­ meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors SA1-133 SA1-133, SA1-134 SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible to change the contents of these sectors. These s ectors generally hold system boot code. T he WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. August 8, 2003 Table 9. Sector Protection Schemes DYB PPB PPB Lock 0 0 0 Unprotected-PPB and DYB are changeable 0 0 1 Unprotected-PPB not changeable, DYB is changeable 0 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Sector State Protected-PPB and DYB are changeable Protected-PPB not changeable, DYB is changeable Table 9 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: Am29PDL129H Am29PDL129H 25 P R E L I M I N A R Y When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further 26 password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors SA1-133 SA1-133, SA1-134 SA1-134, SA2-0 and SA2-1 without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors SA1-133 SA1-133, SA1-134 SA1-134, SA2-0 and SA2-1 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. August 8, 2003 High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. Am29PDL129H Am29PDL129H 27 P R E L I M I N A R Y START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 4 µs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 4 µs First Write Cycle = 60h? First Write Cycle = 60h? Temporary Sector Unprotect Mode Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Wait 100 µs Increment PLSCNT No Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Reset PLSCNT = 1 Read from sector address with A7-A0 = 00000010 Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Increment PLSCNT No No PLSCNT = 25? Yes Yes Remove VID from RESET# No Yes Protect another sector? PLSCNT = 1000? No Write reset command Remove VID from RESET# Sector Protect complete Write reset command Device failed Read from sector address with A7-A0 = 00000010 Data = 01h? Sector Protect complete Sector Protect Algorithm Yes Remove VID from RESET# Write reset command Set up next sector address No Data = 00h? Yes Last sector verified? No Yes Remove VID from RESET# Sector Unprotect complete Write reset command Device failed Sector Unprotect complete Sector Unprotect Algorithm Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms 28 Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors SA1-133 SA1-133, SA1-134 SA1-134, SA2-0 and SA2-1 will remain protected). 2. All previously protected sectors are protected once again. Temporary Sector Unprotect Operation SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses i nd ica tor bi ts ( D Q6 , D Q7 ) to i nd ica te th e factory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see "Enter SecSiTM Sector/Exit August 8, 2003 Factory-Locked Area (64 words) The factory-locked area of the SecSi Sector (000000h-00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a "1". AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using AMD's ExpressFlash service. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Customer-Lockable Area (64 words) Temporary Sector Unprotect Completed (Note 2) Figure 2. SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as "0" and can be permanently locked to "1" by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. Am29PDL129H Am29PDL129H 29 P R E L I M I N A R Y The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE#, CE1#, CE2# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE1# =CE2# = VIH or WE# = VIH. To initiate a write 30 cycle, CE1#/CE2# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 10­13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10­13. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Table 10. CFI Query Identification String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string "QRY" 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Table 11. System Interface String Addresses Data 1Bh 0027h VCC Min. (write/erase) D7­D4: volt, D3­D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7­D4: volt, D3­D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0004h Typical timeout per single byte/word write 2N µs 20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0005h Max. timeout for byte/word write 2N times typical 24h 0000h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) August 8, 2003 Description Am29PDL129H Am29PDL129H 31 P R E L I M I N A R Y Table 12. Device Geometry Definition Addresses 27h 0018h Device Size = 2N byte 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 00FDh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 32 Data Description 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y Table 13. Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string "PRI" 43h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 000Ch Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0007h Sector Protect/Unprotect scheme 01 =29F040 29F040 mode, 02 = 29F016 29F016 mode, 03 = 29F400 29F400, 04 = 29LV800 29LV800 mode 4Ah 00E7h Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0002h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 0085h 4Eh 0095h 4Fh 0001h 50h 0001h 57h 0004h 58h 0027h 59h 0060h 5Ah 0060h 5Bh 0027h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag August 8, 2003 00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Am29PDL129H Am29PDL129H 33 P R E L I M I N A R Y COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 14 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE1#/CE2#, whichever happens later. All data is latched on the rising edge of WE# or CE1#/CE2#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the eras e-sus pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The table provides the read parameters, and Figure 12 shows the timing diagram. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m an d re tur n s th at b a nk t o t he e ra se- suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Reset Command Table 14 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. 34 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector Am29PDL129H Am29PDL129H August 8, 2003 P R E L I M I N A R Y command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 14 shows the address and data requirements for both command sequences. See also "SecSiTM (Secured Silicon) Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 14 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 14 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue th