80C186 186ER 186ED Am186CC 16-BIT 20-BIT A19/S6 A16/S3 H8/300L H8/300 H8/300H - Datasheet Archive

 

The register-based 80186 architecture is built on the 8086 core. The 80186 supports approximately 120 instructions and 14 16-bit

 

80186 The register-based 80186 architecture is built on the 8086 core. The 80186 supports approximately 120 instructions and 14 16-bit registers, organized into four general-purpose, four pointer, four segment, and two special registers. The CPU addresses each general-purpose register as a 16-bit register or two 8-bit registers. The segment registers point to code, stack, and two local data segments. The core architecture includes the processor-execution and the bus-interface units, which asynchronously communicate to the outside world via an 8- or a 16-bit multiplexed system bus. Some AMD 186s support a nonmultiplexed address/data bus, which frees the processor to run at nearly twice the speed of standard 80C186 80C186 controllers-without an increase in external-memory speed requirements. The unit uses a 6-byte instruction-prefetch queue to hold pending instructions fetched by the bus-interface unit. All memory addressing is base-relative, which is a help for embedded code because you can easily change the address base to relocate code. Address segmentation lets the CPU address as much as 1 Mbyte of memory. The 80186 adds a 16bit offset supporting a 64-kbyte segment to the segment base address (the segment register shifts 4 bits left) to attain a 20bit address and 1 Mbyte of addressing capability. The CPU bus supports multiprocessing. The local-bus controller deploys a HOLD/HLDA (hold/hold-acknowledge) protocol that enables another bus master, typically DMA, to take over the common system bus. Power management: Only the Intel versions of the 186 have idle and power-down power-saving modes. Idle shuts off the CPU clock, leaving all integrated peripherals active. Power- CLKOUT down disables the clock input. In addition, you can programmably divide the internal-processor frequency by a factor as high as 256 and slow all internal logic. Special instructions: Math instructions include signed and unsigned multiply and divide, add, subtract, BCD, and decimal adjust. The 80x86 performs a register-exchange repeat prefix for repeating string operations (execute until zero or equal). Wait examines the test pin and suspends instruction execution if the pin is high. Special on-chip peripherals: AMD's 186ER 186ER is the only 186 to support 32 kbytes of on-chip RAM. The 186ED 186ED integrates a DRAM controller. The new Am186CC Am186CC integrates four channels of high-level data-link control (HDLC) and a Universal Serial Bus (USB) peripheral controller. Each HDLC channel has a maximum data rate of 10 Mbps. The USB interface is a 12-Mbps device controller with six endpoints and an integrated USB differential driver/receiver. Development tools: The x86 architecture has more development tools than any other architecture. These tools include emulators, compilers, assemblers, simulators, debuggers, and more. AMD provides demonstration and evaluation kits for AMD-specific devices. The company also sponsors a third-party FusionE86 partner program, comprising a network of tool vendors that offer industry-standard x86 hardware and software. Second sources: AMD and Intel are the primary suppliers of 186 devices. NEC (www.nec.com) and Vadem (www.vadem. com) make code-compatible mPs and mCs.) Harris Semiconductor (www. harris.com) is the second source for the 8086 and 80286. TIMER INTERRUPT/ACKNOWLEDGES DRQ0 NMI DRQ1 PROGRAMMABLE TIMERS VCC X1 0 X2 PROGRAMMABLE INTERRUPT CONTROLLER CLOCK GENERATOR GND POWER SAVE CONTROL REGISTERS CONTROL REGISTERS DMA-CONTROL UNIT 0 1 2 MAXIMUM COUNT REGISTER B MAXIMUM COUNT REGISTER A 16-BIT 16-BIT COUNT REGISTERS CONTROL REGISTERS 1 20-BIT 20-BIT SOURCE POINTERS 20-BIT 20-BIT DESTINATION POINTERS 16-BIT 16-BIT COUNT REGISTERS CONTROL REGISTERS INTERNAL BUS CONTROL REGISTERS READY LOGIC SEGMENT REGISTERS REFRESHCONTROL UNIT BUS-INTERFACE UNIT 6-BYTE PREFETCH QUEUE AD15 TO A19/S6 A19/S6 TO AD0 A16/S3 A16/S3 EXECUTION UNIT 16-BIT 16-BIT GENERAL REGISTERS CONTROL REGISTERS CHIP-SELECT CONTROL UNIT 16-BIT 16-BIT ALU BUS-CONTROL SIGNALS CHIP SELECTS EDN SEPTEMBER 24, 1998 b 95 Hitachi H8 The register-based H8 series includes the H8/300L H8/300L and H8/300 H8/300 8-bit mCs with 16-bit instruction words and 16-bit ALUs and the H8/300H H8/300H and H8S 16-bit mCs with 32-bit ALUs. Most future development in this family will be along the H8S line. Each series is upward-compatible. The H8 devices have eight general-purpose registers, a program counter, and program-status-word registers. The H8S further adds single-cycle execution of the common standard-logic instructions, a multiply-accumulate (MAC) unit in the H8S/2655 H8S/2655 series, and extended-control registers. These registers are not part of a register-banking or third addressing-space scheme. The 8-bit 300L and 300 chips treat registers as 8 or 16 bits, referencing registers as a set of eight 16-bit registers or 16 8-bit registers. The 300H and H8S registers are accessible as 8, 16, or 32 bits. You can dynamically resize the 8- or 16-bit-wide external datapath. H8 devices have a fixed instruction word with a supplemental word for additional data and a RISC-like load/store architecture. All CPUs have a unified address space. The address space includes a 128-byte register file to access onchip peripherals as memory-mapped I/O. Power management: In sleep mode, CPU operation halts, register and RAM contents remain unchanged, and peripherals continue to function. In standby, CPU and peripheral operations halt, and registers and RAM contents remain unchanged. H8S devices can individually control the operation of each of their peripherals. In addition, the H8/300L H8/300L series and some of the H8S-series devices support 32-kHz subclock operation but require an external switching circuit. Special instructions: H8 devices are code-compatible and all share an instruction base with 55 to 69 instructions, mnemonics, and a basic addressing philosophy. Bit-manipulation instructions include set, clear, test, and various logic operations. Math functions include add, subtract, increment, decrement, decimal adjust, multiply, divide, and extend sign; the H8S/2655 H8S/2655 series includes a MAC instruction. H8 devices also perform block moves. Special on-chip peripherals: Depending on the device series, Hitachi offers an LCD drive; a vacuum-fluorescent-display drive for small displays, such as a stereo-system display; a keyboard-interface controller that performs keyboard scan; a DRAM refresh; a DMA controller; and an I2C interface. In addition, several H8 devices come with on-chip, 5 or 12V flash memory. Development tools: Hitachi and third parties offer development tools. The E3000 E3000, E6000 E6000, and E7000 E7000 emulator development platforms from Hitachi support the various members of the H8/300L H8/300L, 300, 300H, and H8S/2000 H8S/2000 series on SPARC, Hewlett-Packard (www.hp.com), and PC environments. Hitachi also offers evaluation kits for product evaluation, benchmarking, and development. These packages typically include a compiler suite, a development/debugger environment, a development board, and supporting documentation and examples. IAR Systems (www.iar.com), Cygnus (www. cygnus.com), and Green Hills Software (www.ghs. com) offer compiler support. Hewlett-Packard and Orion Instruments (www.yokogawa. com) offer emulators. Data I/O (www. dataio.com), BP Microsystems (www.bpmicro.com), Yamaichi (www.yeu.com), and others provide programmer and socket support. Second sources: There are no second sources for the H8 series. Intel MCS-96/296 MCS-96/296 The MCS-96 MCS-96 microcontroller product family comprises the event-processor array (EPA), the high-speed I/O (HSIO), and the motion-control (MC) lines. The EPA line comprises the KR, NT, NP, and NU devices. The HSIO line consists of the KB, KC, and KD devices. The MC line, which comprises the MC, MD, and MH devices, supports motor-control applications. Intel's MCS-296 MCS-296 microcontroller is the most recent addition to the 196 family. The 80296SA 80296SA improves performance over the 8xC196NP and 8xC196NU controllers and maintains binary-code compatibility. You can drop it into an 8xC196NP/NU socket. The 80296SA 80296SA exhibits improved math performance over previous architectures, making it suitable for embedded digital-signal processing and feedback-control systems. The 80296SA 80296SA uses the same peripherals as the 8xC196NP/NU. Intel built the MCS-96 MCS-96 around 256 RAM-based registers; most of the registers can function as a result accumulator. The first 23 of these registers are special-function registers to control the on-chip peripherals. Some family members have onchip RAM that can hold small, critical dynamic code or data and can implement register windowing. Register windowing can substitute a block in RAM for a block of registers. The MCS-96 MCS-96 maps accesses to a register in the window block to the windowed block in RAM. This technique eases fast context switches by shifting the register window to another 96 b EDN SEPTEMBER 24, 1998 block. Block sizes can be programmed for 32, 64, or 128 bytes. The MCS-96 MCS-96 has approximately 220 instructions comprising one, two, or three operands. Some instructions are more than one word. Register windowing helps minimize instruction size by letting 8 bits address a register in a movable window. The address space of the MCS-96 MCS-96 works with both 8- and 16-bit external data buses. The external bus multiplexes data and address lines, so a buffer must hold the address stable during data transfers. However, the 8xC196NP has a demultiplexed external bus. An on-chip memory controller lets the MCS-96 MCS-96 use a range of memory types and speeds. Externalmemory wait states are programmable. Most 96/296 devices can access as much as 64 kbytes of memory; some versions can extend this memory range to 16 Mbytes. The CPU can use autoprogramming to program the internal EPROM with an 8-bit external data interface. All MCS-96 MCS-96 chips except the Mx have a full-duplex serial port, which the 196Kx uses to program the mC. Power management: Idle mode shuts off the CPU clock, leaving all integrated peripherals active. Power-down mode disables the clock input. Special instructions: Math instructions include add, subtract, multiply, divide, and multiply-accumulate. Special instructions include a block move of data; indirect-auto- Intel MCS-96/296 MCS-96/296 (continued) increment addressing; and a table-indexed jump, which lets you jump via a table value. Special on-chip peripherals: The MCS-196 MCS-196's EPA contains two 16-bit timers and 10 capture-and-compare modules. An event interrupt generates edges, starts A/D conversions, and resets timers. The HSIO structure has as many as four input and six output timer/counter-driven lines. The 196 also supports a peripheral-transaction server that is a microcoded, hardware-interrupt handler for responding to data transfers, starting an A/D conversion, and performing similar tasks. The 8xC196 bus controller features programmable waitstate generation, 8- or 16-bit bus width, and support for a HOLD/HLDA (hold/hold-acknowledge) protocol for multiprocessor systems. The 8xC196NP and NU have a dynamically selectable multiplexed/demultiplexed bus and a chipselect unit. The 8xC196NU and 80296SA 80296SA include a PLL. With the PLL, an external clock drives the device at one-half or one-fourth the maximum internal clock frequency. Therefore, a 196/296 system supports a lower frequency external clock or oscillators while maintaining the maximum internal operating frequency. The 296's chip-select unit allows you to window some external-memory locations for direct addressing, an improvement over the 196. Development tools: Intel and many third-party vendors provide tools for the 196 and 296. Intel's evaluation boards provide a low-cost hardware platform for code execution, debugging, and performance analysis. You can configure a board's memory (ROMsim) to closely match the performance and structure of your planned memory configuration. All evaluation boards come with a ROM monitor that can communicate with 196 development-tool debuggers or with a serial interface. Using development tools, you can download 196 object files from the program counter to execute and debug code on the board. You can then use the evaluation board with your application software as part of your prototype-hardware design. The address-bus and data-bus; I/Oport; and other necessary device pins, including reset, power, and ground, are available through headers on each board. You can connect prototype hardware to these pins and operate the board in a stand-alone mode to evaluate the system design. Intel's assembler package comprises a macroassembler, a linker/locator, utilities, and a Windows-based embedded development environment. The linker/locator creates an absolute or executable load image. (Refer to http:// developer.intel.com/design/mcs96/index.htm for more information.) Second sources: There are no second sources for the Intel MCS-96/296 MCS-96/296. 2-kBYTE CODE/DATA RAM PORT 3 MEMORY-ADDRESS BUS MEMORY-ADDRESS BUS (24)(24) SIO MEMORY-DATA BUS (16) BAUD-RATE GENERATOR CHIP-SELECT UNIT BUS-CONTROL SIGNALS PORT 2 A19:16 BUS CONTROLLER A15:0 PERIPHERALBUS INTERFACE AD15:0 PWM ALIGNER QUEUE PORT 4 INTERRUPT CONTROLLER ALU REGISTER MEMORYFILE (THREE- INTERFACE PORT RAM) UNIT DESTINATION ADDRESS (24) DESTINATION DATA (16) 20CS16-3 20CS16-3 DIANE 98 b EDN SEPTEMBER 24, 1998 PERIPHERAL-ADDRESS BUS (8) SOURCE 2 ADDRESS (24) SOURCE 2 DATA (16) EPA PERIPHERAL-DATA BUS (16) SOURCE 1 DATA (16) MEMORY-ADDRESS BUS (24) SOURCE 1 ADDRESS (24) MEMORY-DATA BUS (16) INSTRUCTION SEQUENCER PORT 1 TIMER 1 TIMER 2 Mitsubishi MELPS7700 MELPS7700 Mitsubishi's MELPS7700 MELPS7700 mC family has more than 100 products, which cover commercial and industrial applications. With 109 instructions, the MELPS7700 MELPS7700 architecture builds on the basic MELPS740 MELPS740 instruction set and architecture. The accumulator-based CPU has two 16-bit accumulators, two 16bit index registers, and a 16-bit program counter and stack pointer. Two bus rails feed directly into the ALU. The accumulators, index registers, program counter, stack pointer, program- and data-bank registers, and a 24-bit address incrementer lie between the bus rails. Almost all operations pass through the accumulator. The main registers can function as 8- or 16-bit registers. The semipipelined 7700's CPU fetches the next instruction while executing the current one. A 3-byte prefetch queue holds the next instruction. More than 90% of the instructions execute in less than 1 msec at 25 MHz. The 16-Mbyte address space divides into 256 64-kbyte banks. The highorder bits of a 24-bit address reference the bank; an 8-bit program- or data-bank register supplies this field. Bank 0 holds the special-function registers, internal RAM, and internal ROM. In single-chip mode, executing from on-chip ROM and RAM, the CPU has only one 64-kbyte bank. For debugging, the chip can run in mP mode, in which it executes from offchip program memory. The 7700 has a 256-byte "direct page" for time-critical routines. This page can lie in the first 64-kbyte memory bank or between the first and second banks. The 16-bit direct-page register points to the base (lower) address of the direct page. Accessing the direct page using the direct-page register is 16-BIT 16-BIT ACCUMULATOR A PROCESSOR STATUS 16-BIT 16-BIT ACCUMULATOR B 8-BIT INSTRUCTIONQUEUE BUFFER 8-BIT INSTRUCTION REGISTER INDEX X REGISTER INDEX Y REGISTER DIRECT-PAGE REGISTER DATA-BANK REGISTER INSTRUCTION DECODER DATA BUS 100 b EDN SEPTEMBER 24, 1998 faster and takes only 2 bytes. The external-memory bus can be multiplexed or demultiplexed. For a 16-bit address, the bus is nonmultiplexed; it uses 16-bit addresses and 8-bit data. The CPU can access 16-bit data from odd or even bytes, but performance degrades when using an odd byte. Power management: During wait, oscillation continues, and the integrated peripherals are active. In stop, oscillation stops, and most peripherals are disabled. Special instructions: The 7700's bit-manipulation instructions include bit set, clear, and test for certain flag bits. Math instructions include unsigned multiply and divide, add, subtract, and decimal adjust. The M377XX M377XX performs register A and B exchange and a forced execution breakpoint. Special on-chip peripherals: The M37750F6BFP M37750F6BFP contains 48 kbytes of 12V flash memory. Some devices, such as the M3807X M3807X and M3820X M3820X, include real-time ports that you can use to send data out to external devices for a specific number of clock cycles, thus creating precise control for applications such as printer-head control and paper positioning in a laser printer. The M3807X M3807X group of devices contains PWMs that you can use to control stepper motors of two, three, or four phases. These PWMs use a single multiplexed output line to control the other coils within the motor. The PWMs' outputs depend on the values of dedicated registers that determine the high and low periods. Most of the MELPS7700 MELPS7700 devices support a main clock and a 32-kHz subclock. The main clock allows the device to operate at full speed when it needs to perform calculations or port operations. Development tools: Third-party development tools for the MELPS7700 MELPS7700 include the Ashling 16-BIT 16-BIT (www.ashling.com) Ultra-7700 ALU mP-development system, which comprises an in-circuit emulator and the PathFinder-7700 for Windows source-level debugger. Hewlett-Packard (www.hp.com) provides the 64147A emulator for ROM real-time measurements. IAR's (www. iar.com) C compiler supports both of these emulators. Additional development tools include the Lauterbach (www RAM .lauterbach. com) Trace 32 and Accelerated Technology's (www .atinucleus.com) Nucleus RTOS. ByteBos (www.bytebos.com) offers a multitasking RTOS for Mitsubishi's M377XX M377XX mCs. Orion 16-BIT 16-BIT PROInstruments (www.yokogawa. GRAM COUNTER com) offers the ADViCE emulation systems hosted by Microview G, a graphical high-level debugger and in-circuit-emulator interface. STACK POINTER Second sources: There are no second sources for the 7700. Mitsubishi M16C The register-based M16C CPU has two banks of registers, each comprised of six 16-bit general-purpose registers and one frame-based register. You can use two of the 16-bit registers as four 8-bit registers and two others as address registers. The CPU also has a static base register, a flag register, a program counter, and stack pointers. A separate, dedicated stack pointer supports interrupt routines, and another stack pointer is for user programs. The M16C contains a hardware multiplier circuit that performs a 16316-bit multiply in five cycles. The CPU supports a multiplexed or demultiplexed external bus. You can set up the address bus to access the 1-Mbyte address space linearly or divided into four chip-select areas. In the multiplexed mode, the M16C's data bus is 8 bits wide; the demultiplexed bus can be 8 or 16 bits wide. Power management: The M16C can use a 32-kHz oscillator in addition to the main clock-oscillation circuitry. Low-frequency, subclock, wait, and stop power-saving modes support the CPU. The low-frequency mode divides the clock by 2, 4, 8, or 16. In the subclock mode, the CPU runs on the 32kHz subclock. In wait mode, the CPU clock stops with peripheral functions and the oscillator running. Stop mode stops all operation, including oscillation. Special instructions: The M16C has 91 instructions, including bit-manipulation instructions for sequence control, 8 8 8 graphics, and data communications. Other special instructions include high-level C-language and operating-system support instructions. Special on-chip peripherals: Some of the functions available on M16 devices include a 10-bit ADC with S/H circuitry; a subscriber-interface module; an array of multifunction timers; and full-duplex UARTs. The M16C also supports a masked-ROM program-correction function that uses an address-match interrupt scheme to allow designers to correct two faulty mask-ROM program areas with an external EEPROM. These mCs also have 16-bit CRC circuitry that uses the CRC-CCITT (X16+X12+X5+1) polynomial with either of the chip's UARTs. Development tools: IAR Systems (www.iar.com) and Tasking (www.tasking.com) offer third-party support in C compilers and assemblers. Hewlett-Packard (www.hp.com), Orion Instruments (www.yokogawa.com), and Nohau Corp (www.nohau.com) provide in-circuit emulators. CMX Co (www.cmx.com), Embedded Systems Products (www.esphou. com), and Bytebos (www.bytebos.com) provide RTOS kernels. Mitsubishi offers its own development tools, which include evaluation boards, in-circuit emulators, assemblers, C compilers, RTOSs, and programming adapters. Second sources: There are no second sources for the M16C. 8 8 8 8 I/O PORT P0 P1 INTERNAL PERIPHERAL FUNCTION TIMER 16-BIT 16-BIT TIMER TA0 16-BIT 16-BIT TIMER TA1 16-BIT 16-BIT TIMER TA2 16-BIT 16-BIT TIMER TA3 16-BIT 16-BIT TIMER TA4 16-BIT 16-BIT TIMER TB0 16-BIT 16-BIT TIMER TB1 16-BIT 16-BIT TIMER TB2 15-BIT 15-BIT WATCHDOG TIMER TWO-CHANNEL DMAC P2 10-BIT 10-BIT, EIGHTTO 10-CHANNEL 10-CHANNEL ADC 8-BIT, THREE- CHANNEL SIM/IER UART/CLOCK SYNCHRONOUS SIO P4 P5 SYSTEM CLOCK GENERATION XIN-XOUT XCIN-XCOUT M16C/60 M16C/60 SERIES CPU CORE REGISTERS 19 0 R0H R01 PROGRAM COUNTER R1H R0L R2 R3 A0 A1 FB 15 0 SB VECTOR TABLE INTB STACK POINTER ISP USP 15 0 FLG P6 8 P7 7 P8 CRC-OPERATION CIRCUIT (CCITT) 8-BIT, TWOCHANNEL DAC 102 b EDN SEPTEMBER 24, 1998 P3 RAM 8 ROM P9 16316 MULTIPLY CIRCUIT P10 8 Motorola 68HC12 68HC12 Although the 68HC12 68HC12 is a true 16-bit architecture, it has the same register set and interrupt stacking order as the 68HC11 68HC11. In addition, the 208 instructions of the HC12 are a superset of the HC11's instruction set, making the HC12 upwardly compatible with the HC11. To run HC11 code on the HC12, you need only to reassemble your code and account for changes to timing loops resulting from a clock-speed increase to 8 MHz and shorter instruction-cycle times. As with the 68HC16 68HC16 and 68300 families, Motorola based the HC12 on a modular design methodology. Motorola designers use the Lite Module Bus, which is similar to the InterModule Bus, to connect the core to peripheral modules. The HC12's core contains a module that includes a multiplexed or nonmultiplexed external bus, runtime monitors, and Motorola's background-debugging mode (BDM). The runtime monitors include a watchdog timer, a clock monitor that uses a resistor/capacitor time constant to monitor the speed of the crystal, and a periodic interrupt timer. The BDM, a single-wire implementation (versus four wires on the HC16 and 68300), offers code patching and two hardware breakpoints. (However, the hardware breakpoints are not available 32-kBYTE FLASH EEPROM 1-kBYTE RAM AN3 AN4 AN5 CPU12 CPU12 AN6 BKGD SMODN/TAGHI PERIODIC INTERRUPT AN7 CLOCK MONITOR BREAKPOINTS EXTAL XTAL RESET XIRQ IRQ/VPP IOC0 IOC1 IOC2 TIMER AND IOC3 PULSE OC7 IOC4 ACCUMULATOR IOC5 IOC6 PAI ECLK I/O I/O SDI/MISO SDO/MOSI SCK CS/SS DDRS IPIPE0/MODA RxD TxD I/O LITE INTEGRATION MODULE IPIPE1/MODB DBE MULTIPLEXED ADDRESS/DATA BUS PWM I/O DDRA I/O I/O I/O I/O DDRB PORT A PW0 PW1 PW2 PW3 PORT B BDLC I/O 104 b EDN SEPTEMBER 24, 1998 DLCRx DLCTx I/O I/O I/O I/O I/O DDRP PORT E LSTRB/TAGLO SCI SPI R/W DDRDLC SINGLE-WIRE BACKGROUNDDEBUG MODULE DDRT COP WATCHDOG PORT T PORT AD AN2 PORT S 768-BYTE 768-BYTE EEPROM AN0 AN1 PORT P ADC PORT DLC VFP on all HC12 derivatives.) BDM also performs nonintrusive reads and writes to memory while the CPU runs at full speed, and the BDM accesses on-chip memory during CPU dead cycles. You can use the BDM to program the on-chip flash or EEPROM or for programming the address comparators to set hardware breakpoints. BDM lets debuggers do source-level debugging and monitor variables without intruding on users' software. Power management: The HC12 uses a PLL to hit 8 MHz and to help with the CPU's power management. Current implementations of the core operate from voltages of 2.7 to 5.5V with a path to 1.8V. The HC12 has wait and stop power-saving modes and many other power-saving features in the core. Each module has controls to save power when idle, low noise drivers are available on each I/O pin, and external-bus actions halt when the CPU is accessing internal events. Special instructions: The HC12 supports several indexed addressing modes, the most important of which is stackpointer referencing to handle stack-based parameters. Autoincrement and autodecrement indexed addressing is useful for loop counters in C-language programming. You can use the HC12's load-effective-address instruction VRH in C programs to allocate and deallocate stack space. VRL For case statements, indexed indirect-addressing VDDA VSSA modes allow you to put a computed GOTO in line. A new division instruction on the HC12 allows you to divide a 16-bit number by a 16-bit number instead of using a sign-extended, 32-bit number. Furthermore, the HC12 performs this divide in 12 cycles compared with 41 cycles for the HC11. A 16316-bit multiply executes in 375 nsec. Minimum/maximum functions compare two values and store the result in the accumulator or the memory. For example, for a minimum function, the mC stores the smaller of the two values. Similar to the 68300 family, the HC12 performs table-look-up and interpolate functions for operations such as compressing table data. The HC12 also includes four instructions to assist with fuzzy logic. Development tools: A relatively large number of vendors support the relatively new 68HC12 68HC12. Archimedes Software (www.archimedesinc.com), Cosmic Software (www.cosmic-software.com), and IAR Systems (www.iar.com) offer compiler support. CMX Co (www.cmx.com), Embedded Systems Products (www.esphou.com), and Motorola provide RTOSs. Eight vendors offer debuggers, eight offer emulators, and 15 supply programmers. Axiom (www.axman.com) and Motorola supply evaluation boards. For example, Motorola's $99 68HC912B32 68HC912B32 evaluation board operates in BDM and acts as a target and debugger. Inform's (www.fuzzytech.com) Fuzzytech HC11/HC12 HC11/HC12 version generates the fuzzy-logic system as assembly code for the target mC. It also allows you to perform in-circuit debugging using BDM, but, unlike with in-circuit emulators, you need not halt the running system to modify the fuzzy-logic control strategy. Second sources: There are no second sources for the 68HC12 68HC12. Motorola 68HC16 68HC16 Motorola's 68HC16 68HC16 mC is a superset of and source-code-compatible with the 8-bit 68HC11 68HC11; the HC16 has 261 instructions. The 68HC16 68HC16 is an accumulator-based architecture; processing centers on two 16bit accumulators. Three 16-bit index registers work with the accumulators. These index registers have 4-bit extensions for creating 20-bit addresses. Similarly, the stack pointer and program counter, both 16-bit registers, have 4-bit extensions, providing 20-bit address capability to a flat, 1Mbyte memory map. An integrated multiply-accumulate DATA (MAC) unit comprises a 16-bit multipliBUS cand register, a 16-bit multiplier register, a 16 36-bit accumulator, and two 8-bit-address mask registers. It performs a MAC cycle in ADDRESS BUS 480 nsec at 25 MHz. The MAC unit uses a simplified form of modulo addressing to 32 implement FIR filters and circular buffers. Motorola built the 68HC16 68HC16 modular architecture on the internal InterModule Bus (IMB), which simplifies the addition of on-chip peripherals. Bus protocols are based on the 68020 bus. The IMB contains circuitry to support exception processing, address-space partitioning, multiple interrupt levels, and vectored interrupts. The 68HC16 68HC16 has a system-integration module that supports an external 20-bit address bus, a 16-bit data bus, and as many as 12 programmable chip selects. The module includes watchdog and periodic timers and a PLL that boosts a 32.76-kHz or 4.2-MHz crystal to system clock speeds as high as 25 MHz. You access memory-mapped, on-chip peripherals through dedicated peripheral registers. The HC16 includes Motorola's in-circuit backgrounddebugging mode (BDM), which allows read and write access of the target system's registers and memory and offers a set of debugging commands. You use BDM to program the on-chip flash and RAM. BDM lets debuggers do source-level debugging and monitor variables without using other processor resources, such as RAM or serial ports. Program and data share a common address or use two separate spaces. The 68HC16 68HC16's addressing space expands to 1 Mbyte (2 Mbytes for separate code and data spaces for larger applications). Instruction boundaries are on even boundaries and use big-endian addressing. The CPU accesses words on word or byte boundaries. Power management: Wait reduces current by stopping CPU execution while leaving the clock running. A low-power-stop (LPSTOP) instruction stops the clock. Special instructions: The 68HC16 68HC16 performs bit manipulation with instructions such as bit set, clear, and test. It also supports math instructions, such as add, subtract, BCD, decimal-adjust add, and signed and unsigned multiply and divide. A background operating mode uses special debugging instructions. Development tools: The HC16 family has extensive development-tool support, including assemblers, compilers, emulators, debuggers, evaluation boards, and programmers from third-party vendors. (Visit www.mcu.motsps.com/dev_tools/ 3rd/index.html.) 106 b EDN SEPTEMBER 24, 1998 SEQUENCER CONTROL UNIT INSTRUCTION PIPELINE AND DECODE EXECUTION UNIT BUS CONTROL BUS CONTROL Second sources: There are no second sources for the HC16 family. Philips 80C51XA 80C51XA The 16-bit architecture of Philips' 80C51XA 80C51XA is compatible with and shares the programmer's model of the 8051. Operation centers on a 21-word register file. You access these registers, which can perform all ALU functions, as words, bytes, or individual bits. Some instructions, such as 32-bit shifts, multiplies, and divides, allow addressing pairs of word registers as double words. The XA architecture supports as many as 32 maskable interrupts and has exception-handling circuitry for fault-tolerant systems. The architecture also supports multitasked applications and handles as many as 255 independent tasks. The XA-S3's 24-bit program counter provides addressing for as much as 16 Mbytes of linear code space; other XA derivatives address only as much as 1 Mbyte. The prefetch queue holds the next instruction to be executed, improving the instruction-execution performance. The XA's memory structure is the same as that of the 80C51 80C51. It has separate datamemory and special-function-register (SFR) spaces. The XA divides its 16-Mbyte data-memory space into 256 64-kbyte segments. The SFRs have the same role in the XA as in the 80C51 80C51: controlling and monitoring the on-chip peripheral functions. The XA's stack resides in the data-memory space and can be as large as 64 kbytes. The stack can reside in the on- or off-chip memory space or both on and off chip. The external-memory interface supports the 24-bit memory address, and you can configure it for 8- or 16-bit accesses. At power-on or dynamically under software control, you can configure the data-bus width for 8- and 16-bit accesses. Programmable wait states help you control external-memory accesses, and a wait pin allows easy interfac- ing to external memory and other devices. Power management: A software-controlled idle mode shuts down processor functions but leaves most of the on-chip peripherals and external interrupts functioning; power-down mode shuts down everything, including the on-chip oscillator. Special instructions: The XA supports all of the 80C51 80C51 instructions and a variety of new instructions to benefit C programming. The XA performs extensive bit manipulation with instructions such as jump on bit set or clear, set, clear, move, AND, and OR. Math instructions include add, subtract, 16316-bit multiplication, signed and unsigned 32316-bit divide, and 32-bit shifts. The XA also has instructions to normalize and sign-extend operands for floating-point support, move data blocks, jump double indirect, breakpoint and trap, and reset. Special on-chip peripherals: The XA-S3 derivatives have an eight-channel, 10-bit A/D converter with automatic channelscan and repeat functions. They also contain a five-channel, 16-bit programmable counter array. Development tools: Third-party development tools from many vendors support the XA. These tools include assemblers, simulators, C compilers, RTOSs, in-circuit emulators, EPROM programmers, development boards, and adapter sockets. Philips' $499 EB-XA emulator serially links to a PC and can emulate in ROMless or ROM mode. The emulator uses a Philips bond-out chip that emulates the mC and reveals the internal resources to the user. The EB-XA supports debugging and breakpoints and allows real-time execution of XA code. Second sources: There are no second sources for the XA. RESET REGISTER FILE EXECUTION AND CONTROL INSTRUCTION REGISTER 16-BIT 16-BIT DATA/ADDRESS/CONTROL BUS 16-BIT 16-BIT ALU EXCEPTION CONTROLLER PSWL PSWH PROGRAM COUNTER SFR-BUS INTERFACE SCR CS PROGRAMMEMORY INTERFACE 8/16-BIT 8/16-BIT SFR BUS PCON OSCILLATOR SSEL CPU CLOCK ES DATA-MEMORY INTERFACE ON-CHIP RAM 108 b EDN SEPTEMBER 24, 1998 DS EXTERNAL DATA MEMORY ON-CHIP PERIPHERALS EXTERNAL SFR DEVICES ON-CHIP ROM/ EPROM EXTERNAL PROGRAM MEMORY Siemens SABC16x Operations within Siemens 166/165/167 mCs center on 16bit registers in as many as 16 banks, as well as on a 16-bit program counter and a 16-bit program-status word. The dualported RAM banks let the CPU read a register for the next operation while writing back the results of the current operation to another register. On-chip peripherals work independently of the CPU with a separate clock generator. The CPU and peripherals interchange data and control information via special-function registers. The main core of the CPU comprises a four-stage pipeline: fetch, decode, execute, and write back; a one-cycle barrel shifter; and a fast-multiply/divide-function unit. Pipeline stages clock in 100-nsec cycles, so most of the mC's 240 instructions appear to execute in one cycle. Instruction latency is four cycles, or 400 nsec. A peripheral-event controller performs byte or word transfers between peripherals and memory in one cycle without interrupting the CPU. The CPU uses code segmentation and data paging to address as many as 256 kbytes (the 166) or 16 Mbytes (165/167) of the unified instruction-data memory space. The external-memory bus controller has four programmable modes, chip selects, and a wait-state generator. You can partition physical memory into multiple segments and five address ranges (the 166 has only two), each having a different type of memory with or without wait states. You can program a hold/acknowledge mechanism on the external bus so that external devices take control for critical data transfers. A system stack of as much as 512 bytes stores temporary data. Instructions are 2 or 4 bytes long. The mCs can handle a 4byte instruction fetch from on-chip ROM in one 100-nsec stage. A single fetch gets an entire instruction. However, because the 16-bit external bus permits only a single-word access, off-chip program accesses suffer at least a one-cycle stall for a 4-byte instruction. The 166/165/167 mCs cache branch-target instructions and use them to supply the next iteration of a branch, allowing execution without pipeline stalls. First-pass loop branches pay a single-cycle penalty. Nonaligned, double-word, branch-target instructions also pay a one-cycle penalty. Power management: Idle mode shuts off the CPU clock, leaving all integrated peripherals active. Power-down mode disables the clock input. Any reset or interrupt request can terminate idle mode; only a hardware reset can terminate power-down. Special instructions: Bit-manipulation instructions include bit set, clear, move, and various logical operations. Math instructions are add, subtract, 16316-bit multiply and divide, and 32316-bit divide. The mCs can perform as many as 15 shifts or rotates in one instruction cycle. Every jump has 16 conditions. Development tools: The list of third-party support for the 166 is too extensive, so check out www.directories. mfi.com/ embedded/siemens/. In addition, Siemens has developed a CD-ROM-hosted digital application engineer (DAvE) that helps you program the C166 by offering wizards to configure the chip and automatically generate C-level templates with appropriate driver functions for all on-chip peripherals and interrupt controls. The company also has a useful Web site at www.spacetools.com (SiemensPartners for Applications using Chips for Embedded control) for finding applicationoriented support. Second sources: The ST10 devices from STMicroelectronics are 166-compatible. CPU STACK POINTER MLD STKUN PSW SYSCON 1-kBYTE INTERNAL RAM BIT-MASK GEN INSTRUCTION REG FOUR-STAGE PIPELINE 32 R15 MUL/DIV-HW EXECUTION UNIT INSTRUCTION PTR ROM 16 MDH STKOV ALU GENERALPURPOSE REGISTERS 16-BIT 16-BIT BARREL SHIFTER R15 CONTEXT POINTER BUSCON0 BUSCON1 ADDRSEL 1 BUSCON2 ADDRSEL 2 BUSCON3 ADDRSEL 3 ADDRSEL 4 BUSCON4 DATA-PAGE POINTERS 110 b EDN SEPTEMBER 24, 1998 CODE-SEGMENT POINTERS R0 16 R0 Toshiba TLCS-900 TLCS-900 Toshiba uses the TLCS-900 TLCS-900 architecture in several product cores, including the 900, 900/L 900/L, 900/H 900/H, and 900/H2 900/H2. The TLCS-900 TLCS-900 is a general-purpose, 16-bit core. The TLCS-900/L TLCS-900/L adds a clock gear and 3V operation to benefit applications requiring low power consumption. The TLCS-900/H TLCS-900/H targets higher performance applications, and 900 core modifications allow these devices to execute some instructions in fewer states. The TLCS-900/H2 TLCS-900/H2 uses the same register and instruction set as the 900 but includes a 32-bit bus, an internal clock multiplier, and improved code-execution time to achieve four times the performance of the 900/H 900/H core. All of the TLCS-900 TLCS-900 cores are instruction-set-compatible. The TLCS-900 TLCS-900 architecture centers on a flexible register set that you can configure for 8-, 16-, or 32-bit processing using a 16-bit ALU and datapaths. Toshiba designed the generalpurpose register set for fast context switching, and you partition it into four register banks, each with four 32-bit registers, or eight register banks, each with eight 16-bit registers. The chip operates in minimum mode with a 16-bit program counter and registers or 32-bit maximum mode with 32-bit datapaths, a program counter, and registers. The TLCS-900 TLCS-900, with 300 to 400 instructions, is backwardcompatible with the TLCS-90 TLCS-90 but offers a substantial performance increase by using a three-stage pipeline with a 4byte prefetch queue. The 32-bit maximum mode accommodates large-scale arithmetic and addressing (16 Mbytes) with a basic 16-bit CPU. Configuring peripheral interrupts to bypass CPU interrupts enhances I/O processing. Instead, an I/O controller or special peripheral mDMA processor handles CPU interrupts. Using the I/O controller avoids the overhead of interrupt processing. Peripheral events trigger I/O-controller processing and "DMA" the data to or from memory and internal peripherals. The I/O controller handles as many as four mDMA channels. The CPU can execute from external memory and can dynamically shift bus sizes between 8 and 16 bits while running. Power management: Idle mode shuts down the CPU, leaving all integrated peripherals active. Power-down, or stop, ANALOG INPUT 20 MHz 10-BIT 10-BIT, EIGHT-CHANNEL ADC ROM CS/WAIT FOUR-BLOCK CS/WAIT 112 b EDN SEPTEMBER 24, 1998 8-BIT, TWO-CHANNEL TIMER RAM 32 kHz WATCHDOG TIMER disables the oscillator. Any reset or interrupt request can terminate idle mode; only a hardware reset (nonmaskable interrupt and interrupt 0) can terminate power-down. Special instructions: Bit-manipulation instructions include bit set, clear, change, test, search forward and reverse, and various logical operations. Math instructions include add, subtract, decimal adjust, signed and unsigned 838-bit and 16316-bit multiply, signed and unsigned 1638-bit divide, and shift 1 bit one to 16 times. The TLCS-900 TLCS-900 also has a multiply-accumulate instruction and modulo increment/decrement instructions for circular-buffer pointers. It can also perform block moves and pattern searches in memory. Special on-chip peripherals: Some members of the TLCS900/H TLCS900/H family contain a DRAM controller that operates with either 8- or 16-bit DRAMs. The DRAM controller supplies the control signals for refresh, read/write access control, and a row-column-address multiplexer. Toshiba's clock-gear function allows you to divide the operating frequency of the device by 2, 4, 8, or 16. You can dynamically change the clock gear to meet the instantaneous processing needs of the application. Many of the TLCS-900 TLCS-900 devices contain a pattern generator that comprises a 4-bit output port and the control logic to drive a stepper motor. The devices can also contain an LCD driver/controller that supports a 403four-segment common. An integrated voltage-boost circuit generates the LCD voltages from the battery supply. Development tools: Toshiba offers a real-time in-circuit emulator for the 16- and 32-bit versions of the TLCS-900 TLCS-900 series. The emulator contains a controller that interfaces to a PC system through RS-232C RS-232C or local-area-network connection. The emulator mimics the target microcontroller. For software support, Toshiba offers a software suite that comprises an assembler, a C compiler, a simulator, and an RTOS. In addition, Avocet Systems (www.2500ad.com) and others provide third-party support. Second sources: There are no second sources for the TLCS900 TLCS900. 900/L 900/L CORE (µDMA) TWO-CHANNEL SIO UART 16-BIT 16-BIT, TWO-CHANNEL TIMER TIMER OUTPUT TIMER INPUT PULSE OUTPUT TIMER/ COUNTER INPUT 8-BIT, TWO-CHANNEL PWM TIMER PULSE OUTPUT 4-BIT, TWO-CHANNEL PATTERN GENERATOR PATTERN OUTPUT Zilog Z80/80180/80380 Z80/80180/80380 TWO 16-BIT 16-BIT PROGRAMMABLE RELOAD TIMERS TXS RXS/CTS1 CKS CLOCKED SERIAL-I/O PORT MMU ADDRESS BUFFER A19 TO A0 114 b EDN SEPTEMBER 24, 1998 D7 TO D0 INT2 INT1 INT0 NMI ST E BUSACK RFSH BUSREQ WAIT HALT MREQ IORQ3 WR M1 RD even more power by stopping the oscillator but lengthens the restart time. Special instructions: Instructions allow you to perform exchanges between registers and between registers and memory. Register-bank-selection instructions allow fast context switching. The architectures support decimal arithmetic via decimal-adjust and rotate-digit-left and -right instructions. The Z80180 Z80180 adds an 838-bit multiply; the Z80380 Z80380 includes 16316-bit multiply and divide as well as 32-bit add, subtract, increment, decrement, load, and store. Block-transfer and -search instructions support automatic address incrementing and decrementing. The 380 instruction set includes mode settings; instruction prefixes for identifying 16- or 32-bit data; and new instructions that control whether load, store, and arithmetic instructions operate on 16- or 32-bit data. Special on-chip peripherals: Z18x devices beyond the Z80180 Z80180 include memory-chip select, wait-state generation, and general-purpose I/O ports, various mixtures of one or two multiprotocol serial channels, a 16450/16550 "mimic" interface for applications such as PC-internal modems, a bidirectional parallel port, on-chip ROM, and a watchdog timer. The basic Z80380 Z80380 includes only memory-chip select and waitstate generation, whereas the Z80382 Z80382 includes four generalpurpose I/O ports, two UARTs, two timers, mimic, and watchdog timer from the 180 family, plus eight advanced DMA channels, three high-speed data-link-control channels, a PCMCIA interface, and a plug-and-play ISA interface. Development tools: Except for one low-cost Z80180 Z80180 emulator, Zilog relies on third parties for emulation support for the Z80, Z8018x, and Z8038x devices. Emulator support is available from Avocet System (www.2500ad.com), Orion Instruments (www.yokogawa. BUS-STATE CONTROL INTERRUPT com), iSystem (www.isystem. CPU com), and Softaid (www.softaid.com). Software support is DREQ1 available from Avocet Systems, TEND1 TWO DMACs IAR Systems (www.iar.com), and Softools Inc (www.softools.com). Zilog supplies several evaluation TXA0 boards and a low-cost emulator. CKA0,DREQ0 ASYNCHRONOUS Unlike with the Z180, developRXA0 SCI ment support for the Z380 is minRTS0 (CHANNEL 0) CTS0 imal; Zilog provides an assembler, DCD0 an evaluation board, and a Production Languages Corp (www. TXA1 plcorp.com) C compiler with an ASYNCHRONOUS CKA1,TEND0 SCI optimizer program to improve RXA1 (CHANNEL 1) performance and code size. Microtec (www. microtec.com) offers a Z80380 Z80380 C compiler. Second sources: Seven licensed VCC DATA vendors act as second sources for VSS BUFFER the Z80. Hitachi acts as a second source for the 180. There are no second sources for the 380. 8-BIT DATA BUS A18/TOUT A18/TOUT TIMING GENERATOR 16-BIT 16-BIT ADDRESS BUS 0 RESET XTAL EXTAL The Z80, 180, and 380 processor families represent three generations of upward-compatible mPs. The Z80 includes 150 instructions, many of which have numerous variants for operand location and addressing modes. The 180 includes 10 additional instructions, and the 380 adds 65 more. The Z80 and 180 include two banks of registers; each bank comprises an 8-bit accumulator and six 8-bit registers that you can also use as three 16-bit registers. The Z80 and 180 also include two 16-bit index registers and a 16-bit stack pointer and program counter. The 380 quadruples the register set of the Z80 and 180, making eight banks of registers. All registers on the 380 are 32 bits wide. All Z80, 180, and 380 processors include separate memory- and I/O-address spaces. The Z80 memory-address space is 65 kbytes, and the I/O space accesses as much as 256 bytes. The 180 uses a memory-management unit (MMU) to expand the physical memory-address space to 1 Mbyte and maintains 16-bit-wide logical addresses for Z80 compatibility. The 180 also includes instructions that expand I/O addressing to 16 bits. The 380 has a native mode for Z80-compatible memory addressing and an extended mode that provides 32-bit linear addressing, eliminating the need for the MMU. (Some device versions do not pin out all the address bits.) Power management: Most members of the Z8018x and Z8038x families include power-management facilities. Sleep mode keeps the main oscillator running to permit quick restart but blocks clocking to the processor and most peripherals to reduce power consumption. Standby mode saves