ATR0600 4536G QFN28 ATR0610 ATR0620 ATR0600-PJQ ATR0600-PJQW CH-1705 - Datasheet Archive

 

· · · · · · Very Low Power Design ( 50 mW) Single IF Concept 1.5-bit ADC on Chip Small

 

Features · · · · · · Very Low Power Design ( 50 mW) Single IF Concept 1.5-bit ADC on Chip Small QFN Package (28 Pins) Highly Integrated, Few External Components UHF6 Technology Electrostatic sensitive device. Observe precautions for handling. GPS Front-end IC ATR0600 ATR0600 1. Description With the growing importance of mobile communication, location awareness is a key feature for more and more products and services. Due to its small size and minimum power consumption, the GPS front-end IC ATR0600 ATR0600 is an ideal solution for mobile applications and navigation systems. Rev. 4536G 4536G­GPS­09/05 Figure 1-1. Block Diagram 96.76 MHz 1575.42 MHz Ant LC-BP NBPI BPI BP NBP VS3 REF VDIG Dig. IF at 4.35 MHz LNA RFIN SIGH SAW SIGL VGA amp BP-Filter RFNIN SC VCO 1478.6 MHz 64 1 VS2 AGCO OR 1 4 GC PFD VS1 23.104 MHz VS5 Power control XTO VS7 X P2 NXTO NX P1 XTO 23.104 MHz 2. Pin Configuration Pinning QFN28 QFN28 NC RFNIN RFIN VS3 P1 P2 NC Figure 2-1. 14 13 12 11 10 9 8 15 16 17 Paddle 18 GND 19 20 21 22 23 24 25 26 27 28 7 6 5 4 3 2 1 X VS5 XTO NXTO VS7 NX AGCO GC VS2 REF SIGL SIGH VDIG SC BP NBP BPI NBPI VS1 NC NC 2 ATR0600 ATR0600 4536G 4536G­GPS­09/05 ATR0600 ATR0600 Table 2-1. Pin Description Pin Symbol Type(1) Paddle GND P 1 AGCO O Signal level output ESD3 2 NX OB Complementary to X ESD3 Function Common ground Protection Level ­ 3 VS7 P ECL - blocks supply ESD2 4 NXTO IB Complementary to XTO ESD3 5 XTO IB Quartz input ESD3 6 VS5 P XTO supply ESD2 7 X OB Quartz intermediate output ESD3 8 NC ­ Not connected 9 P2 I Power-up quartz oscillator ESD3 10 P1 I Power-up RF part ESD3 ­ 11 VS3 P Reference supply ESD2 12 RFIN IB RF input 1.575 GHz ESD3 13 RFNIN IB Complementary to RFIN ESD3 14 NC ­ Not connected 15 BP IB Open-collector output of mixer ESD3 16 NBP IB Complementary to BP ESD3 17 BPI IB IF - filter input ESD3 18 NBPI IB Complementary to BPI ESD3 19 VS1 P VCO + mixer + VGA supply ESD2 20 NC ­ Not connected 21 NC ­ Not connected 22 GC I Gain control input ESD3 23 VS2 P Subsampling unit supply ESD2 ­ ­ ­ 24 REF O Defining low threshold voltage ESD3 25 SIGL O Digital interface subsampled output high threshold voltage refered to REF1 ESD3 26 SIGH O Digital interface subsampled output low threshold voltage refered to REF2 ESD3 27 VDIG P Digital interface supply voltage 1.8V ESD2 28 SC O Digital interface clock output ESD3 Note: 1. O: Output, OB: Differential output, P: Supply, I: Input, IB: Differential input 3 4536G 4536G­GPS­09/05 3. Functional Description The specification of GPS receivers for personal mobile applications strongly differs from standalone GPS receiver specifications. One reason is the presence of strong blocking signals from mobile transmitters which might cause unacceptable levels of degradation in the carrier-to-noise ratio of a GPS system if not sufficiently suppressed. The other reason is the requirement for very low power consumption. The ATR0600 ATR0600 GPS receiver IC has been especially designed for GPS applications in mobile phones. From this system point of view, it incorporates highest isolation between GPS and cellular antennas, as well as low power consumption. The ATR0600 ATR0600 contains a low-power single IF design and integrates a complete frequency synthesizer. It is fully functional over a supply-voltage range of 2.7V to 3.3V and is housed in a 28-pin QFN package. The GPS receiver's input signal is a Direct Sequence Spread Spectrum (DSSS) signal at 1575.42 MHz with a 1.023 Mbps Bi-Phase-Shift-Keying (BPSK) modulated spreading code. As the input signal power at the antenna is approximately ­140 dBm, the desired signal is below the thermal noise floor. 3.1 LNA/Mixer Stage The ATR0600 ATR0600 receives the L1 GPS signal via an external LNA. The LNA bandwidth should be as narrow as possible to avoid jamming from out-of-band signals (especially from those of the 1800 GSM band). We recommend to use Atmel's ATR0610 ATR0610 for that purpose. Combined with the antenna the LNA provides a first filtering of the GPS signal. The LNA in addition should have a power shutdown feature. The shutdown signal will be generated inside the digital section of the GPS receiver. The output of the LNA drives an external SAW filter, which provides the image rejection for the mixer and the isolation of GSM bands. The output of the SAW filter drives a highly linear mixer which down-converts the GPS signal to an IF of 96.76 MHz. 3.2 IF Stage The mixer directly drives an external LC-bandpath filter. In order to provide the ultimate selectivity of the GPS frequency before the A/D conversion of the receiver part, the signal path of the ATR0600 ATR0600 combines an external filter and a second integrated filter. We recommend to design the external filter as a 2-pole filter with quality factor Q > 25. 3.3 VGA Amplifier Stage The output of the LC-filter drives an on-chip Variable Gain-Controlled amplifier (VGA) which is combined with an integrated IF-bandpath filter to perform additional filtering of GSM jamming signals. The AGC stage provides the additional gain needed to optimally load the signal range of the following analog/digital converter. The AGC control loop can be selected either on-chip close loop or open loop mode. Connecting the AGC_OUT output directly to the AGC_CNTRL input activates the internal control loop. In that case, the VGA control signal is passed to the VGA via an integrated buffer stage including all necessary filtering (low-pass filter). The external control loop is closed by the baseband IC ATR0620 ATR0620. 4 ATR0600 ATR0600 4536G 4536G­GPS­09/05 ATR0600 ATR0600 3.4 A/D Converter Stage The output of the VGA drives the integrated 1.5-bit analog-to-digital converter stage, which comprises two comparators and two output drivers in order to provide sign and magnitude output bits to the baseband IC ATR0620 ATR0620. The comparator LOW- and HIGH- thresholds (in Figure 1-1 on page 2 for SIGH and SIGL) are adjustable via external resistor. The OR gate closes the internal AGC control loop. 3.5 Power Save Setting Stage The integrated power-control stage is controlled by the baseband IC ATR0620 ATR0620 via P1 and P2. The input signals control the shutdown of the reference crystal oscillator (P2) or the shutdown of the whole RF section (P1). 4. Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage VS ­0.3 to +3.7 V Input voltage Vin ­0.3 to +3.7 V Operating temperature Storage temperature range Tj ­40 to +125 °C Tstg ­55 to +125 °C Symbol Value Unit RthJA 125 K/W Value Unit 5. Thermal Resistance Parameters Junction ambient 6. Recommended Operating Conditions Parameters Symbol VS 2.7 to 3.3 V Temperature range Temp -40 to +85 °C Input frequency fin, mixer 1575.42 MHz fref 23.104 MHz VDD 1.65 to 2.0 V V 0.9 V Supply voltage Reference frequency Supply voltage digital interface, pin 27 Supply voltage difference V = VS ­ VDD 5 4536G 4536G­GPS­09/05 7. Electrical Characteristics No. 1 Parameters Test Conditions Pin Symbol 3, 6, 11, 19, 23 Min. IS Typ. Max. Unit Type* 18 mA A Common 1.1 Supply current P1 = P2 = VPUon 1.2 Supply current XTO P1 = VPUoff P2 = VPUon 6 IXTO 2 mA A 1.3 Supply current digital interface P1 = P2 = VPUon 27 IDD 250 µA A 1.4 Supply current (power down) P1 = P2 = VPUOFF 3, 6, 11, 19, 23, 27 IS, pd µA A 1.5 Total gain RFIN, RFNIN matched, to 50, VGC = 2.2V 1 G dB B 1.6 Noise figure (SSB) dB C 2 20 95 6.9 NF st Mixer and 1 IF-filter 2.1 Output frequency fref = 23.104 MHz 15, 16 fIF 96.76 MHz B 2.2 Input impedance fref = 1575 MHz 12, 13 Zin, IF 13 ­ j80 C fin, VGA 96.76 MHz 3 VGA and 2nd IF-filter 3.1 Bandpass center frequency fref = 23.104 MHz 3.2 Minimum gain VGC = 1.0V GVGA, min 0 dB D 3.3 Maximum gain VGC = 2.2V GVGA, max 75 dB D 3.4 Control-voltage sensitivity VGC = 2.2V VGC = 1.0V Nvga, min Nvga, max 6.6 150 dB/V dB/V D D 3.5 Gain-control output cut-off frequency Without external load Fagc_out 100 kHz D 3.6 Gain-control output voltage at 50 pF load V B 4 1 Vagc_out 1.0 2.2 Reference Oscillator 4.1 XTO phase noise at 100 Hz 28 Pn100 ­80 dBc/Hz C 4.2 XTO phase noise at 1 kHz 28 Pn1k ­100 dBc/Hz C 28 fclk 23.104 MHz A 5 Clock and Data Driver 5.1 Clock driver frequency 5.2 Clock output level Cload = 10 pF 28 Vclkhigh 0.8 × VDD V B, C 5.3 Clock output level Cload = 10 pF 28 Vclklow 0.2 × VDD V C 5.4 Data output level Cload = 10 pF 25, 26 Vdatahigh 0.8 × VDD V C *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 6 ATR0600 ATR0600 4536G 4536G­GPS­09/05 ATR0600 ATR0600 7. Electrical Characteristics (Continued) No. Parameters Test Conditions 5.5 Data output level Cload = 10 pF 6 Pin Symbol 25, 26 Min. Typ. Vdatalow Max. Unit Type* V C V C 0.2 × VDD Power-up, Pins P1 and P2 6.1 Power-on voltage level on 9, 10 VPUon 6.2 Power-on voltage level off 9, 10 VPUoff 0.3 V C 6.3 Power-on delay time 9, 10 TPUon, off 6 µs C 0.9 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 8. Interface Description Figure 8-1. Clock Interface VDIG 20k SC I 10p Chip Figure 8-2. SC Maximum load capacitance SIGH Interface VDIG 20k SIGH I 10p Maximum load cap. Chip Figure 8-3. SIGH SIGL Interface VDIG 20k SIGL I Chip SIGL 10p Maximum load cap. 7 4536G 4536G­GPS­09/05 Figure 8-4. Supply VDIGI Interface VDIG VDIG 1.8V Chip Figure 8-5. Supply Power Control Interface P1 20k VDD P1 P1 50k 100k Chip Figure 8-6. Application Power Control Interface P2 20k VDD P2 P2 50k 100k Application Chip Figure 8-7. Automatic Gain-control Interface VCC 32 µA I 150k 44k AGCO AGCO 50p GC 100p Chip Chip, connected to AGCO Figure 8-8. A/D Reference Level-control Interface Ref VCC I Ref Ref Chip Application Select value on test R optional 8 ATR0600 ATR0600 4536G 4536G­GPS­09/05 ATR0600 ATR0600 Figure 8-9. Mixer Input Interface VCC 250 µA 2.5k 2.5k RF NRF 2 mA Chip RFx RF NRF NRFx Application (Matching) Figure 8-10. XTO Interface 100k XTO NXTO X 220 NX 220 Chip NXTO XTO 47p X 47p 68p NX Application 9 4536G 4536G­GPS­09/05 Figure 8-11. IF-filter Interface BP Imax BP 2p 220 nH 2 mA 300 fF VCC BPI BPI 220 nH 2p 60 µA 5p VCC NBPI NBPI 2p 220 nH VCC 300 fF 60 µA NBP NBP Imax 5p 220 nH 2p 2 mA Application (IF-Filter) Chip Figure 8-12. Mixer Input Impedance at RF-NRF S-Parameter Response : Z11 imOhm : Z11 reOhm 0.0 70 60 -100 50 -200 40 30 -300 20 10 -400 500M 10 1.30G 2.10G 500M 1.30G 2.10G ATR0600 ATR0600 4536G 4536G­GPS­09/05 ATR0600 ATR0600 9. Ordering Information Extended Type Number Package Remarks ATR0600-PJQ ATR0600-PJQ QFN28 QFN28 - 5x5 Taped and reeled ATR0600-PJQW ATR0600-PJQW QFN28 QFN28 - 5x5 Taped and reeled, lead-free 10. Package Information 11 4536G 4536G­GPS­09/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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