ATF-33143 SC-70 ATF-36163 ATF-3X143 LL1608-FH10NK LL1608-FH22NK LL1608FH10NK - Datasheet Archive

 

1930 to 1990 MHz Using the ATF-33143 PHEMT Application Note AN 1195 Introduction The Avago Technologies ATF-33143 is one of a

 

A Low Noise High Intercept Point Amplifier for 1930 to 1990 MHz Using the ATF-33143 ATF-33143 PHEMT Application Note AN 1195 Introduction The Avago Technologies ATF-33143 ATF-33143 is one of a family of high dynamic range, low noise PHEMT devices designed for use in low cost commercial applications in the VHF through 6 GHz frequency range. The ATF-33143 ATF-33143 is the device with the largest gate periphery (1600 micron gate width) with 2 GHz performance tested and guaranteed at a Vce of 4 V and Id of 80 mA. The ATF-33143 ATF-33143 is housed in a 4lead SC-70 SC-70 (SOT-343) surface mount plastic package. In this application note, the ATF-33143 ATF-33143 is described in a high dynamic range low noise amplifier designed specifically for the 1930 to 1990 MHz PCS base station market. When biased at a Vds of 4 volts and an Ids of 80 mA, the ATF-33143 ATF-33143 amplifier has a minimum of 13 dB gain, a 0.7 dB noise figure and an output intercept point of +32.5 dBm. The amplifier has an input return loss of 8 to 9 dB and an output return loss of greater than 20 dB. The design techniques presented in this application note can be applied to LNAs at other frequencies in the 1500 MHz through 2500 MHz frequency range. The amplifier is etched on 0.031 inch thickness FR-4 printed circuit board material for low manufacturing costs. The amplifier makes use of low cost miniature multilayer chip inductors for small size. Source Grounding of FETs and Biasing One of the first items to consider in the design of any LNA is the method of biasing the device. Most microwave FETs are of the depletion mode type, which requires a negative voltage on the gate to pinch off the flow of drain current. Without the application of a negative voltage on the gate, the device will pull maximum drain current which is called Idss. to the drain. This configuration is shown in Figure 1. The gate voltage is then adjusted for the desired value of drain current. The gate voltage required to support a desired drain current, Id, is dependent on the device's pinchoff voltage, Vp, and the saturated drain current, Idss. Id is calculated with the following equation. Vgs = Vp ( 1 ­ SQRT Id Idss ) Idss for the ATF-33143 ATF-33143 is specified at 237 mA typical. Vp is specified to be -0.5 V typical at 10% Idss as opposed to Id = 0 mA. Measuring Vgs in a high volume environment for Id = 10% Idss is easier than determining Vp when Id = 0 mA. Vgs at 10% Idss can be converted to Vp by substitution in the above formula. It was found that Vp = 1.462 x Vgs @ 10% Idss. Therefore, Vp calculates to be -0.73 V. Substituting these parameters into the above equation predicts a typical Vgs for 80 mA Id to be -0.31 V. Each source lead is connected to ground through top side micro-stripline etch (LL) and a plated through hole to the bottom groundplane. The effect of these seemingly short lengths of transmission lines is in the form of additional inductance (LL) added in series with each source lead to ground. The additional inductance LL can have a very pronounced effect on amplifier performance. Its effect will be covered later in this application note. Q1 C IN L IN C OUT L OUT LL LL Vdd Vgg The LNA described in this application note uses dc grounded source leads, which necessitates the application of a negative voltage at the gate terminal to set the proper desired drain current. The negative voltage is required in addition to the positive voltage that is normally connected Figure 1. Biasing FET with dc grounded source leads necessitating both positive and negative voltage power supplies. Another option is to insert a resistor or resistors (Rs) in series with the source lead(s) to ground and then dc ground the gate lead. This is shown in Figure 2. From a dc standpoint this has the same effect of making the gate more negative than the source, which is required to set the desired amount of drain current. From an RF standpoint, each of the source resistors must be bypassed to ground with a capacitor, Cs, which provides a low impedance at the frequency of operation. The capacitors are not perfect and therefore add additional series inductance with each lead. The additional inductance in series with each bypass capacitor is in addition to the inductance associated with the existing microstripline etch (LL) and plated through holes that provide the path(s) to the bottom ground plane. As mentioned previously, the inductance in series with each of the source leads has a pronounced effect on LNA operation. Some of the effects are undesired, such as outof-band gain peaking and stability issues. Other effects, such as improved in-band stability and improved input return loss, can be secured with a small or moderate amount of source inductance. Usually only a few tenths of a nanohenry of inductance is required. This is effectively equivalent to increasing the source leads by only 0.050 inch or so. The effect can be easily modeled using one of the Avago/EEsof microwave circuit simulators. The amount of source inductance that can be safely added depends on the device. Very short gate width devices such as the 200 micron gate width ATF-36163 ATF-36163 can tolerate very little source inductance. Usually the inductance associated with just two plated through holes through 0.031 inch thickness printed circuit board is all that the device can tolerate. Hence the smaller gate width devices such as the ATF-36163 ATF-36163 are typically used as low noise amplifiers for C and Ku Band applications such as TVRO and DBS. The usual side effect of excessive source inductance with short gate width devices is very Q1 C IN C OUT L OUT L IN LL RS CS Vdd LL CS RS Figure 2. Biasing FET with single polarity power supply. Source resistors are used to make gate voltage negative with respect to the source. 2 1.156" Figure 3. 1X artwork for the ATF-3X143 ATF-3X143 series of low noise PHEMT devices. high frequency gain peaking and resultant oscillations. The larger gate width devices such as the 1600 micron ATF-33143 ATF-33143 have less high frequency gain and therefore the high frequency performance is not as sensitive to source inductance as a smaller device would be. LNA Matching Networks The low noise amplifier is designed for a Vds of 4 volts and an Ids of 80 mA. Typical power supply voltage, Vdd, would then be approximately 5 volts. The generic demo board shown in Figure 3 is etched on low cost 0.031" thickness FR-4 material. The demo board offers the designer several biasing and circuit topology options during the prototyping stage. The demo board was designed such that the input and output impedance matching networks can be either lumped element networks or etched microstrip networks for lower cost. Either low pass or high pass structures can be generated based on system requirements. The demo board also allows the FET to be either self biased or with grounded sources the FET can be biased with a negative voltage applied to the gate terminal. Extra length is included in this demo board to allow standard EF Johnson SMA connectors to be used to prototype the amplifier. The schematic diagram of the completed amplifier is shown in Figure 4. The amplifier is designed for DC grounded source leads which allows gain and output power to be adjusted by varying the gate voltage Vgg. The parts list is shown in Table 1. The demo board as modified per this application note is shown in Figure 5. The modifications are discussed in the next section. The amplifier uses a high-pass impedance matching network for the noise match. The high-pass network consists of a series capacitor (C1) and a shunt inductor (L1). The high-pass topology is especially well suited for PCS and WLAN applications as it offers good low frequency gain reduction which can minimize the amplifier's susceptibility to cellular and pager transmitter overload. L1 also INPUT Q1 C1 OUTPUT C2 R3 ZO ZO L1 R1 L2 L4 L3 C3 R2 C5 C4 C6 Vgg Vdd Figure 4. Schematic diagram of the 1.9 GHz high dynamic range, low noise ATF-33143 ATF-33143 amplifier. Table 1. Component Parts List for the ATF-33143 ATF-33143 Amplifier C1, C2 C3 C4, C6 C5 L1 L2, L3 L4 Q1 R1 R2 R3 Zo 2.7 pF chip capacitor 4.7 pF chip capacitor 10,000 pF chip capacitor 10 pF chip capacitor 10 nH inductor (Toko LL1608-FH10NK LL1608-FH10NK) Strap each source pad to the ground pad with 0.040" wide etch. The jumpered etch is placed a distance of either 0.050" or 0.075" away from the point where each source lead contacts the source pad. Cut off unused source pad. See text for differences in performance. 22 nH inductor (Toko LL1608-FH22NK LL1608-FH22NK) Avago Technologies ATF-33143 ATF-33143 PHEMT 50 chip resistor 10 chip resistor Normally not used. Jumper with etch. See text for more information. 50 Microstripline doubles as a means of inserting gate voltage for biasing up the PHEMT. This requires a good bypass capacitor in the form of C3. C1 also doubles as a dc block. The Q of L1 is extremely important from the standpoint of circuit loss which will directly relate to noise figure. The Toko LL1608FH10NK LL1608FH10NK is a small multilayer chip inductor with a rated Q of 45 at 800 MHz. Lower element Qs may increase circuit noise figure and should be considered carefully. This network has been optimized primarily for noise figure with secondary emphasis on input return loss. Resistor R1 and capacitor C4 provide low frequency stability by providing a resistive termination. The amplifier uses a similar high-pass structure for the output impedance matching network. L4 and C2 provide the proper match for best output return loss and maximum gain. L4 also doubles as a means of inserting voltage 3 1.156" Figure 5. Component placement drawing for the ATF-33143 ATF-33143 low noise amplifier. to the drain. Resistor R2 and capacitor C6 provide a low frequency resistive termination for the device which helps stability. C6 was chosen to be 10000 pF or 0.01 mF over a 1000 pF capacitor in order to improve output intercept point slightly by terminating the F2-F1 difference component of the two test signals used to measure IP3. This can be especially important for the typical 1.25 MHz spacing used in CDMA IP3 evaluation. Resistor R3 was not incorporated in the original design as the circuit was unconditionally stable without R3. Depending on the final layout and component parasitics, circuit stability may be different. A small value of resistance in the 5 to 22 can be inserted at R3 to further help circuit stability. The use of R3 will lower gain and lower power output capabilities of the amplifier, so caution is advised. The original demo board incorporates an additional series microstripline in the input impedance matching network. The microstripline is not required for this amplifier design and can be removed from the demo board. It should be replaced with a small 0.040" wide piece of etch. There is also space allocated for a resistor in series with the drain of the device. When R3 is not used, the gap should be bridged with a small piece of etch. Inductors L2 and L3 are actually very short transmission lines between each source lead and ground. The inductors act as series feedback. The amount of series feedback has a dramatic effect on in-band and out-of-band gain, stability and input and output return loss. The amplifier demo board is designed such that the amount of source inductance is variable. Each source lead is connected to a microstripline which can be connected to a ground pad at any point along the line. For minimal inductance, the source lead pad is connected to the ground pad with a very short piece of etch at the point closest to the device source lead. For the 1900 MHz amplifier, each source lead is connected to its corresponding ground pad at a distance of approximately 0.050" from the source lead. The 0.050" is measured 17 LL = 0.050 IN. 15 GAIN (dB) 13 11 from the edge of the source lead to the closest edge of the ground strap. The remaining unused source lead pad should be removed by cutting off the unused etch. On occasion, the unused etch which looks like an open circuited stub has caused high frequency oscillations. During the initial prototype stage, the amount of source inductance can be tuned to optimize performance. The subject of source inductance and its effect on amplifier performance is covered in Appendix 1. LNA Performance The amplifier is tested at a Vds of 4 volts and Id of 80 mA. The source lead length is also varied to analyze its effect on LNA performance. The measured gain and noise figure of the completed amplifier is shown in Figures 6 and 7. The gain at 1960 MHz with LL = 0.050" is a nominal 13.8 dB and 13 dB with LL = 0.075". Noise figure at 1960 MHz is a nominal 0.69 dB with LL = 0.075" and 0.73 dB at LL = 0.050". Measured input and output return loss is shown in Figures 8 and 9. The nominal input return loss at 1960 MHz is -7.3 dB with LL = 0.050" and -8.6 dB with LL = 0.075". Further improvement in input return loss is possible with some degradation in noise figure by altering the input impedance matching network. Increasing the amount of source inductance LL will offer further improvement in input return loss at the expense of in-band gain. Another potential problem may be out-of-band gain peaking as discussed earlier. The output return loss measured -19 dB with LL = 0.050" and -23 dB with LL = 0.075". LL = 0.075 IN. 9 7 5 100 600 1100 1600 2100 FREQUENCY (MHz) 2600 3100 The amplifier intercept point was measured using two test signals with a spacing of 1.25 MHz. The output intercept point (OIP3) was measured at a nominal +32.5 dBm at 1960 MHz at a dc bias point of 4 volts Vds and an Id of 80 mA. Based on a nominal gain of 13 dB, the corresponding input intercept point (IIP3) calculates to be nearly +20 dBm. Figure 6. ATF-33143 ATF-33143 amplifier gain vs. frequency and source lead length LL. 0 0.9 -1 LL = 0.050 IN. 0.8 INPUT RETURN LOSS (dB) NOISE FIGURE (dB) 0.6 LL = 0.075 IN. 0.5 0.4 0.3 0.2 0.1 0 1800 -3 -4 -5 -6 -7 -8 -9 1900 2000 2100 2200 FREQUENCY (MHz) 2300 Figure 7. ATF-33143 ATF-33143 amplifier noise figure vs. frequency and source lead length LL. 4 LL = 0.050 IN. -2 0.7 -10 100 LL = 0.075 IN. 600 1100 1600 2100 FREQUENCY (MHz) 2600 3100 Figure 8. ATF-33143 ATF-33143 amplifier input return loss vs. frequency and source lead length LL. 0 S2P SNP1 FILE = "C:\S_DATA\FET\f33143e.S2P" OUTPUT RETURN LOSS (dB) -5 -10 LL = 0.050 IN. -15 -20 LL = 0.075 IN. -25 -30 100 600 1100 1600 2100 FREQUENCY (MHz) 2600 3100 Figure 9. ATF-33143 ATF-33143 amplifier output return loss vs. frequency and source lead length LL. MLIN TL8 SUBST = "MSUB1" W = 30 MIL L = 50 MIL VIA V2 D1 = 25 MIL D2 = 25 MIL H = 6 MIL T = 1.14 MIL MLIN TL7 SUBST = "MSUB1" W = 30 MIL L = 50 MIL VIA V1 D1 = 25 MIL D2 = 25 MIL H = 6 MIL T = 1.14 MIL Figure 10. Avago/EEsof ADS simulation of the .S2P file with source inductance and vias to bottom groundplane. Linear Circuit Analysis The ATF-33143 ATF-33143 amplifier circuit was simulated using Avago Technologies' EEsof Advanced Design System (ADS) software. Due to the complexity of the simulation, the design is presented in three sections. First, the ATF33143 ATF33143 and its associated source grounding is shown in Figure 10. The S Parameters for the ATF-33143 ATF-33143 and other Avago transistors can be downloaded from the Avago RF Help Web Site @ http://www.semiconductor.Avago.com/rf/index.html grounds, the S and Noise Parameters include the effects of the test fixture grounds. Therefore, when simulating a 0.031" thickness printed circuit board, only the difference in the printed circuit board thickness is included in the simulation, i.e., 0.031" - 0.025" = 0.006". The transmission lines that connect each source lead to its corresponding plated through hole is simulated as a microstripline (MLIN). Second, the input matching circuit schematic is shown in Figure 11 and the output matching circuit is shown in Figure 12. The low-pass filter circuit at the input and output connectors models the effects of the end launch SMA connectors used on the demo board. In order to maximize the accuracy of the simulation, the parasitics of all capacitors and inductors have been included in the simulation. Component mounting pads have been modeled as MLINs and junctions have been modeled with MTEEO and MSTEP. The results of the simulation are shown in the following dia- As noted on the data sheet, the ATF-33143 ATF-33143 S and Noise Parameters are tested in a fixture that includes plated through holes through a 0.025" thickness printed circuit board. Due to the complexity of de-embedding these 5 MSUB MSUB MSUB1 H = 31 MIL Er = 4.8 MUR = 1 COND = 1.0 E + 306 HU = 3.9 e + 034 MIL T = 1.4 MIL TAN D = 0.1 ROUGH = 0 MIL L L1 L = 0.1 nH R= PORT P1 NUM = 1 C C1 C = 0.1 pF MLIN TL1 SUBST = "MSUB1" W = 50 MIL L = 125 MIL MLIN TL4 SUBST = "MSUB1" W = 60 MIL L = 20 MIL C C1 C = 0.04 pF _ V_DC SRC1 + VDC = VGS V R3 R = 50 OHM CAPQ MLIN C9 TL20 C = 4.7 pF SUBST = "MSUB1" Q = 100 W = 60 MIL F = 100.0 MHz L = 60 MIL MODE = PROPORTIONAL TO FREQ. L L7 L = 0.7 nH R= VIA V5 D1 = 25 MIL D2 = 25 MIL H = 31 MIL T = 1.14 MIL MLIN TL3 SUBST = "MSUB1" W = 50 MIL L = 30 MIL L MLIN L5 L = 0.75 nH TL2 SUBST = "MSUB1" R= W = 50 MIL L = 30 MIL C C2 C = 0.1 pF SLC SLC6 L = 1.4 nH C = 10000 pF VIA V6 D1 = 25 MIL D2 = 25 MIL H = 31 MIL T = 1.14 MIL CAPQ C7 C = 2.7 pF OPT{1 pF TO 10 pF} Q = 100 F = 100.0 MHz MODE = PROPORTIONAL TO FREQUENCY MLIN TL19 SUBST = "MSUB1" W = 20 MIL L = 20 MIL MSTEP STEP8 SUBST = "MSUB1" W1 = 60 MIL W2 = 20 MIL MTEEO TEE1 SUBST = "MSUB1" W1 = 50 MIL W2 = 50 MIL W3 = 60 MIL MLIN TL5 SUBST = "MSUB1" W = 30 MIL L = 30 MIL MSTEP STEP1 SUBST = "MSUB1" W1 = 50 MIL W2 = 30 MIL INDQ L2 L = 10 nH OPT{1 nH TO 10 nH} Q = 32 F = 800 MHz MODE = PROPORTIONAL TO FREQUENCY RDC = 0.0 OHM MLIN TL18 SUBST = "MSUB1" W = 60 MIL L = 60 MIL MSTEP STEP7 SUBST = "MSUB1" W1 = 20 MIL W2 = 60 MIL VAR VAR1 VGS = 0.55 Figure 11. Avago / EEsof ADS tdiagram of the input impedance matching network for the ATF-33143 ATF-33143 amplifier. 6 MLIN TL6 SUBST = "MSUB1" W = 20 MIL L = 10 MIL MSTEP STEP2 SUBST = "MSUB1" W1 = 30 MIL W2 = 20 MIL MLIN TL9 SUBST = "MSUB1" W = 20 MIL L = 10 MIL R R1 R = 0.1 OHM MLIN TL11 SUBST = "MSUB1" W = 50 MIL L = 50 MIL CAPQ C8 C = 2.7 pF NO OPT{1 pF TO 10 pF} Q = 50 L F = 100.0 MHz L3 MODE = PROPORTIONAL L = 0.1 nH TO FREQUENCY R= MTEEO TEE2 SUBST = "MSUB1" W1 = 50 MIL W2 = 50 MIL W3 = 60 MIL MLIN TL21 SUBST = "MSUB1" W = 50 MIL L = 50 MIL MLIN TL12 SUBST = "MSUB1" W = 50 MIL L = 20 MIL MLIN TL22 SUBST = "MSUB1" W = 25 MIL L = 100 MIL MLIN TL13 SUBST = "MSUB1" W = 50 MIL L = 100 MIL C C4 C = 0.1 pF MLIN TL14 SUBST = "MSUB1" W = 60 MIL L = 10 MIL C C6 C = 0.05 pF MLIN TL17 SUBST = "MSUB1" W = 60 MIL L = 60 MIL L L8 L = 7.5 nH R= VIA V3 D1 = 25 MIL D2 = 25 MIL H = 31 MIL T = 1.14 MIL CAPQ C10 C = 8.2 pF Q = 100 F = 100.0 MHz MODE = PROPORTIONAL TO FREQ. MSTEP STEP6 SUBST = "MSUB1" W1 = 60 MIL W2 = 20 MIL R R2 R = 10 OHM 1_PROBE 1_PROBE 1 + _ MLIN TL16 SUBST = "MSUB1" W = 20 MIL L = 20 MIL SLC SLC4 L = 1.4 nH C = 10,000 pF INDQ L4 L = 22 nH NO OPT{1 nH TO 10 nH} Q = 32 F = 800 MHz MODE = PROPORTIONAL TO FREQUENCY MLIN TL15 SUBST = "MSUB1" W = 60 MIL L = 60 MIL MSTEP STEP5 SUBST = "MSUB1" W1 = 20 MIL W2 = 60 MIL VIA V4 D1 = 25 MIL D2 = 25 MIL H = 31 MIL T = 1.14 MIL V_DC SRC2 VDC = 4 V Figure 12. Avago/EEsof ADS output impedance matching circuit for the ATF-33143 ATF-33143 amplifier. 7 PORT P2 NUM = 2 C C5 C = 0.1 pF grams. It is especially important to insure that the Rollett Stability factor K be greater than 1 over the entire frequency range over which the device has usable gain. See Figure 17. 17 15 GAIN (dB) 13 11 Non-Linear Circuit Analysis Once the circuit has been optimized using the linear analysis with the published S and Noise Parameters, the circuit can be analyzed using the available non-linear Statz model. The Statz model parameters have been optimized by Avago to give accurate results at or near the published bias point of Vds = 4 V and Ids = 80 mA. At a bias point significantly lower than the rated bias point, the model's accuracy diminishes. ADS predicts a nominal +33 dBm output IP3 at 1960 MHz when biased at a Vds = 4 V and Id = 80 mA. ADS can be used to make tradeoffs between OIP3 and output return loss. 9 Conclusion 7 5 0.1 0.6 1.1 1.6 2.1 FREQUENCY (GHz) 2.6 3.1 Figure 14. Simulated noise figure performance vs. frequency. The ATF-33143 ATF-33143 has been shown to yield a very low 0.7 dB noise figure, greater than 13 dB gain and a very high, +32.5 dBm OIP3 at a Vds = 4 V and Id = 80 mA. Test results correlate very well to the Avago/EEsof ADS simulation prediction. 0.9 0 0.8 -1 -2 0.6 -3 RETURN LOSS (dB) NOISE FIGURE (dB) 0.7 0.5 0.4 0.3 0.2 -4 -5 -6 -7 -8 0.1 -9 0 1.8 1.9 2.0 2.1 FREQUENCY (GHz) 2.2 -10 0.1 2.3 Figure 13. Simulated gain performance vs. frequency. ROLLETT STABILITY FACTOR K RETURN LOSS (dB) 2.6 3.1 5 -5 -10 -15 -20 -25 4 3 2 1 0 0.6 1.1 1.6 2.1 FREQUENCY (GHz) 2.6 Figure 16. Simulated output return loss performance vs. frequency. 8 1.1 1.6 2.1 FREQUENCY (GHz) Figure 15. Simulated input return loss vs. frequency. 0 -30 0.1 0.6 3.1 0 2 4 6 FREQUENCY (GHz) 8 10 Figure 17. Simulated rollett stability factor Appendix 1. Determining the Optimum Amount of Source Inductance and has some margin in the design so as to account for S21 variations in the device. Adding additional source inductance has the positive effect of improving input return loss and low frequency stability. A potential down-side is reduced low frequency gain. However, decreased gain also correlates to higher input intercept point. The question then becomes how much source inductance can one add before one has gone too far? A wide-band plot of S21 for an amplifier using the 400 micron ATF-35143 ATF-35143 amplifier is shown in Figure 18. The ATF-35143 ATF-35143 is used in this example because it is more sensitive to source inductance, i.e., high frequency gain is greater with smaller gate width devices. Similar behavior is to be expected using the 800 micron ATF-34143 ATF-34143 but to a lesser degree because of its greater gate width. The plot shown in Figure 18 represents an amplifier that uses minimal source inductance and has a relatively smooth gain roll-off at the higher frequencies. For an amplifier operating in the 2 GHz frequency range, excessive source inductance will manifest itself in the form of a gain peak in the 6 to 10 GHz frequency range. Normally the high frequency gain rolloff will be gradual and smooth. Adding source inductance begins to add bumps or gain peaks to the once smooth gain roll-off. The source inductance, while having a degenerative effect at low frequencies, is having a regenerative effect at higher frequencies. This shows up as a very high frequency gain peak in S21 and also shows up as input return loss S11 becoming more positive. Some shift in upper frequency performance is OK as long as the amount of source inductance is fixed The wideband gain plot shown in Figure 19 is for the same amplifier that uses additional source inductance. Increased source inductance improves low frequency stability by lowering gain. Input return loss will also be improved while noise figure will stay relatively constant. The effect of adding additional source inductance can be seen as some gain peaking in the 6 GHz frequency range. This level of gain peaking shown in Figure 19 is not considered a problem because of its relatively low level compared to the in-band gain. 20 GAIN (dB) 10 0 -10 -20 0 5 FREQUENCY (GHz) 10 Figure 18. Wide-band gain plot of amplifier using minimal source inductance. Excessive source inductance will cause gain to peak at the higher frequencies and may even cause the input and output return loss to be positive. Adding excessive source inductance will most likely generate a gain peak at about 6 GHz which could approach 20 to 30 dB. Its effect can be seen in Figure 20. The end result is poor amplifier stability, especially when the amplifier is placed in a housing with walls and a cover. Larger gate width devices such as the 800 micron ATF-34143 ATF-34143 will be less sensitive to source inductance than the smaller gate width devices and can therefore tolerate more source inductance before instabilities occur. The wide-band gain plot does give the designer a good overall picture as to what to look for when analyzing the effect of excessive source inductance. 20 20 15 15 10 GAIN (dB) GAIN (dB) 10 5 0 0 -5 -5 -10 -10 0 5 FREQUENCY (GHz) 10 Figure 19. Wide-band gain plot of amplifier with an acceptable amount of source inductance. 9 5 0 5 FREQUENCY (GHz) 10 Figure 20. Wide-band gain plot of amplifier with an unacceptable amount of source inductance producing undesirable gain peaking. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. 5968-9877E 5968-9877E April 6, 2007