AT91SAM7X256 AT91SAM7X128 AT91SAM7X256/ 6120C ISO7816 RS485 AT91SAM7X256/128 - Datasheet Archive

 

· Incorporates the ARM7TDMI® ARM® Thumb® Processor · · · · · ·

 

Features · Incorporates the ARM7TDMI® ARM® Thumb® Processor · · · · · · · · · · · · ­ High-performance 32-bit RISC Architecture ­ High-density 16-bit Instruction Set ­ Leader in MIPS/Watt ­ Embedded ICETM In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash ­ 256 Kbytes (AT91SAM7X256 AT91SAM7X256) Organized in 1024 Pages of 256 Bytes ­ 128 Kbytes (AT91SAM7X128 AT91SAM7X128) Organized in 512 Pages of 256 Bytes ­ Single Cycle Access at Up to 30 MHz in Worst Case Conditions ­ Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed ­ Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms ­ 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit ­ Fast Flash Programming Interface for High Volume Production Internal High-speed SRAM, Single-cycle Access at Maximum Speed ­ 64 Kbytes (AT91SAM7X256 AT91SAM7X256) ­ 32 Kbytes (AT91SAM7X128 AT91SAM7X128) Memory Controller (MC) ­ Embedded Flash Controller, Abort Status and Misalignment Detection Reset Controller (RSTC) ­ Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector ­ Provides External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR) ­ Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL Power Management Controller (PMC) ­ Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode ­ Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) ­ Individually Maskable, Eight-level Priority, Vectored Interrupt Sources ­ Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) ­ 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) ­ 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) ­ 12-bit key-protected Programmable Counter ­ Provides Reset or Interrupt Signals to the System ­ Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Real-time Timer (RTT) ­ 32-bit Free-running Counter with Alarm ­ Runs Off the Internal RC Oscillator Two Parallel Input/Output Controllers (PIO) ­ Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os ­ Input Change Interrupt Capability on Each I/O Line ­ Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output AT91 ARM® Thumb®-based Microcontrollers AT91SAM7X256/ AT91SAM7X256/ AT91SAM7X128 AT91SAM7X128 Preliminary 6120C 6120C­ATARM­25-Oct-05 · Thirteen Peripheral DMA Controller (PDC) Channels · One USB 2.0 Full Speed (12 Mbits per second) Device Port ­ On-chip Transceiver, 1352-byte Configurable Integrated FIFOs · One Ethernet MAC 10/100 base-T · · · · · · · · · · · · · · 2 ­ Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) ­ Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive One Part 2.0A and Part 2.0B Compliant CAN Controller ­ Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter One Synchronous Serial Controller (SSC) ­ Independent Clock and Frame Sync Signals for Each Receiver and Transmitter ­ I²S Analog Interface Support, Time Division Multiplex Support ­ High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Two Universal Synchronous/Asynchronous Receiver Transmitters (USART) ­ Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation ­ Support for ISO7816 ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 RS485 Support ­ Full Modem Line Support on USART1 Two Master/Slave Serial Peripheral Interfaces (SPI) ­ 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counter (TC) ­ Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel ­ Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit Power Width Modulation Controller (PWMC) One Two-wire Interface (TWI) ­ Master Mode Support Only, All Two-wire Atmel EEPROMs Supported One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BATM Boot Assistance ­ Default Boot program ­ Interface with SAM-BA Graphic User Interface IEEE 1149.1 JTAG Boundary Scan on All Digital Pins 5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each Power Supplies ­ Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components ­ 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply ­ 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: Up to 55 MHz at 1.65V and 85° C Worst Case Conditions Available in a 100-lead LQFP Green Package AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 1. Description Atmel's AT91SAM7X256/128 AT91SAM7X256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and 64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM7X256/128 AT91SAM7X256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the AT91SAM7X256/128 AT91SAM7X256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring communication over, for example, Ethernet, CAN wired and Zigbee ® wireless networks. 2. Configuration Summary of the AT91SAM7X256 AT91SAM7X256 and AT91SAM7X128 AT91SAM7X128 The AT91SAM7X256 AT91SAM7X256 and AT91SAM7X128 AT91SAM7X128 differ only in memory sizes. Table 2-1 summarizes the configurations of the two devices. Table 2-1. Configuration Summary Device Flash SRAM AT91SAM7X256 AT91SAM7X256 256K bytes 64K bytes AT91SAM7X128 AT91SAM7X128 128K bytes 32K bytes 3 6120C 6120C­ATARM­25-Oct-05 3. AT91SAM7X256/128 AT91SAM7X256/128 Block Diagram Figure 3-1. AT91SAM7X256/128 AT91SAM7X256/128 Block Diagram TDI TDO TMS TCK ICE JTAG SCAN ARM7TDMI Processor JTAGSEL 1.8 V Voltage Regulator System Controller TST FIQ VDDCORE AIC VDDIO Memory Controller PIO IRQ0-IRQ1 SRAM DBGU Embedded Flash Controller PDC Address Decoder Abort Status DRXD DTXD VDDIN GND VDDOUT Misalignment Detection 64/32 Kbytes PDC PCK0-PCK3 PLLRC XIN XOUT OSC VDDFLASH PLL Flash ERASE 256/128 Kbytes PMC RCOSC Peripheral Bridge VDDCORE VDDFLASH BOD Peripheral DMA Controller VDDCORE POR Reset Controller ROM PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1 Fast Flash Programming Interface 13 Channels NRST PIT APB SAM-BA WDT RTT DMA FIFO PIOB PIO PIOA Ethernet MAC 10/100 PDC USART0 PDC PDC USB Device USART1 PDC Transceiver VDDFLASH FIFO PWMC PDC PIO PDC SPI0 SSC PDC PDC PIO RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 RI1 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 PDC Timer Counter SPI1 TC0 PDC PDC TC1 TC2 ADC ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL, ECRSDV ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 EF100 TWI CAN DDM DDP PWM0 PWM1 PWM2 PWM3 TF TK TD RD RK RF TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK CANRX CANTX ADVREF 4 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 4. Signal Description Table 4-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDIN Voltage Regulator and ADC Power Supply Input Power 3V to 3.6V VDDOUT Voltage Regulator Output Power 1.85V VDDFLASH Flash and USB Power Supply Power 3V to 3.6V VDDIO I/O Lines Power Supply Power 3V to 3.6V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.95V GND Ground Ground Clocks, Oscillators and PLLs XIN Main Oscillator Input XOUT Main Oscillator Output PLLRC PLL Filter PCK0 - PCK3 Input Programmable Clock Output Output Input Output ICE and JTAG TCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistor. TDO Test Data Out TMS Test Mode Select Input No pull-up resistor. JTAGSEL JTAG Selection Input Pull-down resistor. Output Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Input High Pull-down resistor I/O Low Pull-Up resistor, Open Drain Output Input High Pull-down resistor Reset/Test NRST Microcontroller Reset TST Test Mode Select Debug Unit DRXD Debug Receive Data DTXD Input Debug Transmit Data Output AIC IRQ0 - IRQ1 External Interrupt Inputs Input FIQ Fast Interrupt Input Input PA0 - PA30 Parallel IO Controller A I/O Pulled-up input at reset PB0 - PB30 Parallel IO Controller B I/O Pulled-up input at reset PIO 5 6120C 6120C­ATARM­25-Oct-05 Table 4-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments USB Device Port DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog USART SCK0 - SCK1 Serial Clock I/O TXD0 - TXD1 Transmit Data I/O RXD0 - RXD1 Receive Data Input RTS0 - RTS1 Request To Send CTS0 - CTS1 Clear To Send Input DCD1 Data Carrier Detect Input DTR1 Data Terminal Ready DSR1 Data Set Ready Input RI1 Ring Indicator Input Output Output Synchronous Serial Controller TD Transmit Data Output RD Receive Data Input TK Transmit Clock I/O RK Receive Clock I/O TF Transmit Frame Sync I/O RF Receive Frame Sync I/O Timer/Counter TCLK0 - TCLK2 External Clock Inputs Input TIOA0 - TIOA2 I/O Line A I/O TIOB0 - TIOB2 I/O Line B I/O PWM Controller PWM0 - PWM3 PWM Channels Output Serial Peripheral Interface - SPIx SPIx_MISO Master In Slave Out I/O SPIx_MOSI Master Out Slave In I/O SPIx_SPCK SPI Serial Clock I/O SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low Two-wire Interface TWD Two-wire Serial Data I/O TWCK Two-wire Serial Clock I/O 6 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary Table 4-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments Analog-to-Digital Converter AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset AD4-AD7 Analog Inputs Analog Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference Input Analog Fast Flash Programming Interface PGMEN0-PGMEN1 Programming Enabling Input PGMM0-PGMM3 Programming Mode Input PGMD0-PGMD15 PGMD0-PGMD15 Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low PGMCK Programming Clock Input PGMNCMD Programming Command Input Low CAN Controller CANRX CAN Input CANTX Input CAN Output Output Ethernet MAC 10/100 EREFCK Reference Clock Input RMII only ETXCK Transmit Clock Input MII only ERXCK Receive Clock Input MII only ETXEN Transmit Enable Output ETX0 - ETX3 Transmit Data Output ETX0 - ETX1 only in RMII ETXER Transmit Coding Error Output MII only ERXDV Receive Data Valid Input MII only ECRSDV Carrier Sense and Data Valid Input RMII only ERX0 - ERX3 Receive Data Input ERX0 - ERX1 only in RMII ERXER Receive Error Input ECRS Carrier Sense Input MII only ECOL Collision Detected Input MII only EMDC Management Data Clock EMDIO Management Data Input/Output EF100 EF100 Force 100 Mbits/sec. Output I/O Output High RMII only 7 6120C 6120C­ATARM­25-Oct-05 5. Package The AT91SAM7X256/128 AT91SAM7X256/128 is available in 100-lead LQFP package. 5.1 100-lead LQFP Mechanical Overview Figure 5-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 5-1. 100-lead LQFP Package Pinout (Top View) 75 51 76 50 100 26 1 5.2 8 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TDI GND PB16 PB4 PA23/PGMD11 PA23/PGMD11 PA24/PGMD12 PA24/PGMD12 NRST TST PA25/PGMD13 PA25/PGMD13 PA26/PGMD14 PA26/PGMD14 VDDIO VDDCORE PB18 PB19 PB20 PB21 PB22 GND PB23 PB24 PB25 PB26 PA27/PGMD15 PA27/PGMD15 PA28 PA29 AT91SAM7X256/128 AT91SAM7X256/128 Pinout Table 5-1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 25 Pinout in 100-lead TQFP Package ADVREF GND AD4 AD5 AD6 AD7 VDDOUT VDDIN PB27/AD0 PB27/AD0 PB28/AD1 PB28/AD1 PB29/AD2 PB29/AD2 PB30/AD3 PB30/AD3 PA8/PGMM0 PA9/PGMM1 VDDCORE GND VDDIO PA10/PGMM2 PA10/PGMM2 PA11/PGMM3 PA11/PGMM3 PA12/PGMD0 PA12/PGMD0 PA13/PGMD1 PA13/PGMD1 PA14/PGMD2 PA14/PGMD2 PA15/PGMD3 PA15/PGMD3 PA16/PGMD4 PA16/PGMD4 PA17/PGMD5 PA17/PGMD5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA18/PGMD6 PA18/PGMD6 PB9 PB8 PB14 PB13 PB6 GND VDDIO PB5 PB15 PB17 VDDCORE PB7 PB12 PB0 PB1 PB2 PB3 PB10 PB11 PA19/PGMD7 PA19/PGMD7 PA20/PGMD8 PA20/PGMD8 VDDIO PA21/PGMD9 PA21/PGMD9 PA22/PGMD10 PA22/PGMD10 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TDO JTAGSEL TMS TCK PA30 PA0/PGMEN0 PA1/PGMEN1 GND VDDIO PA3 PA2 VDDCORE PA4/PGMNCMD PA5/PGMRDY PA6/PGMNOE PA7/PGMNVALID ERASE DDM DDP VDDFLASH GND XIN/PGMCK XOUT PLLRC VDDPLL AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6. Power Considerations 6.1 Power Supplies The AT91SAM7X256/128 AT91SAM7X256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: · VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. In order to decrease current consumption , if the voltage regulator and the ADC are not used, VDDIN, ADVREF, AD5, AD6 and AD7 should be connected to GND. In this case, VDDOUT should be left unconnected. · VDDOUT pin. It is the output of the 1.8V voltage regulator. · VDDIO pin. It powers the I/O lines; voltage ranges from 3.0V to 3.6V, 3.3V nominal. · VDDFLASH pin. It powers the USB transceivers and a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal. · VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. · VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin. No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. 6.2 Power Consumption The AT91SAM7X256/128 AT91SAM7X256/128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. The dynamic power consumption on VDDCORE is less than 90 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA. 6.3 Voltage Regulator The AT91SAM7X256/128 AT91SAM7X256/128 embeds a voltage regulator that is managed by the System Controller. In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current. The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and GND. 9 6120C 6120C­ATARM­25-Oct-05 Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 6.4 Typical Powering Schematics The AT91SAM7X256/128 AT91SAM7X256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 6-1 shows the power schematics to be used for USB bus-powered systems. Figure 6-1. 3.3V System Single Power Supply Schematic VDDFLASH Power Source ranges from 4.5V (USB) to 18V DC/DC Converter VDDIO VDDIN Voltage Regulator 3.3V VDDOUT VDDCORE VDDPLL 10 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 7. I/O Lines Considerations 7.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. 7.2 Test Pin The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7X256/128 AT91SAM7X256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low. Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results. 7.3 Reset Pin The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset all the components of the system. The NRST pin integrates a permanent pull-up resistor to VDDIO. 7.4 ERASE Pin The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing time is 200 ms. 7.5 PIO Controller Lines All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset. 11 6120C 6120C­ATARM­25-Oct-05 7.6 I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. 12 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 8. Processor and Architecture 8.1 ARM7TDMI Processor · RISC processor based on ARMv4T Von Neumann architecture ­ Runs at up to 55 MHz, providing 0.9 MIPS/MHz · Two instruction sets ­ ARM® high-performance 32-bit instruction set ­ Thumb® high code density 16-bit instruction set · Three-stage pipeline architecture ­ Instruction Fetch (F) ­ Instruction Decode (D) ­ Execute (E) 8.2 Debug and Test Features · Integrated Embedded ICETM (embedded in-circuit emulator) ­ Two watchpoint units ­ Test access port accessible through a JTAG protocol ­ Debug communication channel · Debug Unit ­ Two-pin UART ­ Debug communication channel interrupt handling ­ Chip ID Register · IEEE1149 IEEE1149.1 JTAG Boundary-scan on all digital pins 8.3 Memory Controller · Programmable Bus Arbiter ­ Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA Controller · Address decoder provides selection signals for ­ Three internal 1 Mbyte memory areas ­ One 256 Mbyte embedded peripheral area · Abort Status Registers ­ Source, Type and all parameters of the access leading to an abort are saved ­ Facilitates debug by detection of bad pointers · Misalignment Detector ­ Alignment checking of all data accesses ­ Abort generation in case of misalignment · Remap Command ­ Remaps the SRAM in place of the embedded non-volatile memory ­ Allows handling of dynamic exception vectors 13 6120C 6120C­ATARM­25-Oct-05 · Embedded Flash Controller ­ Embedded Flash interface, up to three programmable wait states ­ Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states ­ Key-protected program, erase and lock/unlock sequencer ­ Single command for erasing, programming and locking operations ­ Interrupt generation in case of forbidden operation 8.4 Peripheral DMA Controller · Handles data transfer between peripherals and memories · Thirteen channels ­ Two for each USART ­ Two for the Debug Unit ­ Two for the Serial Synchronous Controller ­ Two for each Serial Peripheral Interface ­ One for the Analog-to-digital Converter · Low bus arbitration overhead ­ One Master Clock cycle needed for a transfer from memory to peripheral ­ Two Master Clock cycles needed for a transfer from peripheral to memory · Next Pointer management for reducing interrupt latency requirements 14 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 9. Memory 9.1 AT91SAM7X256 AT91SAM7X256 · 256 Kbytes of Flash Memory ­ 1024 pages of 256 bytes ­ Fast access time, 30 MHz single-cycle access in Worst Case conditions ­ Page programming time: 6 ms, including page auto-erase ­ Page programming without auto-erase: 3 ms ­ Full chip erase time: 15 ms ­ 10,000 write cycles, 10-year data retention capability ­ 16 lock bits, each protecting 16 sectors of 64 pages ­ Protection Mode to secure contents of the Flash · 64 Kbytes of Fast SRAM ­ Single-cycle access at full speed 9.2 AT91SAM7X128 AT91SAM7X128 · 128 Kbytes of Flash Memory ­ 512 pages of 256 bytes ­ Fast access time, 30 MHz single-cycle access in Worst Case conditions ­ Page programming time: 6 ms, including page auto-erase ­ Page programming without auto-erase: 3 ms ­ Full chip erase time: 15 ms ­ 10,000 write cycles, 10-year data retention capability ­ 8 lock bits, each protecting 8 sectors of 64 pages ­ Protection Mode to secure contents of the Flash · 32 Kbytes of Fast SRAM ­ Single-cycle access at full speed 15 6120C 6120C­ATARM­25-Oct-05 9.3 9.3.1 Memory Mapping Internal RAM · The AT91SAM7X256 AT91SAM7X256 embeds a high-speed 64-Kbyte SRAM bank · The AT91SAM7X128 AT91SAM7X128 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 9.3.2 Internal ROM The AT91SAM7X256/128 AT91SAM7X256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains FFPI and SAM-BA program. 9.3.3 Internal Flash · The AT91SAM7X256 AT91SAM7X256 features one bank of 256 Kbytes of Flash · The AT91SAM7X128 AT91SAM7X128 features one bank of 128 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash. This GPNVM bit can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface. Setting the GPNVM Bit 2 selects the boot from the Flash. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from the ROM by default. Figure 9-1. Internal Memory Mapping with GPNVM Bit 2 = 0 (default) 0x0000 0000 0x000F FFFF ROM Before Remap SRAM After Remap 1 M Bytes 0x0010 0000 Internal FLASH 1 M Bytes Internal SRAM 1 M Bytes Internal ROM 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000 Undefined Areas (Abort) 252 M Bytes 0x0FFF FFFF 16 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary Figure 9-2. Internal Memory Mapping with GPNVM Bit 2 = 1 0x0000 0000 0x000F FFFF Flash Before Remap SRAM After Remap 1 M Bytes 0x0010 0000 Internal FLASH 1 M Bytes Internal SRAM 1 M Bytes Internal ROM 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000 Undefined Areas (Abort) 252 M Bytes 0x0FFF FFFF 9.4 Embedded Flash 9.4.1 Flash Overview · The Flash of the AT91SAM7X256 AT91SAM7X256 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. · The Flash of the AT91SAM7X128 AT91SAM7X128 is organized in 512 pages of 256 bytes. It reads as 32,768 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. When Flash is not used (read or write access), it is automatically placed into standby mode. 9.4.2 Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows: · programming of the access parameters of the Flash (number of wait states, timings, etc.) · starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. · getting the end status of the last command · getting error status · programming interrupts on the end of the last commands or on errors The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. 17 6120C 6120C­ATARM­25-Oct-05 9.4.3 9.4.3.1 Lock Regions AT91SAM7X256 AT91SAM7X256 The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X256 AT91SAM7X256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region's erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 16 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 9.4.3.2 AT91SAM7X128 AT91SAM7X128 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X128 AT91SAM7X128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region's erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 8 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 9.4.4 Security Bit Feature The AT91SAM7X256/128 AT91SAM7X256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application. 9.4.5 Non-volatile Brownout Detector Control Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. These two GPNVM bits can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface. 18 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary · GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. · The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. 9.4.6 Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 9.5 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high. 9.6 SAM-BA Boot Assistant The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program insitu the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. · Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection. · Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when the GPNVM Bit 2 is set to 0. 19 6120C 6120C­ATARM­25-Oct-05 10. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 10-1. System Controller Block Diagram System Controller jtag_nreset Boundary Scan TAP Controller nirq irq0-irq1 Advanced Interrupt Controller fiq periph_irq[2.19] nfiq proc_nreset ARM7TDMI PCK int debug pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq ice_nreset force_ntrst MCK periph_nreset dbgu_irq Debug Unit force_ntrst dbgu_txd dbgu_rxd security_bit Periodic Interval Timer SLCK periph_nreset cal gpnvm[0] ice_nreset jtag_nreset POR efc_irq bod_rst_en Memory Controller MCK proc_nreset Reset Controller periph_nreset proc_nreset flash_poe rstc_irq NRST Voltage Regulator Mode Controller standby Voltage Regulator cal SLCK RCOSC SLCK periph_clk[2.18] UDPCK pck[0-3] XIN OSC Embedded Flash gpnvm[0.2] wdt_fault WDRPROC gpnvm[1] flash_wrdis BOD wdt_irq flash_poe flash_wrdis cal SLCK debug idle proc_nreset en rtt_irq Watchdog Timer periph_nreset pit_irq Real-Time Timer MCK debug MAINCK XOUT Power Management Controller periph_clk[11] PCK periph_nreset UDPCK USB Device Port periph_irq[11] MCK usb_suspend PLLRC PLL PLLCK pmc_irq int idle periph_nreset periph_clk[4.19] usb_suspend periph_nreset irq0-irq1 periph_clk[2-3] dbgu_rxd Embedded Peripherals periph_irq{2-3] periph_nreset PIO Controller fiq periph_irq[4.19] dbgu_txd in PA0-PA30 PA0-PA30 PB0-PB30 PB0-PB30 20 out enable AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 10.1 System Controller Mapping The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 10-2 shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space. Figure 10-2. System Controller Mapping Address Peripheral Peripheral Name Size 0xFFFF F000 Advanced Interrupt Controller 512 Bytes/128 registers DBGU Debug Unit 512 Bytes/128 registers PIOA PIO Controller A 512 Bytes/128 registers PIOB PIO Controller B 512 Bytes/128 registers PMC Power Management Controller 256 Bytes/64 registers RSTC Reset Controller 16 Bytes/4 registers RTT Real-time Timer 16 Bytes/4 registers PIT Periodic Interval Timer 16 Bytes/4 registers Watchdog Timer 16 Bytes/4 registers Voltage Regulator Mode Controller 4 Bytes/1 register Memory Controller 256 Bytes/64 registers AIC 0xFFFF F1FF 0xFFFF F200 0xFFFF F3FF 0xFFFF F400 0xFFFF F5FF 0xFFFF F600 0xFFFF F7FF 0xFFFF F800 Reserved 0xFFFF FBFF 0xFFFF FC00 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F Reserved 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F WDT Reserved 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 VREG Reserved MC 0xFFFF FFFF 21 6120C 6120C­ATARM­25-Oct-05 10.2 Reset Controller · Based on one power-on reset cell and one brownout detector · Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset · Controls the internal resets and the NRST pin output · Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. 10.2.1 Brownout Detector and Power-on Reset The AT91SAM7X256/X128 AT91SAM7X256/X128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or powerdown sequences or if brownouts occur on the power supplies. The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device. The brownout detector monitors the VDDCORE and VDDFLASH levels during operation by comparing them to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE or VDDFLASH. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot18-, defined as Vbot18 - hyst/2), the brownout output is immediately activated. When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs. The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated. When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger level (Vbot33-, defined as Vbot33 - hyst/2), the brownout output is immediately activated. When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs. The VDDFLASH threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of ± 3.5% and is factory calibrated. The brownout detector is low-power, as it consumes less than 28 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash. 22 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 10.3 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: · RC Oscillator ranges between 22 KHz and 42 KHz · Main Oscillator frequency ranges between 3 and 20 MHz · Main Oscillator can be bypassed · PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 10-3. Clock Generator Block Diagram Clock Generator Embedded RC Oscillator XIN Slow Clock SLCK Main Oscillator Main Clock MAINCK PLL and Divider PLL Clock PLLCK XOUT PLLRC Status Control Power Management Controller 23 6120C 6120C­ATARM­25-Oct-05 10.4 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: · the Processor Clock PCK · the Master Clock MCK · the USB Clock UDPCK · all the peripheral clocks, independently controllable · four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. Figure 10-4. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK PCK int Idle Mode Prescaler /1,/2,/4,.,/64 MCK Peripherals Clock Controller periph_clk[2.18] ON/OFF Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64 pck[0.3] USB Clock Controller ON/OFF PLLCK 10.5 Divider /1,/2,/4 UDPCK Advanced Interrupt Controller · Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor · Individually maskable and vectored interrupt sources ­ Source 0 is reserved for the Fast Interrupt Input (FIQ) ­ Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) ­ Other sources control the peripheral interrupts or external interrupts ­ Programmable edge-triggered or level-sensitive internal sources ­ Programmable positive/negative edge-triggered or high/low level-sensitive external sources · 8-level Priority Controller ­ Drives the normal interrupt nIRQ of the processor ­ Handles priority of the interrupt sources 24 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary ­ Higher priority interrupts can be served during service of lower priority interrupt · Vectoring ­ Optimizes interrupt service routine branch and execution ­ One 32-bit vector register per interrupt source ­ Interrupt vector register reads the corresponding current interrupt vector · Protect Mode ­ Easy debugging by preventing automatic operations · Fast Forcing ­ Permits redirecting any interrupt source on the fast interrupt · General Interrupt Mask ­ Provides processor synchronization on events without triggering an interrupt 10.6 Debug Unit · Comprises: ­ One two-pin UART ­ One Interface for the Debug Communication Channel (DCC) support ­ One set of Chip ID Registers ­ One Interface providing ICE Access Prevention · Two-pin UART ­ USART-compatible User Interface ­ Programmable Baud Rate Generator ­ Parity, Framing and Overrun Error ­ Automatic Echo, Local Loopback and Remote Loopback Channel Modes · Debug Communication Channel Support ­ Offers visibility of COMMRX and COMMTX signals from the ARM Processor · Chip ID Registers ­ Identification of the device revision, sizes of the embedded memories, set of peripherals ­ Chip ID is 0x275B 0940 (VERSION 0) for AT91SAM7X256 AT91SAM7X256 ­ Chip ID is 0x275A 0740 (VERSION 0) for AT91SAM7X128 AT91SAM7X128 10.7 Period Interval Timer · 20-bit programmable counter plus 12-bit interval counter 10.8 Watchdog Timer · 12-bit key-protected Programmable Counter running on prescaled SLCK · Provides reset or interrupt signals to the system · Counter may be stopped while the processor is in debug state or in idle mode 10.9 Real-time Timer · 32-bit free-running counter with alarm running on prescaled SLCK · Programmable 16-bit prescaler for SLCK accuracy compensation 25 6120C 6120C­ATARM­25-Oct-05 10.10 PIO Controllers · Two PIO Controllers, each controlling 31 I/O lines · Fully programmable through set/clear registers · Multiplexing of two peripheral functions per I/O line · For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) ­ Input change interrupt ­ Half a clock period glitch filter ­ Multi-drive option enables driving in open drain ­ Programmable pull-up on each I/O line ­ Pin data status register, supplies visibility of the level on the pin at any time · Synchronous output, provides Set and Clear of several I/O lines in a single write 10.11 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 26 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 11. Peripherals 11.1 Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 11-1. User Peripheral Mapping Peripheral Name Size Timer/Counter 0, 1 and 2 16 Kbytes USB Device Port 16 Kbytes Two-Wire Interface 16 Kbytes 0xF000 0000 Reserved 0xFFF9 FFFF 0xFFFA 0000 TC0, TC1, TC2 0xFFFA 3FFF 0xFFFA 4000 Reserved 0xFFFA FFFF 0xFFFB 0000 UDP 0xFFFB 3FFF 0xFFFB 4000 Reserved 0xFFFB 7FFF 0xFFFB 8000 TWI 0xFFFB BFFF 0xFFFB C000 Reserved 0xFFFB FFFF 0xFFFC 0000 USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 16 Kbytes USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 16 Kbytes 0xFFFC 3FFF 0xFFFC 4000 0xFFFC 7FFF 0xFFFC 8000 Reserved 0xFFFC BFFF 0xFFFC C000 PWMC PWM Controller 16 Kbytes CAN CAN Controller 16 Kbytes Serial Synchronous Controller 16 Kbytes Analog-to-Digital Converter 16 Kbytes Ethernet MAC 16 Kbytes SPI0 Serial Peripheral Interface 0 16 Kbytes SPI1 Serial Peripheral Interface 1 16 Kbytes 0xFFFC FFFF 0xFFFD 0000 0xFFFD 3FFF 0xFFFD 4000 SSC 0xFFFD 7FFF 0xFFFD 8000 ADC 0xFFFD BFFF 0xFFFD C000 EMAC 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 0xFFFE 7FFF 0xFFFE 8000 Reserved 0xFFFE FFFF 27 6120C 6120C­ATARM­25-Oct-05 11.2 Peripheral Multiplexing on PIO Lines The AT91SAM7X256/128 AT91SAM7X256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller. Table 11-1 on page 29 and Table 11-2 on page 30 defines how the I/O lines of the peripherals A, B or the analog inputs are multiplexed on the PIO Controller A and PIO Controller B. The two columns "Function" and "Comments" have been inserted for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only, may be duplicated in the table. At reset, all I/O lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected. 28 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 11.3 PIO Controller A Multiplexing Table 11-1. Multiplexing on PIO Controller A PIO Controller A Peripheral B Application Usage I/O Line Peripheral A Comments PA0 RXD0 High-Drive PA1 TXD0 High-Drive PA2 SCK0 SPI1_NPCS1 High-Drive PA3 RTS0 SPI1_NPCS2 High-Drive PA4 CTS0 SPI1_NPCS3 PA5 RXD1 PA6 TXD1 PA7 SCK1 SPI0_NPCS1 PA8 RTS1 SPI0_NPCS2 PA9 CTS1 SPI0_NPCS3 PA10 TWD PA11 TWCK PA12 SPI_NPCS0 PA13 SPI0_NPCS1 PCK1 PA14 SPI0_NPCS2 IRQ1 PA15 SPI0_NPCS3 TCLK2 PA16 SPI0_MISO PA17 SPI0_MOSI PA18 SPI0_SPCK PA19 CANRX PA20 CANTX PA21 TF SPI1_NPCS0 PA22 TK SPI1_SPCK PA23 TD SPI1_MOSI PA24 RD SPI1_MISO PA25 RK SPI1_NPCS1 PA26 RF SPI1_NPCS2 PA27 DRXD PCK3 PA28 DTXD PA29 FIQ SPI1_NPCS3 PA30 IRQ0 Function Comments PCK2 29 6120C 6120C­ATARM­25-Oct-05 11.4 PIO Controller B Multiplexing Table 11-2. Multiplexing on PIO Controller B PIO Controller A Application Usage I/O Line Peripheral B PB0 ETXCK/EREFCK PCK0 PB1 ETXEN PB2 ETX0 PB3 ETX1 PB4 ECRS PB5 ERX0 PB6 ERX1 PB7 ERXER PB8 EMDC PB9 EMDIO PB10 ETX2 SPI1_NPCS1 PB11 ETX3 SPI1_NPCS2 PB12 ETXER TCLK0 PB13 ERX2 SPI0_NPCS1 PB14 ERX3 SPI0_NPCS2 PB15 ERXDV/ECRSDV PB16 ECOL SPI1_NPCS3 PB17 ERXCK SPI0_NPCS3 PB18 EF100 EF100 ADTRG PB19 PWM0 TCLK1 PB20 PWM1 PCK0 PB21 PWM2 PCK1 PB22 PWM3 PCK2 PB23 TIOA0 DCD1 PB24 TIOB0 DSR1 PB25 TIOA1 DTR1 PB26 TIOB1 RI1 PB27 TIOA2 PWM0 AD0 PB28 TIOB2 PWM1 AD1 PB29 PCK1 PWM2 AD2 PB30 30 Peripheral A Comments PCK2 PWM3 Function Comments AD3 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 11.5 Peripheral Identifiers The AT91SAM7X256/128 AT91SAM7X256/128 embeds a wide range of peripherals. Table 11-3 defines the Peripheral Identifiers of the AT91SAM7X256/128 AT91SAM7X256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 11-3. Peripheral Identifiers Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 0 AIC Advanced Interrupt Controller FIQ (1) 1 SYSIRQ 2 PIOA Parallel I/O Controller A 3 PIOB Parallel I/O Controller B 4 SPI0 Serial Peripheral Interface 0 5 SPI1 Serial Peripheral Interface 1 6 US0 USART 0 7 US1 USART 1 8 SSC Synchronous Serial Controller 9 TWI Two-wire Interface 10 PWMC Pulse Width Modulation Controller 11 UDP USB device Port 12 TC0 Timer/Counter 0 13 TC1 Timer/Counter 1 14 TC2 Timer/Counter 2 15 CAN CAN Controller 16 EMAC 17 ADC (1) 18 - 29 Reserved 30 AIC Advanced Interrupt Controller IRQ0 31 AIC Advanced Interrupt Controller IRQ1 Note: Ethernet MAC Analog-to Digital Converter 1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller and ADC are continuously clocked. 31 6120C 6120C­ATARM­25-Oct-05 11.6 Ethernet MAC · DMA Master on Receive and Transmit Channels · Compatible with IEEE Standard 802.3 · 10 and 100 Mbit/s operation · Full- and half-duplex operation · Statistics Counter Registers · MII/RMII interface to the physical layer · Interrupt generation to signal receive and transmit completion · 28-byte transmit FIFO and 28-byte receive FIFO · Automatic pad and CRC generation on transmitted frames · Automatic discard of frames received with errors · Address checking logic supports up to four specific 48-bit addresses · Support Promiscuous Mode where all valid received frames are copied to memory · Hash matching of unicast and multicast destination addresses · Physical layer management through MDIO interface · Half-duplex flow control by forcing collisions on incoming frames · Full-duplex flow control with recognition of incoming pause frames · Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames · Multiple buffers per receive and transmit frame · Jumbo frames up to 10240 bytes supported 11.7 Serial Peripheral Interface · Supports communication with external serial devices ­ Four chip selects with external decoder allow communication with up to 15 peripherals ­ Serial memories, such as DataFlash® and 3-wire EEPROMs ­ Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors ­ External co-processors · Master or slave serial peripheral bus interface ­ 8- to 16-bit programmable data length per chip select ­ Programmable phase and polarity per chip select ­ Programmable transfer delays per chip select, between consecutive transfers and between clock and data ­ Programmable delay between consecutive transfers ­ Selectable mode fault detection ­ Maximum frequency at up to Master Clock 11.8 Two-wire Interface · Master Mode only · Compatibility with standard two-wire serial memories 32 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary · One, two or three bytes for slave address · Sequential read/write operations 11.9 USART · Programmable Baud Rate Generator · 5- to 9-bit full-duplex synchronous or asynchronous serial communications ­ 1, 1.5 or 2 stop bits in Asynchronous Mode ­ 1 or 2 stop bits in Synchronous Mode ­ Parity generation and error detection ­ Framing error detection, overrun error detection ­ MSB or LSB first ­ Optional break generation and detection ­ By 8 or by 16 over-sampling receiver frequency ­ Hardware handshaking RTS - CTS ­ Modem Signals Management DTR-DSR-DCD-RI on USART1 ­ Receiver time-out and transmitter timeguard ­ Multi-drop Mode with address generation and detection · RS485 RS485 with driver control signal · ISO7816 ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards ­ NACK handling, error counter with repetition and iteration limit · IrDA modulation and demodulation ­ Communication at up to 115.2 Kbps · Test Modes ­ Remote Loopback, Local Loopback, Automatic Echo 11.10 Serial Synchronous Controller · Provides serial synchronous communication links used in audio and telecom applications · Contains an independent receiver and transmitter and a common clock divider · Offers a configurable frame sync and data length · Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal · Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 11.11 Timer Counter · Three 16-bit Timer Counter Channels ­ Three output compare or two input capture · Wide range of functions including: ­ Frequency measurement ­ Event counting ­ Interval measurement ­ Pulse generation 33 6120C 6120C­ATARM­25-Oct-05 ­ Delay timing ­ Pulse Width Modulation ­ Up/down capabilities · Each channel is user-configurable and contains: ­ Three external clock inputs · Five internal clock inputs, as defined in Table 11-4 Table 11-4. Timer Counter Clocks Assignment TC Clock input Clock TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 MCK/32 TIMER_CLOCK4 MCK/128 MCK/128 TIMER_CLOCK5 MCK/1024 MCK/1024 ­ Two multi-purpose input/output signals ­ Two global registers that act on all three TC channels 11.12 Pulse Width Modulation Controller · Four channels, one 16-bit counter per channel · Common clock generator, providing thirteen different clocks ­ One Modulo n counter providing eleven clocks ­ Two independent linear dividers working on modulo n counter outputs · Independent channel programming ­ Independent enable/disable commands ­ Independent clock selection ­ Independent period and duty cycle, with double buffering ­ Programmable selection of the output waveform polarity ­ Programmable center or left aligned output waveform 11.13 USB Device Port · USB V2.0 full-speed compliant,12 Mbits per second · Embedded USB V2.0 full-speed transceiver · Embedded 1352-byte dual-port RAM for endpoints · Six endpoints ­ Endpoint 0: 8 bytes ­ Endpoint 1 and 2: 64 bytes ping-pong ­ Endpoint 3: 64 bytes ­ Endpoint 4 and 5: 256 bytes ping-pong ­ Ping-pong Mode (two memory banks) for bulk endpoints · Suspend/resume logic 34 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 11.14 CAN Controller · Fully compliant with CAN 2.0A and 2.0B · Bit rates up to 1Mbit/s · Eight object oriented mailboxes each with the following properties: ­ CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message ­ Object configurable to receive (with overwrite or not) or transmit ­ Local tag and mask filters up to 29-bit identifier/channel ­ 32-bit access to data registers for each mailbox data object ­ Uses a 16-bit time stamp on receive and transmit message ­ Hardware concatenation of ID unmasked bitfields to speedup family ID processing ­ 16-bit internal timer for time stamping and network synchronization ­ Programmable reception buffer length up to 8 mailbox objects ­ Priority management between transmission mailboxes ­ Autobaud and listening mode ­ Low power mode and programmable wake-up on bus activity or by the application ­ Data, remote, error and overload frame handling 11.15 Analog-to-Digital Converter · 8-channel ADC · 10-bit 384 Ksamples/sec. Successive Approximation Register ADC · -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity · Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs · External voltage reference for better accuracy on low voltage inputs · Individual enable and disable of each channel · Multiple trigger sources ­ Hardware or software trigger ­ External trigger pin ­ Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger · Sleep Mode and conversion sequencer ­ Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels · Four of eight analog inputs shared with digital signals 35 6120C 6120C­ATARM­25-Oct-05 36 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 12. ARM7TDMI Processor Overview 12.1 Overview The ARM7TDMI core executes both the 32-bit ARM® and 16-bit Thumb® instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages. The main features of the ARM7tDMI processor are: · ARM7TDMI Based on ARMv4T Architecture · Two Instruction Sets ­ ARM® High-performance 32-bit Instruction Set ­ Thumb® High Code Density 16-bit Instruction Set · Three-Stage Pipeline Architecture ­ Instruction Fetch (F) ­ Instruction Decode (D) ­ Execute (E) 37 6120C 6120C­ATARM­25-Oct-05 12.2 ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B 0210B) 12.2.1 Instruction Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 12.2.2 Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries. Unaligned data access behavior depends on which instruction is used where. 12.2.3 ARM7TDMI Operating Mode The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes: User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources. 12.2.4 ARM7TDMI Registers The ARM7TDMI processor has a total of 37registers: · 31 general-purpose 32-bit registers · 6 status registers These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer. At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer. 38 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary Table 12-1. ARM7TDMI ARM Modes and Registers Layout User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ Mode-specific banked registers Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a generalpurpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor. 12.2.4.1 Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers. 39 6120C 6120C­ATARM­25-Oct-05 A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 12.2.4.2 Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: · four ALU flags (Negative, Zero, Carry, and Overflow) · two interrupt disable bits (one for each type of interrupt) · one bit to indicate ARM or Thumb execution · five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception. 12.2.4.3 Exception Types The ARM7TDMI supports five types of exception and a privileged processing mode for each type. The types of exceptions are: · fast interrupt (FIQ) · normal interrupt (IRQ) · memory aborts (used to implement memory protection or virtual memory) · attempted execution of an undefined instruction · software interrupts (SWIs) Exceptions are generated by internal and external sources. More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways: · by using a data-processing instruction with the S-bit set, and the PC as the destination · by using the Load Multiple with Restore CPSR instruction (LDM) 12.2.5 ARM Instruction Set Overview The ARM instruction set is divided into: · Branch instructions · Data processing instructions · Status register transfer instructions · Load and Store instructions · Coprocessor instructions · Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 12-2 gives the ARM instruction mnemonic list. 40 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary Table 12-2. ARM Instruction Mnemonic List Mnemonic Mnemonic Operation MOV Move CDP Coprocessor Data Processing ADD Add MVN Move Not SUB Subtract ADC Add with Carry RSB Reverse Subtract SBC Subtract with Carry CMP Compare RSC Reverse Subtract with Carry TST Test CMN Compare Negated AND Logical AND TEQ Test Equivalence EOR Logical Exclusive OR BIC Bit Clear MUL Multiply ORR Logical (inclusive) OR SMULL Sign Long Multiply MLA Multiply Accumulate SMLAL Signed Long Multiply Accumulate UMULL Unsigned Long Multiply MSR Move to Status Register UMLAL Unsigned Long Multiply Accumulate B Branch MRS Move From Status Register BX Branch and Exchange BL Branch and Link LDR Load Word SWI Software Interrupt LDRSH Load Signed Halfword STR Store Word LDRSB Load Signed Byte STRH Store Half Word LDRH Load Half Word STRB Store Byte LDRB Load Byte STRBT Store Register Byte with Translation LDRBT Load Register Byte with Translation STRT Store Register with Translation LDRT Load Register with Translation STM Store Multiple LDM Load Multiple SWPB Swap Byte SWP Swap Word MRC Move From Coprocessor MCR Move To Coprocessor STC Store From Coprocessor LDC 12.2.6 Operation Load To Coprocessor Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: · Branch instructions · Data processing instructions · Load and Store instructions · Load and Store Multiple instructions · Exception-generating instruction In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the 41 6120C 6120C­ATARM­25-Oct-05 Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 12-3 gives the Thumb instruction mnemonic list. Table 12-3. Thumb Instruction Mnemonic List Mnemonic Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry CMP Compare CMN Compare Negated TST Test NEG Negate AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR LSL Logical Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right MUL Multiply B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH 42 Operation Push Register to stack POP Pop Register from stack AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 13. Debug and Test Features 13.1 Description The AT91SAM7X AT91SAM7X Series features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 13.2 Block Diagram Figure 13-1. Debug and Test Block Diagram TMS TCK TDI ICE/JTAG TAP Boundary TAP JTAGSEL TDO ICE POR Reset and Test TST PIO ARM7TDMI PDC DTXD DBGU DRXD 43 6120C 6120C­ATARM­25-Oct-05 13.3 13.3.1 Application Examples Debug Environment Figure 13-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 13-2. Application Debug Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91SAM7Xxx RS232 RS232 Connector Terminal AT91SAM7Xxx-based Application Board 44 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 13.3.2 Test Environment Figure 13-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the "board in test" is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n AT91SAM7Xxx Chip 2 Chip 1 AT91SAM7Xxx-based Application Board In Test 13.4 Debug and Test Pin Description Table 13-1. Pin Name Debug and Test Pin List Function Type Active Level Input/Output Low Input High Reset/Test NRST Microcontroller Reset TST Test Mode Select ICE and JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Input JTAGSEL JTAG Selection Input Output Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output 45 6120C 6120C­ATARM­25-Oct-05 13.5 13.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 13.5.2 Embedded ICETM (Embedded In-circuit Emulator) The ARM7TDMI Embedded ICE is supported via the ICE/JTAG port. The internal state of the ARM7TDMI is examined through an ICE/JTAG port. The ARM7TDMI processor contains hardware extensions for advanced debugging features: · In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system. · In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor. There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded ICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B DDI0210B). 13.5.3 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7X256 AT91SAM7X256 Debug Unit Chip ID value is 0x275B 0940 on 32-bit width. The AT91SAM7X128 AT91SAM7X128 Debug Unit Chip ID value is 0x275A 0740 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 13.5.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds 46 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 13.5.4.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associated control signals. Each AT91SAM7X AT91SAM7X input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 13-2. Bit Number AT91SAM7X AT91SAM7X JTAG Boundary Scan Register Pin Name Pin Type 187 186 Associated BSR Cells INPUT PA30/IRQ0/PCK2 PA30/IRQ0/PCK2 IN/OUT OUTPUT 185 CONTROL 184 INPUT 183 PA0/RXD0 IN/OUT OUTPUT 182 CONTROL 181 INPUT 180 PA1/TXD0 IN/OUT OUTPUT 179 CONTROL 178 INPUT 177 PA3/RTS0/SPI1_NPCS2 IN/OUT OUTPUT 176 CONTROL 175 INPUT 174 PA2/SCK0/SPI1_NPCS1 IN/OUT OUTPUT 173 CONTROL 172 INPUT 171 PA4/CTS0/SPI1_NPCS3 IN/OUT OUTPUT 170 CONTROL 169 INPUT 168 PA5/RXD1 IN/OUT OUTPUT 167 CONTROL 166 CONTROL 165 164 PA6/TXD1 IN/OUT INPUT OUTPUT 47 6120C 6120C­ATARM­25-Oct-05 Table 13-2. Bit Number AT91SAM7X AT91SAM7X JTAG Boundary Scan Register (Continued) Pin Name Pin Type 163 162 CONTROL PA7/SCK1/SPI0_NPCS1 IN/OUT 161 160 INPUT OUTPUT ERASE IN 159 158 Associated BSR Cells INPUT INPUT PB27/TIOA2/PWM0/AD0 PB27/TIOA2/PWM0/AD0 IN/OUT OUTPUT 157 CONTROL 156 INPUT 155 PB28/TIOB2/PWM1/AD1 PB28/TIOB2/PWM1/AD1 IN/OUT OUTPUT 154 CONTROL 153 INPUT 152 PB29/PCK1/PWM2/AD2 PB29/PCK1/PWM2/AD2 IN/OUT OUTPUT 151 CONTROL 150 INPUT 149 PB30/PCK2/PWM3/AD3 PB30/PCK2/PWM3/AD3 IN/OUT OUTPUT 148 CONTROL 147 INPUT 146 PA8/RTS1/SPI0_NPCS2 IN/OUT OUTPUT 145 CONTROL 144 INPUT 143 PA9/CTS1/SPI0_NPCS3 IN/OUT OUTPUT 142 CONTROL 141 INPUT 140 PA10/TWD PA10/TWD IN/OUT OUTPUT 139 CONTROL 138 INPUT 137 PA11/TWCK PA11/TWCK IN/OUT OUTPUT 136 CONTROL 135 INPUT 134 PA12/SPI0 PA12/SPI0_NPCS0 IN/OUT OUTPUT 133 CONTROL 132 INPUT 131 PA13/SPI0 PA13/SPI0_NPCS1/PCK1 130 48 IN/OUT OUTPUT CONTROL AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary Table 13-2. Bit Number AT91SAM7X AT91SAM7X JTAG Boundary Scan Register (Continued) Pin Name Pin Type 129 128 Associated BSR Cells INPUT PA14/SPI0 PA14/SPI0_NPCS2/IRQ1 IN/OUT OUTPUT 127 CONTROL 126 INPUT 125 PA15/SPI0 PA15/SPI0_NPCS3/TCLK2 IN/OUT OUTPUT 124 CONTROL 123 INPUT 122 PA16/SPI0 PA16/SPI0_MISO IN/OUT OUTPUT 121 CONTROL 120 INPUT 119 PA17/SPI0 PA17/SPI0_MOSI IN/OUT OUTPUT 118 CONTROL 117 INPUT 116 PA18/SPI0 PA18/SPI0_SPCK IN/OUT OUTPUT 115 CONTROL 114 INPUT 113 PB9/EMDIO IN/OUT OUTPUT 112 CONTROL 111 INPUT 110 PB8/EMDC IN/OUT OUTPUT 109 CONTROL 108 INPUT 107 PB14/ERX3/SPI0 PB14/ERX3/SPI0_NPCS2 IN/OUT OUTPUT 106 CONTROL 105 INPUT 104 PB13/ERX2/SPI0 PB13/ERX2/SPI0_NPCS1 IN/OUT OUTPUT 103 CONTROL 102 INPUT 101 PB6/ERX1 IN/OUT OUTPUT 100 CONTROL 99 INPUT 98 97 PB5/ERX0 IN/OUT OUTPUT CONTROL 49 6120C 6120C­ATARM­25-Oct-05 Table 13-2. Bit Number AT91SAM7X AT91SAM7X JTAG Boundary Scan Register (Continued) Pin Name Pin Type 96 95 Associated BSR Cells INPUT PB15/ERXDV/ECRSDV PB15/ERXDV/ECRSDV IN/OUT OUTPUT 94 CONTROL 93 INPUT 92 PB17/ERXCK/SPI0 PB17/ERXCK/SPI0_NPCS3 IN/OUT OUTPUT 91 CONTROL 90 INPUT 89 PB7/ERXER IN/OUT OUTPUT 88 CONTROL 87 INPUT 86 PB12/ETXER/TCLK0 PB12/ETXER/TCLK0 IN/OUT 85 CONTROL 84 83 OUTPUT INPUT PB0/ETXCK/EREFCK/PCK0 PB0/ETXCK/ERE FCK/PCK0 OUTPUT 82 CONTROL 81 INPUT 80 PB1/ETXEN PB1/ETXEN OUTPUT 79 CONTROL 78 INPUT 77 PB2/ETX0 PB2/ETX0 OUTPUT 76 CONTROL 75 INPUT 74 PB3/ETX1 PB3/ETX1 OUTPUT 73 CONTROL 72 INPUT 71 PB10/ETX2/SPI1 PB10/ETX2/SPI1_NPCS1 IN/OUT OUTPUT 70 CONTROL 69 INPUT 68 PB11/ETX3/SPI1 PB11/ETX3/SPI1_NPCS2 IN/OUT OUTPUT 67 CONTROL 66 INPUT 65 PA19/CANRX PA19/CANRX 64 50 IN/OUT OUTPUT CONTROL AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary Table 13-2. Bit Number AT91SAM7X AT91SAM7X JTAG Boundary Scan Register (Continued) Pin Name Pin Type 63 62 Associated BSR Cells INPUT PA20/CANTX PA20/CANTX IN/OUT OUTPUT 61 CONTROL 60 INPUT 59 PA21/TF/SPI1 PA21/TF/SPI1_NPCS0 IN/OUT OUTPUT 58 CONTROL 57 INPUT 56 PA22/TK/SPI1 PA22/TK/SPI1_SPCK IN/OUT OUTPUT 55 CONTROL 54 INPUT 53 PB16/ECOL/SPI1 PB16/ECOL/SPI1_NPCS3 IN/OUT OUTPUT 52 CONTROL 51 INPUT 50 PB4/ECRS IN/OUT OUTPUT 49 CONTROL 48 INPUT 47 PA23/TD/SPI1 PA23/TD/SPI1_MOSI IN/OUT OUTPUT 46 CONTROL 45 INPUT 44 PA24/RD/SPI1 PA24/RD/SPI1_MISO IN/OUT OUTPUT 43 CONTROL 42 INPUT 41 PA25/RK/SPI1 PA25/RK/SPI1_NPCS1 IN/OUT OUTPUT 40 CONTROL 39 INPUT 38 PA26/RF/SPI1 PA26/RF/SPI1_NPCS2 IN/OUT OUTPUT 37 CONTROL 36 INPUT 35 PB18/EF100/ADTRG PB18/EF100/ADTRG IN/OUT OUTPUT 34 CONTROL 33 INPUT 32 31 PB19/PWM0/TCLK1 PB19/PWM0/TCLK1 IN/OUT OUTPUT CONTROL 51 6120C 6120C­ATARM­25-Oct-05 Table 13-2. Bit Number AT91SAM7X AT91SAM7X JTAG Boundary Scan Register (Continued) Pin Name Pin Type 30 29 Associated BSR Cells INPUT PB20/PWM1/PCK0 PB20/PWM1/PCK0 IN/OUT OUTPUT 28 CONTROL 27 INPUT 26 PB21/PWM2/PCK2 PB21/PWM2/PCK2 IN/OUT OUTPUT 25 CONTROL 24 INPUT 23 PB22/PWM3/PCK2 PB22/PWM3/PCK2 IN/OUT OUTPUT 22 CONTROL 21 INPUT 20 PB23/TIOA0/DCD1 PB23/TIOA0/DCD1 IN/OUT OUTPUT 19 CONTROL 18 INPUT 17 PB24/TIOB0/DSR1 PB24/TIOB0/DSR1 IN/OUT OUTPUT 16 CONTROL 15 INPUT 14 PB25/TIOA1/DTR1 PB25/TIOA1/DTR1 IN/OUT OUTPUT 13 CONTROL 12 INPUT 11 PB26/TIOB1/RI1 PB26/TIOB1/RI1 IN/OUT OUTPUT 10 CONTROL 9 INPUT 8 PA27DRXD/PCK3 PA27DRXD/PCK3 IN/OUT OUTPUT 7 CONTROL 6 INPUT 5 PA28/DTXD PA28/DTXD IN/OUT OUTPUT 4 CONTROL 3 INPUT 2 PA29/FIQ/SPI1 PA29/FIQ/SPI1_NPCS3 1 52 IN/OUT OUTPUT CONTROL AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 13.5.5 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 MANUFACTURER IDENTITY 3 2 1 0 1 · VERSION[31:28]: Product Version Number Set to 0x0. · PART NUMBER[27:12]: Product Part Number AT91SAM7X256 AT91SAM7X256: 0x5B17 AT91SAM7X128 AT91SAM7X128: 0x5B16 · MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. AT91SAM7X256 AT91SAM7X256: JTAG ID Code value is 05B1_003F AT91SAM7X128 AT91SAM7X128: JTAG ID Code value is 05B0_F03F 53 6120C 6120C­ATARM­25-Oct-05 54 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 14. Reset Controller (RSTC) 14.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. 14.2 Block Diagram Figure 14-1. Reset Controller Block Diagram Reset Controller bod_rst_en Brownout Manager brown_out Main Supply POR bod_reset Reset State Manager Startup Counter rstc_irq proc_nreset user_reset NRST NRST Manager nrst_out periph_nreset exter_nreset WDRPROC wd_fault SLCK 55 6120C 6120C­ATARM­25-Oct-05 14.3 Functional Description The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: · proc_nreset: Processor reset line. It also resets the Watchdog Timer. · periph_nreset: Affects the whole set of embedded peripherals. · nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 14.3.1 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14-2 shows the block diagram of the NRST Manager. Figure 14-2. NRST Manager RSTC_MR URSTIEN RSTC_SR URSTS NRSTL rstc_irq RSTC_MR URSTEN Other interrupt sources user_reset NRST RSTC_MR ERSTL nrst_out 14.3.1.1 External Reset Timer exter_nreset NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 14.3.1.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the "nrst_out" signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 56 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. 14.3.2 Brownout Manager Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal. The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read. The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 14-3. Brownout Manager bod_rst_en bod_reset RSTC_MR BODIEN RSTC_SR brown_out BODSTS rstc_irq Other interrupt sources 57 6120C 6120C­ATARM­25-Oct-05 14.3.3 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 14.3.3.1 Power-up Reset When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device. The startup time, as shown in Figure 14-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset. When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately. Figure 14-4. Power-up Reset SLCK Any Freq. MCK Main Supply POR output proc_nreset Startup Time Processor Startup = 3 cycles periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles 58 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 14.3.3.2 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 14-5. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 59 6120C 6120C­ATARM­25-Oct-05 14.3.3.3 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered. When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset. Figure 14-6. Brownout Reset State SLCK MCK Any Freq. brown_out or bod_reset Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x5 = Brownout Reset periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 60 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 14.3.3.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: · PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. · PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. · EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 61 6120C 6120C­ATARM­25-Oct-05 14.3.3.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: · If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. · If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 62 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 14.3.4 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: · Power-up Reset · Brownout Reset · Watchdog Reset · Software Reset · User Reset Particular cases are listed below: · When in User Reset: ­ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. ­ A software reset is impossible, since the processor reset is being activated. · When in Software Reset: ­ A watchdog event has priority over the current state. ­ The NRST has no effect. · When in Watchdog Reset: ­ The processor reset is active and so a Software Reset cannot be programmed. ­ A User Reset cannot be entered. 14.3.5 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: · RSTTYP field: This field gives the type of the last reset, as explained in previous sections. · SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. · NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. · URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. · BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. 63 6120C 6120C­ATARM­25-Oct-05 Figure 14-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 64 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 14.4 Reset Controller (RSTC) User Interface Table 14-1. Reset Controller (RSTC) Register Mapping Offset Register Name Access Reset Value 0x00 Control Register RSTC_CR Write-only - 0x04 Status Register RSTC_SR Read-only 0x0000_0000 0x08 Mode Register RSTC_MR Read/Write 0x0000_0000 65 6120C 6120C­ATARM­25-Oct-05 14.4.1 Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 ­ 22 ­ 21 ­ 20 ­ 19 ­ 18 ­ 17 ­ 16 ­ 15 ­ 14 ­ 13 ­ 12 ­ 11 ­ 10 ­ 9 ­ 8 ­ 7 ­ 6 ­ 5 ­ 4 ­ 3 EXTRST 2 PERRST 1 ­ 0 PROCRST · PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. · PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. · EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. · KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 66 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 14.4.2 Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 ­ 30 ­ 29 ­ 28 ­ 27 ­ 26 ­ 25 ­ 24 ­ 23 ­ 22 ­ 21 ­ 20 ­ 19 ­ 18 ­ 17 SRCMP 16 NRSTL 15 ­ 14 ­ 13 ­ 12 ­ 11 ­ 10 9 RSTTYP 8 7 ­ 6 ­ 5 ­ 4 ­ 3 ­ 2 ­ 1 BODSTS 0 URSTS · URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. · BODSTS: Brownout Detection Status 0 = No brownout high-to-low transition happened since the last read of RSTC_SR. 1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR. · RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP Reset Type Comments 0 0 0 Power-up Reset VDDCORE rising 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor reset required by the software 1 0 0 User Reset NRST pin detected low 1 0 1 Brownout Reset BrownOut reset occurred · NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). · SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 67 6120C 6120C­ATARM­25-Oct-05 14.4.3 Reset Controller Mode Register Register Name: RSTC_MR Access Type: Read/Write 31 30 29 28 27 26 25 24 17 ­ 16 BODIEN 9 8 1 ­ 0 URSTEN KEY 23 ­ 22 ­ 21 ­ 20 ­ 19 ­ 18 ­ 15 ­ 14 ­ 13 ­ 12 ­ 11 10 7 ­ 6 ­ 5 ­ 4 URSTIEN 3 ­ ERSTL 2 ­ · URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. · URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. · BODIEN: Brownout Detection Interrupt Enable 0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq. · ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. · KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 68 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 6120C 6120C­ATARM­25-Oct-05 AT91SAM7X256/128 AT91SAM7X256/128 Preliminary 15. Real-time Timer (RTT) 15.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value. 15.2 Block Diagram Figure 15-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK RTTINCIEN reload 16-bit Divider set 0 RTT_MR RTTRST RTTINC RTT_SR 1 reset 0 rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set rtt_alarm = RTT_AR 15.3 ALMV Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Re