AT91CAP9-STK AT91CAP9-MZ AT91CAP9-MB AT91CAP9A-STK AT91CAP9S ARM926EJ-STM - Datasheet Archive

 

. User Guide 6351A­CAP­14-Nov-07 1-2 6351A­CAP­14-Nov-07

 

AT91CAP9-STK AT91CAP9-STK Starter Kit . User Guide 6351A­CAP­14-Nov-07 1-2 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Table of Contents Section 1 Introduction. 1-1 1.1 Purpose. 1-1 1.2 CAPTM Starter Kit Board . 1-1 1.3 CAP Starter Kit Development Tools. 1-2 1.4 Related Documents . 1-2 1.5 Glossary. 1-3 Section 2 Requirements . 2-1 2.1 General Description . 2-1 2.2 Interface and Function General Overview . 2-2 2.3 External Interfaces . 2-4 2.4 Characteristics . 2-12 Section 3 Board Strap and Switch Configuration . 3-1 3.1 Connectors 1x2. 3-1 3.2 Connectors 1x3. 3-2 3.3 Switches. 3-3 Section 4 AT91CAP9-STK AT91CAP9-STK Schematics. 4-1 4.1 This section contains the following appended schematics . 4-1 Section 5 Revision History . 5-1 5.1 Revisioin Hisory . 5-1 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide i 6351A­CAP­14-Nov-07 Section 1 Introduction 1.1 Purpose This document is a presentation of the hardware associated with the AT91CAP9-STK AT91CAP9-STK® Starter Kit. This product is derived from the Atmel AT91CAP9-MZ AT91CAP9-MZ and AT91CAP9-MB AT91CAP9-MB demonstration boards. 1.2 CAPTM Starter Kit Board The AT91CAP9A-STK AT91CAP9A-STK Starter Kit is built on a single PCB, including: AT91CAP9S AT91CAP9S ARM926EJ-STM ARM926EJ-STM -based microcontroller system-on-chip 64M Bytes of SDRAM application memory 512M Bytes of NAND Flash DataFlash® with up to 8M Bytes External interfaces for: ­ 10/100 Base-T Ethernet ­ USB Host and Full Speed/High Speed Device ­ ¼ VGA LCD Panel with Touch Screen ­ SD Card ­ 4 analog inputs ­ audio headphones Altera® Stratix®2 EP2S15F484 EP2S15F484 FPGA and its associated EPCS16 EPCS16 serial configuration memory. The FPGA provides 15600 four-input Lookup Table (LUT) equivalents, corresponding to approximately 124800 gates in the CAP MP Block. 64 general-purpose I/O connections from the AT91CAP9S AT91CAP9S, and 2 banks of 64 I/Os from the FPGA, for application-specific external interfaces CE-JTAG interface for CAP9 JTAG programming, and a USB-Blaster-JTAG interface for Stratix2 JTAG programming. These facilitate system debug. Atmel's AT73C224 AT73C224 and AT73C239 AT73C239 ICs for power supply and battery management. Atmel's AT73C213 AT73C213 for audio DAC Atmel's AT73C205 AT73C205 for battery charger AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 1-1 6351A­CAP­14-Nov-07 Introduction 1.3 CAP Starter Kit Development Tools The CAP Starter Kit is supplied with an essential set of development tools in order to get started immediately. These include: KickStart version of IAR Embedded Workbench® for ARM® Microsoft® Windows CE ® Board Support Package and demonstration from Adeneo Instructions for downloading Altera's free Quartus® 2 Web Edition tools for FPGA programming 1.4 Related Documents 1.4.1 Standards JTAG IEEE® 1149.1 Standard. 1.4.2 Reference Documents Table 1-1. Reference Documents Description Reference Evaluation motherboard ORCAD schematics 20061027_11H20 11H20_AT91CAP9 AT91CAP9.dsn Evaluation motherboard BOM 20061212_BOMASSY_ID2400 ID2400_MOTHERBOARD.xls Evaluation mezzanine board ORCAD schematics 20061122_09H00 09H00_AT91CAP9 AT91CAP9_MEZ.dsn Evaluation mezzanine board BOM 20061207_ID2399 ID2399_BOMASSY_MEZZANINE.xls Atmel Specification New Specification CAP9 Starter Kit CAP9-STK hardware description.doc ref. 4658D03 4658D03 CAP9-STK ORCAD schematics ref. ADEC101389001 ADEC101389001 CAP9-STK BOM ref. ADEC101389003 ADEC101389003 CAP9-STK equipment plan ref. ADEC101389EQ2 ADEC101389EQ2 1-2 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Introduction 1.5 Glossary BOM Bill Of Materials ICE In-Circuit Emulator JTAG Joint Test Action Group CAP Customizable Microcontroller-based SoC Platform CAP9-STK CAP9 Starter Kit FPGA Field Programmable Gate Array I/O Input/Output MCI Multimedia Card Interface MPB Metal Programmable Block MPIO Metal Programmable I/O NC Not Connected OHCI Open Host Controller Interface PLL Phase Locked Loop PMC Power Management Circuit AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 1-3 6351A­CAP­14-Nov-07 Section 2 Requirements 2.1 General Description The CAP9-STK's objective is to provide a rapid evaluation of the AT91CAP9 AT91CAP9 product and its derivatives. It does not allow a full emulation of a customized version of the CAP9, but is intended to familiarize the user with the customization concept and architecture of the CAP9. It also demonstrates the operations of the analog companions provided by Atmel's AT73C AT73C family of products and the availability of the operating systems and software layers. AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-1 6351A­CAP­14-Nov-07 Requirements 2.2 Interface and Function General Overview AT91CAP9-STK AT91CAP9-STK interfaces and functions are as follows: (Refer also to Figure 2-1 on page 2-3.) Interface EI1: 1 external Lithium-Ion battery EI2: 5V AC/DC sector adapter EI3: 1 RMII 10/100 Base-T Ethernet EI4: 1 Serial port, connected to the Debug Unit EI5: 1 SD Card slot EI6: 2 USB HOST interface EI7: 1 USB High Speed Device interface EI8: ¼ VGA LCD panel with Touch Screen EI9: 1 Audio stereo headset EI10: 4 Analog inputs EI11: 2 JTAG and 1 serial configuration interfaces EI12: 1 Manganese-Lithium coin battery EI13: 64-lead extension connector for the CAP9 I/O lines EI14: Two 64-lead extension connectors for the FPGA I/O lines Function F1: AT91CAP9 AT91CAP9 microcontroller F2: FPGA and MPIO bus F3: RMII 10/100 Base-T Fast-Ethernet PHY Auto-MDIX. F4: RS232 RS232 driver F5: USB Host and Device F6: Touch screen controller and LCD panel F7: Audio DAC F8: Analog Inputs adaptation F9: SD Card F10: Power supplies and low power mode F11: Battery charger F12: RTC and Backup F13: Reset configuration F14: Programming and configuration F15: Prototyping Area 2-2 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements Figure 2-1. AT91CAP9-STK AT91CAP9-STK Interface and Function Overview 3V Coin Cell 3V Battery Holder VBACKUP (EI12) 1.2V VDDBU AT73C239 AT73C239 (F12) 40-pin FPC ZIF (E18) 2.75V 5V 2x1.8V 3.3V 5V Power Supply AT73C224 AT73C224 Power Jack (EI2) Touch Screen Controller & LCD Panel (F6) 3.3V LTC3412 LTC3412 5V Prototyping Areas (F15) 1.8V 1.2V (+RTC) SPI 64 Mbytes Application Memory LCDC (F10) EBI 512 Mbytes NAND Flash SHDN AT73C205 AT73C205 Battery Charger (F11) HE14 3pts (EI1) VBAT CAP9 JTAG RESET_FPGA# Reset (F13) RESET_CAP9# ADC Serial Config Configuration Jumpers & Serial PROM (F14) 10/100 PHY ethernet (F3) RJ4S (EI3) RS232 RS232 Drivers (F4) SUBD9 (EI4) SSC + SPI AT73C213 AT73C213 Audio DAC (F7) Audio Jack (EI9) FPGA JTAG Serial AS mode MPIOB(0.44) UDPHS CAP9 JTAG Blaster JTAG RMI OHCI AD8040 AD8040 Analog Inputs (F8) MKDS Terminal Block EI10 Serial Config ICE HE10 20pts 2 x HE10 10pts (EI11) DBGU USB Host and Device HS adaptation (F8) USB Type B EI7) Blaster JTAG AT91CAP9 AT91CAP9 + Oscillators and PLLs (F1) MPIOA(0.31) Dual USB Type A (EI6) 4 Mbytes Optional DataFlash SPI CAP9_POK FPGA_POK PIO FPGA Stratix2 (F2) SDCard Slot (EI5) MCI + pull-up (F9) 64-lead 2,54 TSM Extension Connector (EI13) 2x64 - lead 2.54 mm TSM Extension Connector (EI14) AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-3 6351A­CAP­14-Nov-07 Requirements 2.3 External Interfaces 2.3.1 EI1: External Lithium-ion Battery The AT91CAP9-STK AT91CAP9-STK board implements one external Li-Ion battery 3-pin HE14 type connector. Table 2-1. HE 14-3 Pinout Pin Description Type Level 1 VBAT Battery power I/O 4,5V 2 GND Electrical ground O - 3 2.3.2 Signal Name BAT_TS Thermistor temperature sense I 4,5V EI2: 5VAC/DC Sector Adapter CAP9-STK board implements one RAPC722 RAPC722 Switchcraft right angle miniature power jack with the following electrical characteristics: Contact resistance: 30 m max Current carrying capability: 5A 2.3.3 EI3: RMII 10/100 Base-T Ethernet An RJ45 8-pin Integrated Magnetics Connector is implement for the 10/100 Base-T Ethernet interface. The connector integrates a 1 nF capacitor for HF shielding of the signal with chassis ground. (External connection between chassis and electrical ground is possible too.) Table 2-2. RJ45-8 RJ45-8 Pinout Pin Description Type 1 TX+ Positive differential emission O 2 TX- Negative differential emission O 3 RX+ Positive differential reception I 6 RX- Negative differential reception I 4, 5, 7, 8 2.3.4 Signal Name NC - - EI4: Serial Port, Connected to the Debug Unit A Debug right angle SUBD-9 connector is available in order to communicate with the AT91CAP9 AT91CAP9 microcontroller debug unit. This port is an electrical RS232 RS232 type connection. The connector integrates 2 additional pins (10, 11) for signal shielding. Table 2-3. SUBD-P Pinout Pin Type Level RXD RS232 RS232 receive I ±30V 3 TXD RS232 RS232 transmit O ±5V to ±5.2V 5, 10, 11 GND Electrical ground - - 1, 4, 6, 7, 8, 9 2-4 Description 2 6351A­CAP­14-Nov-07 Signal Name NC - - - AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements 2.3.5 EI5: SD Card Slot The AT91CAP9-STK AT91CAP9-STK board implements a 12-pin short type SDCARD slot on the bottom side. Table 2-4. SD CARD Pinout Pin Description Type Level 1 MCI_DA3 Data 3 I/O 3.3V 2 MCI_CDA Command/response I/O open-drain 3.3V 3 GND Electrical ground - - 4 3V3 3.3V power supply O 3.3V 5 MCI_CK Clock O 3.3V 6 GND Electrical ground - - 7 MCI_DA0 DATA 0 I/O 3.3V 8 MCI_DA1 DATA 1 I/O 3.3V 9 MCI_DA2 DATA 2 I/O 3.3V 10 MCI_CD Card Detect I 3.3V 11 GND Electrical ground - - 12 2.3.6 Signal Name NC - - - EI6: Two USB Host Interfaces Two USB HOST connectors are available on a sign dual-port Type A connector. Table 2-5. Dual-port Type A Connector Pinout Pin Description Type A1 5V 5V power supply (fuse 500mA) O A2 HDMA Negative differential port A I/O A3 HDPA Positive differential port A I/O A4 GND Electrical ground - B1 5V 5V power supply (fuse 500mA) O B2 HDMB Negative differential port B I/O B3 HDPB Positive differential port B I/O B4 GND Electrical ground - 1 to 4 2.3.7 Signal Name GND Electrical ground - EI7: USB High Speed Device Interface One USB Device High/Full Speed connector is available on a Type B connector. Table 2-6. Type B Connector Pinout Pin Signal Name Description 5V supply Type Level I 1 1 VBUS 2 HSDM / FSDM Negative differential port A I/O 2 3 HSDP / FSDP Positive differential port A I/O 3 4, 5, 6 GND Electrical - 4, 5, 6 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-5 6351A­CAP­14-Nov-07 Requirements 2.3.8 EI8: 1/4 VGA LCD Panel with Touch Screen The AT91CAP9-STK AT91CAP9-STK board implements a 0.5 FPC, 40-pin ZIF LCD Panel connector, with contact on the bottom side. The connector integrates two additional pins (MC1, MC2) for signal shielding. Table 2-7. 40-pin ZIF Connector Pinout Pin Type Level 3V3 3.3V power supply O 3.3V 2 3V3 3.3V power supply O 3.3V 3 3V3 3.3V power supply O 3.3V 4 LCDDOTCK Dot clock O 3.3V 5 GND Electrical ground - - 6 LCDHSYNC Horizontal synchronization pulse O 3.3V 7 GND Electrical ground - - 8 LCDDEN Timing signal for data O 3.3V 9 GND Electrical ground - - 10 NC - - - 11 GND Electrical ground - - 12 LCDD7 RED data 5 O 3.3V 13 LCDD6 RED data 4 O 3.3V 14 LCDD5 RED data 3 O 3.3V 15 GND Electrical ground - - 16 LCDD4 RED data 2 O 3.3V 17 LCDD3 RED data 1 O 3.3V 18 LCDD2 RED data 0 O 3.3V 19 GND Electrical ground - - 20 LCDD15 LCDD15 GREEN data 5 O 3.3V 21 LCDD14 LCDD14 GREEN data 4 O 3.3V 22 LCDD13 LCDD13 GREEN data 3 O 3.3V 23 GND Electrical ground - - 24 LCDD12 LCDD12 GREEN data 2 O 3.3V 25 LCDD11 LCDD11 GREEN data 1 O 3.3V 26 LCDD10 LCDD10 GREEN data 0 O 3.3V 27 GND Electrical ground - - 28 LCDD23 LCDD23 BLUE data 5 O 3.3V 29 LCDD22 LCDD22 BLUE data 4 O 3.3V 30 LCDD21 LCDD21 BLUE data 3 O 3.3V 31 GND Electrical ground - - 32 LCDD20 LCDD20 BLUE data 2 O 3.3V 33 LCDD19 LCDD19 BLUE data 1 O 3.3V 34 LCDD18 LCDD18 BLUE data 0 O 3.3V 35 2-6 Description 1 6351A­CAP­14-Nov-07 Signal Name PCI Power control O 3.3V AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements Table 2-7. 40-pin ZIF Connector Pinout (Continued) Pin Description Type Level 36 VCTRL LED current control O 3.3V 37 Y_UP Touch panel upper side O 3.3V 38 X_LEFT Touch panel left side O 3.3V 39 Y_LOW Touch panel low side O 3.3V 40 2.3.9 Signal Name X_RIGHT Touch panel right side O 3.3V EI9: Audio Stereo Headset A headset audio interface connector is available for a 3.5 phone jack stereo plug. SMT 1503-03 Lumberg is used. 2.3.10 EI10: Analog Inputs The AT91CAP9-STK AT91CAP9-STK board implements a 3.81mm-pitch Phoenix MKDS 6-pin terminal block. This connector receives four analog inputs. Table 2-8. MKDS 6-pin Terminal Block Pinout Pin Description Type Level 1 ANALOG_I1 Analog input 1 I 3.3V 2 ANALOG_I2 Analog input 2 I 3.3V 3 ANALOG_I3 Analog input 3 I 3.3V 4 ANALOG_I4 Analog input 4 I 3.3V 5 GND Electrical ground - - 6 2.3.11 Signal Name NC (3V3) - (It can be connected to 3.3V by 0 strap) - (O) - (3.3V) EI11: JTAG and Serial Configuration Interfaces Two programming JTAG interfaces and one serial configuration device interface are available on the board. 2.3.11.1 ICE-JTAG Interface One ICE-JTAG interface is a right angle male, HE10 2x10-pin connector, to receive CAP9 ICE debugger probe for CAP9 JTAG programming. Table 2-9. HE10 2x10-pin Connector Pinout Pin Signal Name Description Type Level 1 3V3 3.3V power supply O 3.3V 3 NTRST Test Reset I 3.3V (active low) 5 TDI Test Data In I 3.3V 7 TMS Test Mode Select I 3.3V 9 TCK Test Clock I 3.3V 11 RTCK Returned Test Clock O 3.3V 13 TDO Test Data Out O 3.3V AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-7 6351A­CAP­14-Nov-07 Requirements Table 2-9. HE10 2x10-pin Connector Pinout (Continued) Pin Signal Name Description Type Level 15 NRST Microcontroller Reset I/O 3.3V (active low) 17, 19 NC - - - 4, 6, 8, 10, 12, 14, 16, 18, 20 GND Electrical ground - - 2.3.11.2 USB-Blaster-JTAG Interface One USB-Blaster-JTAG interface is a straight male, HE10 2x5-pin connector, to receive the Altera FPGA USB Blaster probe for Stratix2 JTAG programming. Table 2-10. HE10 2x5-pin Connector Pinout Pin Signal Name Description Type Level 1 TCK Test Clock I 3.3V 3 TDO Test Data Out O 3.3V 5 TMS Test Mode Select I 3.3V 9 TDI Test Data In I 3.3V 4, 6 3V3 3.3V power supply O 3.3V 7, 8 NC - - - 2, 10 GND Electrical ground - - 2.3.11.3 Serial Configuration Device Interface The serial configuration device interface is a straight male, HE10 2x5-pin connector, to receive the Altera FPGA USB Blaster probe for serial EPCS Device programming. Table 2-11. HE10 2x5-pin Connector Pinout Pin Description Type Level 1 DCLK Configuration Clock pin O 3.3V 3 CONF_DONE Configuration Status pin I/O 3.3V open-drain 5 nCONFIG Configuration Control input I 3.3V 6 nCE Configuration Chip enable I 3.3V (active low) 7 DATA0 Configuration Data input I 3.3V 8 nCSO Configuration Chip select O 3.3V 9 ASDO_FPGA Configuration Read enable O 3.3V 4 3V3 3.3V power supply O 3.3V 2, 10 2.3.12 Signal Name GND Electrical ground - - EI12: Manganese-Lithium Coin Battery The AT91CAP9-STK AT91CAP9-STK board implements a coin cell battery holder for 12 mm rechargeable 3V Manganese-Lithium coin battery, Panasonic ML1220 ML1220 type. 3V non-rechargeable Lithium coin batteries are not supported. 2-8 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements 2.3.13 EI13: 64-lead Extension Connector for the AT91CAP9 AT91CAP9 I/O Lines A straight male, 2.54 mm-pitch, 64-pin connector is available on the board as a CAP9 extension connector. Table 2-12. 64-pin Connector Pinout Pin Signal Name Level Pin Signal Name Level 1 5V 5V 2 5V 5V 3 5V 5V 4 GND - 5 GND - 6 GND - 7 3V3 3.3V 8 3V3 3.3V 9 PA2/SPI0_SPCK 3.3V 10 GND - 11 GND - 12 PA0/SPI0_MISO 3.3V 13 PA9 3.3V 14 GND - 15 GND - 16 PA1/SPI0_MOSI 3.3V 17 PD1/SPI0_NPCS3 3.3V 18 PD0 3.3V 19 GND - 20 3V3 3.3V 21 TWCK 3.3V open-drain 22 PA10/IRQ0 PA10/IRQ0 3.3V 23 GND - 24 PA14/IRQ1 PA14/IRQ1 3.3V 25 TWD 3.3V open-drain 26 PA22/TXD0 PA22/TXD0 VDDIOP1 27 PA24/RTS0 PA24/RTS0 VDDIOP1 28 PA23/ PA23/ RXD0 VDDIOP1 29 GND - 30 PB12/SPI1 PB12/SPI1_MISO 3.3V 31 PA27/PCK1 PA27/PCK1 VDDIOP1 32 PB13/SPI1 PB13/SPI1_MOSI 3.3V 33 VDDIOP1 3.3V or 1.8V 34 GND - 35 PA26 VDDIOP1 36 PB14/SPI1 PB14/SPI1_SPCK 3.3V 37 PA29 VDDIOP1 38 GND - 39 PA30 VDDIOP1 40 PB15/SPI1 PB15/SPI1_NPCS0 3.3V 41 PA31 VDDIOP1 42 PB16/SPI1 PB16/SPI1_NPCS1 3.3V 43 VDDIOP1 3.3V or 1.8V 44 3V3 3.3V 45 GND - 46 3V3 3.3V 47 PC12 3.3V 48 PC29 3.3V 49 PC13 3.3V 50 GND - 51 PD2 3.3V 52 PD5/DMARQ2 3.3V 53 PC3 3.3V 54 GND - 55 GND - 56 PD6/NWAIT 1.8V 57 PD8/NCS5 1.8V 58 PD7/NCS4 1.8V 59 PD10/SCK1 PD10/SCK1 1.8V 60 PD9/SCK2 1.8V 61 PD13/A24 PD13/A24 1.8V 62 PD12/A23 PD12/A23 1.8V 63 PD14 / A25 1.8V 64 1V8_CAP9 1,8V AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-9 6351A­CAP­14-Nov-07 Requirements 2.3.14 EI14: Two 64-lead Extension Connectors for the FPGA I/O Lines Two straight male, 2.54 mm-pitch, 64-pin connectors are available on the board as FPGA extension connectors. The pinouts for both FPGA connectors are given in Table 2-13 and Table 2-14 Table 2-13. 64-pin Connector Pinout and Bank Assignment Pin FPGA IO/Power Name Bank Pin FPGA IO/Power Name Bank 1 GND - 2 VCCIO4 BANK4 3 FPGA_IO0 BANK4 4 VCCIO4 BANK4 5 FPGA_IO1 BANK4 6 FPGA_IO2 BANK4 7 FPGA_IO3 BANK4 8 FPGA_IO4 BANK4 9 FPGA_IO5 BANK4 10 GND - 11 FPGA_IO6 BANK4 12 FPGA_IO7 BANK4 13 FPGA_IO8 BANK4 14 FPGA_IO9 BANK4 15 FPGA_IO10 BANK4 16 FPGA_IO11 BANK4 17 FPGA_IO12 BANK4 18 FPGA_IO13 BANK4 19 GND - 20 FPGA_IO14 BANK4 21 FPGA_IO15 BANK4 22 FPGA_IO16 BANK4 23 FPGA_IO17 BANK4 24 FPGA_IO18 BANK4 25 FPGA_IO19 BANK4 26 FPGA_IO20 BANK4 27 FPGA_IO21 BANK4 28 GND - 29 FPGA_IO22 BANK4 30 FPGA_IO23 BANK4 31 FPGA_IO24 BANK4 32 FPGA_IO25 BANK4 33 FPGA_IO26 BANK4 34 FPGA_IO27 BANK4 35 GND - 36 FPGA_IO28 BANK6 37 FPGA_IO29 BANK6 38 FPGA_IO30 BANK6 39 FPGA_IO31 BANK6 40 FPGA_IO32 BANK6 41 FPGA_IO33 BANK6 42 FPGA_IO34 BANK6 43 FPGA_IO35 BANK6 44 FPGA_IO36 BANK6 45 FPGA_IO37 BANK6 46 GND - 47 FPGA_IO38 BANK6 48 FPGA_IO39 BANK6 49 FPGA_IO40 BANK6 50 FPGA_IO41 BANK6 51 FPGA_IO42 BANK6 52 FPGA_IO43 BANK6 53 FPGA_IO44 BANK6 54 FPGA_IO45 BANK6 55 GND - 56 FPGA_IO46 BANK6 57 FPGA_IO47 BANK6 58 FPGA_IO48 BANK6 59 FPGA_IO49 BANK6 60 FPGA_IO50 BANK6 61 VCCIO6 BANK6 62 FPGA_IO51 BANK6 63 VCCIO6 BANK6 64 GND - 2-10 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements Table 2-14. 64-pin Connector Pinout and Bank Assignment Pin FPGA IO/Power Name Bank Pin FPGA IO/Power Name Bank 1 GND - 2 VCCIO6 BANK6 3 FPGA_IO BANK6 4 VCCIO6 BANK6 5 FPGA_IO BANK6 6 FPGA_IO BANK6 7 FPGA_IO BANK6 8 FPGA_IO BANK6 9 FPGA_IO BANK6 10 GND - 11 FPGA_IO BANK7 12 FPGA_IO BANK7 13 FPGA_IO BANK7 14 FPGA_IO BANK7 15 FPGA_IO BANK7 16 FPGA_IO BANK7 17 FPGA_IO BANK7 18 FPGA_IO BANK7 19 GND - 20 FPGA_IO BANK7 21 FPGA_IO BANK7 22 VCCIO7 BANK7 23 FPGA_IO BANK7 24 VCCIO7 BANK7 25 FPGA_IO BANK7 26 FPGA_IO BANK7 27 FPGA_IO BANK7 28 GND - 29 FPGA_IO BANK7 30 FPGA_IO BANK7 31 FPGA_IO BANK7 32 FPGA_IO BANK7 33 FPGA_IO BANK7 34 FPGA_IO BANK7 35 FPGA_IO BANK7 36 FPGA_IO BANK7 37 GND - 38 FPGA_IO BANK7 39 FPGA_IO BANK7 40 FPGA_IO BANK7 41 FPGA_IO BANK7 42 FPGA_IO BANK7 43 VCCIO8 BANK8 44 FPGA_IO BANK7 45 VCCIO8 BANK8 46 GND - 47 FPGA_IO BANK8 48 FPGA_IO BANK8 49 FPGA_IO BANK8 50 FPGA_IO BANK8 51 FPGA_IO BANK8 52 FPGA_IO BANK8 53 FPGA_IO BANK8 54 FPGA_IO BANK8 55 GND - 56 FPGA_IO BANK8 57 FPGA_PLLOUTp 3.3V 58 GND - 59 GND - 60 FPGA_IO BANK8 61 FPGA_PLLOUTn 3.3V 62 GND - 63 GND - 64 3V3 3.3V AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-11 6351A­CAP­14-Nov-07 Requirements 2.4 Characteristics 2.4.1 Functional Characteristics 2.4.1.1 F1: AT91CAP9 AT91CAP9 Microcontroller The AT91CAP9-STK AT91CAP9-STK microcontroller core block implements the necessary digital-system core functions. It's composed of the following elements: One 32-bit-ARM9® AT91CAP9 AT91CAP9 microcontroller core and its power supplies (see below). One 1.8V, 512 Mbytes, 8-bit NAND Flash, One 1.8V, 64 Mbytes, 32-bit SDRAM Application Volatile Memory One optional 3.3V DataFlash® memory from 512 Kbytes to 8 Mbytes One Debug and JTAG Test unit (See "F14: Programming and Configuration" on page 2-27.) One MPB 2.4.1.1.1 AT91CAP9 AT91CAP9 Power Supplies The power supply of the AT91CAP9 AT91CAP9 Microcontroller is shown below. Table 2-15. AT91CAP9 AT91CAP9 Power Supply Power Supply Name Power Supply VDDCORE 1V2_CAP9 VDDPLL 3V3 VDDUPLL 1V2_CAP9 (RC filtered) VDDUTMII 3V3 VDDIOP0 3V3 VDDIOP1 3V3 or 1V8_CAP9 VDDUTMIC 1V2_CAP9 VDDIOM 1V8 VDDMPIO 3V3 or 1V8_FPGA VDDBU 1V2_SAVE or 1V2_CAP9 VDDANA 3V3 filtered VREFP VREFP (3V) For VDDIOP1 and VDDMPI0, the choice is made by 0 resistors: 3V3 R26 0R R151 0R NC VDDIOP1 J24 3V3 0R NC R27 2-12 6351A­CAP­14-Nov-07 2 1 1V8 R152 0R C86 10nF VDDMPIO C268 1 2 100nF 1V8 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements For VDDBU, the choice is made by a jumper on the 3-pin J28 connector: 3 1V2 2 2 1 1 J28 1X3PTS_MD_2MM54 2MM54 VDDBU C101 10nF 1V2_SAVE The implementation of VDDANA and VREEP is shown below. C105 10nF C99 10nF 3 VIN VOUT 1 REF EN VREFP 5 2 1 1 1 C104 10uF_1210 2 C103 10nF 2 4,7µH 220mA 1 2 2 1 C102 10uF_1210 2 2 1 1 4 J29 GND VDDANA L6 C100 47nF 2 3V3 U7 LM4120AIM5-3 LM4120AIM5-3.0 2.4.1.1.2 AT91CAP9 AT91CAP9 Clocks The internal clocks of the AT91CAP9 AT91CAP9 are generated by two external quartz sources: 12 Mhz quartz for the MAINCK internal clock 32,768 kHz quartz for the SLCK internal slow clock 2.4.1.2 F2: FPGA and MPIO Bus 2.4.1.2.1 FPGA Characteristics This function is performed by an Altera Stratix2, EP2S15F484 EP2S15F484 FPGA and its EPCS16 EPCS16 serial configuration device. Stratix2 EP2S,15F484 15F484 FPGA characteristics are: 15600 equivalent LE (LE is four-input LUT-based architecture), 1.2V core power supply, 3.3V or 1.8V I/O bank power supplies, 484-pin FBGA, -5 speed grade. The FPGA aims to emulate the logic to be implemented in the MPB through 5 metal layers. The FPGA also manages the EI14 interface. AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-13 6351A­CAP­14-Nov-07 Requirements 2.4.1.2.2 MPIO Bus Characteristics The FPGA is connected to the AT91CAP9 AT91CAP9 microcontroller through the two MPIO buses: First MPIO bus: MPIOA[0:31], connected to FPGA bank 1 Second MPIO bus: MPIOB[0:44], connected to FPGA banks 2 and 5 Bus frequency: 100MHz Dedicated MPIO bus clock: MPIOB24 MPIOB24 2.4.1.2.3 FPGA Power Supplies Table 2-16. FPGA Bank Power Supplies Bank 1 VDDMPIO (default 1V8_FPGA) Bank 2 VDDMPIO (default 1V8_FPGA) Bank 3 3V3 Bank 4 VCCIO4 (default 3V3) Bank 5 VDDMPIO (default 1V8_FPGA) Bank 6 VCCIO6 (default 1V8_FPGA) Bank 7 VCCIO7 (default 3V3) Bank 8 VCCIO8 (default 3V3) Bank 9 3V3 Bank 10 3V3 Power for VDDMPIO, VCCIO4, VCCIO6, VCCIO7, and VCCIO8 can be supplied either by 3V3 or 1V8 (1V8_CAP9) power supplies. (See "F10: Power Supplies and Low-power Mode" on page 2-22.) Choice is made by 0 resistor as shown below (VCCIO7 example): C271 100nF 2 2 1V8 VCCIO7 1 1 R181 0R AB11 1 AB3 3V3 C256 10nF 2 R183 0R C257 10nF NC Each of the six FPGA PLL blocks have two power supply pins: VCCA_PPLw and VCCD_PPLx (x = from to 6). Table 2-17. FPGA PLL Block Power Supply PLL Supply Pin Name VCCA_PPL1 VCC_PLL12 PLL12 VCCA_PPL3 VCC_PLL34 PLL34 VCCA_PPL4 VCC_PLL34 PLL34 VCCA_PPL5 2-14 VCC_PLL12 PLL12 VCCA_PPL2 6351A­CAP­14-Nov-07 Power Supply VCC_PLL56 PLL56 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements Table 2-17. FPGA PLL Block Power Supply (Continued) PLL Supply Pin Name Power Supply VCCA_PPL6 VCC_PLL56 PLL56 VCCD_PPL1 1V2_CAP9 VCCD_PPL2 1V2_CAP9 VCCD_PPL3 1V2_CAP9 VCCD_PPL4 1V2_CAP9 VCCD_PPL5 1V2_CAP9 VCCD_PPL6 1V2_CAP9 VCC_PLL12 PLL12, VCC_PLL34 PLL34, VCC_PLL56 PLL56 are 1V2 (1V2_CAP9) ferrite isolated power supplies as shown below (VCC_PLL12 PLL12 example): L22 BLM1 8PG600 8PG600 1 2 C225 100nF 1 1 C226 1nF M17 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2 C224 100nF 2 1 VCC_PLL12 PLL12 2 2 1 1V2 C227 1nF M19 2-15 6351A­CAP­14-Nov-07 Requirements 2.4.1.2.4 FPGA Clock The MPIO Bus clock MPIOB24 MPIOB24 is connected to the CLK1p clock input pin of the FPGA. An additional external 12 MHz oscillator generates clock to the CLK14p clock input pin of the FPGA. Spare clock PLL_OUTp and PLL_OUTn are connected to the EI14 interface. FPGA clock part electrical connection is shown below. 3V3 1 2 2 Y5 OE VCC GND OUT MPIOB24 MPIOB24 MPIOB24 MPIOB24 R212 0R M21 N20 N3 M2 M20 N19 N4 M3 L21 N22 N1 L2 L20 N21 N2 L3 Y4 VCCIO7 R215 1K NC A10 C10 B10 D10 B9 C9 CLK1p CLK3p CLK9p CLK11p CLK1n CLK3n CLK9n CLK11n CLK0p/DIFFIO_RX_C0p CLK2p/DIFFIO_RX_C1p CLK8p/DIFFIO_RX_C2p CLK10p/DIFFIO_RX_C3p CLK0n/DIFFIO_RX_C0n CLK2n/DIFFIO_RX_C1n CLK8n/DIFFIO_RX_C2n CLK10n/DIFFIO_RX_C3n 3 2 BLM18PG600 BLM18PG600 C280 100nF 1 1 CLK_12M_R C281 100nF CLK_12M_FPGA R204 22R CLOCK & PLL CLK4p CLK5p CLK6p CLK7p CLK12p CLK13p CLK14p CLK15p CLK4n CLK5n CLK6n CLK7n CLK12n CLK13n CLK14n CLK15n AB13 AA12 AA11 Y10 B11 B12 A13 C13 AA13 Y12 Y11 W10 C11 C12 B13 D13 PLL_ENA PLL5_OUT0p PLL5_OUT1p PLL5_OUT0n PLL5_OUT1n PLL5_FBp/OUT2p PLL5_FBn/OUT2n L25 4 K3750HBE-12MHz U19K C279 330pF 2 1 1 2 R197 10K PLL6_OUT0p PLL6_OUT1p PLL6_OUT0n PLL6_OUT1n PLL6_FBp/OUT2p PLL6_FBn/OUT2n AB10 AA9 AA10 Y9 W9 V9 R220 0R FPGA_PLLOUTp FPGA_PLLOUTn R221 0R EP2S15F484 EP2S15F484 2-16 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements 2.4.1.3 F3: RMII 10/100 Base-T Fast-Ethernet PHY Auto-MDIX The 10/100 Ethernet MAC function is implemented in the AT91CAP9 AT91CAP9 EMAC module. This module manages an RMII 10/100 Base-T Fast-Ethernet PHY Auto-MDIX (SMSC LAN8700 LAN8700) to implement a 10/100 Base-T Ethernet port. The implementation is shown below. R67 10K NC VDDIO_ETH Y4 2 BLM18PG600 BLM18PG600 C125 100nF EREFCK_O 3V3_ANA_ETH 1 R69 22R TP17 C126 100nF REFCK 1 1V8_CORE_ETH EREFCK L10 VDDIO_ETH 1V8_CORE_ETH 3V3_ANA_ETH R76 49R9 R77 49R9 R79 10R 35 33 30 R82 22R RXD[1.0] RXD1 RXD0 R83 ERXER MODE2 MODE1 MODE0 22R R86 22R RMII ECRSDV 22R R87 36 3 EMDC EMDIO EMIRQ# 2 4 1 ERST# 5 VDDA VDDA VDDA VDDCORE RX+ TX- 2 TD- TX- 2 32 RX+ 3 RD+ RX+ 3 RX- 6 U11 RX_CLK RXD[3]/NINTSEL RXD[2]/MODE2 RXD[1]/MODE1 RXD[0]/MODE0 RX_ER/RXD4 RX_DV 5 CT RXREXT RX- 31 34 REXT R84 49R9 MDC MDIO NINT/TX_ER/TXD4 RST# C130 10nF 9 10 11 12 1 VDDIO_ETH REG_OFF RMII R73 1K5 NC R74 1K5 NC EMDC EMDIO 75 75 C194 1nF_2KV 1 2 4 5 8 75 7 8 J00-0061NL J00-0061NL NC 2 D7 2 R91 332R GREEN MODE0 MODE1 MODE2 R72 10K 75 7 NC GREEN LED2 R71 10K R90 332R D6 1 C129 100nF 1nF VDDIO_ETH LED1 37 R156 1K C128 100nF R88 12K4 SPEED100/PHYAD SPEED100/PHYAD[0] LINK/PHYAD[1] ACTIVITY/PHYAD[2] FDUPLEX/PHYAD[3] 6 RD- R85 49R9 LAN8700-AEZG LAN8700-AEZG MODE=0x07 PHYAD=0x1F COL/MII/CRS_DV CRS/PHYAD[4] 1 28 1 ERX[1.0] 20 15 16 17 18 21 19 TX- 2 REG_OFF TX+ 4 CT 1 ETXEN TX_CLK TXD[3] TXD[2] TXD[1] TXD[0] TX_EN J35 1 TD+ TX+ 29 2 TXD1 TXD0 TX+ 1 TXD[1.0] 22 27 26 24 23 6 XTAL2 XTAL1/CLKIN 2 ETX[1.0] 13 14 GND REFCK VDDIO VDDIO 2 8 7 25 pin 8 16 C142 100nF L8 BLM18PG600 BLM18PG600 C127 10nF 15 C143 4,7uF 1 2 BLM18PG600 BLM18PG600 R70 22R 2 1V8 1 1 2 2 J36 1 OUT IQXO71I IQXO71I_50Mhz C124 330pF 2 GND 3 2 1 4 VCC 1 2 2 R155 1K 1 L7 OE 2 1 0R 1 R68 EPWDN# LED3 R75 10K EMIRQ# R96 332R D8 1 2 GREEN R80 10K NC R81 10K NC R78 10K NC LED4 1 D9 2 R97 332R YELLOW The 1.8V core power supply is external by default, to minimize 3.3V power consumption. Use of LAN8700 LAN8700 3.3V/1.8V internal regulator can be done by disconnected J36 and R71 REG_OFF Pullup. AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-17 6351A­CAP­14-Nov-07 Requirements 2.4.1.4 F4: RS232 RS232 Driver An ADM3202 ADM3202 RS232 RS232 driver is implemented for signal adaptation between RS232 RS232 signals (RXD, TXD) on the debug port connector and AT91CAP9 AT91CAP9 Debug unit 3.3V signals (DRXD, DTXD). The implementation is shown below: 3V3 11 C120 1 2 2 RXD 100nF C123 1 2 6 TXD 100nF 14 3V3 3 4 C1C2+ V+ V- 5 C2- C121 100nF 3V3 C122 100nF R62 100K R63 0R 11 T 7 1 1 C1+ 2 J34 SUBD9_M_C 1 6 2 7 3 8 4 9 5 DTXD R64 10 T R65 0R 1K 10 13 12 R 8 R154 0R DRXD 9 R 15 GND TP67 2.4.1.5 U10 VCC 1 0R R153 2 16 C119 100nF 1 2 1 ADM3202ARNZ ADM3202ARNZ F5: USB Host and Device 2.4.1.5.1 USB Host The two USB v2.0 Host interfaces are managed by the AT91CAP9 AT91CAP9 USB Host port, which handles OHCI protocol as well as USB v2.0 Full-speed and Low-speed protocols. Two NUF2101 NUF2101 USB filters are implemented for ESD protection and line adaptation (26.3 to 33.7). One 0603 footprint is implemented on each signal to adjust 39 line impedance if necessary. One 500 mA SMD fuse is added on 5V power supply of each port. F1 F2 1 1 5 0R R226 2-18 6351A­CAP­14-Nov-07 NUF2101MT1G NUF2101MT1G C148 100nF 2 HDP B 3 D-OUT 1 0R B1 B2 B3 B4 FIX4 FIX3 A FIX2 FIX1 1 1 R224 0R L12 1 D+OUT J37 2 4 D-IN C147 10uF_1210 2 1 C146 100nF L11 1 D+OUT 6 D+IN 5V B A1 A2 A3 A4 6 D+IN HDMA R99 2 5 5V 0R 1 R98 5V C145 100nF 2 R223 0R HDMB 2 0A5_13V 2 2 C144 10uF_1210 2 1 0A5_13V 2 2 2 5V C149 100nF 3 D-OUT 4 D-IN NUF2101MT1G NUF2101MT1G HDP A 0R R225 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements 2.4.1.5.2 USB High Speed Device The USB v2.0 High Speed Device interface is managed by the AT91CAP9 AT91CAP9 USB High Speed Device port compliant with the USB rev 2.0 High Speed device specification. The necessary 1.5k Pull-up to 3.3V on HSDP (and FSDP) is included in the AT91CAP9 AT91CAP9 USB device port. The implementation is shown below: R100 12K4 USB_PRES C150 10uF_121 0 R101 22K 2 1 VBUS HSDM 1 R102 39R C151 100nF 1 2 1 2 3 4 5 6 3 S1 GND 2 FSDM 1 D15 S2 VDD S3 S4 6 2 2 J38 R103 0R 1 VBUS 5 C152 22pF NC 4 R105 39R SRV05-4 SRV05-4 1 2 FSDP 2 1 2923 04-1 C153 22pF NC HSDP 2.4.1.6 F6: Touch Screen Controller and LCD Panel An ADS7843E ADS7843E touch screen controller is implemented on the board. It's controlled by the AT91CAP9 AT91CAP9 SPI0 bus, with SPI0_NPCS1 chip select. The figure below, derived from the AT91SAM9261-EK AT91SAM9261-EK schematics, shows the implementation: TOUCH SCREEN CONTROLLER 3V3 3V3 VCC_ADS R124 100K R125 100K ADS7843E ADS7843E C169 10uF_1210 C170 pin 1 R133 0R C171 pin 10 TP22 VREF_ADS 1 TP20 VCC_ADS L18 4,7µH 220mA 2 C172 10nF TP19 TP21 1 2 TP18 BUSY IRQ 0R 3V3 GND R130 100K 9 0R 1 VREF IN3 IN4 R129 VREF_ADS R127 0R 1 7 8 R128 10nF R131 100K 13 11 SPCK MOSI MISO TSC_CS# 2 BUSY PENIRQ 16 14 12 15 1 DCLK DIN DOUT CS 2 X+ Y+ XY- 10nF U14 6 TWO USER'S ANALOG INPUTS Ful l-Scale Input Span 0 to VREF 2 3 4 5 VCC VCC X_LEFT Y_UP X_RIGHT Y_LOW 2 1 10 R126 22R pin 9 The LCD panel controlled the AT91CAP9 AT91CAP9 LCD Controller. AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-19 6351A­CAP­14-Nov-07 Requirements 2.4.1.7 F7: Audio DAC The AT73C213 AT73C213 DAC is used for the I²S audio output. It's controlled by the AT91CAP9 AT91CAP9 SPI0 bus, with SPI0_NPCS2 chip select. I²S DAC dedicated serial interface is managed by AT91CAP9 AT91CAP9 SCC0 bus. The implementation is shown below: 3V3 R107 100K U12 For EMI protection 6 MONON AVDD LINER AVDDHS LINEL VCM 31 J40 HEADPHONE LINE-OUT 32 3 C163 330pF NC 2 2 1 1 2 1 2 4 2.4.1.8 C161 100uF 2 1 R108 0R 3 + 5 + CONN_PHONEJACK_STEREO_CMS R109 0R C164 330pF NC 4 1 C162 100uF 8 AUXP HSR MCLK SDIN LRFS BCLK HSL INGND GNDB VCC_DAC C158 1 2 5 1 VCC_DAC 2 4,7µH 220mA 2 9 L13 1 C159 100nF 2 10uF_1210 20 17 19 18 1 C156 100nF C157 100nF C154 10uF_1210 C155 10uF_1210 C160 2 10uF_1210 MCLK SDIN LRFS BCLK GNDD 33 3V3 1 AUXN AT73C213 AT73C213 R110 R111 1K 1K VREF RESET# 24 1 VDIG 1 MONOP 2 7 PAINP J39 22 21 2 29 SMODE RSTB MISO MOSI SPCK AUDIO_CS# 1 30 HPN LPHN 25 26 27 28 2 16 SPI_DOUT SPI_DIN SPI_CLK SPI_CSB 1 11 10 PAINN VBAT CBP HPP 2 15 12 14 13 23 F8:Analog Input Adaptation Analog input adaptation is realized by an AD8040 AD8040 low-power high-speed rail-to-rail IO amplifier. ADC[1.4] output signals of the amplifier drive the AD[0.7] ADC embedded in the AT91CAP9 AT91CAP9. Table 2-18. Analog Signal Name J52 jumper Position J53 jumper Position J54 jumper Position J55 jumper Position AT91CAP9 AT91CAP9 ADC Name ADC1 1-2 (default) - - - AD4 ADC1 2-3 - - - AD0 ADC2 - 1-2 (default) - - AD5 ADC2 - 2-3 - - AD1 ADC3 - - 1-2 (default) - AD6 ADC3 - - 2-3 - AD2 ADC4 - - - 1-2 (default) AD7 ADC4 - - - 2-3 AD3 The implementation is shown below 2-20 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements D11 BAT54SLT1G BAT54SLT1G 1 2 VDDANA 3 R112 1K U13A 2 R113 100K NC + ADC1 PB17 1 J52 1X3PTS_MD_2MM54 2MM54 PB13 3 - ADC1 AD8040ARZ AD8040ARZ D12 BAT54SLT1G BAT54SLT1G 1 2 VDDANA 3 R114 1K U13B 6 R115 100K NC + 7 ADC2 PB18 1 J53 1X3PTS_MD_2MM54 2MM54 PB14 3 2 5 J41 1 2 3 - ADC2 AD8040ARZ AD8040ARZ ANALOG_I1 ANALOG_I2 ANALOG_I3 ANALOG_I4 D13 BAT54SLT1G BAT54SLT1G 1 2 R116 0R NC R117 1K VDDANA U13C 10 9 R118 100K NC 8 1 J54 1X3PTS_MD_2MM54 2MM54 PB15 3 ADC3 VDDANA U13D AD8040ARZ AD8040ARZ 4 R119 2 R120 100K NC C165 100nF 13 + 14 ADC4 PB20 1 J55 1X3PTS_MD_2MM54 2MM54 PB16 3 2 1 12 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide PB19 - VDDANA 1K ADC3 AD8040ARZ AD8040ARZ 3 D14 BAT54SLT1G BAT54SLT1G 1 2 + 2 MKDS-1/6-3.81 3 1 2 3 4 5 6 - ADC4 11 2-21 6351A­CAP­14-Nov-07 Requirements 2.4.1.9 F9: SD Card The AT91CAP9 AT91CAP9 MCI is directly connected to the SD Card slot. 68k pull-up resistors are added on the MCI_DA[0.3] data signals. The implementation is shown below: 8 7 6 5 3V3 3V3 3V3 1 2 3 4 R134 3K3_1% (PC21/LCDD17/E PC21/LCDD17/E_TX3) MCI_DA1 MCI_DA0 (PA19/MCI1 PA19/MCI1_D1/ISI_D3) (PA18/MCI1 PA18/MCI1_D0/ISI_D1) MCI_CK (PA16/MCI1 PA16/MCI1_CK/ISI_D0) MCI_CDA MCI_DA3 MCI_DA2 2 R135 MCI_CD C173 10nF 1 2 1 R227 68K (PA17/MCI1 PA17/MCI1_CD/ISI_D1) (PA21/MCI1 PA21/MCI1_D3/ISI_D5) (PA20/MCI1 PA20/MCI1_D2/ISI_D4) 0R 8 7 6 5 4 3 2 1 9 J43 12 11 10 FPS009-3202BL FPS009-3202BL 2.4.1.10 F10: Power Supplies and Low-power Mode 0603 footprint (0 resistor) or jumpers are implemented on power supplies in order to measure the current. 2.4.1.10.1Power Supplies Power supply of the board is assumed either by an external 5V/10W AC/DC sector adapter or Li-Ion external battery (VIN_PMC): VIN_PMC 2 5VDC_SECTOR D3 R229 0R 1 1 C55 10uF_1210 C56 + 10UF_16V Q9B 3 5VDC_SECTOR 4 2 2 1 MBRS340T3G MBRS340T3G 5 6 R16 10K SI5515DC SI5515DC VBAT The different power supplies of the board are provided by two AT73C224 AT73C224 chips from the Atmel family of AT73 products (controlled by the AT91CAP9 AT91CAP9 TWI bus) and one LTC3412 LTC3412 as shown below: 2-22 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements First AT73C224 AT73C224 ­ 5V/1A (SEPIC buck boost) ­ 1.8V_FPGA/500mA (boost) 1 ­ 1.2V VBACKUP 2 10 31 32 30 1 TP8 C33 22p F 29 26 27 28 13 14 15 TWCK TWD FP GA_POK 5V_ITB R11 10K EN_PMC R167 10K 12 DL1 DH1 VDD4 VO1 VO4 VDD2 VDDRTC VBK XIN XOUT SW2 GND2 VO2 CK32 2 20 5VB_DL1 19 8 7 5VB_DH1 Q1B SI55 15DC + 2 1 C60 100 uF 18 9 VIN_PMC_SHDN 1V8_SW 2 16 17 11 C32 1UF_ 16V 1V8_FPGA 1V8_SW 2 1 L2 6µH8_7 10mA 2 1V8_FPGA 1 D1 D2 D3 D4 POK ITB Q1A SI5515DC SI5515DC 1 5VB_SENSE TP60 C34 + 33UF_10V 2 VIN_PMC VBACKUP Y1 327 68Hz_1 2.5pF 24 GND3 21 5V C206 4,7uF_ 16V 1 2 2 VBG VINT VCAPP EN GND/AVS S VCAPN 8 5 4 7 AT73C224 AT73C224 C37 220 0pF 1 VO4_PMC1 VSENSE 1 L1 6,8µH_2A4 1 C26 22u F_12 10 2 22 C35 470 nF 2 23 C29 22p F 1 VO3 R8 0R047 0R047_ 2512 2 1 2 VDD1 2 3 VDD0 2 1 VO3_PMC1 VDDDIG VDD3 1 2 U4 2 C25 10nF 6 3 25 6 5 VIN_PMC_SHDN R176 0R 2 1 1 1 3V3 2 100 nF C24 2 1 1 L21 6,8µH_2A4 VIN_PMC_SHDN C23 1UF_16V 1 2 4 VIN_PMC_SHDN C36 100nF 33 Second AT73C224 AT73C224 ­ 3.3V/1AZ (SEPIC buck boost) ­ 1.2V_CAP9/500 CAP9/500 mA (boost) 10K 3V3 R140 10K TP9 29 VO1 VO4 VDD2 VDDRTC VBK XIN XOUT SW2 GND2 VO2 3V3BB_DH1 CAP9_POK 3V3_ITB R168 10K 2 1 S4 BP 3 4 EN_PMC 12 16 VIN_PMC_SHDN 1V2_SW 2 17 11 C50 1UF_16 V 1V2_SW 2 1V2_CAP9 1 1V2_CAP9 L5 6µH8_710mA 1 2 TP64 C51 + 33UF_10V VCAPP VCAPN 8 5 4 7 GND/AVSS AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide C48 100uF 2 VBG VINT EN AT73C224 AT73C224 + 18 CK32 D1 D2 D3 D4 POK ITB 3 Q2B SI5515DC SI5515DC 1 1 26 27 28 13 14 15 8 7 2 9 1 TWCK TWD 3V3 C45 4,7uF_16V 2 2 3V3BB_DL1 19 Q2A SI5515DC SI5515DC 3V3BB_SENSE 20 1 4 DL1 DH1 VDD4 21 1 R10 10K 10 31 32 30 GND3 C46 22uF_1210 2 2 1 R139 1 C49 4,7 uF_16V 24 1V8_CAP9 VSENSE 1 2 TP63 2 1 VO3 22 L4 6,8µH_2A4 1 C54 2200pF 1 23 VDD1 2 3 VDD0 VDD3 R15 0R047 0R047_2512 2 1 1 VDDDIG 1 6 2 25 U5 2 1V8_CAP9 2 C44 10nF VIN_PMC_SHDN VO3_PMC2 R177 0R 1 2 3V3 L3 6,8µH_2A4 6 5 100nF C43 2 VIN_PMC_SHDN C52 470nF 2 1 VIN_PMC_SHDN C38 1UF_16 V 1 2 1 ­ 1.8V_CAP9/200 CAP9/200 mA (LDO) C53 100nF 33 2-23 6351A­CAP­14-Nov-07 Requirements LTC3412 LTC3412: 1.2V_FPGA/1A VIN_PMC_SHDN 9 16 14 15 11 10 1 2 1UH_1A8 6 SYNC/MODE 1 PGND PGND 12 13 17 R165 C204 1K 220p F 100V NC 2 Case R164 294K SGND 1 RT R160 1K LTC3412EFE LTC3412EFE C203 2200pF 2 C200 22uF_1210 1 R166 6K81 4 2 5 J58 RUN/SS 8 R163 10K C202 2200pF TP65 2 SW14 SW15 SW11 SW10 VFB R162 820K NC 1V2_FPGA 1 1 7 C198 2200pF C199 220p F 100V 1 1 2 1 2 C197 220p F 100V R159 0R L20 ITH 1 C196 1UF_16V 2 1 C195 22uF_1210 2 2 1 3 PGOOD 2 2 FPGA_POK PVIN PVIN U18 SVIN R158 100K 1 VIN_PMC_SHDN R169 0R C201 1UF_16V NC R161 12K4 2.4.1.10.2Low-power Mode The power supply of this 3 PMC (VIN_PMC_SHDN) is managed by the AT91CAP9 AT91CAP9 SHDN signal (power by VDDBU. (See "F12: RTC and Backup" on page 2-25.) When AT91CAP9 AT91CAP9 commands low power mode, it drives it's SDHN pin low and so switches off the 3 PMC power supply. The implementation of the switch is shown below: C59 100nF R142 100K 4 2 Q8B SI5515DC SI5515DC 8 7 SHDN 1 R141 100K 2 C58 10nF 5 6 3 VIN_PMC_SHDN 1 VIN_PMC Q8A SI5515DC SI5515DC 2 1 No external pull-up is required on the SHDN signal (even at start-up). 2-24 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements 2.4.1.11 F11: Battery Charger An Atmel AT73C205 AT73C205 stand alone battery charger is implemented on the board. It manages the charge of an external Li-Ion battery plugs on the EI1 interface, from 5V AC/DC sector adapter or VBUS USB Device external power source. The battery charger is controlled by the AT91CAP9 AT91CAP9 TWI bus. Two LEDs (yellow and green) indicate the charge status. The implementation of the AT73C205 AT73C205 battery charger is shown below. 1 5VDC_SECTOR 2 R1 1K 1 6 7 MAXS LED1 LED2 ACDC USB BAT R3 10K TW D TW CK CHARGER_IRQ C282 3V3 10nF 2 1 2 2 1 R173 0R 2 VBAT 3 R174 BATS 1 2 U1 8 D2 GREEN 3V3 C6 + 10UF_16V 1 1 C8 1nF TS 11 12 13 14 15 16 EN DIN/ISET1 ADCAUX DOUT/ISET2 SCLK/IUSBSET CSB/BATTYPE ITB GND GNDPAD 4 9 0R BAT_TS TP1 10 NC C9 10uF_1210 1 D1 YELLOW 2 2 2 C5 10uF_1210 1 J4 2 3 HE14_3PTS 2 R2 1K 1 R172 0R MAXS VBUS 1 BATTERY CHARGER C7 10uF_1210 C3 + 10UF_16V 2 1 C4 100nF C1 10uF_1210 2 C2 100nF 1 2 1 5VDC_SECTOR 5 17 AT73C205 AT73C205 2.4.1.12 F12: RTC and Backup 2.4.1.12.1Backup The first AT73C224 AT73C224 PMC provides a 3V VBACKUP power supply on its VBK power pin, from non-managed VIN_PMC supply on it's VDDRTC power in. This VBACKUP power supply recharges a manganese-lithium rechargeable coin battery in the EI12 interface. It also supplies the AT73C239 AT73C239 chip on it's VBAT power pin, which generates (VO4 output) 1.2V_SAVE to supply the VDDBU AT91CAP9 AT91CAP9 power supply. When no external power supplies are applied on the board, the AT73C239 AT73C239 is only supplied by the manganese-lithium rechargeable coin battery to maintain the VDDBU AT91CAP9 AT91CAP9 power supply 2.4.1.12.2RTC The first AT73C224 AT73C224 PMC described above integrates an RTC module with an external 32,768 kHz quartz connection. (See "First AT73C224 AT73C224" on page 2-23.) The RTC module is powered by a non-managed VIN_PMC source on it's VDDRTC power pin. When no external power supplies are applied on the board, the RTC module is powered on it's VBK power pin by the manganese-lithium rechargeable coin battery, VBACKUP supply. AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-25 6351A­CAP­14-Nov-07 Requirements 2.4.1.13 F13: Reset Configuration Reset of the board is assumed by the reset circuit as shown below. NRST 3V3 R17 100K 3V3 1 RESET_CAP9# R20 0R D4 BAT54CWP BAT54CWP bF 3 2 1 R18 10K C57 10UF_1210 1 0R R21 2 POR FPGA_POK 2 CAP9_POK 3 1X3PTS_MD_2MM54 2MM54 J16 NTRST 2 1 3 4 R19 10K 3V3 BAT54SLT1G BAT54SLT1G 1 2 D5 R143 0R DONE_FPGA_CAP9 3 BP S5 R144 1K NC DONE_FPGA 1 2 RESET_FPGA# 3 3V3 1X3PTS_MD_2MM54 2MM54 J17 R145 10K 8 7 Q9A SI5515DC SI5515DC 2 1 RST_SOFT_FPGA Each AT73C224 AT73C224 PMC provides an active low reset signal when an error occurs on one of it's power supply outputs. These open-drain output signals, CAP9_POK and FPGA_POK, with 10k to 3.3V pull-up, are connected to a push button for manual hardware reset and provide the POR signal. Reset signals are: POR: Power On Reset signal, managed by CAP9_POK, FPGA_POK or manual hardware reset push button (active low) NRST: ICE probe AT91CAP9 AT91CAP9 microcontroller reset signal (active low) RESET_CAP9: AT91CAP9 AT91CAP9 microcontroller reset signal (active low) NTRST: test reset (active low) RESET_FPGA: FPGA reset signal, it drives the nCONFIG signal of the FPGA (active low) RST_SOFT_FPGA: FPGA reset from AT91CAP9 AT91CAP9 microcontroller (active high) 2-26 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements Two jumpers on the 3-pin connectors, J16 and J17 define reset configuration of the board and the way status reset signals are driven. Status reset signals are: DONE_FPGA: the CONF_DONE FPGA configuration status signal DONE_FPGA_CAP9: indicates the FPGA configuration status to the AT91CAP9 AT91CAP9 microcontroller (PIO Table 2-19. Reset Configuration Reset Configuration Reset Description J16 Jumper Position J17 Jumper Position 1 Uncontrolled reset-then-start CAP9 and FPGA order 1-2 1-2 2 Reset CAP9 resets FPGA, start CAP9 and then start FPGA 1-2 2-3 3 Reset FPGA resets CAP9, start FPGA and then start CAP9 2-3 1-2 4 Forbidden (no reset available) 2-3 2-3 2.4.1.14 F14: Programming and Configuration 2.4.1.14.1JTAG Programming Two different JTAG programming chains are implemented on the board: Stand-alone JTAG chains (default) Each programmable device (microcontroller and FPGA) has it's own JTAG programming chain. (See "EI11: JTAG and Serial Configuration Interfaces" on page 2-7.) ­ ICE-JTAG chain for AT91CAP9 AT91CAP9 JTAG programming ­ USB-Blaster chain for FPGA JTAG programming ICE-only JTAG daisy chain It's possible to use only the ICE-JTAG interface to program microcontroller and FPGA on a unique JTAG daisy chain. AT91CAP9 AT91CAP9 is the first device in the daisy chain, FPGA is the second one. Configuration of the jumper positions must be as shown in the table that follows. Table 2-20. Jumper Position Configuration JTAG Programming Chain J59 Jumper Position J60 Jumper Position J61 Jumper Position J62 Jumper Position J63 Jumper Position J64 Jumper Position Note Stand-alone JTAG chains 1-2 2-3 2-3 2-3 2-3 2-3 Default chain ICE-only JTAG daisy chain 2-3 1-2 1-2 1-2 1-2 1-2 - 2.4.1.14.2Serial Device Configuration Three ways can be used to program the FPGA EPCS16 EPCS16 serial device. Serial device configuration port The FPGA EPCS16 EPCS16 serial device configuration can be programmed via the EI11 serial device configuration port with Altera USB Blaster probe. Altera SFL (Serial Flash Loader) function AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-27 6351A­CAP­14-Nov-07 Requirements In this case, the serial device is programmed via FPGA JTAG interface. The advantage is that it makes it possible to configure the FPGA and program serial configuration devices using the same JTAG interface. The disadvantage is that programming is very slow because SFL needs to configure the FPGA before programming the serial configuration device. Microcontroller programs serial configuration device In this case, the AT91CAP9 AT91CAP9 microcontroller drives the following signals via its PIO Table 2-21. AT91CAP9 AT91CAP9 PIO Signal Control Signal Name Signal Description AT91CAP9 AT91CAP9 I/O nCE Configuration Chip enable PB6 nCSO Configuration Chip select PB3 DCLK Configuration Clock pin PB7 ASDO_FPGA Configuration Read enable PB8 To use this mode of programming, R216 to R219 0 resistors must be mounted and reset configuration must be set to 2. (See "F13: Reset Configuration" on page 2-26.) Once the serial configuration device is programmed, FPGA configuration is initiated at start-up between FPGA and the serial configuration device via the DATA0, DCLK, nCSO and ASDO signals. The FPGA AS mode configuration scheme is set by the MSEL[0.3] signals (default Fast AS). Table 2-22. FPGA AS Mode Configuration Configuration Scheme MSEL3 MSEL2 MSEL1 MSEL0 Fast AS (40 MHz) 1 0 0 0 Remote system upgrade fast AS (40 MHz) 1 0 0 1 AS (20 MHz) 1 1 0 1 Remote system upgrade AS (20 MHz) 1 1 1 0 2.4.1.15 F15: Prototyping Area Two prototyping areas are implemented on the board. The first one is a 20x18 points, 1.24 mm-pitch matrix, with two 1x8 points, 1.24 mm-pitch line, connected to 5V and 3.3V added on top of the matrix, and 1x20 points, 1.2 4 mm pitch line, connected to GND added on the bottom of the matrix. The second one is a 10x8 points, 2.54 mm-pitch matrix, with two 1x4points, 2.54 mm-pitch line, connected to 5V and 3.3V added on top of the matrix, and 1x8 points, 2.54 mm-pitch line, connected to GND added on the bottom of the matrix. 2-28 6351A­CAP­14-Nov-07 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Requirements 2.4.2 Physical Characteristics 2.4.2.1 Mechanical The format of the CAP9-STK board is 185x120 mm. 2.4.2.1.1 LCD Panel Support An LCD panel support is implemented on the board to receive the TX09D70VM1CCA TX09D70VM1CCA Hitachi LCD. 2.4.2.1.2 BGA Socket A 22.225x22.225 mm BGA socket can be implemented on the board to receive the AT91CAP9 AT91CAP9 400-ball LFBGA. 2.4.2.2 Electrical The nominal consumption of the board is less than 10 W. 2.4.2.3 Environmental No requirements are specified. However, the board is designed to run normally under 0°C to 55°C temperature. All components mounted on the board are RoHS compliant. 2.4.2.4 Packaging The CAP9-STK packaging includes the following items: The CAP9 Starter Kit Standalone Board wrapped in an ESD packaging. A CD of documentation and software, including software development tools and FPGA development tools The power supply of the board with adaptors for Europe, United Kingdom, China and United States A set of communication cables, including cables for USB, Ethernet and serial port. A manganese-lithium 3V rechargeable coin battery AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 2-29 6351A­CAP­14-Nov-07 Section 3 Board Strap and Switch Configuration 3.1 Connectors 1x2 Table 3-1. Connectors 1x2 Name J5 J6 (1) Descriptions Position (default) Closed Not VIN_AT73C239 AT73C239 power supply is 5V if S1 in 1-3 Connected Open VIN_AT73C239 AT73C239 power supply is VIN_SURV_AT73C239 AT73C239 if S1 is in 1-2 position. VIN_AT73C239 AT73C239 power supply Connector VIN_SURV_AT73C239 AT73C239 is VIN_PMC if S1 is in 1-2 VIN_SURV_AT73C239 AT73C239 power supply is VIN_PMC if S2 not power supply is 3V3 if S2 is position and S2 is in 1-3 is in 1-3 position. Mounted in 1-2 position. position. J7 1-2 Reset out of AT73C239 AT73C239 (U3) if VIN_AT73C239 AT73C239 < 2.6V on FIQ# (Fast Interrupt) of CAP9 FIQ# = open (not used by CAP9) J8 1-2 TP2 = VO1 of AT73C239 AT73C239 (U3) Measure VO1 current of AT73C239 AT73C239 (U3) if a charge is connected between TP2 and TP.3 J9 1-2 TP4 = VO2 of AT73C239 AT73C239 (U3) Measure VO2 current of AT73C239 AT73C239 (U3) if a charge is connected between TP4 and TP5. J11 1-2 VBAT of AT73C239 AT73C239 (U3) supply by VIN_AT73C239 AT73C239 if S9 is in 1-3 posotion. J12 1-2 TP6 = VO3 of AT73C239 AT73C239 (U3) Measure VO3 current of AT73C239 AT73C239 (U3) if a charge is connected between TP6 and TP7. J20 1-2 VDDCORE supply by 1V2 VDDCORE is off. J21 1-2 VDDIOM supply by 1V8 VDDIOM is off. J22 1-2 VDDPLL supply by 3V3 VDDPLL is off. J23 1-2 VDDIOP0 supply by 3V3 VDDPLL is off. J24 1-2 VDDIOP1 supply by 3V3 if R26 is connected but R27 is not connected. VDDIOP1 supply by 1V8 if R27 is connected but R26 is not connected. VDDIOP1 is off. J25 1-2 VDDUPLL supply by 1V2 VDDUPLL is off. J26 1-2 VDDUTMIC supply by 1V2 VDDUTMIC is off. J27 1-2 VDDUTMII supply by 3V3 VDDUTMII is off. J29 1-2 VDDANA supply by 3V3 filtered VDDANA is off. J39 1-2 Chip select audio DAC (U12) by CAP9 The audio DAC (U12) not selected. AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide VBAT of AT73C239 AT73C239 (U3) is not connected. VBAT of AT73C239 AT73C239 (U3) supply by VBACKUP if S9 is in 1-2 postion. 3-1 6351A­CAP­14-Nov-07 Board Strap and Switch Configuration Table 3-1. Connectors 1x2 (Continued) Descriptions Name Position (default) J44 1-2 Chip select SPI DATA FLASH (U17) by CAP9 The SPI DATA FLASH (U17) not selected J48 1-2 TP24 = VO3_PMC1 of AT73C224 AT73C224 (U4) Measure VO3_PMC1 current of AT73C224 AT73C224 (U4) if a charge is connected between TP24 and TP25 J49 1-2 TP26 = VO4_PMC1 of AT73C224 AT73C224 (U4) Measure VO4_PMC1 current of AT73C224 AT73C224 (U4) if a charge is connected between TP26 and TP27 J50 1-2 TP28 = VO3_PMC2 of AT73C224 AT73C224 (U5) Measure VO3_PMC2 current of AT73C224 AT73C224 (U5) if a charge is connected between TP28 and TP29 J58 1-2 1V2_FPGA is connected 1V2_FPGA is off J66 1-2 Flash NAND CE# signal is driven by FN_CE# CAP9 signal Flash NAND CE# signal is pull-up to 1V8 J67 1-2 1V2_FPGA is connected Note: 3.2 Closed Open 1V8_FPGA is off 1. J6 connector is not mounted on the prototype. Connectors 1x3 Table 3-2. Connectors 1x3 Descriptions Name Position (default) J16 1-2 POR (manually or AT73C224 AT73C224) resets the CAP9 Reset sthe CAP9 during the programming of FPGA J17 2-3 POR (manually or AT73C224 AT73C224) resets the FPGA Resest the FPGA by CAP9 software J28 1-2 VDDBU supply by 1V2_SAVE VDDBU supply by 1V2 J31 1-2 BMS pull-up to 3V3 BMS tied to GND J52 1-2 Analog input 1 on CAP9 ADC channel 4 Analog input 1 on CAP9 ADC channel 0 J53 1-2 Analog input 2 on CAP9 ADC channel 5 Analog input 2 on CAP9 ADC channel 1 J54 1-2 Analog input 3 on CAP9 ADC channel 6 Analog input 3 on CAP9 ADC channel 2 J55 1-2 Analog input 4 on CAP9 ADC channel 7 Analog input 4 on CAP9 ADC channel 3 J59 1-2 TDO ICE port signal is CAP9 TDO signal (with J60 on 2-3). FPGA TDI signal is CAP9 TDO signal (with J64 on 1-2). J60 2-3 TDO ICE port signal is FPGA TDO signal (with J63 on 1-2). TDO ICE port signal is CAP9 TDO signal (with J59 on 1-2). J61 2-3 FPGA TMS JTAG signal is ICE port TMS signal. FPGA TMS JTAG signal is FPGA JTAG port TMS signal. J62 2-3 FPGA TCK JTAG signal is ICE port TCK signal. FPGA TCK JTAG signal is FPGA JTAG port TCK signal. J63 2-3 TDO ICE port signal is FPGA TDO signal (with J60 on 1-2). FPGA JTAG port TDO signal is FPGA JTAG TDO signal. J64 2-3 FPGA TDI JTAG signal is CAP9 TDO signal (with J59 on 2-3). 3-2 6351A­CAP­14-Nov-07 1-2 2-3 FPGA JTAG TDI signal is FPGA JTAG port TDI signal. AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide Board Strap and Switch Configuration 3.3 Switches Table 3-3. Switches Descriptions Name Position (default) S1 1-3 VIN_AT73C239 AT73C239 power supply is 5V if J5 is connected. VIN_AT73C239 AT73C239 power supply is VIN_SURV_AT73C239 AT73C239 Not connected by default for AT73C239 AT73C239 (connected for power supply. AT73C237 AT73C237 mounting). S2 1-3 VIN_SURV_AT73C239 AT73C239 power supply is 3V3 power supply. VIN_SURV_AT73C239 AT73C239 power supply is VBACKUP (J6 connector not mounted, VBACKUP strap on S2 pin 3). S7 1-2 AT73C239 AT73C239 TWCK signal is pull -up to VIN_SURV_AT73C239 AT73C239 and controlled by CAP9 PA7 PIO (allows hibernate mode). AT73C239 AT73C239 TWCK signal is CAP9 I2C bus TWCK signal. S8 1-2 AT73C239 AT73C239 TWCK signal is VIN_SURV_AT73C239 AT73C239 power supply. AT73C239 AT73C239 TWD signal is CAP9 I2C bus TWD signal. S9 1-2 AT73C239 AT73C239 VBAT power supply is VBACKUP. AT73C239 AT73C239 VBAT power supply is VIN_AT73C239 AT73C239 power supply. 1-2 AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 1-3 3-3 6351A­CAP­14-Nov-07 Section 4 AT91CAP9-STK AT91CAP9-STK Schematics 4.1 This section contains the following appended schematics Top View Battery Charger and Backup PMC AT73C224 AT73C224 Power Switch and Reset FPGA Core Supply IO Connectors and Proto Area CAP9 Power EBI and PIO System USB Clock FPGA Power FPGA IO Bank FPGA IO Bank FPGA Clock and Configuration Debug Ethernet SMSC USB Host and Device Audio Analog LCD and TSC SDCARD SDRAM, NAND and DataFlash AT91CAP9-STK AT91CAP9-STK Starter Kit User Guide 4-1 6351A­CAP­14-Nov-07 5 4 3 2 1 D D PAGE 01 : TITLE PAGE 02 : TOP VIEW PAGE 03 : BATTERY CHARGER & BACKUP PAGE 04 : PMC AT73C224 AT73C224 PAGE 05 : POWER SWITCH & RESET PAGE 06 : FPGA CORE SUPPLY PAGE 07 : IO CONNECTORS &PROTO AREA PAGE 08 : CAP9 POWER C PAGE 09 : EBI & PIO C PAGE 10 : SYSTEM USB CLOCK PAGE 11 : FPGA POWER PAGE 12 : FPGA IO BANK PAGE 13 : FPGA CLOCK & CONFIG PAGE 14 : DEBUG PAGE 15 : ETHERNET SMSC PAGE 16 : USB HOST & DEVICE PAGE 17 : AUDIO PAGE 18 : ANALOG B PAGE 19 : LCD & TSC B PAGE 20 : SDCARD PAGE 21 : SDRAM, NAND & DATAFLASH A A 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic TITLE Format A3 Date: Dessinateur / Drawer Référence / Reference O. Boitet ADEC101389001 ADEC101389001 Friday, November 02, 2007 Page 1 Rév. 2C de / of 21 5 4 3 03 - AT91CAP9 AT91CAP9 3V3 3V3 1V8_CAP9 1V8 D[16.31] 1V2_CAP9 3V3 1V8_CAP9 1V8_FPGA D 5V 1V2 3V3 TWCK TWD 1V8_CAP9 A[0.17] VDDANA GND 1V2_CAP9 1V2_SAVE 5V_ITB PB10 VDDMPIO PA11 1V2_SAVE 1V2_FPGA 3V3_ITB CHARGER_IRQ PIO_BACKUP VBUS VBUS SHDN FIQ# RESET_FPGA# RST_SOFT_FPGA DONE_FPGA DONE_FPGA_CAP9 PA7 NRST NTRST RESET_CAP9 SHDN A[2.15] SDCLK SDCKE SDCS SDRAS SDCAS SDW E SDA10 SDA10 SDCLK SDCKE SDDRCS RAS CAS SDWE SDA10 SDA10 NBS[0.3] BA[0.1] BA0 BA1 NBS[0.3] NBS0 NBS1 NBS2 NBS3 02 - IO CONNECTORS & PROTO AREA VDDIOM VDD_MEM 5V GND SD_CLK SD_CKE SD_CS# SD_RAS# SD_CAS# SD_WE# SDA10 SDA10 PCI VCTRL PC[6.11] GND PA[0.31] 09 - MEMORY PC[22.27] PC2 PC1 PC3 SPCK MOSI MISO TSC_CS# BUSY IRQ TW D TW CK PA2 PA1 PA0 PA3 PB[0.31] PC[0.31] PD[0.12] MPIOA[0.31] MPIOB[0.44] MPIOB24 MPIOB24 04 - FPGA STRATIX 2 3V3 1V8 VDDMPIO VDDMPIO 1V2_FPGA TCK_ICE TMS_ICE TDO_FPGA TDO_CAP9 NTRST 1V2 VCCIO4 VCCIO4 VCCIO6 VCCIO6 VCCIO7 VCCIO8 nCSO_CAP9 nCE_CAP9 DCLK_CAP9 ASDO_CAP9 JTAG_TCK JTAG_TMS JTAG_TDO_FPGA JTAG_TDO_CAP9 GND MPIOA[0.31] MPIOB[0.44] FPGA_IO[0.95] RESET_FPGA# DONE_FPGA FPGA_PLLOUTp FPGA_PLLOUTn MPIOA[0.31] MPIOB[0.44] FPGA_IO[0.95] PD[0.12] 5V HSDM HSDP PD[0.12] HSDM HSDP NTRST PB3 PB6 PB7 PB8 HSDM HSDP FSDP FSDM PA8 VBUS MPIOA[0.31] MPIOB[0.44] HDMB HDPB HDMA HDPA 3V3 3V3 PB[0.31] MPIOB24 MPIOB24 FPGA_PLLOUTn VDDIO_ETH PA[0.31] PC[0.31] TWCK TWD FPGA_IO[0.95] FPGA_PLLOUTp 3V3 FPGA_PLLOUTp FPGA_PLLOUTn PCK0 PCK1 02 - IO CONNECTORS & PROTO AREA FSDP FSDM USB_PRES PB21 PB31 EREFCK EPWDN# VBUS HDMB HDPB HDMA HDPA PB26 PB25 PB27 ETX1 ETX0 PB24 PB23 ETX[1.0] ETX[1.0] ETXEN DRXD DTXD ERX1 ERX0 ERX[1.0] PB28 PB22 PB9 ECRSDV ERST# PC30 PC31 PC29 PA27 C FPGA_IO[0.95] GND ERX[1.0] ERXER HDMB HDPB HDMA HDPA TCK_ICE TMS_ICE TDO_FPGA TDO_CAP9 PB11 PB29 PB30 EMIRQ# EMDC EMDIO B 05 - COMMUNICATION 03 - AT91CAP9 AT91CAP9 VCCIO7 VCCIO8 PC[0.31] PD[0.12] 05 - COMMUNICATION TWD TWCK FSDP FSDM 07 - LCD & TSC 3V3 PB[0.31] PC[0.31] NANDCS NANDW E NANDOE 5V PA[0.31] PC5 PC4 DCLK HSYNC DTMG 1V8_FPGA PA[0.31] TW CK TW D R[0.5] G[0.5] B[0.5] PC[14.19] VCCIO8 06 - AUDIO & ANALOG PB17 PA1 PA0 PA4 PA2 RESET_CAP9 PA15 PB2 PB0 PB1 RESET_FPGA# MOSI MISO AUDIO_CS# SPCK VDDANA 3V3 1 VDDANA MCLK SDIN LRFS BCLK ADC1 ADC2 ADC3 ADC4 PB19 1 J54 1X3PTS_MD_2MM54 2MM54 PB15 3 ADC1 ADC3 3V3 GND RESET# J52 1X3PTS_MD_2MM54 2MM54 PB13 3 2 PC0 PC28 VCCIO7 ADC1 ADC2 ADC3 ADC4 PB18 1 J53 1X3PTS_MD_2MM54 2MM54 PB14 3 PB20 1 J55 1X3PTS_MD_2MM54 2MM54 PB16 3 2 GND VCCIO6 VCCIO7 PB[0.31] 2 3V3 VCCIO4 VCCIO6 PA1 PA0 PA5 PA2 MOSI MISO NOR_CS# SPCK 2 3V3 VDDIOP1 VCCIO4 VCCIO8 SD_BA0 SD_BA1 D 1V8_CAP9 VDDIOP1 PD11 RESET_CAP9 NANDW E A21 A22 NANDCS NANDOE SHDN NANDCS NANDWE NANDOE 5V 3V3 1V8_CAP9 FN_R/B# FN_WP# FN_WE# FN_ALE FN_CLE FN_CE# FN_RE# SD_DQM0 SD_DQM1 SD_DQM2 SD_DQM3 3V3 RESET_CAP9 RESET# RESET_FPGA# PA12 DONE_FPGA PA13 D[0.31] A[2.15] BA[0.1] NRST NTRST RESET_CAP9 3V3 VDD_IO D[0.31] LCD & TSC C A A[18.25] 1V2_SAVE 01 - POW ER SUPPLY B A[18.25] VDDMPIO PA6 NRST NTRST RESET_CAP9# SHDN PD4 1V2_SAVE 09 - MEMORY A[0.17] VDDIOM GND 1V2_FPGA D[16.31] VDDIOP1 VDDIOM 1V8_FPGA 1V2_CAP9 VDDANA VDDIOP1 TW CK TW D 1 D[0.15] D[0.15] 01 - POW ER SUPPLY 5V 2 ADC2 ADC4 06 - AUDIO & ANALOG CONF_DONE SDCARD A FPGA_PLLOUTp FPGA_PLLOUTn VDDIOP1 3V3 GND 04 - FPGA STRATIX 2 MCI_CK MCI_DA0 MCI_DA1 MCI_DA2 MCI_DA3 MCI_CD MCI_CDA 08 - SDCARD PA16 PA18 PA19 PA20 PA21 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com PC21 PA17 Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic TOP LEVEL Format A3 Date: Dessinateur / Drawer Référence / Reference O. Boitet ADEC101389001 ADEC101389001 Friday, November 02, 2007 Page 2 Rév. 2C de / of 21 5 4 3 2 1 2 C1 10uF_1210 2 MAXS C8 1nF MAXS 6 7 LED1 LED2 USB 1 2 3 4 TS 1 D2 GREEN 1 BATS 1 2 R1 1K ACDC BAT D1 YELLOW 2 C5 10uF_1210 VBAT U1 8 R2 1K C4 100nF C6 + 10UF_16V 2 R172 0R 1 ON ON OFF OFF C7 10uF_1210 D VBUS 1 BATTERY CHARGER 2 ON OFF ON OFF R173 0R 5VDC_SECTOR 2 Time out or Battery Absent Charge complete Charge progressing Low Power Supply LED2 1 LED1 1 CHARGE STATE 2 D C3 + 10UF_16V 2 C2 100nF 1 1 Battery Charger & Backup 1V2_SAVE 2 1V2_SAVE 1 5VDC_SECTOR 9 R174 0R J4 1 2 3V3 C 11 12 13 14 15 16 TW D TW CK CHARGER_IRQ 3 TP1 EN DIN/ISET1 ADCAUX DOUT/ISET2 SCLK/IUSBSET CSB/BATTYPE ITB GND GNDPAD C9 10uF_1210 10 NC HE14_3PTS 1 R3 10K BAT_TS C 2 C282 3V3 10nF 1 2 5 17 AT73C205 AT73C205 3V3 VIN_AT73C239 AT73C239 C11 22uF_1210 BACKUP VIN_SURV_AT73C239 AT73C239 2 1 R238 0R R175 10K 1 C10 100nF 2 U3 16 VDD1 VBG 13 VO1 14 VIN_AT73C239 AT73C239 J8 VIN_SURV_AT73C239 AT73C239 R6 10K XRESIN XRESO TW CK_AT73C239 AT73C239 TW D_AT73C239 AT73C239 VIN_SURV_AT73C239 AT73C239 1 FIQ# J7 2 1 4 11 12 6 XRESIN XRESO TWCK TWD GNDD VDD2 VO2 R235 3K3 8 VIN_AT73C239 AT73C239 VIN_SURV_AT73C239 AT73C239 TW D 1 2 TW D_AT73C239 AT73C239 5 VO4 VDD3 1V2_SAVE C17 1UF_16V TP5 3 VO3 C14 4,7uF_16V 2 VIN_SURV_AT73C239 AT73C239 TP6 1 C16 10nF 3 VBAT 2 S7 INT_1K2 7 VIN_SURV_AT73C239 AT73C239 AT73C239 AT73C239 2 TW D TW CK_AT73C239 AT73C239 1 1 2 J9 TP4 VZAP 1 3 2 TW CK TP3 10 J11 TW CK B C13 4,7uF_16V 9 2 R4 100K PIO_BACKUP TP2 1 GNDA/AVSS GNDPAD 2 C205 1UF_16V 1 2 B VIN_SURV_AT73C239 AT73C239 1 VBACKUP 15 17 J12 C18 4,7uF_16V TP7 S8 INT_1K2 A A 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic BATTERY CHARGER & BACKUP Format Dessinateur / Drawer Référence / Reference A3 O. Boitet ADEC101398001 ADEC101398001 Date: Friday, November 02, 2007 Page 3 Rév. 2C de / of 21 5 4 3 2 1 1 AT73C224 AT73C224 PMC Power Supplies VIN_PMC_SHDN VO1 18 VDD2 9 SW2 16 GND2 17 VO2 11 1 29 2 VBG C15 1UF_16V R167 10K EN_PMC 12 2 C 7 1 VCAPN TP26 VO4_PMC1 C37 2200pF C35 470nF C36 100nF TP27 1 33 TP61 1 VIN_PMC_SHDN R177 0R U5 VDDDIG VDD0 VDD1 GND3 22 21 10K TP9 29 R10 10K VDD2 S4 BP 3 4 16 GND2 17 VO2 11 VIN_PMC_SHDN 1V2_SW 2 C50 1UF_16V 12 1V2_SW 2 1V2_CAP9 1V2_CAP9 L5 6µH8_710mA 1 2 J50 TP64 D1 D2 D3 D4 POK ITB R230 C51 + 33UF_10V TP29 5 4 VCAPN 1K 8 7 A 1 VBG VINT EN GND/AVSS AT73C224BBU AT73C224BBU TP28 VO3_PMC2 CK32 1 EN_PMC 2 9 SW2 2 2 1 + C48 47UF_10V 18 VCAPP R168 10K B TP62 2 26 27 28 13 14 15 CAP9_POK 3V3_ITB 1 Q2B SI5515DC SI5515DC 1 1 TW CK TW D 3V3 C54 2200pF 1 R140 R234 0R 8 7 1 10K 3V3 C45 4,7uF_16V 2 3V3BB_DH1 VO1 VDDRTC VBK XIN XOUT 1 VO4 10 32 31 30 3V3BB_DL1 19 C52 470nF 2 2 R139 1 C49 4,7uF_16V 20 VDD4 24 1V8_CAP9 Q2A SI5515DC SI5515DC 1 TP63 1 DL1 DH1 23 2 3V3BB_SENSE 2 1V8_CAP9 L4 6,8µH_2A4 1 C46 22uF_1210 1 2 VSENSE 2 VO3 3 6 VDD3 1 1 2 VO3_PMC2 25 R15 0R047 0R047_2512 2 2 VIN_PMC_SHDN VO3_PMC2 1 1 C44 10nF pin 23 C47 4,7uF_16V 2 3 1 2 3V3 2 4 1 L3 6,8µH_2A4 2 pin 2 100nF C43 C42 10nF VIN_PMC_SHDN C38 1UF_16V 1 2 6 5 2 C41 1UF_16V 1 C40 10nF 1 2 2 C39 1UF_16V 1 2 1 TP25 4 CAP9 POWER SUPPLIES A C34 + 33UF_10V 5 GND/AVSS AT73C224 AT73C224 VIN_PMC_SHDN B TP24 J49 VINT EN pin 31 J48 VO3_PMC1 1K 8 1 R11 10K J67 R231 TP60 2 R7 1K5 1 D1 D2 D3 D4 POK ITB VCAPP FPGA_POK 5V_ITB VBACKUP J10 1V8_SW 2 1V8_FPGA L2 6µH8_710mA 1 2 2 26 27 28 13 14 15 TW CK TW D C32 1UF_16V 1V8_FPGA 1 3V Manganese - Li RECHARGEABLE ONLY 4 VIN_PMC_SHDN 1V8_SW 2 CK32 C33 22pF C + C60 47UF_10V 1 TP8 1 1 VDDRTC VBK XIN XOUT 8 7 2 2 VBACKUP Q1B SI5515DC SI5515DC 5VB_DH1 2 1 2 5VB_DL1 19 Q1A SI5515DC SI5515DC TP59 1 VO4 10 32 31 30 R237 0R pin 10 20 DH1 VIN_PMC 1 2 1 Y1 32768Hz_12.5pF 2 DL1 24 VO4_PMC1 2 5VB_SENSE VDD4 VO3_PMC1 R236 0R C31 10nF 21 GND3 23 VIN_PMC C30 1UF_16V 22 VSENSE VO3 1 C26 22uF_1210 1 2 VDD1 3 GND VDD0 VDD3 1 D 5V C206 4,7uF_16V 1 2 1 VDDDIG 2 C25 10nF 6 L1 6,8µH_2A4 1 C28 4,7uF_16V 25 U4 2 C27 4,7uF_16V VO3_PMC1 1 2 VO4_PMC1 R8 0R047 0R047_2512 1 2 2 6 5 VIN_PMC_SHDN 1V2_CAP9 R176 0R 1 pin 23 1V8_FPGA 1V2_CAP9 3V3 2 3 2 pin 2 1V8_CAP9 1V8_FPGA 2 100nF C24 C22 10nF 1 1V8_CAP9 C29 22pF 2 1 C21 1UF_16V L21 6,8µH_2A4 VIN_PMC_SHDN C23 1UF_16V 1 2 2 3V3 C20 10nF 1 3V3 C19 1UF_16V 1 5V 1 5V 1 D 2 2 2 VIN_PMC 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com C53 100nF 33 Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic PMC AT73C224 AT73C224 Format Dessinateur / Drawer Référence / Reference A3 O. Boitet ADEC101389001 ADEC101389001 Date: Friday, November 02, 2007 Page 4 Rév. 2C de / of 21 5 4 3 2 1 Power Switch & Reset D D SWITCH 5VDC_SECTOR - VBAT VIN_PMC R229 0R D3 2 5VDC_SECTOR 5VDC_SECTOR 1 MBRS340T3G MBRS340T3G 1 J15 3 Q9B C56 + 10UF_16V 5VDC_SECTOR 3 1 4 2 2 5 6 RAPC722 RAPC722 R16 10K SI5515DC SI5515DC VBAT C RESET CONFIG J16 jumper Uncontroled reset then start CAP9 and FPGA order Reset CAP9 resets FPGA, start CAP9 and then start FPGA Reset FPGA resets CAP9, start FPGA and then start CAP9 Forbidden (no reset available) 1-2 1-2 2-3 2-3 C RESET CONTROL J17 jumper NRST 1-2 2-3 1-2 2-3 3V3 R17 100K 3V3 SHUTDOWN VIN_PMC 1 RESET_CAP9# 2 2 0R R21 1X3PTS_MD_2MM54 2MM54 J16 NTRST 3V3 BAT54SLT1G BAT54SLT1G 1 2 D5 R143 0R SHDN 1 R142 100K C59 100nF B Q8A SI5515DC SI5515DC 2 1 J70 DONE_FPGA_CAP9 3 R19 10K 3 4 5 6 3 Q8B SI5515DC SI5515DC 8 7 2 1 BP S5 R141 100K 3 4 FPGA_POK B 1 2 C58 10nF CAP9_POK POR VIN_PMC_SHDN 1 3 VIN_PMC C57 10UF_0805 NC 2 R20 0R D4 BAT54CW BAT54CW PbF 2 1 R18 10K FORCE ON R144 1K DONE_FPGA 2 RESET_FPGA# 1 3 3V3 1X3PTS_MD_2MM54 2MM54 J17 R145 10K 8 7 A Q9A SI5515DC SI5515DC 2 1 A RST_SOFT_FPGA 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic POWER SWITCH & RESET Format A3 Date: Dessinateur / Drawer Référence / Reference O. Boitet ADEC101389001 ADEC101389001 Friday, November 02, 2007 Page 5 Rév. 2C de / of 21 5 4 3 2 1 D D FPGA Core Supply VIN_PMC_SHDN 1V2_FPGA VIN_PMC_SHDN 9 16 ITH SW14 SW15 SW11 SW10 2 1µH_1A8 RT R160 1K PGND PGND 12 13 Case SGND 8 R164 294K R165 1K C204 220pF C203 2200pF 1 2 C200 22uF_1210 2 1 SYNC/MODE 6 1 5 1 R166 6K81 4 2 C202 2200pF 17 R163 10K 1 R162 820K NC TP65 J58 1 RUN/SS VFB 1 C199 220pF 100V 1 2 7 14 15 11 10 2 2 R158 0R C198 2200pF 1V2_FPGA 1 C201 1UF_16V NC 2 1V8_FPGA C197 220pF 100V C R159 0R NC L20 1 C196 1UF_16V 2 1 2 1 2 PGOOD PVIN PVIN U18 2 3 C195 22uF_1210 1 R169 0R FPGA_POK SVIN C 1V2_FPGA LTC3412EFE LTC3412EFE R161 12K4 B B A A 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic FPGA CORE SUPPLY Format Dessinateur / Drawer Référence / Reference A3 O. Boitet ADEC101389001 ADEC101389001 Date: Friday, November 02, 2007 Page 6 Rév. 2C de / of 21 5 4 1V8_CAP9 1 3V3 VDDIOP1 VDDIOP1 5V D 2 CAP9 & FPGA PIO Connectors 1V8_CAP9 3V3 3 5V VCCIO4 GND 1 TP66 VCCIO8 PC[0.31] PC[0.31] CAP9 PIO CONNECTOR VCCIO7 VCCIO8 PB[0.31] PB[0.31] VCCIO6 VCCIO7 PA[0.31] PA[0.31] D VCCIO4 VCCIO6 FPGA_IO[0.95] FPGA_IO[0.95] PD[0.12] PD[0.12] FPGA PIO CONNECTORS J18 5V 3V3 PA2 SPI0_SPCK PA9 PD1 SPI0_NPCS3 TW CK C TW D PA24 RTS0 PCK1 PA28 PA29 PA30 PA31 VDDIOP1 VDDIOP1 PC12 PC13 PD2 PD3 PD8 PD10 PD13 PD14 NCS5 SCK1 A24 A25 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 5V J56 3V3 SPI0_MISO IRQ0 IRQ1 TXD0 RXD0 SPI1_MISO SPI1_MOSI FPGA_IO0 FPGA_IO1 FPGA_IO3 FPGA_IO5 FPGA_IO6 FPGA_IO8 FPGA_IO10 FPGA_IO12 PA0 SPI0_MOSI PA1 PD0 3V3 PA10 PA14 PA22 PA23 PB12 PB13 SPI1_SPCK FPGA_IO15 FPGA_IO17 FPGA_IO19 FPGA_IO21 FPGA_IO22 FPGA_IO24 FPGA_IO26 PB14 SPI1_NPCS0 SPI1_NPCS1 PB15 PB16 FPGA_IO29 FPGA_IO31 FPGA_IO33 FPGA_IO35 FPGA_IO37 FPGA_IO38 FPGA_IO40 FPGA_IO42 FPGA_IO44 3V3 PCK0 DMARQ2 NW AIT NCS4 SCK2 A23 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 PD5 PD6 PD7 PD9 PD12 FPGA_IO47 FPGA_IO49 1V8_CAP9 VCCIO6 TSM-132-01-L-DV TSM-132-01-L-DV J19 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 VCCIO4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 FPGA_IO52 FPGA_IO53 FPGA_IO55 FPGA_IO57 FPGA_IO58 FPGA_IO60 FPGA_IO62 FPGA_IO64 FPGA_IO2 FPGA_IO4 FPGA_IO7 FPGA_IO9 FPGA_IO11 FPGA_IO13 FPGA_IO14 FPGA_IO16 FPGA_IO18 FPGA_IO20 FPGA_IO67 FPGA_IO68 FPGA_IO69 FPGA_IO71 FPGA_IO72 FPGA_IO74 FPGA_IO76 FPGA_IO78 FPGA_IO23 FPGA_IO25 FPGA_IO27 FPGA_IO28 FPGA_IO30 FPGA_IO32 FPGA_IO34 FPGA_IO36 FPGA_IO81 FPGA_IO83 VCCIO8 FPGA_IO39 FPGA_IO41 FPGA_IO43 FPGA_IO45 FPGA_IO46 FPGA_IO48 FPGA_IO50 FPGA_IO51 FPGA_IO86 FPGA_IO88 FPGA_IO90 FPGA_IO92 FPGA_PLLOUTp FPGA_PLLOUTn TSM-132-01-L-DV TSM-132-01-L-DV 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 VCCIO6 FPGA_IO54 FPGA_IO56 FPGA_IO59 FPGA_IO61 FPGA_IO63 FPGA_IO65 FPGA_IO66 C VCCIO7 FPGA_IO70 FPGA_IO73 FPGA_IO75 FPGA_IO77 FPGA_IO79 FPGA_IO80 FPGA_IO82 FPGA_IO84 FPGA_IO85 FPGA_IO87 FPGA_IO89 FPGA_IO91 FPGA_IO93 FPGA_IO94 FPGA_IO95 3V3 TSM-132-01-L-DV TSM-132-01-L-DV USER'S GRID AREA B B H10 H11 1MM27 1MM27 1MM27 1MM27 3V3 5V H58 1,27mm 20x18 matrix H12 1MM27 1MM27 H13 H14 3V3 5V 2MM54 2MM54 2MM54 2MM54 H59 2,54mm 9x8 matrix A A H15 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com 2MM54 2MM54 Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic IO CONNECTORS & PROTO AREA Format A3 Date: Dessinateur / Drawer Référence / Reference O. Boitet ADEC101389001 ADEC101389001 Friday, November 02, 2007 Page 7 Rév. 2C de / of 21 5 4 3 2 1 CAP9 - Power supply 1V2 VDDCORE 1 capacitor close to each VDDCORE VDDIOP1 D VDDIOP1 1V2_SAVE J20 10nF 1 1 C73 10nF 2 10nF C72 2 1 1 10nF C71 2 10nF C70 2 1 1 10nF C69 2 10nF C68 2 1 1 10nF C67 2 10nF C66 2 1 C65 2 10nF 1 1 C64 2 2 10nF 2 1 1 2 10nF C63 1V2_SAVE 3V3 1V8 C74 10nF 1V8 1V2 VDDMPIO 3V3 VDDIOM 1 capacitor close to each VDDIOM GND 10nF 10nF 1 2 10R R170 C81 2 1 1 10nF C80 2 10nF C79 2 1 C78 2 10nF 1 C77 2 1 10nF 2 2 10nF C76 2 1 1 1 C75 VDDANA VDDPLL J22 C82 10nF 2 J21 VDDIOM VDDANA 1 1V8 VDDMPIO VDDIOM 1 capacitor close to each PLLxVDD33 (G17, E17) D 3V3 1V2 C62 C83 10nF U6A CAP9 - POWER N10 T11 N13 W20 L15 H17 D14 F10 E7 K8 H7 R5 T4 VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDPLL G17 E17 PLLAVDD33 PLLAVDD33 PLLBVDD33 PLLBVDD33 VDDUPLL C18 VDDUTMII B19 VDDIOP0 B17 A15 E11 G9 F7 J6 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDCORE VDDIOP0 3V3 R26 0R 1 capacitor close to each VDDIOP0 pin 1 1 1 10nF C90 10nF 2 10nF C89 2 10nF C84 2 C88 2 2 10nF 1 C87 2 1 1 C VDDIOP1 J24 1V8 1 J23 C85 10nF 2 3V3 0R NC R27 C86 10nF Capacitor close to VDDIOP1 (H6) VDDMPIO 10nF 1 1 1 1 10nF C94 10nF C95 2 10nF C93 2 VDDUTMII J27 C92 2 3V3 VDDUTMIC J26 10nF 1 capacitor close to PLL480VDD PLL480VDD (C18) C96 10nF 1 capacitor close to UTMI_VDD (C19) C97 1 capacitor close to UTMI_VDD33 VDD33 (B19) 10nF 1 2 1 1 1V2 VDDUPLL C91 2 R171 10R J25 1 1V2 2 1 USB POWER SUPPLIES C98 1 capacitor close to each VDDMPIOx 10nF GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE GNDCORE Y4 V10 L13 K13 M17 G18 H14 A8 G8 J8 L7 M7 GNDPLLA GNDPLLB F17 H15 PLL480 PLL480_VDD PLL480 PLL480_GND D20 UTMI_VDD33 VDD33 UTMI_GND D19 GNDIOP0 GNDIOP0 GNDIOP0 GNDIOP0 GNDIOP0 GNDIOP0 GNDIOP0 GNDIOP1 B18 A16 F11 D9 H9 H8 K6 L6 UTMI_GND33 GND33 B20 GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM G7 N7 E6 W4 P10 J13 U12 2 2 B H6 C19 UTMI_VDD VDDIOM 2 VDDIOP1 VDDUTMIC V5 R8 R13 R11 F6 N8 P6 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Y14 U16 VDDMPIOA VDDMPIOA GNDMPIOA GNDMPIOA T14 W19 V20 P20 H12 VDDMPIOB VDDMPIOB VDDMPIOB GNDMPIOA GNDMPIOA GNDMPIOA M15 L14 J20 E18 VDDBU B12 VREFP C11 VDDADC J28 1X3PTS_MD_2MM54 2MM54 VDDBU VDDMPIO 2 1 1 C100 47nF Capacitor close to VREFP (B12) 2 2 EN VREFP 5 1 REF 3 GND C99 10nF VOUT 2 C105 10nF 2 1 1 C104 10UF_0805 2 C103 10nF VIN 1 1 2 4,7µH 220mA 4 J29 2 1 C102 10UF_0805 2 1 1 2 U7 LM4120AIM5-3 LM4120AIM5-3.0 VDDANA L6 3 1V2 3V3 C101 10nF C Capacitor close to VDDBU (E18) B 1V2_SAVE VDDBU VREFP Capacitor close to VDDADC (C11) VDDANA A13 GNDBU GNDBU J15 J14 VSSADC AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 A A 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic CAP9 POWER Format Dessinateur / Drawer Référence / Reference A3 O. Boitet ADEC101389001 ADEC101389001 Date: Friday, November 02, 2007 Page 8 Rév. 2C de / of 21 5 A16 A17 NBS0 NBS1 NBS2 NBS3 4 BA0 BA1 A0 3 2 CAP9 - Busses BA[0.1] A[0.17] A[0.17] NBS[0.3] A1 PA[0.31] A[18.25] D U4 Y3 W6 N11 Y5 W7 N12 U9 Y6 P11 Y7 V9 P12 U10 W8 Y8 R12 W9 Y9 W10 U11 Y10 V11 U3 R4 D7 W3 M13 W11 NBS1 U7 NBS3 P7 W2 RASO V2 T10 V3 SDCLKO Y1 Y2 T5 SDW EO W1 CASO NANDOE NANDW E SDA10 SDA10 SDCKE SDDRCS Y11 N9 C T6 U8 A0/NBS0 A1/NWR2/NBS2 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16/BA0 A16/BA0 A17/BA1 A17/BA1 A18 A19 A20 A21 A22 CAP9 - EBI BCCLK CAS/BCOE NANDOE NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW OWAIT RAS/BCADV SDA10 SDA10 SDCKE/BCCRE SDCK SDCKN SDDRCS SDWE/BCWE NCS0 NCS1/BCCS CAP9 - PIOB CAP9 - PIOA D[0.15] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 U5 U6 R6 V4 T7 V6 W5 R7 P8 V7 P9 T8 R10 R9 T9 V8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 R29 1K5 DQS0 DQS1 R30 1K5 PB4 TW D PB5 MPIOA[0.31] MPIOB[0.44] MPIOB0 MPIOB1 MPIOB2 MPIOB3 MPIOB4 MPIOB5 MPIOB6 MPIOB7 MPIOB8 MPIOB9 MPIOB10 MPIOB10 MPIOB11 MPIOB11 MPIOB12 MPIOB12 MPIOB13 MPIOB13 MPIOB14 MPIOB14 MPIOB15 MPIOB15 MPIOB16 MPIOB16 MPIOB17 MPIOB17 MPIOB18 MPIOB18 MPIOB19 MPIOB19 MPIOB20 MPIOB20 MPIOB21 MPIOB21 MPIOB22 MPIOB22 MPIOB23 MPIOB23 MPIOB24 MPIOB24 MPIOB25 MPIOB25 MPIOB26 MPIOB26 MPIOB27 MPIOB27 MPIOB28 MPIOB28 MPIOB29 MPIOB29 MPIOB30 MPIOB30 MPIOB31 MPIOB31 MPIOB32 MPIOB32 MPIOB33 MPIOB33 MPIOB34 MPIOB34 MPIOB35 MPIOB35 MPIOB36 MPIOB36 MPIOB37 MPIOB37 MPIOB38 MPIOB38 MPIOB39 MPIOB39 MPIOB40 MPIOB40 MPIOB41 MPIOB41 MPIOB42 MPIOB42 MPIOB43 MPIOB43 MPIOB44 MPIOB44 P15 MPIOB0 P16 MPIOB1 R17 MPIOB2 T18 MPIOB3 R18 MPIOB4 V19 MPIOB5 U19 MPIOB6 P17 MPIOB7 P14 MPIOB8 U20 MPIOB9 P18 MPIOB10 MPIOB10 N14 MPIOB11 MPIOB11 N16 MPIOB12 MPIOB12 N15 MPIOB13 MPIOB13 N17 MPIOB14 MPIOB14 N18 MPIOB15 MPIOB15 M16 MPIOB16 MPIOB16 T19 MPIOB17 MPIOB17 T20 MPIOB18 MPIOB18 R19 MPIOB19 MPIOB19 R20 MPIOB20 MPIOB20 P19 MPIOB21 MPIOB21 N19 MPIOB22 MPIOB22 N20 MPIOB23 MPIOB23 M20 MPIO_CLK M19 MPIOB25 MPIOB25 M14 MPIOB26 MPIOB26 M18 MPIOB27 MPIOB27 L16 MPIOB28 MPIOB28 L20 MPIOB29 MPIOB29 K15 MPIOB30 MPIOB30 L19 MPIOB31 MPIOB31 L17 MPIOB32 MPIOB32 K14 MPIOB33 MPIOB33 L18 MPIOB34 MPIOB34 K16 MPIOB35 MPIOB35 K20 MPIOB36 MPIOB36 K19 MPIOB37 MPIOB37 K17 MPIOB38 MPIOB38 J17 MPIOB39 MPIOB39 K18 MPIOB40 MPIOB40 J19 MPIOB41 MPIOB41 J16 MPIOB42 MPIOB42 J18 MPIOB43 MPIOB43 H18 MPIOB44 MPIOB44 PCK0 U6D AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 E4 E3 E2 F1 F2 F4 F5 G1 F3 G4 G2 G3 G5 H1 H2 H4 J7 J4 L8 J5 K7 K2 L1 K5 K3 L2 M1 K4 M8 L3 M2 L4 PA0 PA1 SPCK0 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PCK2 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PCK1 PA28 PA29 PA30 PA31 PB0/TF0 PB1/TK0 PB2/TD0 PB3/RD0 PB4/RK0/TWD PB5/RF0/TWCK PB6/TF1/TIOA1 PB7/TK1/TIOB1 PB8/TD1/PWM2 PB9/RD1/LCDCC PB10/RK1/PCK1 PB10/RK1/PCK1 PB11/RF1 PB11/RF1 PB12/SPI1 PB12/SPI1_MISO PB13/SPI1 PB13/SPI1_MOSI PB14/SPI1 PB14/SPI1_SPCK PB15/SPI1 PB15/SPI1_NPCS0 PB16/SPI1 PB16/SPI1_NPCS1 PB17/SPI1 PB17/SPI1_NPCS2 PB18/SPI1 PB18/SPI1_NPCS3 PB19/PWM0 PB19/PWM0 PB20/PWM1 PB20/PWM1 PB21/ETXCK/EREFCK/TIOA2 PB21/ETXCK/EREFCK/TIOA2 PB22/ERXDV/TIOB2 PB22/ERXDV/TIOB2 PB23/ETX0/PCK3 PB23/ETX0/PCK3 PB24/ETX1 PB24/ETX1 PB25/ERX0 PB25/ERX0 PB26/ERX1 PB26/ERX1 PB27/ERXER PB27/ERXER PB28/ETXEN/TCLK0 PB28/ETXEN/TCLK0 PB29/EMDC/PWM3 PB29/EMDC/PWM3 PB30/EMDIO PB30/EMDIO PB31/ADTRIG/EF100 PB31/ADTRIG/EF100 PA2 PA15 PA27 G14 D16 G15 D15 H11 E15 F13 C15 G13 C14 H10 E14 C12 B11 A11 A12 B13 A10 A9 B10 B9 G12 D13 F12 B15 G11 A14 B14 E13 C13 E12 D12 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 SPCK1 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PB14 C U6F AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 U6E AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 PC29 R147 22R PCK1 PC[0.31] PD[0.12] PA27 R31 22R SDW EO SDW E CAP9 - PIOC R32 22R SDCLKO SDCLK R33 22R RASO RAS R34 22R CASO CAS R35 22R SPCK0 PA2 R36 22R SPCK1 PB14 R37 22R PCK2 PA15 R222 22R MPIO_CLK MPIOB24 MPIOB24 PB21 PD4 C106 22pF CAP9 - PIOD PC0/LCDVSYNC PC1/LCDHSYNC PC2/LCDDOTCK PC3/LCDDEN/PWM1 PC4/LCDD0/LCDD3 PC5/LCDD1/LCDD4 PC6/LCDD2/LCDD5 PC7/LCDD3/LCDD6 PC8/LCDD4/LCDD7 PC9/LCDD5/LCDD10 PC9/LCDD5/LCDD10 PC10/LCDD6/LCDD11 PC10/LCDD6/LCDD11 PC11/LCDD7/LCDD12 PC11/LCDD7/LCDD12 PC12/LCDD8/LCDD13 PC12/LCDD8/LCDD13 PC13/LCDD9/LCDD14 PC13/LCDD9/LCDD14 PC14/LCDD10/LCDD15 PC14/LCDD10/LCDD15 PC15/LCDD11/LCDD19 PC15/LCDD11/LCDD19 PC16/LCDD12/LCDD20 PC16/LCDD12/LCDD20 PC17/LCDD13/LCDD21 PC17/LCDD13/LCDD21 PC18/LCDD14/LCDD22 PC18/LCDD14/LCDD22 PC19/LCDD15/LCDD23 PC19/LCDD15/LCDD23 PC20/LCDD16/E PC20/LCDD16/E_TX2 PC21/LCDD17/E PC21/LCDD17/E_TX3 PC22/LCDD18/E PC22/LCDD18/E_RX2 PC23/LCDD19/E PC23/LCDD19/E_RX3 PC24/LCDD20/E PC24/LCDD20/E_TXER PC25/LCDD21/E PC25/LCDD21/E_CRS PC26/LCDD22/E PC26/LCDD22/E_COL PC27/LCDD23/E PC27/LCDD23/E_RXCK PC28/PWM0/TCLK1 PC28/PWM0/TCLK1 PC29/PCK0/PWM2 PC29/PCK0/PWM2 PC30/DRXD PC30/DRXD PC31/DTXD PC31/DTXD A5 A4 A3 A2 E9 A1 C8 D8 G10 B6 B5 B4 C7 E8 B3 C6 B2 B1 C5 D6 C4 C3 C2 C1 F8 D5 D4 D3 D2 D1 E1 E5 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PCK0 PC30 PC31 U6G AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 FIQ 1 MPIOA0 MPIOA1 MPIOA2 MPIOA3 MPIOA4 MPIOA5 MPIOA6 MPIOA7 MPIOA8 MPIOA9 MPIOA10 MPIOA10 MPIOA11 MPIOA11 MPIOA12 MPIOA12 MPIOA13 MPIOA13 MPIOA14 MPIOA14 MPIOA15 MPIOA15 MPIOA16 MPIOA16 MPIOA17 MPIOA17 MPIOA18 MPIOA18 MPIOA19 MPIOA19 MPIOA20 MPIOA20 MPIOA21 MPIOA21 MPIOA22 MPIOA22 MPIOA23 MPIOA23 MPIOA24 MPIOA24 MPIOA25 MPIOA25 MPIOA26 MPIOA26 MPIOA27 MPIOA27 MPIOA28 MPIOA28 MPIOA29 MPIOA29 MPIOA30 MPIOA30 MPIOA31 MPIOA31 2 T12 V12 W12 Y12 U13 W13 V13 Y13 W14 T13 V14 U14 W15 V15 Y15 W16 U15 V16 Y16 Y17 V17 W17 W18 U17 T16 T15 Y18 V18 U18 T17 Y19 Y20 TW CK R146 22R CAP9 - PROTO MPIOA0 MPIOA1 MPIOA2 MPIOA3 MPIOA4 MPIOA5 MPIOA6 MPIOA7 MPIOA8 MPIOA9 MPIOA10 MPIOA10 MPIOA11 MPIOA11 MPIOA12 MPIOA12 MPIOA13 MPIOA13 MPIOA14 MPIOA14 MPIOA15 MPIOA15 MPIOA16 MPIOA16 MPIOA17 MPIOA17 MPIOA18 MPIOA18 MPIOA19 MPIOA19 MPIOA20 MPIOA20 MPIOA21 MPIOA21 MPIOA22 MPIOA22 MPIOA23 MPIOA23 MPIOA24 MPIOA24 MPIOA25 MPIOA25 MPIOA26 MPIOA26 MPIOA27 MPIOA27 MPIOA28 MPIOA28 MPIOA29 MPIOA29 MPIOA30 MPIOA30 MPIOA31 MPIOA31 PA0/MCI0_D0/SPI0_MISO PA1/MCI0_CD/SPI0_MOSI PA2/MCI0_CK/SPI0_SPCK PA3/MCI0_D1/SPI0_NPCS1 PA4/MCI0_D2/SPI0_NPCS2 PA5/MCI0_D3/SPI0_NPCS0 PA6/AC97FS PA6/AC97FS PA7/AC97CK PA7/AC97CK PA8/AC97TX PA8/AC97TX PA9/AC97RX PA9/AC97RX PA10/IRQ0/PWM1 PA10/IRQ0/PWM1 PA11/DMARQ0/PWM3 PA11/DMARQ0/PWM3 PA12/CANTX/PCK0 PA12/CANTX/PCK0 PA13/CANRX PA13/CANRX PA14/TCLK2/IRQ1 PA14/TCLK2/IRQ1 PA15/DMARQ3/PCK2 PA15/DMARQ3/PCK2 PA16/MCI1 PA16/MCI1_CK/ISI_D0 PA17/MCI1 PA17/MCI1_CD/ISI_D1 PA18/MCI1 PA18/MCI1_D0/ISI_D2 PA19/MCI1 PA19/MCI1_D1/ISI_D3 PA20.MCI1_D2/ISI_D4 PA21/MCI1 PA21/MCI1_D3/ISI_D5 PA22/TXD0/ISI PA22/TXD0/ISI_D6 PA23/RXD0/ISI PA23/RXD0/ISI_D7 PA24/RTS0/ISI PA24/RTS0/ISI_PCK PA25/CTS0/ISI PA25/CTS0/ISI_HSYNC PA26/SCK0/ISI PA26/SCK0/ISI_VSYNC PA27/PCK1/ISI PA27/PCK1/ISI_MCK PA28/SPI0 PA28/SPI0_NPCS3/ISI_D8 PA29/TIOA0/ISI PA29/TIOA0/ISI_D9 PA30/TIOB0/ISI PA30/TIOB0/ISI_D10 PA31/DMARQ1/ISI PA31/DMARQ1/ISI_D11 VDDIOP0 U6C AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 A PB[0.31] A[18.25] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 D B 1 PD0/TXD1/SPI0_NPCS2 PD1/RXD1/SPI0_NPCS3 PD2/TXD2/SPI1_NPCS2 PD3/RXD2/SPI1_NPCS3 PD4/FIQ PD5/DMARQ2/RTS2 PD6/NWAIT/CTS2 PD7/NCS4/CFCS0/RTS1 PD8/NCS5/CFCS1/CTS1 PD9/CFCE1/SCK2 PD10/CFCE2/SCK1 PD10/CFCE2/SCK1 PD11/NCS2 PD11/NCS2 PD12/A23 PD12/A23 PD13/A24 PD13/A24 PD14/A25/CFRNW PD14/A25/CFRNW PD15/NCS3/NANDCS PD15/NCS3/NANDCS PD16/D16 PD16/D16 PD17/D17 PD17/D17 PD18/D18 PD18/D18 PD19/D19 PD19/D19 PD20/D20 PD20/D20 PD21/D21 PD21/D21 PD22/D22 PD22/D22 PD23/D23 PD23/D23 PD24/D24 PD24/D24 PD25/D25 PD25/D25 PD26/D26 PD26/D26 PD27/D27 PD27/D27 PD28/D28 PD28/D28 PD29/D29 PD29/D29 PD30/D30 PD30/D30 PD31/D31 PD31/D31 PC29 H3 H5 J2 J1 K1 J3 L5 N1 N2 P1 G6 M3 M4 M5 P2 M6 N3 R2 P3 N4 N5 R1 T1 T2 R3 U1 V1 P4 P5 N6 T3 U2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 A23 A24 A25 B PD12 NANDCS D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 U6H AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 R149 10K NC 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création D[16.31] A Projet / Project CAP9-STK Schéma électronique / Schematic EBI & PIO Format Dessinateur / Drawer Référence / Reference A3 O. Boitet ADEC101389001 ADEC101389001 Date: Friday, November 02, 2007 Page 9 Rév. 2C de / of 21 5 4 3 2 1 CAP9 - USB, PLL, ICE 3V3 3V3 D 3V3 GND TCK_ICE R38 100K TMS_ICE R39 100K R40 100K D R41 100K R42 0R NTRST J30 1 3 5 7 9 11 13 15 17 19 TDI_ICE TMS TCK R44 0R R43 NC 0R RTCK TDO_ICE 2 4 6 8 10 12 14 16 18 20 HE10_2X10PTS 2X10PTS_MC UTMI_FSDM A19 C9 C10 D10 B8 E10 B7 F18 HSDP TDO W KUP0 VDDBU A17 UTMI_FSDP JTAGSEL NRST VBUS_ON F14 3 1 3 1 TDO F19 VBUS F15 TDO_CAP9 C TDO_FPGA TDO_ICE R228 10M NC RESET_CAP9 ID H16 VDDBU BP A7 SHDW G16 J68 H13 JTAGSEL J60 1X3PTS_MD_2MM54 2MM54 VBUS_DRV HDPA C16 B16 C17 USBHB_DP HDMB D17 3V3 USBHA_DM HDPB SHDN R48 1K USBHA_DP HDMA 2 FSDP J59 1X3PTS_MD_2MM54 2MM54 S6 C FSDP ICE connector R46 100K 2 HSDP A18 HSDP FSDM NTRST TDI TMS TCK RTCK TDO WKUP0 1 FSDM 2 HSDM 1 2 A20 0R R45 4 3 HSDM NRST NRST VDDBU CAP9 - SYSTEM & USB HSDM TST R49 100K BMS A6 BMS 2 USBHB_DM G19 TST U6I AT91CAP9 AT91CAP9 CPN = AT91ICS002 AT91ICS002 3 1 J31 1X3PTS_MD_2MM54 2MM54 B D11 E16 F16 F9 P13 R14 R15 R16 B 2 C111 22pF 1 A 2 C114 22pF OSC32K OSC32K_XIN H20 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 LFT_PLL480 PLL480 F20 LFT_PLLA C108 10nF 2 C110 1 R51 953R OSC32K OSC32K_XIN LFT_PLLB H19 1 OSC12M OSC12M_XOUT Y3 32768Hz_12.5pF OSC32K OSC32K_XOUT TP16 R53 1K40 OSC32K OSC32K_XOUT U6B AT91CAP9 AT91CAP9 CPN = AT91ICS039 AT91ICS039 PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND PACK_GND 1 E20 D18 OSC12M OSC12M_XIN Y2 12MHz_20pF OSC12M OSC12M_XOUT LFT_PLL480 PLL480 LFT_PLLA E19 J10 J11 J12 J9 K10 K11 K12 K9 L10 L11 L12 L9 M10 M11 M12 M9 C109 33pF 1 2 CAP9 - MISC POWER & ANALOG OSC12M OSC12M_XIN 2 C107 33pF 2 1 1 G20 2 1nF LFT_PLLB 1 C113 1 R54 6K81 USBDEV_BIAS C20 VBG C112 2 10nF 2 1nF 1 A 2 C115 10pF 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic SYSTEM USB CLOCK Format Dessinateur / Drawer Référence / Reference A3 O. Boitet ADEC101389001 ADEC101389001 Date: Friday, November 02, 2007 Page 10 Rév. 2C de / of 21 5 4 3V3 1V8 1V2 1 1V2 VDDMPIO VDDMPIO VCCIO6 M16 M6 1V2 VDDMPIO M17 M19 M4 M6 F12 R12 M16 M18 M5 L6 G11 U11 1 2 2 1 R178 0R NC 2 AA1 M1 R183 0R A20 1 2 AB11 1V8 B 1 1 C271 100nF C256 10nF 2 C259 10nF 2 C258 10nF C253 10nF VCCIO7 R181 0R 2 C270 100nF AB3 C252 10nF 3V3 1 VCCIO3 1 3V3 C269 100nF 1 A12 2 1V8 2 R179 0R 1 VCCIO6 1 3V3 C257 10nF NC C272 100nF C262 10nF C263 10nF AB12 AB20 1V8 NC C273 100nF 1 VCCIO8 R185 0R 1 3V3 C260 10nF 2 2 C261 10nF NC G10 R11 2 C264 10nF 1 VCCIO10 VCCIO10 1 3V3 1 C274 100nF 2 2 1 VCCIO9 C275 100nF 2 1V8 1 VCCIO4 R188 0R GNDA_PLL6 GNDA_PLL6 GNDA_PLL5 GNDA_PLL5 GNDA_PLL4 GNDA_PLL4 GNDA_PLL3 GNDA_PLL3 GNDA_PLL2 GNDA_PLL2 GNDA_PLL1 GNDA_PLL1 R187 0R A11 2 A3 1 R190 0R 3V3 2 G7 F6 W5 U7 C267 10nF 2, Chemin du Ruisseau BP 121 69136 Ecully Tél : 04 72 18 08 40 Fax : 04 72 18 08 41 www.adeneo.adetelgroup.com 1 C222 10nF 2 1 C221 10nF 2 1 C220 10nF 2 1 C219 10nF 2 1 C218 10nF 2 1 C217 10nF 2 C216 10nF 2 1 A 1 C215 10nF 2 1 C214 10nF 2 C213 10nF 2 1 C212 10nF 2 1 C211 10nF 2 1 C210 10nF 2 1 C209 10nF 2 1 C208 10nF 2 1 2 1 C207 10nF 1 CORE POWER SUPPLY 1V2 2 FPGA I/O POWER SUPPLY C266 10nF 3V3 A 1 1 1 C265 10nF 2 C255 10nF T11 T12 F10 F11 L4 L5 N5 N6 N17 N18 L17 L18 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND RUP4 RDN4 RUP7 RDN7 AB4 A1 A9 A14 A22 AA2 AA21 AB1 AB9 AB14 AB22 B2 B21 H15 J1 J10 J12 J14 J22 K9 K11 K13 L10 L12 L14 M7 M9 M11 M13 M15 N10 N12 N14 P1 P11 P13 P22 R10 2 1 1 1 1 1 C254 10nF L1 2 VCCIO8 VCCIO8 C251 10nF B1 1 AB12 AB20 C250 10nF L22 2 VCCIO7 VCCIO7 VCCIO8 U19L R20 V20 L19 F18 B14 D16 D7 D9 J4 F3 U3 P4 W8 W6 Y19 AA14 B22 2 AB3 AB11 EP2S15F484 EP2S15F484 VCCIO6 VCCIO6 VCCIO7 VREFB1N0 VREFB1N1 VREFB2N1 VREFB2N0 VREFB3N0 VREFB3N1 VREFB4N0 VREFB4N1 VREFB5N0 VREFB5N1 VREFB6N0 VREFB6N1 VREFB7N0 VREFB7N1 VREFB8N0 VREFB8N1 M22 2 VCCIO6 AA1 M1 U11 1V8 AA22 1 B G11 C249 10nF 2 2 VCCIO5 VCCIO5 L6 C248 10nF 100nF 2 B1 L1 VDDMPIO C247 10nF C268 1 VCCIO4 VCCIO4 C246 10nF M5 1 2 A3 A11 1 M18 R152 0R VCCA_PLL1 VCCA_PLL2 VCCA_PLL3 VCCA_PLL4 VCCA_PLL5 VCCA_PLL6 VCCD_PLL1 VCCD_PLL2 VCCD_PLL3 VCCD_PLL4 VCCD_PLL5 VCCD_PLL6 VCCIO3 VCCIO3 VCCIO4 R12 C R151 0R NC 2 A12 A20 C231 1nF MPIO POWER SUPPLY VCCIO2 VCCIO2 VCCIO3 C245 10nF 2 2 C244 10nF 2 C243 1nF 1 1 1 C242 1nF 2 2 C241 100nF 2 B22 L22 G10 R11 VCCIO1 VCCIO1 VDDMPIO VCC_PLL5_OUT VCC_PLL6_OUT VCCPD1 VCCPD2 VCCPD3 VCCPD4 VCCPD5 VCCPD6 VCCPD7 VCCPD8 P15 K14 H13 H10 L9 N9 P10 R13 H8 J9 J11 J13 K10 K12 L11 L13 M8 M10 M12 M14 N11 N13 P9 P12 P14 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT AA22 M22 1 1 1 F12 3V3 VDDMPIO C230 1nF VCC_PLL34 PLL34 1 1 C240 100nF 2 VCCIO9 VCC_PLL56 PLL56 3V3 VCC_PLL34 PLL34 VCC_PLL12 PLL12 1V2 C229 100nF 1V2 L24 BLM18PG600 BLM18PG600 2 M4 VCCIO10 VCCIO10 C228 100nF M19 1 1V2 C239 10nF 1 C C227 1nF 1 C238 10nF 2 C237 10nF 2 1 1 C236 10nF 2 2 C235 10nF 2 1 1 C234 10nF 2 1 C233 10nF 2 1 C232 10nF 2 2 1 M17 VCC_PLL56 PLL56 2 C226 1nF L23 BLM18PG600 BLM18PG600 2 2 2 C225 100nF 1 2 C224 100nF JTAG POWER SUPPLY 3V3 VCC_PLL12 PLL12 2 1 GND 1V2 L22 BLM18PG600 BLM18PG600 2 1 1 2 1V2 1 VCCIO8 2 VCCIO7 VCCIO8 D 1 VCCIO7 PLL POWER SUPPLY VCCIO4 2 VCCIO4 VCCIO6 D 2 FPGA Power 3V3 1V8 3 C223 10nF Rév. Date Auteur 2C 02/11/07 OBO Historique / Background history Création Projet / Project CAP9-STK Schéma électronique / Schematic FPGA POWER Format A3 Date: Dessinateur / Drawer Référence / Reference O. Boitet ADEC101389001 ADEC101389001 Friday, November 02, 2007 Page 11 Rév. 2C de / of 21 5 4 3 2 1 FPGA IO Bank MPIOA[0.31]