AT89LV51 MCS-51TM 0303C 0000H 89LV51 H/12V AT89LV51-12AC AT89LV51-12JC

Features · · · · · · · · · · · Compatible with

AT89LV51 AT89LV51 Features · · · · · · · · · · · Compatible with MCS-51TM MCS-51TM Products TM 4 Kbytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles 2.7 V to 6 V Operating Range Fully Static Operation: 0 Hz to 12 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes 8-Bit Microcontroller with 4 Kbytes Flash Description The AT89LV51 AT89LV51 is a low-voltage, high-performance CMOS 8-bit microcomputer with 4 Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard MCS-51TM MCS-51TM instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89LV51 AT89LV51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89LV51 AT89LV51 provides the following standard features: 4 Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89LV51 AT89LV51 is (continued) Pin Configurations PDIP P1 .0 P1 .1 P1 .2 P1 .3 P1 .4 P1 .5 P1 .6 P1 .7 R ST (R XD ) P3 .0 (T XD ) P3 .1 (IN T 0 ) P3 .2 (IN T 1 ) P3 .3 (T 0 ) P3 .4 (T 1 ) P3 .5 (WR ) P3 .6 (R D ) P3 .7 XTAL 2 XTAL 1 GND (AD 0 ) (AD 1 ) (AD 2 ) (AD 3 ) PQFP/TQFP 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2 .7 (A1 5 ) P2 .6 (A1 4 ) P2 .5 (A1 3 ) (R XD ) (T XD ) (IN T 0 ) (IN T 1 ) (T 0 ) (T 1 ) P1 .5 P1 .6 P1 .7 R ST P3 .0 NC P3 .1 P3 .2 P3 .3 P3 .4 P3 .5 (AD 0 ) (AD 1 ) (AD 2 ) (AD 3 ) INDEX CORNER 40 3 8 36 34 41 39 3 7 35 P1 .4 P1 .3 P1 .2 P1 .1 P1 .0 NC VCC P0 .0 P0 .1 P0 .2 P0 .3 42 (WR ) P3 .6 (R D ) P3 .7 XTAL 2 XTAL 1 GND GND (A8 ) P2 .0 (A9 ) P2 .1 (A1 0 ) P2 .2 (A11 ) P2 .3 (A1 2 ) P2 .4 P1 .5 P1 .6 P1 .7 R ST (R XD ) P3 .0 NC (T XD ) P3 .1 (IN T 0 ) P3 .2 (IN T 1 ) P3 .3 (T 0 ) P3 .4 (T 1 ) P3 .5 43 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2 .7 (A1 5 ) P2 .6 (A1 4 ) P2 .5 (A1 3 ) P2 .4 (A1 2 ) P2 .3 (A11 ) P2 .2 (A1 0 ) P2 .1 (A9 ) P2 . 0 (A 8 ) 6 4 2 44 42 40 1 5 3 43 41 39 7 8 38 9 37 36 10 35 11 34 12 33 13 32 14 31 15 16 30 17 19 21 23 25 27 29 18 20 22 24 26 28 (WR ) P3 .6 (R D ) P3 .7 XTAL 2 XTAL 1 GND NC (A8 ) P2 .0 (A9 ) P2 .1 (A1 0 ) P2 .2 (A11 ) P2 .3 (A1 2 ) P2 .4 44 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PLCC P1 .4 P1 .3 P1 .2 P1 .1 P1 .0 NC VCC P0 .0 P0 .1 P0 .2 P0 .3 INDEX CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2 .7 (A1 5 ) P2 .6 (A1 4 ) P2 .5 (A1 3 ) 0303C 0303C 3-49 Block Diagram 3-50 AT89LV51 AT89LV51 AT89LV51 AT89LV51 Description (Continued) designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and program verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89LV51 AT89LV51 as listed below: Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (extenal interrupt 0) INT1 (extenal interrupt 1) T0 (timer 0 extenal input) T1 (timer 1 external input) WR (extenal data memory write strobe) RD (external data memory read strobe) Port 3 also receives some control signals for Flash programming and programming verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. PSEN Program Store Enable is the read strobe to external program memory. When the AT89LV51 AT89LV51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, when 12-volt programming is selected. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. 3-51 Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-bytwo flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections C2 XTAL2 C1 XTAL1 Idle Mode GND In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Notes: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Figure 2. External Clock Drive Configuration NC XTAL2 EXTERNAL OSCILLATOR SIGNAL XTAL1 Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. GND Status of External Pins During Idle and Power Down Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data 3-52 AT89LV51 AT89LV51 AT89LV51 AT89LV51 Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Lock Bit Protection Modes(1) Program Lock Bits 1 LB1 U LB2 U LB3 U 2 P U U 3 4 P P P P U P Note: Protection Type No program lock features. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. Same as mode 2, also verify is disabled. Same as mode 3, also external execution is disabled. 1. The lock bits can only be erased with the chip erase operation. Programming the Flash The AT89LV51 AT89LV51 is normally shipped with the on-chip Flash memory array in the erased state (i.e. contents=FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (5-volt) program enable signal. The low voltage programming mode provides a convenient way to program the AT89LV51 AT89LV51 inside the user's system while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89LV51 AT89LV51 is shipped with either the High-Voltage or Low-Voltage programming mode enabled. The respective topside marking and device signature codes are listed below: VPP = 12 V Top-Side Mark Signature VPP = 5 V AT89LV51 AT89LV51 xxxx yyww (030H)=1EH (031H)=61H (032H)=FFH AT89LV51 AT89LV51 xxxx-5 yyww (030H)=1EH (031H)=61H (032H)=05H The AT89LV51 AT89LV51 code memory array is programmed byte-bybyte in either programming mode. To program any non-blank byte in the on-chip PEROM Code Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89LV51 AT89LV51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89LV51 AT89LV51, the following sequence should be followed: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12-V if in the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89LV51 AT89LV51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array and the lock bits are erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all "1"s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are: (030H) = 1EH indicates manufactured by Atmel (031H) = 61H indicates 89LV51 89LV51 (032H) = FFH (High-Voltage) or 05H (Low-Voltage) programming mode 3-53 Programming Interface All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. Flash Programming Modes ALE/ PROG EA/ VPP P2.6 P2.7 P3.6 P3.7 H/12V H/12V(1) L H H H H L L H H H/12V H/12V H H H H H/12V H/12V H H L L L H/12V H/12V H L H L H L H/12V H/12V H L L L H Mode L H L L L L RST PSEN Write Code Data H L Read Code Data H L Bit - 1 H L Bit - 2 H L Bit - 3 H Chip Erase Read Signature Byte Write Lock Notes: 1. The signature byte at location 032H designates whether VPP = 12 V or VPP = 5 V should be used to enable programming. 3-54 AT89LV51 AT89LV51 H (2) H 2. Chip Erase requires a 10 ms PROG pulse. AT89LV51 AT89LV51 Figure 4. Verifying the Flash Figure 3. Programming the Flash +5V +5V AT89LV51 AT89LV51 A0 - A7 ADDR. OOOOH/OFFFH A8 - A11 AT89LV51 AT89LV51 A0 - A7 ADDR. OOOOH/OFFFH VCC P1 P2.0 - P2.3 P0 PGM DATA A8 - A11 P2.6 SEE FLASH PROGRAMMING MODES TABLE P1 VCC P2.0 - P2.3 P0 PGM DATA (USE 10K PULLUPS) P2.6 ALE P2.7 PROG P2.7 SEE FLASH PROGRAMMING MODES TABLE P3.6 ALE P3.6 P3.7 VIH P3.7 XTAL 2 EA VIH/VPP XTAL 2 XTAL 1 4-20 MHz EA RST 4-20 MHz XTAL 1 GND RST VIH PSEN GND VIH PSEN Flash Programming and Verification Characteristics TA = 21°C to 27°C, VCC = 5.0 ± 10% Symbol Parameter Min Max Units VPP(1) IPP(1) Programming Enable Voltage 11.5 12.5 V 25 µA 1/tCLCL Oscillator Frequency 4 12 MHz tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL Programming Enable Current tSHGL VPP Setup to PROG Low 10 µs tGHSL(1) VPP Hold After PROG 10 µs tGLGH PROG Width 1 tAVQV Address to Data Valid 48tCLCL tELQV ENABLE Low to Data Valid 48tCLCL tEHQV Data Float After ENABLE tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 2.0 ms Note: 0 110 µs 48tCLCL 1. Only used in 12-volt programming mode. 3-55 Flash Programming and Verification Waveforms - High Voltage Mode PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.3 VERIFICATION ADDRESS tAVQV PORT 0 DATA IN tDVGL tAVGL tGHDX DATA OUT tGHAX ALE/PROG tSHGL tGLGH VPP tGHSL LOGIC 1 LOGIC 0 EA/VPP tEHSH tEHQZ tELQV P2.7 (ENABLE) tGHBL P3.4 (RDY/BSY) BUSY READY tWC Flash Programming and Verification Waveforms - Low Voltage Mode PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.3 VERIFICATION ADDRESS tAVQV PORT 0 DATA IN tDVGL tAVGL tGHDX DATA OUT tGHAX ALE/PROG tSHGL tGLGH LOGIC 1 LOGIC 0 EA/VPP tEHSH tEHQZ tELQV P2.7 (ENABLE) tGHBL P3.4 (RDY/BSY) BUSY tWC 3-56 AT89LV51 AT89LV51 READY AT89LV51 AT89LV51 Absolute Maximum Ratings* Operating Temperature. -55°C to +125°C Storage Temperature. -65°C to +150°C Voltage on Any Pin with Respect to Ground . -1.0 V to +7.0 V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage . 6.6 V DC Output Current . 15.0 mA D.C. Characteristics TA = -40°C to 85°C, VCC = 2.7 V to 6.0 V (unless otherwise noted) Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA) -0.5 0.2 VCC-0.1 V VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V (1) VOL Output Low Voltage (Ports 1,2,3) IOL = 1.6 mA 0.45 V VOL1 Output Low Voltage(1) (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V VOH Output High Voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5 V ± 10% 2.4 V IOH = -20 µA 0.75 VCC V IOH = -10 µA 0.9 VCC V 2.4 V IOH = -300 µA 0.75 VCC V IOH = -80 µA 0.9 VCC V IOH = -800 µA, VCC = 5 V ± 10% VOH1 Output High Voltage (Port 0 in External Bus Mode) IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45 V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2 V -650 µA ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 300 K CIO Pin Capacitance 10 pF Power Supply Current ICC Power Down Mode(2) 50 Test Freq. = 1 MHz, TA = 25°C Active Mode, 12 MHz, VCC = 6 V/3 V 20/5.5 mA Idle Mode, 12 MHz, VCC = 6 V/3 V 5/1 mA VCC = 6 V 100 µA VCC = 3 V 20 µA Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin:10 mA Maximum IOL per 8-bit port: Port 0:26 mA Ports 1,2, 3:15 mA Maximum total IOL for all output pins:71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2 V. 3-57 A.C. Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics 12 MHz Oscillator Variable Oscillator Min Min Max Units 0 12 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tLHLL ALE Pulse Width 127 2tCLCL-40 ns tAVLL Address Valid to ALE Low 28 tCLCL-25 ns tLLAX Address Hold After ALE Low 48 tCLCL-25 ns tLLIV ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low 43 tCLCL-25 ns tPLPH PSEN Pulse Width 205 3tCLCL-45 ns tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold After PSEN tPXIZ Input Instruction Float After PSEN tPXAV PSEN to Address Valid tAVIV Address to Valid Instruction In 312 5tCLCL-80 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6tCLCL-100 ns tWLWH WR Pulse Width 400 6tCLCL-100 ns tRLDV RD Low to Valid Data In tRHDX Data Hold After RD tRHDZ Data Float After RD 97 2tCLCL-28 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns tAVDV Address to Valid Data In 585 9tCLCL-165 ns tLLWL ALE Low to RD or WR Low 200 3tCLCL+50 ns tAVWL Address to RD or WR Low 203 4tCLCL-75 ns tQVWX Data Valid to WR Transition 23 tCLCL-30 ns tQVWH Data Valid to WR High 433 7tCLCL-120 ns tWHQX Data Hold After WR 33 tCLCL-25 ns tRLAZ RD Low to Address Float tWHLH RD or WR High to ALE High 3-58 AT89LV51 AT89LV51 Max 233 4tCLCL-65 145 0 3tCLCL-60 0 59 75 tCLCL-8 0 5tCLCL-90 3tCLCL-50 0 43 123 ns ns 0 300 ns ns tCLCL-25 252 ns ns ns 0 tCLCL-25 ns tCLCL+25 ns AT89LV51 AT89LV51 External Program Memory Read Cycle tLHLL ALE tAVLL tLLIV tLLPL tPLIV PSEN tPXAV tPLAZ tPXIZ tLLAX tPXIX A0 - A7 PORT 0 tPLPH INSTR IN A0 - A7 tAVIV A8 - A15 PORT 2 A8 - A15 External Data Memory Read Cycle tLHLL ALE tWHLH PSEN tLLDV tRLRH tLLWL RD tLLAX tAVLL PORT 0 tRLDV tRLAZ A0 - A7 FROM RI OR DPL tRHDZ tRHDX DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH 3-59 External Data Memory Cycle tLHLL ALE tWHLH PSEN tLLWL WR tWLWH tLLAX tQVWX tAVLL tWHQX tQVWH DATA OUT A0 - A7 FROM RI OR DPL PORT 0 A0 - A7 FROM PCL INSTR IN tAVWL P2.0 - P2.7 OR A8 - A15 FROM DPH PORT 2 A8 - A15 FROM PCH External Clock Drive Waveforms tCHCX tCHCX VCC - 0.5 V tCLCH tCHCL 0.7 VCC 0.2 VCC - 0.1 V 0.45 V tCLCX tCLCL External Clock Drive TA = -40°C to 85°C Min VCC = 2.7 V Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL VCC = 3.0 V Max VCC = 3.3 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V Units 12 16 20 MHz 0 0 0 Clock Period 83.3 62.5 50 ns tCHCX High Time 20 15 10 ns tCLCX Low Time 20 15 10 ns tCLCH Rise Time 20 15 10 ns tCHCL Fall Time 20 15 10 ns 3-60 AT89LV51 AT89LV51 AT89LV51 AT89LV51 Serial Port Timing: Shift Register Mode Test Conditions (VCC = 2.7 V to 6 V; Load Capacitance = 80 pF) 12 MHz Osc Variable Oscillator Symbol Parameter Min Min tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-117 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid Max Units Max 700 10tCLCL-133 ns Shift Register Mode Timing Waveforms INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH tXHQX WRITE TO SBUF 0 1 2 tXHDV OUTPUT DATA CLEAR RI VALID 3 4 5 6 tXHDX VALID VALID SET TI VALID VALID VALID VALID AC Testing Input/Output Waveforms (1) Note: Float Waveforms V OL -0.1 V Timing Reference Points VLOAD 0.2 V - 0.1 V CC 1. AC Inputs during testing are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0." (1) VLOAD+ 0.1 V 0.2 VCC + 0.9 V TEST POINTS 0.45 V VALID SET RI INPUT DATA VCC - 0.5 V 7 VLOAD -0.1 V Note: V OL+ 0.1 V 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs. 3-61 AT89LV51 AT89LV51 ICC (mA) TYPICAL ICC (ACTIVE) at 25o C 24 VCC = 6.0 V 20 16 VCC = 5.0 V 12 8 VCC = 3.0 V 4 0 0 4 8 12 F (MHz) 16 20 24 AT89LV51 AT89LV51 o TYPICAL ICC (IDLE) at 25 C ICC (mA) 4.8 VCC = 6.0 V 4.0 3.2 VCC = 5.0 V 2.4 1.6 VCC = 3.0 V 0.8 0.0 0 3-62 4 AT89LV51 AT89LV51 8 12 F (MHz) 16 20 24 AT89LV51 AT89LV51 AT89LV51 AT89LV51 TYPICAL ICC vs. VOLTAGE - POWER DOWN (85°C) 20 I 15 C C 10 µ A 5 0 3.0V 4.0V Vcc VOLTAGE 5.0V 6.0V 3-63 Ordering Information Speed Power (MHz) Supply 12 2.7 V to 6 V Ordering Code Package AT89LV51-12AC AT89LV51-12AC AT89LV51-12JC AT89LV51-12JC AT89LV51-12PC AT89LV51-12PC AT89LV51-12QC AT89LV51-12QC 44A 44J 40P6 44Q Ordering Information Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP) 3-64 AT89LV51 AT89LV51 Operation Range Commercial (0°C to 70°C)