AT84AS003/4 AT84AS003 AT84AS004 5428B MC100LVEP14 SY898830 MC10EP08 SY10EP08 - Datasheet Archive

 

Introduction Atmel AT84AS003/4 10-bit 1.5 Gsps or 2 Gsps ADC with 1:2/4 combined DMUX, feature two independent reset signals DRRB

 

Atmel AT84AS003/4 AT84AS003/4 ADC Reset Implementation Introduction Atmel AT84AS003/4 AT84AS003/4 10-bit 1.5 Gsps or 2 Gsps ADC with 1:2/4 combined DMUX, feature two independent reset signals DRRB and ASYNCRST which must be used to start the device properly. As DRRB and ASYNCRST are not active at the same level (DRRB active low and ASYNCRST active high) they should be applied simultaneously, one possible way to implement both signals is to use the positive and negative signals of a differential pair, thus ensuring that both resets occur simultaneously. This Application note provides some ideas to implement the reset circuit for the AT84AS003 AT84AS003 or AT84AS004 AT84AS004 (please refer to the last version available of the device datasheet, reference 5403 and 5431 respectively). AT84AS003/4 AT84AS003/4 Reset Implementation Application Note 1. AT84AS003 AT84AS003 DRRB and ASYNCRST 1.1 Description There are two reset signals available for the AT84AS003/4 AT84AS003/4: DRRB and ASYNCRST. These reset signals DRRB and ASYNCRST are required to start the device properly. It is recommended to apply both reset signals at the same time and to hold the input clock low during reset See "Timing Requirements" on page 4. · The DRRB / ASYNCRST signal frequency should be 200 MHz maximum · The reset pulse should be 1 ns minimum · DRRB is active low while ASYNCRST is active high As it is recommended to apply both reset signals simultaneously, one possible solution is to use a differential driver so that DRRB and ASYNCRST are generated as the two signals of a differential pair. This would allow for both the simultaneous application of the signals to the device and a simple way to drive both signals. An example is provided in Figure 1-1 on page 2 (principle of operation). 5428B 5428B­BDC­11/05 Figure 1-1. AT84AS003/4 AT84AS003/4 DRRB and ASYNCRST Driver Scheme DRRB 1 ns Pulse Source Signal Common Mode ASYNCRST 2. Electrical Characteristics Table 2-1. DRRB and ASYNCRST Absolute Maximum Ratings Parameter Symbol Value Unit ADC reset DRRB -0.3 to VCCA + 0.3 V ASYNCRST -0.3 to VCCD + 0.3 V DMUX asynchronous reset Table 2-2. DRRB and ASYNCRST Recommended Conditions of Use Parameter Symbol Recommended Unit ADC reset DRRB 2.5V ECL, HSTL, LVCMOS levels V ASYNCRST 2.5V ECL, HSTL, LVCMOS levels V DMUX asynchronous reset Table 2-3. DRRB and ASYNCRST Electrical Characteristics Parameter Symbol Min Typ Max Unit DRRB -0.3 VCCA- 0.3 0 VCCA 1.4 0.3 VCCA + 0.3 V V ASYNCRST -0.3 VCCD - 0.3 0 VCCD 1.4 0.3 VCCD + 0.3 V V DRRB Logic low Logic high Threshold ASYNCRST Logic low Logic high Threshold 2 AT84AS003/4 AT84AS003/4 Reset Implementation 5428B 5428B­BDC­11/05 AT84AS003/4 AT84AS003/4 Reset Implementation 3. Case When the Input Clock Is Held Low During Reset 3.1 Timing Diagrams Figure 3-1. Asynchronous Reset Timing Diagram, 1:2 Mode, Simultaneous Mode, Input Clock Held Low During Reset (Principle of Operation) TA = 160 ps N VIN CLK 1 ns min DRRB 1 ns min ASYNCRST TOD + 5.5 cycles A0.A9 N N+2 B0.B9 N+1 N+3 N+4 N+5 DR (DR mode) DR (DR/2 mode) 3 5428B 5428B­BDC­11/05 Figure 3-2. Asynchronous Reset Timing Diagram, 1:4 Mode, Simultaneous Mode, Input Clock Held Low During Reset (Principle of Operation) TA = 160 ps N VIN CLK 1 ns min DRRB 1 ns min ASYNCRST TOD + 7.5 cycles A0.A9 N B0.B9 N+1 C0.C9 N+2 D0.D9 N+3 DR (DR mode) DR (DR/2 mode) 3.2 3.2.1 Hardware Implementation Timing Requirements Figure 3-3. AT84AS003/4 AT84AS003/4 Reset Signals Timing Requirements CLK Source CLK Enable CLK Input 1 ns min Reset Pulse 500 ps min DRRB 500 ps min ASYNCRST 4 AT84AS003/4 AT84AS003/4 Reset Implementation 5428B 5428B­BDC­11/05 AT84AS003/4 AT84AS003/4 Reset Implementation 3.2.2 Example of Synopsis In the following section, Figure 3-4 on page 5 and Figure 3-5 on page 6 give one alternative solution to implement the clock and reset circuitry using discrete components. Figure 3-4. AT84AS003/4 AT84AS003/4 Reset Signals Implementation Timing Diagram using a Binary Up Counter CLK Source LOAD End of Count PE (Parallel Load Enable) COUNT CE (Count Enable) = COUNT HOLD Q0 0 1 0 1 0 1 1 1 Q1 1 1 0 0 1 1 1 1 Q2 0 0 1 1 1 1 1 1 Q3 - Q7 1 1 1 1 1 1 1 1 Clock Enable = PE XOR COUNT CLK Input 2 clock cycles Reset = NOT (Q1) 1.5 clock cycles 2 clock cycles DRRB = NOT (Reset) ASYNCRST = Reset In Figure 3-4 on page 5, the theoretical timing diagram is presented as a possible way to satisfy the timing requirements described in Figure 3-3 on page 4. The idea is to ensure that the reset signals: 1. Are applied only 1.5 clock cycles after the input clock is held low (thanks to an enable signal) 2. Last at least 2 clock cycles (satisfying the requirement of 1 ns minimum since the maximum frequency of operation of the ADC is 2 Gsps, yielding a clock cycle of 500 ps) 3. And are released after 2 clock cycles (satisfying the requirement of 500 ps minimum before the clock restarts) With the use of one counter, both the reset signals and the enable signal needed for the clock driver are generated. The example given in Figure 3-5 on page 6 gives a possible implementation. However, the part within the dotted rectangle will not be further explained in the following section as it might be more easily implemented in an FPGA for example. This is why the stress is only led on the differential buffer to be used as the reset signals driver See "Practical Example" on page 11. 5 5428B 5428B­BDC­11/05 Figure 3-5. AT84AS003/4 AT84AS003/4 Reset Signals Implementation Synopsis 10-bit 1.5 or 2 Gsps ADC With 1:2/4 DMUX 20 20 Analog Input 20 20 Clock Clock Source Clock Driver A0/A0N.A9/A9N B0/B0N.B9/B9N C0/C0N.C9/C9N D0/D0N.D9/D9N Input DRRB ASYNRST EN 2 DR/2 or DR Output clock XOR CE COUT PE P0 - P7 = 01011111 COUT Counter MR Q1 TCPLD Differential Buffer Discrete or programmed into an ASIC or FPGA (recommended) Note: 6 References for the XOR gate, the binary up counter and the clock driver are provided in Table 3-1 on page 7. This table is not exhaustive and is only intended to provide examples to help you with the design. AT84AS003/4 AT84AS003/4 Reset Implementation 5428B 5428B­BDC­11/05 AT84AS003/4 AT84AS003/4 Reset Implementation Table 3-1. Differential Buffer/Gates Examples (For Information Only) Manufacturer Part Number Description Input Compatibility Output Compatibility Max Frequency Propagation Delay VCC On Semiconductor MC100LVEP14 MC100LVEP14 Clock Driver ECL/PECL/HSTL ECL/PECL 2 GHz 400 ps 3.3V Micrel SY898830 SY898830 Clock Driver 2.5 GHz 450 ps 3.3V On Semiconductor MC10EP08 MC10EP08 XOR Gate ECL ECL 3 GHz 250 ps 3.3V Micrel SY10EP08 SY10EP08 XOR Gate ECL ECL 3 GHz 200 ps 3.3V On Semiconductor MC10LVEP16 MC10LVEP16 Differential Driver ECL ECL 4 GHz 240 ps 3.3V On Semiconductor NB6L11 NB6L11 Differential Driver/translator ECL ECL 6 GHz 150 ps 2.5V Micrel SY58012U SY58012U Differential Driver/translator LVPECL 5 GHz 260 ps 2.5V Micrel SY89311U SY89311U Differential Driver ECL/PECL 3 GHz 300 ps 3.3V Micrel SY8985 SY8985 Differential Driver/translator LVPECL/CML/ LVPECL 2 GHz 380 ps 2.5V On Semiconductor MC100EP016A MC100EP016A Counter ECL 1.4 GHz 550 ps 3.3V PECL/LVPECL ECL/HSTL LVPECL/LVDS/ CML PECL/LVPECL/E CL LVDS PECL ECL 4. Case When the Input Clock Is Not Held Low During Reset 4.1 Timing Diagrams Figure 4-1. Reset Timing Diagram, 1:2 Mode, Simultaneous Mode CLK 1 ns minimum ASYNCRST DRRB 5.5 Clock cycles + TRDR2 TRDR1 = 4ns DR (DR mode) DR (DR/2 mode) 7 5428B 5428B­BDC­11/05 Figure 4-2. Reset Timing Diagram, 1:4 Mode, Simultaneous Mode CLK 1 ns minimum ASYNCRST DRRB 5.5 Clock cycles + TRDR2 TRDR1 = 4 ns DR (DR mode) DR (DR/2 mode) Figure 4-3. Reset Timing Requirements CLK 1 ns minimum ASYNCRST DRRB Forbidden Area Forbidden Area Forbidden Area Forbidden Area The reset (activation or de-activation) is taken into account on the clock edge marked with an arrow. 8 AT84AS003/4 AT84AS003/4 Reset Implementation 5428B 5428B­BDC­11/05 AT84AS003/4 AT84AS003/4 Reset Implementation Figure 4-4. Reset Forbidden Area CLK ASYNCRST Reset Activation Reset De-Activation DRRB Forbidden Area = 80 % of the clock Rise time (minimum = 50 ps) Table 4-1. Forbidden Area = 80 % of he clock Rise time t (minimum = 50 ps) Reset Timing Characteristics Parameter Symbol Reset to Data Ready (Reset activation) TRDR1 Reset to Data Ready (Reset De-activation) TRDR2 Min. Typ. Max. 4 0 Forbidden Area 50 Reset Minimum Pulse Width 1 ns 6 80% of the input clock Rise Time Unit ns ns ns 9 5428B 5428B­BDC­11/05 4.2 Example of Synopsis Figure 4-5. Proposed Implementation Scheme Data DR/2 FPGA ADC RESET Single to Differential driver (optional) Logic block CLK The idea is that the reset signal is generated using the output clock of the ADC which has a phase relationship with the input clock. The reset signals can be generated inside the FPGA using the following sequence: The Internal Reset goes high on the first rising edge of the Data ready clock and remains high until the next Data Ready rising edge, it then goes low until the next interruption (restart or external interruption) for example. A driver can be used between the FPGA and the ADC. The same references as mentioned previously in the section dedicated to the reset when the clock is held low apply. Figure 4-6. Reset Implementation Using the Output Clock (1:4 DMUX, DR/2 Mode) - Principle CLK DR/2 Internal Reset 8 input clock cycles ASYNCRST DRRB 10 AT84AS003/4 AT84AS003/4 Reset Implementation 5428B 5428B­BDC­11/05 AT84AS003/4 AT84AS003/4 Reset Implementation Figure 4-7. Timing Requirements CLK TDR = 6.7 ns DR/2 Internal propagation delay Internal Reset External propagation delay ASYNCRST DRRB What is important is to ensure that the total delay between the input clock falling edge and the reset (ASYNCRST) rising edge is different from a multiple of half the clock period so that the reset edge will never occur during a forbidden zone as described previously: ­ TDR + Internal propagation delay + External propagation delay N x Tclk/2 ­ with N integer number (N = 0, 1, 2, .etc). ­ and TDR = 6.7 ns 4.3 Practical Example This is an example of use of the MC10LVEP16 MC10LVEP16 ECL Differential Receiver/Driver from On Semiconductor as the AT84AS003/4 AT84AS003/4 DRRB and ASYNCRST reset signals driver. AT84AS003/4 AT84AS003/4 Interfacing with MC10LVEP16 MC10LVEP16 Buffer Termination Scheme 10- bit 1.5 or 2 Gsps ADC with 1:2/4 DMUX MC10LVE MC10LVE P16 Z0 = 50 DRRB Q Z0 = 50 ASYNCRST Q VCC = 2.5V 50 50 VOLmax = 930 mV VOHmin = 1430 mV VCC ­ 2V = 0.5V 11 5428B 5428B­BDC­11/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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