AT17CXXX AT34CXXX A13-A0 4000H 00RESET/OE - Datasheet Archive

 

Programming Specification for Atmel's Configuration Memories (AT17CXXX and AT34CXXX) The Configurator The Configurator is a

 

Configurator Programming Specification for Atmel's Configuration Memories (AT17CXXX AT17CXXX and AT34CXXX AT34CXXX) The Configurator The Configurator is a serial memory which can be used not only as a serial memory but also can be used to load programmable devices. It can perform that latter action either as a slave, in which it responds to demands from the programmable logic and the address is implied, or as a master in which it autonomously loads the programmable logic. Its behavior is controlled by a program which is stored, interleaved with the data it contains, within the EEPROM memory. This memory can be read from or written to while the Configurator is in the system. The Configurator can also be programmed before it is inserted into the system. This document describes only the features needed to program the Configurator before it is placed in the system. Configurator Versions The Configurator comes in two versions: the AT17CXXX AT17CXXX, and the AT34CXXX AT34CXXX (generically referred to as "the device" in this document). There is only one difference in the programming specification for these two devices. The AT17CXXX AT17CXXX has an additional step, to set the default reset polarity in the user mode.The programming algorithm is independent of the package; only 8 pins are used in either package for programming. The pins not used in the 20 pin version are set to zero. Configurator Programming Specification Serial Bus Overview The serial bus is a two wire bus; one wire (CLOCK) functions as a clock and is provided by the programmer, the second wire (DATA) is a bi-directional signal and is used to provide data and control information. Information is transmitted on the serial bus in messages. Each MESSAGE is preceded by a START BIT and is ended with a STOP BIT. The message consists of an integer number of bytes, each byte consists of 8 bits of data and is followed by a ninth ACKNOWLEDGE BIT. This ACKNOWLEDGE BIT is provided by the recipient of the data. This is possible because devices only drive the CLOCK and DATA low, the system (in the programming case the Programmer) provides a small pull-up current (3k Ohm equivalent). The MESSAGE FORMAT consists of the bytes shown in the Message Bytes table below. The MESSAGE FORMAT is preceded by a start bit and ended by a stop bit. The complete MESSAGE FORMAT is shown in the Message Format table below. Application Note Message Bytes DEVICE ADDRESS 1ST ADDRESS WORD 2ND ADDRESS WORD DATA BYTE(S) Message Format START BIT DEVICE ADDRESS 1ST ADDRESS WORD 1ST ADDRESS WORD DATA BYTE(S) STOP BIT 0437A 3-11 Serial Bus Overview (Continued) Bit Format The programmer provides all the bytes except for the data bytes when the device is being read. Note that each byte is individually acknowledged. This acknowledgment is provided by the Configurator in all cases except for the data bytes in the read mode, in which case the acknowledge is provided by the programmer. Data on the DATA pin may change only during CLOCK low times. Start and Stop Bits The START BIT is indicated by a high-to-low transition of DATA when CLOCK is high. Similarly, the STOP BIT is generated by a low-to-high transition of DATA when CLOCK is high, as shown below. Start and Stop Bits SCL SDA 8th BIT ACK tWR Word n Start Condition Stop Condition Acknowledge Bit The ACKNOWLEDGE BIT is shown in the above figure. Note that the ACKNOWLEDGE BIT is provided by the device receiving the byte. The receiving device can accept the byte, by asserting a low value, on DATA or it can refuse the byte by asserting (not driving the signal) a 1 on DATA. All bytes must be terminated by either the ACKNOWLEDGE BIT or a STOP BIT. Bit Ordering Protocol The most significant bit is the first bit of a byte transmitted on DATA for the DEVICE ADDRESS BYTE and the EEPROM ADDRESS BYTES. It is followed by the lesser significant bits until the eighth bit, the least significant bit is transmitted. This is followed by the acknowledge bit. However, for DATA BYTES (both writing and reading) the first bit transmitted is the least significant bit. This protocol is shown in the tables below: Device Address Byte The contents of the Device Address Byte are shown below, along with the order in which the bits are clocked into the device. The A2 bit is provided to allow 2 devices to share a common bus; when programming a single device, the A2 bit and the A2 pin on the device will usually both be at 0v. MSB LSB 1 0 1 0 A2 1 1 R/W# 1st 2nd 3rd 4th 5th 6th 7th 8th Where:R/W#=1 Read =0 Write A2=1 if A2 pin is at VCC =0 if A2 pin is at GROUND EEPROM Address The EEPROM address consists of two bytes, each of which is followed by an acknowledge bit. These two bytes define a 14 bit address A13-A0 A13-A0 where A13 is the most significant address bit. MSB 0 st 1 3-12 LSB 0 nd 2 A13 A12 A11 rd th th 3 4 5 A10 th 6 A9 A8 th th 7 Configurator 8 The order in which each byte is clocked into the device is also indicated. MSB Ack LSB A7 A6 A5 A4 A3 A2 A1 A0 st nd rd th th th th th 1 2 3 4 5 6 7 8 Ack Configurator Data Byte The organization of the Data Byte is shown below. Note that in this case, the data byte is clocked into the device LSB first and MSB last. Writing All writing takes place in pages. A page is 64 bytes long and the page boundaries are addresses where A5-0 are all zero. Writing can start at any address within a page and the number of bytes written is the number of data bytes transmitted and must be 64. The first byte is written at the transmitted address. The address is incremented in the device following the receipt of each data word received. Only the lower six bits of the address are incremented and the if the address is incremented after the 64th byte in the page is sent, then the next byte to be written is the first byte of the page. LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 1st 2nd 3rd 4th 5th 6th 7th 8th A write action consists of a Start Bit a Device Address with R/W# =0 An Acknowledge Bit From the device First Word of the Address An Acknowledge Bit From the device Second Word of the Address An Acknowledge Bit From the device One or more data bytes Each followed by an Acknowledge Bit From the device a Stop bit On receipt of the stop bit, the device enters an internally timed write cycle. While the device is busy with this write cycle it will not acknowledge any transfers. Thus the programmer can start the next page write by sending the Start Bit followed by the Device Address. If this is not acknowledged, then the programmer should abandon the transfer without asserting a stop bit. The programmer can then repeat this until an acknowledge is received. When this is received the write action can proceed i.e. the next byte to be sent is the device address. Reading Read operations are initiated the same way as write operations with the exception that the R/W# bit in the device address is set to one. There are three read operations: current address read, random read and sequential read. Current Address Read: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. If the last operation was a read at address n, then the current address would be n+1. If the final operation was a write at address n, then the current address would again be n+1 with one exception. If address 4 was the 64th byte address in the memory row, the incremented address n+1 would "roll over" to the 1st byte address in the page. Once the device address with the R/W# select bit set is clocked in and acknowledged by the device the current address word is serially clocked out. The programmer does not acknowledge the read but does generate a following stop condition. A current address read action consists of a Start Bit a Device Address with R/W# =1 An Acknowledge Bit From the device a data byte from the device a stop bit from the programmer. 3-13 Random Read: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the device, the programmer must generate another start condition. The programmer now initiates a current address read by sending a device address with the R\W# bit high. The device acknowledges the device address and serially clocks out the data word. The programmer does not acknowledge the read but does generate a following stop condition. A random address read action consists of a Start Bit a Device Address with R/W# =0 An Acknowledge Bit From the device First Word of the Address An Acknowledge Bit From the device Second Word of the Address An Acknowledge Bit From the device a Start Bit a Device Address with R/W# =1 An Acknowledge Bit From the device a data byte from the device a stop bit from the programmer. Sequential Read: Sequential reads are initiated by either a current address read or a random address read. After the programmer receives a data word, it responds with an acknowledge. As long as the device receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the programmer does not respond with an acknowledge but generates a stop condition. Programming Pins Eight pins are used to program the devices. These eight pins, and their mapping to the package pins are shown in the following table. 8-Pin Device 20-Pin Device (1) DATA 1 2 CLOCK 2 4 RESET/OE# 3 6 CE# 4 8 GROUND 5 10 A2 OR CEO# 6 14 SER_EN# 7 17 VCC 8 20 Pin Note: 3-14 Configurator 1. The unused pins in the 20-pin package must be grounded during programming. Configurator Programmer Functions The programmer needs to perform the following functions: 1. Check the Manufacturers Code and the Device Code 2. Program the device 3. Verify the device 4. AT17CXXX AT17CXXX only: 5. Set the Reset Polarity option. In the order given above. The are performed in the following manner. Reading Manufacturers and Device Code These two bytes are read from addresses 0 and 1 respectively with : RESET/OE#=0V CE#=11.5 ± 0.5 A2=(Same as applied to A2 Pin, usually 0v) SER_EN#=0V The correct codes are (1) Manufacturers Code Device Code Note: - Byte 0 1E Byte 1 (Both devices) FF AT17CXXX AT17CXXX FE AT34CXXX AT34CXXX 1. The Manufacturer's Code and Device Code are read using the same byte ordering specified in the beginning of this document; i.e. LSB first, MSB last. Programming the Device All the bytes in the device's 64 byte page must be written. The order is not important but it is suggested that the device be written sequentially from Byte 0. Writing is accomplished by using the DATA and CLOCK pins and setting the other programming pins as follows: RESET/OE#=0V CE#=0V A2=(Same as applied to A2 Pin, usually 0v) SER_EN#=0V Verifying the Device All bytes in the device must be read and compared to their intended values. Reading is done using the CLOCK and DATA pins with the other programming pins set to the same value as in programming i.e. RESET/OE#=0V CE#=0V A2=(Same as applied to A2 Pin, usually 0v) SER_EN#=0V AT17CXXX AT17CXXX Only - Setting the Polarity Option The AT17CXXX AT17CXXX can has a programmable polarity on the RESET/OE# pin. This has a default value of ACTIVE LOW but it can be changed during the programming. If a data file is used to program the AT17CXXX AT17CXXX, the four bytes defining the polarity are stored at address 4000H 4000H in the file. If these bytes are: FF FF FF FFRESET/OE# polarity must be set ACTIVE LOW as indicated below 00 00 00 00RESET/OE 00RESET/OE# polarity must be set ACTIVE HIGH as indicated below 3-15 Any other valueinvalid (no action need be taken) Setting the Polarity Option Active Low: Write a byte of data set to FF to address 3FFF, using CLOCK and DATA, with the other programming pins set to the following: RESET/OE#=5±0.25 CE#=5±0.25 A2=(Same as applied to A2 Pin, usually 0v) SER_EN#=0v This will change RESET/OE# pin functionality to RESET#/OE. Setting the Polarity Option Active High: Write a byte of data set to FF to address 3FFF , using CLOCK and DATA, with the other programming pins set to the following: RESET/OE#=0v CE#=5±0.25 v A2=(Same as applied to A2 Pin, usually 0v) SER_EN#=0v This will change RESET#/OE functionality to RESET/OE# (the default condition). Using A Programmed Device as the Data Source If a programmed (master) device is to be used as the source for the data to be programmed into some new devices, then the programmer can read the data from the master. This can be done without any difficulty for the AT34CXXX AT34CXXX; however the polarity of the RESET/OE# must be known before this can be done successfully for the AT17CXXX AT17CXXX. Depending on the capabilities of the programming device, one of the following algorithms can be used to read the data and polarity of the RESET/OE# pin. 1. If the programmer is able to sense s tri-state condition: Switch the power on with RESET/OE#=0V CE#=0V A2 (CEO#)=Input to programmer (High Z) SER_EN#=5±0.25 CLOCK=0 DATA=Input to programmer In this condition, if the SDA pin is tri-stated, then the RESET/OE# fuse is PROGRAMMED; if the SDA pin reads a "0" or a "1", then the RESET/OE# fuse is ERASED. 2. If the programmer is NOT able to sense a tri-state condition: Switch the power on with RESET/OE#=5±0.25 CE#=0V A2 (CEO#)=Input to programmer SER_EN#=5±0.25 CLOCK=0 DATA=Input to programmer Hold this configuration for 10 seconds after Vcc reaches 5V. Then set RESET/OE# to low and pulse the clock 131,072 (128K) times reading the data provided at each clock pulse. After the last clock has been issued CEO# should drop from high to low. If it does so then the polarity is RESET/OE#. If CEO# remains high, then the polarity is RESET#/OE. In this latter case, none of the data read is reliable and it should be discarded. The procedure should be redone with RESET/OE# = 0V on power up and switched to 5±0.25V before starting the clock. The data read is now good data. 3-16 Configurator Configurator D.C. Characteristics Symbol Parameter Test Condition VCC Supply Voltage ICC Supply Current VCC = 5V ILL Input Leakage Current VIN = VCC or VSS ILO Output Leakage Current Min VOUT = VCC or VSS Max 5.0 5.25 V 2.0 3.0 mA 0.10 3.0 A 0.05 4.75 Typ Units 3.0 A VIH VCC x 0.7 VCC ± 0.5 V VIL -1.0 VCC x 0.3 V A.C. Characteristics ? Symbol Parameter fCLOCK Max Clock Frequency, Clock Units 400 Min kHz tLOW Clock Pulse Width Low 1.2 tHIGH Clock Pulse Width High 0.6 s s tAA Clock Low to Data Out Valid 5 s tBUF Time the bus must be free before a new transmission can start 1.2 s tHD;STA Start Hold Time 0.6 s tSU;STA Start Set-Up Time 0.6 s tHD DAT Data In Set-up Time 0 s tSU DAT Data In Set-up Time 100 tR Inputs Rise Time 0.3 s tF Inputs Fall Time 300 ns tSU STO Stop Set-up Time 0.6 tDH Data Out Hold Time 50 tWR Write Cycle Time ns s ns 10 ns Serial Data Timing Diagram tLOW tHIGH SCL tR tHD.STA tF tSU.STO tSU.DAT tSU.STA tHD.DAT SDA IN tBUF tAA tDH SDA OUT 3-17