AS998/AS998A AS998/A 0-105C AS998 AS998N AS998D AS998A AS998AN AS998AD DS998A

AS998/AS998A ASTEC Preliminary SEMICONDUCTOR AS998/A Power Management IC Features Description · Low start-up current 64uA

Power Management IC AS998/AS998A AS998/AS998A ASTEC Preliminary SEMICONDUCTOR AS998/A AS998/A Power Management IC Features Description · Low start-up current 64uA (typ) · Low running current 2mA (typ) · Low power light load mode Low power · activated standby when OV is The AS998/AS998A AS998/AS998A is an IC intended for use as a PWM controller for switch mode power supplies. The device is particularly suited as a primary side controller for adapter, printer, peripheral, mobile chargers and desktop auxiliary power supplies. The AS998/AS998A AS998/AS998A is manufactured in BiCMOS technology and exhibits very low start-up and operating power. This allows the device to be suitable in applications where stringent standby or Blue Angel criteria are required. Extended commercial operating · temperature range to 0-105C 0-105C On-board fixed · 100kHz (typ) frequency oscillator Frequency randomizer to reduce · EMC emissions · Dedicated OV shutdown pin On-board voltage · compensation ramp · On-board current sense filtering · Optional primary side regulation Pin Configuration - Many of the external functions associated with PWM controllers have been integrated into the AS998/AS998A AS998/AS998A allowing the external component count to be significantly reduced. Features such as fixed internal oscillator, internal ramp compensation and current filters all reduce the external support components. The AS998/AS998A AS998/AS998A has an output rise and fall time of 250/ 210 nS typical. Top view PDIP (N) OV SOIC (D) VREG OV VREG COMP VCC COMP VCC VFB OUT VFB OUT I SENSE GND I SENSE GND Ordering Information Description Temperature Range Order Codes AS998 AS998 8-Pin Plastic DIP 0 to 105° C AS998N AS998N AS998 AS998 8-Pin Plastic SOIC 0 to 105° C AS998D AS998D AS998A AS998A 8-Pin Plastic DIP 0 to 105° C AS998AN AS998AN AS998A AS998A 8-Pin Plastic SOIC 0 to 105° C AS998AD AS998AD ASTEC Semiconductor ASTEC Semiconductor May 2001 May 2001 Page of 6 Page 1 1 of 6 DS998A DS998A DS998A DS998A Rev. A3 Rev. A3 AS998/AS998A AS998/AS998A Power Management IC Functional Block Diagram ASTEC Semiconductor May 2001 Page 2 of 6 DS998 DS998 Rev. A3 Power Management IC AS998/AS998A AS998/AS998A Pin Descriptions Pin # 1 LABEL OV DESCRIPTION Overvoltage Pin. The OV input/output function is implemented by an on chip latch. This pin is driven to the Reg voltage if the on chip circuitry senses a VDD level greater than the OV threshold (VDDov). This error condition stops the part from generating any more output pulses until VDD has been reduced to the VDDul level and then raised as in a normal power-on sequence. Alternatively, the OV error condition can be cleared by forcing the OV pin to near ground. The output is immediately enabled following an OV clear function. The OV error condition can also be generated externally by temporarily forcing the OV pin to a voltage greater than the VOV threshold. This will force the part to latch an OV condition and not generate any more output pulses unless cleared as described. 2 COMP Compensation Pin. This pin is the output of the error amplifier and can also be used as an input for an optocoupled control signal to the PWM comparator. Generally this pin is connected to a feedback network to FB. If an optocoupler feedback is used, COMP connects to the collector of the common emitter optocoupler, generally with a pull-up resistor to VDD or Reg. 3 FB Feedback Pin. Inverting input to the error amplifier. This pin is tied to an internal default divider which will tend to regulate VDD at a nominal 11 V. 4 CSNS Current Sense Input. The signal on this pin is fed via a low pass filter to the PWM comparator. Superimposed on the input to the PWM is a slope compensation ramp derived from the main oscillator. In addition to the above, the current sense signal is connected directly to an over-current comparator that detects an overload condition and immediately terminates the gate drive pulse with a minimum propagation delay. 5 GND Circuit Common Ground. 6 OUT Gate Drive Output. The current source and sink capability of the output buffer is tailored to minimize EMI. When the IC is not running, this pin is held low so a pull down resistor on the FET gate is not required. 7 VDD Positive Supply Voltage. An on-board shunt regulator allows this IC to be powered via a simple resistor from a widely varying bias supply. The ICs power management block keeps the part in startup current mode while VDD is ramping up until the part turns on at the UVLhigh threshold. The IC then draws the specified supply current while operating unless VDD drops below the UVLlow threshold. If VDD drops below UVLlow, then the part will return to startup current mode. 8 REG Voltage Regulator. Decoupling pin as required for internal low voltage supply. This pin may be used to source 1mA for the control opto coupler. ASTEC Semiconductor May 2001 Page 3 of 6 DS998A DS998A Rev. A3 AS998/AS998A AS998/AS998A Power Management IC IC Block Diagram Description POWER MANAGEMENT This block contains reference generators and comparators to determine the under-voltage shutdown point, the power-on point, the primary regulation operating point, and the overvoltage shutdown point. INTERNAL POWER / REFERENCE This block includes a coarse regulator for on chip power and cascade voltages for HV circuitry, a bandgap for comparator references, a bias current generator, PTAT, BiasP and BiasN. TEMPERATURE COMPENSATED CURRENT SOURCE This block generates a constant current as a function of voltage and temperature with no off-chip components. OSCILLATOR Mirrored currents from the reference block are used to charge a capacitor to a threshold voltage at which point the direction is switched to an opposing 3X mirror to drive the capacitor to a lower limit threshold value. This generates a 75% duty cycle digital clock to the output latch, and a 100KHz ramp voltage to be used in the feedback control. FEEDBACK CONTROL This block senses one of the various feedback methods to control the output duty cycle. It includes a current sense, a low pass filter, current amplifier, summing amp, and comparators. This block sums the analog ramp from the OSC, sense, and compensation node voltages into a comparator which triggers the falling edge of the PWM clock signal. This provides supply voltage compensation and load regulation to the power converter system. OUT_DRV A high speed, high current bipolar output stage capable of providing approximately 500 mA sink and 250 mA source current to charge and discharge the gate of a large power FET. It is understood that the total delay from the comp pin to the output pin should be about 100 ns. Absolute Maximum Ratings Parameter Symbol Rating Units Supply Voltage (Low Impedance Source) VDD 13 V Supply Current (High Impedance Source) IDD 15 mA Output Peak Current IOUT 600 mA REGULATOR CURRENT IREG 10 mA Continuous Power at 25° C 8L SOIC PD 750 mW 1000 8L PDIP mW Junction Temperature TJ 150 °C Storage Temperature TSTG 65 to 150 °C TL 300 °C Lead Temperature, Soldering 10 Seconds Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ASTEC Semiconductor May 2001 Page 4 of 6 DS998 DS998 Rev. A3 Power Management IC AS998/AS998A AS998/AS998A Electrical Characteristics Over full junction temperature range of 0-105°C. Ambient temperature deratings will bepend on power dissipation and package thermal characteristics. Vdd = 12V, OV = 0V, CSNS = 0V. Cload = 1800pf, Creg = 100nf (AVVD to GND) unless otherwise stated. To start chip, Vdd must be raised above UVLhigh. Parameter Symbol Test Condition Startup Current IDDO UVLHIGH Threshold Supply Current IDD No Load Startup Threshold UVLHIGH AS998 AS998 AS998A AS998A UVL off Threshold UVLLOW Bias Current at POS VCLAMP Int. Regulator Voltage VREG Min Typ Max Unit 64 100 µA 1 2 4 mA 9 9.5 10 10 11 10.5 V V 7.6 8 8.4 V IDD = 10mA No Load 13 14 14.7 V IREG = 1mA 5.5 6.25 7.0 V Test Condition Min Typ Max Unit 8.4V < VDD < 13.3V ; 15 cycle average - AS998 AS998 8.4V < VDD < 13.3V ; 15 cycle average - AS998A AS998A 7.3 8.1 9.3 9.3 11.7 10.7 µs µs Oscillator Parameter Symbol Mean Period TOSC Modulation Repetition Rate TREP Peak-to-Peak Modulation TDEV Max. Duty Cycle DMAX 15 Peak-to-Peak change in period cycles 13.7 16.5 23 % 70 75 78 % Min Typ Error Amplifier Parameter Symbol FB Divider R Test Condition RFB Max 100 Unit k VDD Regulation Point VDDREG 11.4 FB Threshold VREF COMP = FB, VDD =12V Gain (DC) AVOL No load on COMP 85 dB Gain-Bandwidth Product GBP No load on COMP 10 MHz COMP Output High VCOMPH FB = 2V COMP Output Low VCOMPL ICOMPH COMP = 3V, FB = 2V COMP Sink Current ICOMPL COMP = 1V, FB = 3V Test Condition 12.6 V 2.37 2.5 2.62 V FB = 3V COMP Source Current 12 4.5 V 100 250 mV 25 50 100 µA 25 300 500 µA Min Typ Max Unit Current Sense Comparator Parameter Symbol Scaling of COMP AC Input Impedance to CSNS input RCSAC Input Filter FCS Prop. Delay to Output 0.4 Fin Fco 100 k Time Constant 320 ns 700 ns tpd1 ASTEC Semiconductor May 2001 Page 5 of 6 DS998A DS998A Rev. A3 AS998/AS998A AS998/AS998A Power Management IC Electrical Characteristics (cont.) Over Current Comparator Parameter Symbol Test Condition Min Typ Max Unit Comparator Threshold VCSTH COMP = 1V, FB = 3V 1.25 V Propagation Delay to Output tpd2 FB = 2, VCS step to 1.65V, from 50% point on CSNS input to 90% point on output H to L transition 100 150 Min Typ Max Unit 13 14 14.7 V ns Over Voltage Input Parameter OV VDD Threshold OV Threshold Symbol Test Condition VDDOV Forcing VDD pin VOV Forcing OV pin 3.5 V OV Latch State Low OVRN OV = Reg - 1V, Equiv. R to Reg 4 8 16 k OV Latch State High OVRP OV = 1V, Equiv. R to Gnd 4 8 16 k OV Hi Impedance Pull-up OVHI OV = 1V, IDD = 10mA 0.3 1 µA OV Unlatch Threshold VDDUL VDD dropped until latch fails 4.75 5 5.25 V Min Typ Max Unit Output Parameter Max. "Off State" Voltage Symbol 1.7 V Output Rise Time tr T = 25°C, 10% - 90% 170 250 290 ns Output Fall Time tf T = 25°C, 10% - 90% 140 210 240 ns ASTEC Semiconductor May 2001 VOFF Test Condition IOUT = 100µA Page 6 of 6 DS998 DS998 Rev. A3