AS7C1028 AS7C1028-12 AS7C1028-12JIN - Datasheet Archive
Advance Information AS7C1028 ® 5V 256K X 4 CMOS SRAM (Common I/O) Features · Industrial (-40o to 85oC) temperature
September 2006 Advance Information AS7C1028 AS7C1028 ® 5V 256K X 4 CMOS SRAM (Common I/O) Features · Industrial (-40o to 85oC) temperature · Organization: 262,144 words × 4 bits · High speed · 28-pin JEDEC standard packages - 400 mil SOJ · ESD protection 2000 volts - 12 ns address access time - 6 ns output enable access time · Low power consumption via chip deselect · One chip select plus one Output Enable pin · Bidirectional data inputs and outputs · TTL-compatible Logic block diagram Pin arrangement VCC GND I/O3 262,144 x 4 Array (262,144) Sense amp A0 A1 A2 A3 A4 A5 A6 A7 Address decoder Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C1028 AS7C1028 28 Pin SOJ (400 mil) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE I/O0 A8 A9 Address decoder WE Control circuit OE CE A A A A A A A A 10 11 12 13 14 15 16 17 12/5/06; V.1.0 Alliance Memory P. 1 of 8 Copyright © Alliance Memory. All rights reserved. AS7C1028 AS7C1028 ® Functional description The AS7C1028 AS7C1028 is a 5V high-performance CMOS 1,048,576-bit Static Random-Access Memory (SRAM) device organized as 262,144 words × 4 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance's advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C1028 AS7C1028 is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 0.5 +7.0 V Voltage on any pin relative to GND Vt2 0.5 VCC + 0.5 V Power dissipation PD 1.25 W Storage temperature (plastic) Tstg 55 +125 oC Ambient temperature with VCC applied Tbias 55 +125 o DC current into outputs (low) IOUT 50 C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Notes: H = VIH, L = VIL, x = Don't care. VLC = 0.2V, VHC = VCC - 0.2V. Other inputs VHC or VLC. 12/5/06; V.1.0 Alliance Memory P. 2 of 8 AS7C1028 AS7C1028 ® Recommended operating conditions Parameter Symbol Min Typical Max Unit VCC 4.5 5.0 5.5 V Supply voltage VIH 2.2 VCC+0.5 V VIL(1) -0.5(1) 0.8 V TA Input voltage 40 85 o Ambient operating temperature (Industrial) C Note: 1 VIL min = 1.5V for pulse width less than 10ns, once per cycle. DC operating characteristics (over the operating range)1 AS7C1028-12 AS7C1028-12 Parameter Symbol Test conditions Min Max Unit Input leakage current |ILI| VCC = Max, Vin = GND to VCC 5 µA Output leakage current |ILO| VCC = Max, CS = VIH, VOUT = GND to VCC 5 µA Operating power supply current ICC VCC = Max, CE VIL f = fMax, IOUT = 0mA 170 mA ISB VCC = Max, CE > VIH f = fMax, IOUT = 0mA 40 mA ISB1 VCC = Max, CE > VCC0.2V VIN < GND + 0.2V or VIN > VCC0.2V, f = 0 10 mA VOL IOL = 8 mA, VCC = Min 0.4 V VOH IOH = 4 mA, VCC = Min 2.4 V Standby power supply current Output voltage Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE Vin = 3dV 8 pF I/O capacitance CI/O I/O Vout = 3dV 8 pF Note: This parameter is guaranteed by device characterization, but is not production tested. 12/5/06; V.1.0 Alliance Memory P. 3 of 8 AS7C1028 AS7C1028 ® Read cycle (over the operating range)3,9 AS7C1028-12 AS7C1028-12 Parameter Symbol Min Max Unit Notes Read cycle time tRC 12 ns Address access time tAA 12 ns 3 Chip enable (CE) access time tACE 12 ns 3 Output enable (OE) access time tOE 6 ns Output hold from address change tOH 4 ns 5 CE LOW to output in low Z tCLZ 3 ns 4, 5 CE HIGH to output in high Z tCHZ 0 6 ns 4, 5 OE LOW to output in low Z tOLZ 0 ns 4, 5 OE HIGH to output in high Z tOHZ 0 5 ns 4, 5 Power up time tPU 0 ns 4, 5 Power down time tPD 12 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined output/don't care Read waveform 1 (address controlled)3,6,7,9 tRC Address tOH tAA Dout Data valid Read waveform 2 (CE controlled)3,6,8,9 tRC1 CE tOE OE tOLZ tOHZ tCHZ tACE Dout Data valid tCLZ Supply current 12/5/06; V.1.0 tPU tPD 50% ICC ISB 50% Alliance Memory P. 4 of 8 AS7C1028 AS7C1028 ® Write cycle (over the operating range)11 AS7C1028-12 AS7C1028-12 Parameter Symbol Min Max Unit Write cycle time tWC 12 ns Chip enable to write end tCW 10 ns Address setup to write end tAW 10 Notes ns Address setup time tAS 0 ns Write pulse width tWP 10 ns Write recovery time tWR 0 ns Address hold from end of write tAH 0 ns Data valid to write end tDW 7 ns Data hold time tDH 0 ns 4, 5 Write enable to output in high Z tWZ 0 5 ns 4, 5 Output active from write end tOW 3 ns 4, 5 Shaded areas contain advance information. Write waveform 1 (WE controlled)10,11 tWC tAW tAH tWR Address tWP WE tAS tDW tDH Data valid Din tWZ tOW Dout Write waveform 2 (CE controlled)10,11 tWC tAW tAH tWR Address tAS tCW CE tWP WE tWZ Din tDW tDH Data valid Dout 12/5/06; V.1.0 Alliance Memory P. 5 of 8 AS7C1028 AS7C1028 ® AC test conditions - Output load: see Figure B or Figure C. Input pulse level: GND to VCC. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent 168 Dout +1.72V (5V) VCC +5V 320 480 VCC GND 90% 10% 90% 3 ns 10% Figure A: Input pulse Dout 255 C(13) GND Figure B: Output load Dout 350 C(13) GND Figure C: Output load Notes: 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±200mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C=30pF, except on High Z and Low Z parameters, where C=5pF. 12/5/06; V.1.0 Alliance Memory P. 6 of 8 AS7C1028 AS7C1028 ® Package diagrams 28-pin SOJ 28-pin SOJ 400 mil e 400 mil Min Max in mils D E1 E2 B A A1 Pin 1 b c Seating Plane A2 A A1 A2 B b c D E E1 E2 e 0.132 - 0.105 0.115 0.024 0.032 0.013 0.021 0.720 0.012 0.354 0.378 0.395 0.405 0.430 0.405 0.430 0.440 0.050 BSC E2 Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06; V.1.0 Alliance Memory .0146 0.062 P. 7 of 8 AS7C1028 AS7C1028 ® Ordering information Package Volt/Temp 12 ns 5V industrial Plastic SOJ, 400 mil AS7C1028-12JIN AS7C1028-12JIN Part numbering system AS7C SRAM prefix 1028 XX Device number Access time X Package: J=SOJ 400 mil I X Temperature range: I = -40C to 85C N=Lead Free Part ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 Copyright © Alliance Memory All Rights Reserved Part Number: AS7C1028 AS7C1028 Document Version: v.1.0 www.alliancememory.com © Copyright 2003 Alliance Memory, Inc. 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