AS5SP128K32DQ MS026-D/BHA EIA/JESD51 AS5SP128K32DQ-5IT AS5SP128K32DQ-6IT - Datasheet Archive

 

AS5SP128K32DQ SSRAM Austin Semiconductor, Inc. A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A

 

COTS PEM AS5SP128K32DQ AS5SP128K32DQ SSRAM Austin Semiconductor, Inc. A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A Plastic Encapsulated Microcircuit 4.0Mb, 128K x 32, Synchronous SRAM Symbol tCYC tCD tOE ADSC\ ADSP\ MODE A0-Ax Address Registers Row Decode 81 84 82 83 85 87 86 89 88 91 90 92 93 95 96 94 97 73 9 72 10 71 11 70 12 69 13 68 15 16 65 17 64 18 63 19 62 20 61 VDD ZZ DQa DQa VDDQ 21 60 VSSQ DQd 22 59 DQd DQd 23 58 24 57 DQa DQa DQa DQd VSSQ VDDQ 25 56 DQa 26 55 27 54 DQd DQd NC 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 100Mhz 10.0 5.0 5.0 28 53 29 52 VSSQ VDDQ DQa DQa 30 51 NC 14 67 DQb DQb VSSQ VDDQ DQb DQb VSS NC 50 49 48 47 46 45 44 43 42 41 66 VDDQ VSSQ DQb DQb VDD NC* NC* A A A A A A A 40 39 38 37 36 35 34 33 32 31 SSRAM [SPB] NC DQb DQb Units ns ns ns General Description ASI's AS5SP128K32DQ AS5SP128K32DQ is a 4.0Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 128K x 32. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. Memory Array x36 SBP Synchronous Pipeline Burst Two (2) cycle load One (1) cycle de-select One (1) cycle latency on Mode change Output Register Output Driver ASI's AS5SP128K32DQ AS5SP128K32DQ includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status Cache controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system's burst sequence control block and are controlled by Address Advance (ADV) control input. DQx, DQPx Input Register Column Decode AS5SP128K32DQ AS5SP128K32DQ Revision 1.1 07/29/04 74 8 VDDQ VSSQ I/O Gating and Control BURST CNTL. 75 7 DQd CE3\ ADV 6 NC VSS DQd CE1\ GW\ 76 VDD CLK BWx\ 77 5 DQc NC ZZ CONTROL BLOCK 4 DQc OE\ BWE\ 78 VSSQ VDDQ Block Diagram CE2 79 3 DQc DQc Fast Access Times Parameter Cycle Time Clock Access Time Output Enable Access Time 80 2 DQc DQc Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support Global Write support On-Chip low power mode [powerdown] via ZZ pin Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention. Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package, MS026-D/BHA MS026-D/BHA Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges 1 DQc DQc VDDQ VSSQ MODE A A A A A1 A0 NC* NC* VSS · · · · · · · 98 NC Features · · · · · · · · · · 99 100 Pipeline Burst, Single Cycle Deselect Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 1 COTS PEM AS5SP128K32DQ AS5SP128K32DQ SSRAM Austin Semiconductor, Inc. Pin Description/Assignment Table Signal Name Clock Symbol CLK Type Input Pin Address A0, A1 Input Address A Input(s) Chip Enable Chip Enable Global Write Enable Byte Enables Input Input Input Input Byte Write Enable Output Enable Address Strobe Controller CE1\, CE3\ CE2 GW\ BWa\, BWb\, BWc\, BWd\ BWE\ OE\ ADSC\ 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 98, 92 97 88 93, 94, 95, 96 Input Input Input 87 86 85 Address Strobe from Processor ADSP\ Input 84 Address Advance ADV Input 83 Power-Down ZZ Input 64 Data Input/Outputs DQa, DQb, DQc Input/ Output DQd Burst Mode Power Supply [Core] Ground [Core] Power Supply I/O MODE VDD VSS VDDQ Input Supply Supply Supply I/O Ground VSSQ Supply No Connection(s) NC NA 89 37, 36 Description This input registers the address, data, enables, Global and Byte writes as well as the burst control functions Low order, Synchronous Address Inputs and Burst counter address inputs Synchronous Address Inputs Active Low True Chip Enables Active High True Chip Enable Active Low True Global Write enable. Write to all bits Active Low True Byte Write enables. Write to byte segments Active Low True Byte Write Function enable Active Low True Asynchronous Output enable Address Strobe from Controller. When asserted LOW, Address is captured in the address registers and A0-A1 are loaded into the Burst When ADSP\ and ADSC are both asserted, only ADSP is recognized Synchronous Address Strobe from Processor. When asserted LOW, Address is captured in the Address registers, A0-A1 is registered in the burst counter. When both ADSP\ and ADSC\ or both asserted, only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH Advance input Address. When asserted HIGH, address in burst counter is incremented. Asynchronous, non-time critical Power-down Input control. Places the chip into an ultra low power mode, with data preserved. 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 31 91, 15, 41, 65 90, 17, 40, 67 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 14, 16, 38, 39, 66 38,39,42,43 Bidirectional I/O Data lines. As inputs they reach the memory array via an input register, the address stored in the register on the rising edge of clock. As and output, the line delivers the valid data stored in the array via an output register and output driver. The data delieverd is from the previous clock period of the READ cycle. Interleaved or Linear Burst mode control Core Power Supply Core Power Supply Ground Isolated Input/Output Buffer Supply Isolated Input/Output Buffer Ground No connections to internal silicon Logic Block Diagram A0, A1, Ax ADDRESS REGISTER MODE 2 A0, A1 ADV\ CLK Burst CounterQ1 and CLR Logic Q0 ADSC\ ADSP\ BWd\ BWc\ BWb\ BWa\ BWE\ GW\ CE1\ CE2 CE3\ OE\ Byte Write Register DQd, DQPd Byte Write Driver DQd, DQPd Byte Write Register DQc, DQPc Byte Write Driver DQc, DQPc Byte Write Register DQb, DQPb Byte Write Driver DQb, DQPb Byte Write Register DQa, DQPa Byte Write Driver DQa, DQPa Enable Register Sense Amps Output Registers Output Buffers DQx, DQPx Input Registers Pipeline Enable Sleep Control ZZ AS5SP128K32DQ AS5SP128K32DQ Revision 1.1 07/29/04 Memory Array Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 2 COTS PEM Austin Semiconductor, Inc. AS5SP128K32DQ AS5SP128K32DQ SSRAM cycle READS are supported. Once the READ operation has been completed and deselected by use of the Chip Enable(s) and either Austin Semiconductor's AS5SP128K32DQ AS5SP128K32DQ Synchronous SRAM ADSP\ or ADSC\, its outputs will tri-state immediately. is manufactured to support today's High Performance platforms utilizing the Industries leading Processor elements including those A Single ADSP\ controlled WRITE operation is initiated when of Intel and Motorola. The AS5SP128K32DQ AS5SP128K32DQ supports both of the following conditions are satisfied at the time of Clock Synchronous SRAM READ and WRITE operations as well as (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip Synchronous Burst READ/WRITE operations. All inputs with Enable(s) are asserted ACTIVE. The address presented to the the exception of OE\, MODE and ZZ are synchronous in nature address bus is registered and loaded on CLK HIGH, then and sampled and registered on the rising edge of the devices input presented to the core array. The WRITE controls Global Write, clock (CLK). The type, start and the duration of Burst Mode and Byte Write Enable (GW\, BWE\) as well as the individual operations is controlled by MODE, ADSC\, ADSP\ and ADV as Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are well as the Chip Enable pins CE1\, CE2, and CE3\. All ignored on the first machine cycle. ADSP\ triggered WRITE synchronous accesses including the Burst accesses are enabled via accesses require two (2) machine cycles to complete. If Global the use of the multiple enable pins and wait state insertion is Write is asserted LOW on the second Clock (CLK) rise, the data supported and controlled via the use of the Advance control presented to the array via the Data bus will be written into the array at the corresponding address location specified by the (ADV). Address bus. If GW\ is HIGH (inactive) then BWE\ and one or The ASI AS5SP128K32DQ AS5SP128K32DQ supports both Interleaved as well as more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\) Linear Burst modes therefore making it an architectural fit for controls the write operation. All WRITES that are initiated in this either the Intel or Motorola CISC processor elements available on device are internally self timed. the Market today. A Single ADSC\ controlled WRITE operation is initiated when The AS5SP128K32DQ AS5SP128K32DQ supports Byte WRITE operations and the following conditions are satisfied: [1] ADSC\ is asserted enters this functional mode with the Byte Write Enable (BWE\) LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). asserted (TRUE or Active), and [4] the appropriate combination Global Writes are supported via the Global Write Enable (GW\) of the WRITE inputs (GW\, BWE\, BWx\) are asserted and Global Write Enable will override the Byte Write inputs and (ACTIVE). Thus completing the WRITE to the desired Byte(s) or the complete data-path. ADSC\ triggered WRITE accesses will perform a Write to all Data I/Os. require a single clock (CLK) machine cycle to complete. The The AS5SP128K32DQ AS5SP128K32DQ provides ease of producing very dense address presented to the input Address bus pins at time of clock arrays via the multiple Chip Enable input pins and Tri-state HIGH will be the location that the WRITE occurs. The ADV pin is ignored during this cycle, and the data WRITTEN to the array outputs. will either be a BYTE WRITE or a GLOBAL WRITE depending on the use of the WRITE control functions GW\ and BWE\ as Single Cycle Access Operations well as the individual BYTE CONTOLS (BWx\). A Single READ operation is initiated when all of the following conditions are satisfied at the time of Clock (CLK) HIGH: [1] Deep Power-Down Mode (SLEEP) ADSP\ or ADSC\ is asserted LOW, [2] Chip Enables are all asserted active, and [3] the WRITE signals (GW\, BWE\) are in The AS5SP128K32DQ AS5SP128K32DQ has a Deep Power-Down mode and is their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. controlled by the ZZ pin. The ZZ pin is an Asynchronous input The address presented to the Address inputs is stored within the and asserting this pin places the SSRAM in a deep power-down Address Registers and Address Counter/Advancement Logic and mode (SLEEP). While in this mode, Data integrity is guaranteed. then passed or presented to the array core. The corresponding For the device to be placed successfully into this operational data of the addressed location is propagated to the Output mode the device must be deselected and the Chip Enables, ADSP\ Registers and passed to the data bus on the next rising clock via and ADSC\ remain inactive for the duration of tZZREC after the the Output Buffers. The time at which the data is presented to the ZZ input returns LOW. Use of this deep power-down mode Data bus is as specified by either the Clock to Data valid conserves power and is very useful in multiple memory page specification or the Output Enable to Data Valid spec for the designs where the mode recovery time can be hidden. device speed grade chosen. The only exception occurs when the device is recovering from a deselected to select state where its outputs are tristated in the first machine cycle and controlled by its Output Enable (OE\) on following cycle. Consecutive single Functional Description AS5SP128K32DQ AS5SP128K32DQ Revision 1.1 07/29/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 3 COTS PEM AS5SP128K32DQ AS5SP128K32DQ SSRAM Austin Semiconductor, Inc. Synchronous Truth Tables CE1\ H L L L L L L L X H X H X H X H CE2 X L X L X H H H X X X X X X X X CE3\ X X H X H L L L X X X X X X X X ADSP\ X L L X X L H H H X H X H X H X ADSC\ L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H WT / RD X X X X X X WT RD RD RD WT WT RD RD WT WT CLK Address Accessed NA NA NA NA NA External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address Operation Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst, READ Begin Burst, WRITE Begin Burst, READ Continue Burst, READ Continue Burst, READ Continue Burst, WRITE Continue Burst, WRITE Suspend Burst, READ Suspend Burst, READ Suspend Burst, WRITE Suspend Burst, WRITE Notes: 1. X = Don't Care 2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE Burst Sequence Tables Burst Control Pin [MODE] First Address State HIGH Case 1 A1 A0 0 0 1 1 Fourth Address Burst Control Pin [MODE] First Address State LOW Capacitance Interleaved Burst Case 2 A1 A0 0 0 1 0 0 1 1 1 Case 1 A1 A0 0 0 1 1 Fourth Address 0 1 0 1 Linear Burst Case 2 A1 A0 0 1 1 0 Case 3 A1 Case 4 A0 1 0 1 0 1 1 0 0 A1 0 1 0 1 1 1 0 0 Case 3 A1 A0 1 0 1 0 BW\ H L L L L L X A1 Max. 5.0 5.0 5.0 Units pF pF pF 0 1 0 1 A0 1 0 1 0 1 1 0 0 1 0 0 1 BWd\ X H H H L L X 1 0 1 0 Operation READ READ WRITE Byte [A] WRITE Byte [B] WRITE Byte [C], [D] WRITE ALL Bytes WRITE ALL Bytes Asynchronous Truth Table BWa\ X H L H H L X BWb\ X H H L H L X BWc\ X H H H L L X Operation Power-Down (SLEEP) READ Parameter Voltage on VDD Pin Voltage on VDDQ Pins Voltage on Input Pins Voltage on I/O Pins Power Dissipation Storage Temperature Operating Temperatures [Screening Levels] Symbol VDD VDDQ VIN VIO PD tSTG /CT /IT /ET /XT Min. Max. 4.6 VDD+0.3 V -0.3 VDDQ+0.3 V -65 150 I/O Status High-Z DQ High-Z Din, High-Z High-Z V -0.3 OE\ X L H X X AC Test Loads Units -0.3 ZZ H L L L L WRITE De-Selected Absolute Maximum Ratings* VDD Output V 1.6 0 70 -40 85 -40 105 -55 125 Rt = 50 ohm Zo=50 ohm Diagram [A] W C 30 pF C Vt= Termination Voltage Rt= Termination Resistor C Vt= 1.50v for 3.3v VDDQ Vt= 1.25v for 2.5v VDDQ C C R= 317 ohm@3.3v R= 1667 ohm@2.5v *Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. AS5SP128K32DQ AS5SP128K32DQ Revision 1.1 07/29/04 Symbol CI CIO CCLK Case 4 A0 Write Table GW\ H H H H H H L Parameter Input Capacitance Input/Output Capacitance Clock Input Capacitance Output 3.3/2.5v 5 pF R= 351 ohm@3.3v R= 1538 ohm@2.5v Diagram [B] Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 4 COTS PEM AS5SP128K32DQ AS5SP128K32DQ SSRAM Austin Semiconductor, Inc. DC Electrical Characteristics (VDD=3.3v -5%/+10%, TA= Min. and Max temperatures of Screening level chosen) Symbol VDD VDDQ VoH Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage Test Conditions 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA VoL Output Low Voltage VDD=Min., IOL=8mA VDD=Min., IOL=1mA VIH Input High Voltage VIL Input Low Voltage IIL IZZL IOL IDD Input Leakage (except ZZ) Input Leakage, ZZ pin Output Leakage Operating Current VDD=Max., VIN=VSS to VDD Output Disabled, VOUT=VSSQ to VDDQ Automatic CE. Power-down Current -TTL inputs Automatic CE. Power-down Current - CMOS Inputs Automatic CE. Power-down Current -TTL inputs Automatic CE. Power-down Current - CMOS Inputs ISB4 ISB3 Max 3.630 VDD mA mA mA mA mA 45 mA 95 85 75 65 Notes 1 1,5 1,4 1,4 1,4 1,4 1,2 1,2 1,2 1,2 3 3 mA mA mA mA Max. VDD, Device De-Selected, 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz 10 ns Cycle, 100 Mhz VIN>/=VIH or VIN/=VIH or VIN