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ARM9TDMI LDM bug

Catalog Datasheet MFG & Type PDF Document Tags

ARM922T

Abstract: ARM920T instruction mov add .2.1 LDM of user mode registers (ARM9TDMI­8)-Category 2 ARM9 Bug tracking database entry : CPC00_CAM_000013 Summary Under specific conditions, a LDM to user mode registers will not operate correctly. These instructions take the form: LDM{} ,^ These instructions , destination is the PC (ARM9TDMI­1)-Category 3 ARM9 Bug tracking database entry : CPC00_CAM , not read-sensitive are cached. A.1.2 Error Response-Category 2 There is a bug in the ERROR
Altera
Original
ARM922T ARM920T instruction mov add ARM920T ARM9TDMI LDM bug INCR16 800-EPLD

100C

Abstract: 101C ARM922T Processor Core A.3.1 LDM of user mode registers (ARM9TDMI­8)-Category 2 ARM9 Bug tracking database entry : CPC00_CAM_000013 Summary Under specific conditions, a LDM to user mode registers will , Response-Category 2 There is a bug in the ERROR response functionality in the wrapper. An ERROR response should , instructions which fall into this category are as follows: I ARM instructions: LDM, STM, SWP, SWPB, LDC , observed in devices based on the ARM9TDMI (for example the ARM9TDMI, ARM920T, and ARM922T cores) only. It
Altera
Original
100C 101C 201C ARM946E-S ARM966E-S EPXA10

CPC00

Abstract: 100C ARM922T Processor Core A.3.1 LDM of user mode registers (ARM9TDMI­8)-Category 2 ARM9 Bug tracking database entry : CPC00_CAM_000013 Summary Under specific conditions, a LDM to user mode registers will , Response-Category 2 There is a bug in the ERROR response functionality in the wrapper. An ERROR response should , instructions which fall into this category are as follows: ARM instructions: LDM, STM, SWP, SWPB, LDC , observed in devices based on the ARM9TDMI (for example the ARM9TDMI, ARM920T, and ARM922T cores) only. It
Altera
Original

200-CIE

Abstract: registers (ARM9TDMI­8)-Category 2 ARM9 Bug tracking database entry : CPC00_CAM_000013 Summary Under , the PC (ARM9TDMI­1)-Category 3 ARM9 Bug tracking database entry : CPC00_CAM_000001 Summary A , There is a bug in the ERROR response functionality in the wrapper. An ERROR response should only be , follows: I ARM instructions: LDM, STM, SWP, SWPB, LDC, STC, LDRD, STRD, MCRR, MRRC. I Thumb instructions , is conditional. Conditions This has been observed in devices based on the ARM9TDMI (for example
Altera
Original
200-CIE

ARM9TDMI

Abstract: 100C ARM922T Processor Core A.3.1 LDM of user mode registers (ARM9TDMI­8)-Category 2 ARM9 Bug tracking database entry : CPC00_CAM_000013 Summary Under specific conditions, a LDM to user mode registers will , Response-Category 2 There is a bug in the ERROR response functionality in the wrapper. An ERROR response should , instructions which fall into this category are as follows: ARM instructions: LDM, STM, SWP, SWPB, LDC , observed in devices based on the ARM9TDMI (for example the ARM9TDMI, ARM920T, and ARM922T cores) only. It
Altera
Original
ARM9TDMI R8-R10

100C

Abstract: 101C necessary for recovery. A burst read is generated by an LDM instruction for which more than one destination , Response-Category 2 There is a bug in the ERROR response functionality in the wrapper. An ERROR response should , instructions which fall into this category are as follows: ARM instructions: LDM, STM, SWP, SWPB, LDC
Altera
Original
mrc 501 ES-EPXA10-2
Abstract: recovery. A burst read is generated by an LDM instruction for which more than one destination register is , are cached. A.1.2 Error Response-Category 2 There is a bug in the ERROR response functionality , . The instructions which fall into this category are as follows: I ARM instructions: LDM, STM, SWP, SWPB Altera
Original

Jazelle v1 Architecture Reference Manual

Abstract: ARM11 datasheet "instruction set summary" provide the extra information you need to identify the bug. For example, assume that an application , information around the bug has been captured and not overwritten. Because trace buffer depths are finite , save time by limiting the information that must be analyzed to find the bug. If you are using the ARM
ARM
Original
ARM1136 Jazelle v1 Architecture Reference Manual ARM11 datasheet "instruction set summary" MVAb ARM1136JF-S ARM processor 0211C