ARM966E-S 0213C 128KB 256MB 128MB

ARM966E-S ARM966E-S (Rev 2) Technical Reference Manual Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C ARM966E-S ARM966E-S Technical Reference Manual Copyright © 2000, 2002 ARM Limited. All rights reserved. Release Information Change history Date Issue Change July 2000 A First release January 2002 B Second release February 2002 C Third release Proprietary Notice Words and logos marked with ® or TM are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Confidentiality Status This document is Open Access. This document has no restriction on distribution. Product Status The information in this document is final (information on a developed product). Web Address http://www.arm.com ii Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Contents ARM966E-S ARM966E-S Technical Reference Manual Preface About this document . xii Feedback . xvi Chapter 1 Introduction 1.1 1.2 1.3 Chapter 2 Programmer's Model 2.1 2.2 2.3 Chapter 3 About the ARM966E-S ARM966E-S memory map . 3-2 Tightly-coupled memory address space . 3-3 Bufferable write address space . 3-4 Tightly-Coupled Memory Interface 4.1 4.2 ARM DDI 0213C 0213C About the programmer's model . 2-2 About the ARM9E-S programmer's model . 2-3 ARM966E-S ARM966E-S CP15 registers . 2-4 Memory Map 3.1 3.2 3.3 Chapter 4 About the ARM966E-S ARM966E-S macrocell . 1-2 Microprocessor block diagram . 1-3 Silicon revision information . 1-4 About ARM966E-S ARM966E-S macrocell tightly-coupled memory interface . 4-2 Enabling TCM . 4-5 Copyright © 2000, 2002 ARM Limited. All rights reserved. iii Contents 4.3 4.4 4.5 4.6 Chapter 5 Bus Interface Unit 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Chapter 6 About the ETM interface . 8-2 Enabling the ETM interface . 8-3 ARM966E-S ARM966E-S trace support features . 8-4 Test Support 9.1 9.2 9.3 iv About the debug interface . 7-2 Debug systems . 7-4 ARM966E-S ARM966E-S scan chain 15 . 7-7 Debug interface signals . 7-9 ARM9E-S core clock domains . 7-14 Determining the core and system state . 7-15 About the EmbeddedICE-RT . 7-16 Disabling EmbeddedICE-RT . 7-18 The debug communications channel . 7-19 Monitor mode debug . 7-23 Debug additional reading . 7-25 Embedded Trace Macrocell Interface 8.1 8.2 8.3 Chapter 9 About the coprocessor interface . 6-2 Coprocessor interface signals . 6-3 LDC/STC . 6-10 MCR/MRC . 6-12 Interlocked MCR . 6-13 CDP . 6-14 Privileged instructions . 6-15 Busy-waiting and interrupts . 6-16 Debug Support 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 Chapter 8 About the BIU . 5-2 AHB instruction prefetch buffer . 5-3 AHB write buffer . 5-6 AHB bus master interface . 5-9 AHB transfer descriptions . 5-10 AHB clocking . 5-15 CLK to HCLK skew . 5-17 Coprocessor Interface 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Chapter 7 TCM interface write buffers . 4-8 Tightly-coupled memory error detection signals . 4-9 Interface operation . 4-10 TCM implementation examples . 4-14 About the ARM966E-S ARM966E-S test methodology . 9-2 Scan insertion and ATPG . 9-3 BIST of tightly-coupled memory . 9-5 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Contents Appendix A Signal Descriptions A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 Appendix B Signal properties and requirements . A-2 Clock interface signals . A-3 AHB signals . A-4 TCM interface signals . A-6 Coprocessor interface signals . A-10 Debug signals . A-12 Miscellaneous signals . A-15 ETM interface signals . A-16 Test wrapper signals . A-18 AC Parameters B.1 Timing diagrams and timing parameters . B-2 Glossary ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. v Contents vi Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C List of Tables ARM966E-S ARM966E-S Technical Reference Manual Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 4-1 Table 6-1 Table 6-2 Table 7-1 Table 7-2 Table 7-3 Table 9-1 Table 9-2 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 ARM DDI 0213C 0213C Change history . ii CP15 register map . 2-4 Register 0, ID code . 2-5 Register 0, TCM size register . 2-6 Register 1, Control register bit definitions . 2-6 Register 13, Trace process identifier . 2-10 Register 15, Test register map . 2-10 Configuration control register . 2-11 BIST control register . 2-13 BIST size encoding examples . 2-14 TCM sizes . 4-3 Coprocessor interface signals . 6-3 Handshake encoding . 6-7 Scan chain 15 addressing mode bit order . 7-7 Mapping of scan chain 15 address field to CP15 registers . 7-7 Coprocessor 14 register map . 7-19 Instruction BIST address and general registers . 9-8 Data BIST address and general registers . 9-9 Clock interface signals . A-3 AHB signals . A-4 Data TCM interface signals . A-6 Instruction TCM interface signals . A-8 Coprocessor interface signals . A-10 Copyright © 2000, 2002 ARM Limited. All rights reserved. vii List of Tables Table A-6 Table A-7 Table A-8 Table A-9 Table B-1 Table B-2 Table B-3 Table B-4 Table B-5 Table B-6 Table B-7 Table B-8 Table B-9 Table B-10 viii Debug signals . A-12 Miscellaneous signals . A-15 ETM interface signals . A-16 Test wrapper signals . A-18 Clock, reset and AHB enable parameters . B-3 AHB bus master timing parameters . B-5 Coprocessor interface parameters . B-7 Debug interface parameters . B-9 JTAG interface parameters . B-11 Exception and configuration parameters . B-12 AHB bus request and grant-related parameters . B-13 INTEST wrapper . B-15 ETM parameters . B-17 TCM parameters . B-19 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C List of Figures ARM966E-S ARM966E-S Technical Reference Manual Figure 1-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 ARM DDI 0213C 0213C Key to timing diagram conventions . xiv ARM966E-S ARM966E-S block diagram . 1-3 ARM966E-S ARM966E-S memory map . 3-2 ITCM aliasing example . 3-3 Single-cycle TCM read/writes . 4-10 Two cycle TCM read/writes . 4-12 DTCM reads with cancels . 4-13 Simplest zero wait state RAM example . 4-14 Byte-banks of RAM example . 4-15 Byte-banks of RAM alternative example . 4-16 Multiple banks of RAM example . 4-17 Sequential RAM example . 4-18 Single or Multiple wait-state RAM example . 4-19 Single port DMA-capable RAM example . 4-20 Dual port RAM example . 4-21 Effect of a nonsequential instruction fetch . 5-4 Nonsequential instruction fetch after a data access . 5-5 Back-to-back data transfer write followed by read . 5-11 Single STM, followed by sequential instruction fetch . 5-12 Data burst crossing a 1KB boundary . 5-13 SWP instruction . 5-14 AHB 3:1 clocking example . 5-15 ARM966E-S ARM966E-S CLK to AHB HCLK sampling . 5-17 Copyright © 2000, 2002 ARM Limited. All rights reserved. ix List of Figures Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 8-1 Figure 9-1 Figure B-1 Figure B-2 Figure B-3 Figure B-4 Figure B-5 Figure B-6 Figure B-7 Figure B-8 Figure B-9 Figure B-10 x Pipeline stages . 6-2 Connecting multiple coprocessors . 6-8 Example handshake logic blocks . 6-9 LDC/STC cycle timing . 6-10 MCR/MRC transfer timing with busy-wait . 6-12 Interlocked MCR/MRC timing with busy-wait . 6-13 Late canceled CDP . 6-14 Privileged instructions . 6-15 Busy-waiting and interrupts . 6-16 Clock synchronization . 7-3 Typical debug system . 7-4 ARM9E-S block diagram . 7-5 Breakpoint timing . 7-10 Watchpoint entry with data processing instruction . 7-11 Watchpoint entry with branch . 7-12 The ARM9E-S, TAP controller, and EmbeddedICE-RT . 7-16 Debug communications channel status register . 7-20 Coprocessor 14 debug status register format . 7-21 ARM966E-S ARM966E-S ETM interface . 8-2 Test flow for BIST . 9-6 Clock, reset and AHB enable timing . B-3 AHB bus master timing . B-4 Coprocessor interface timing . B-6 Debug interface timing . B-8 JTAG interface timing . B-10 Exception and configuration timing . B-12 AHB bus request and grant related timing . B-13 INTEST wrapper timing . B-14 ETM interface timing . B-16 TCM interface timing . B-18 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Preface This preface introduces the ARM966E-S ARM966E-S macrocell and its reference documentation. It contains the following sections: · About this document on page xii · Feedback on page xvi. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. xi Preface About this document This document is a reference manual for the ARM966E-S ARM966E-S (Rev 2) macrocell. Intended audience This document has been written for experienced hardware and software engineers. Using this manual This document is organized into the following chapters: Chapter 1 Introduction Read this chapter for an introduction to the ARM966E-S ARM966E-S macrocell. Chapter 2 Programmer's Model Read this chapter for a description of the programmer's model including a summary of the ARM966E-S ARM966E-S macrocell coprocessor registers. Chapter 3 Memory Map Read this chapter for a description of the ARM966E-S ARM966E-S fixed memory map implementation. Chapter 4 Tightly-Coupled Memory Interface Read this chapter for a description of the requirements and operation of the tightly-coupled memory. Chapter 5 Bus Interface Unit Read this chapter for a description of the operation of the Bus Interface Unit (BIU) and write buffer. Chapter 6 Coprocessor Interface Read this chapter for a description of the coprocessor interface and the operation of common coprocessor instructions. Chapter 7 Debug Support Read this chapter for a description of the debug support for the ARM966E-S ARM966E-S macrocell and the EmbeddedICE-RT logic. Chapter 8 Embedded Trace Macrocell Interface Read this chapter for a description of the ETM interface, including details of how to enable the interface. xii Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Preface Chapter 9 Test Support Read this chapter for a description of the test methodology used for the ARM966E-S ARM966E-S synthesized logic and tightly-coupled memory. Appendix A Signal Descriptions Read this appendix for a description of the ARM966E-S ARM966E-S signals. Appendix B AC Parameters Read this appendix for a description of the timing parameters applicable to the ARM966E-S ARM966E-S macrocell. Typographical conventions The following typographical conventions are used in this document: italic Highlights special terminology, cross-references, and citations. bold Highlights ARM processor signal names, and interface elements such as menu names. Also used for terms in descriptive lists, where appropriate. monospace Denotes text that can be entered at the keyboard, such as commands, file names and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. The underlined text can be entered instead of the full command or option name. monospace italic Denotes arguments to commands or functions where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. xiii Preface Timing diagram conventions This manual contains several timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur. Therefore, no additional meaning should be attached unless specifically stated. Clock HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Valid (correct) sampling point Key to timing diagram conventions Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. xiv Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Preface Further reading This section lists publications by ARM Limited, and by third parties. If you would like further information on ARM products, or if you have questions not answered by this document, please contact info@arm.com or visit our web site at http://www.arm.com. ARM publications This document contains information that is specific to the ARM966E-S ARM966E-S macrocell. Refer to the following documents for other relevant information: · ARM Architecture Reference Manual (ARM DDI 0100) · ARM9E-S (Rev 2.0) Technical Reference Manual (ARM DDI 0240) · AMBA Specification (Rev 2.0) (ARM IHI 0011) · ARM966E-S ARM966E-S (Rev 2) Implementation Guide (ARM DII 0025) · AHB Example AMBA SYstem Technical Reference Manual (ARM DDI 0170) · ETM Technical Reference Manual (ARM DDI 0157). Other publications This section lists relevant documents published by third parties: · ARM DDI 0213C 0213C IEEE Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture. Copyright © 2000, 2002 ARM Limited. All rights reserved. xv Preface Feedback ARM Limited welcomes feedback both on the ARM966E-S ARM966E-S macrocell, and on the documentation. Feedback on the ARM966E-S ARM966E-S macrocell If you have any comments or suggestions about this product, please contact your supplier giving: · the product name · a concise explanation of your comments. Feedback on the documentation If you have any comments about this document, please send email to errata@arm.com giving: · the document title · the document number · the page number(s) to which your comments refer · a concise explanation of your comments. General suggestions for additions and improvements are also welcome. xvi Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Chapter 1 Introduction This chapter introduces the ARM966E-S ARM966E-S macrocell. It contains the following sections: · About the ARM966E-S ARM966E-S macrocell on page 1-2 · Microprocessor block diagram on page 1-3 · Silicon revision information on page 1-4. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 1-1 Introduction 1.1 About the ARM966E-S ARM966E-S macrocell The ARM966E-S ARM966E-S macrocell is a synthesizable macrocell with Tightly-Coupled Memory (TCM) interfaces. It is a member of the ARM9 Thumb family of high-performance, 32-bit System-on-Chip (SoC) processor solutions and is targeted at a wide range of embedded applications where high performance, low system cost, small die size, and low power are all important. The ARM966E-S ARM966E-S processor macrocell provides a high-performance processor subsystem, including an ARM9E-S RISC integer CPU, tightly-coupled data and instruction memory interfaces, write buffer and an AMBA AHB bus interface. Providing this complete high-frequency subsystem frees the SoC designer to concentrate on design issues unique to their system. The synthesizable nature of the device eases integration into ASIC technologies. The TCM interfaces of the ARM966E-S ARM966E-S macrocell enable high-speed operation without incurring the performance and power penalties of accessing the system bus, while having a lower area overhead than a cached memory system. The size of both the instruction and data TCM are implementer-configurable to enable tailoring of the hardware to the embedded application. The ARM9E-S core within the ARM966E-S ARM966E-S macrocell executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing trade off between high performance and high code density. Additionally the ARM9E-S core features: · ARMv5TE 32-bit instruction set with improved ARM/Thumb code interworking and enhanced multiplier designed for improved DSP performance · ARM debug architecture with additional support for real-time debug, which allows critical exception handlers to execute while debugging the system. The ARM966E-S ARM966E-S macrocell includes support for external coprocessors allowing floating point or other application-specific hardware acceleration to be added. To minimize die size and power consumption the ARM966E-S ARM966E-S macrocell does not provide virtual to physical address mapping as this is not required by most embedded systems. A simple fixed memory map is implemented for the local TCM, ideally suited to small, fast, real-time embedded control applications. The ARM966E-S ARM966E-S macrocell synthesizable implementation supports the use of a scan test methodology for the standard cell logic and Built-In-Self-Test (BIST) for the tightly-coupled memory. 1-2 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Introduction 1.2 Microprocessor block diagram The ARM966E-S ARM966E-S macrocell block diagram is shown in Figure 1-1. Figure 1-1 ARM966E-S ARM966E-S block diagram ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 1-3 Introduction 1.3 Silicon revision information This manual is for Revision 2 of the ARM966E-S ARM966E-S macrocell. Register 0, ID code on page 2-5 provides details of the revision number. Differences from Rev 1 are: · The ARM966E-S ARM966E-S macrocell can detect unaligned memory accesses and generate a Data Abort to the core. Refer to Chapter 2 Programmer's Model, Register 1, Control register on page 2-6 for programmer's model changes. · Tightly-coupled memory is external to the ARM966E-S ARM966E-S Rev 2 macrocell. The tightly-coupled memory interface supports wait states. Refer to Chapter 3 Memory Map and Chapter 4 Tightly-Coupled Memory Interface. Tightly-coupled memory error detection support. Refer to Chapter 4 Tightly-Coupled Memory Interface. Refer to Chapter 2 Programmer's Model for Programmer's model changes. · The ARM966E-S ARM966E-S BIU write buffer has changed. The ARM966E-S ARM966E-S BIU includes an instruction prefetch unit. Refer to Chapter 5 Bus Interface Unit. Refer to Chapter 2 Programmer's Model for Programmer's model changes. · Changes to BIST. Refer to BIST of tightly-coupled memory on page 9-5. Refer to Chapter 2 Programmer's Model for Programmer's model changes. Refer to ARM9E-S (Rev 2.0) Technical Reference Manual for details of changes to the ARM9E-S core. 1-4 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Chapter 2 Programmer's Model This chapter describes the programmer's model for the ARM966E-S ARM966E-S macrocell. It contains the following sections: · About the programmer's model on page 2-2 · About the ARM9E-S programmer's model on page 2-3 · ARM966E-S ARM966E-S CP15 registers on page 2-4. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-1 Programmer's Model 2.1 About the programmer's model The programmer's model for the ARM966E-S ARM966E-S macrocell primarily consists of the ARM9E-S core programmer's model (see About the ARM9E-S programmer's model on page 2-3). Additions to this model are required to control the operation of the ARM966E-S ARM966E-S macrocell internal coprocessors, and any coprocessor connected to the external coprocessor interface. There are two internal coprocessors within the ARM966E-S ARM966E-S macrocell: · CP14 within the ARM9E-S core enables software access to the debug communications channel · CP15 enables configuration of the Tightly-Coupled Memory (TCM) and write buffer and other ARM966E-S ARM966E-S system options such as big-endian or little-endian operation. The registers defined in CP14 are accessible with MCR and MRC instructions. These are described in The debug communications channel on page 7-19. The registers defined in CP15 are accessible with MCR and MRC instructions. These are described in ARM966E-S ARM966E-S CP15 registers on page 2-4. Any coprocessors registers and operations, attached to the external coprocessor interface, are accessible with appropriate coprocessor instructions. 2-2 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Programmer's Model 2.2 About the ARM9E-S programmer's model The ARM9E-S processor core implements the ARM architecture v5TE, that includes the 32-bit ARM instruction set and the 16-bit Thumb instruction set. For a description of both instruction sets, see the ARM Architecture Reference Manual. 2.2.1 Data Abort model The ARM9E-S core implements the base restored data abort model, that differs from the base updated data abort model implemented by ARM7TDMI. The difference in the Data Abort model affects only a very small section of operating system code, the Data Abort handler. It does not affect user code. With the base restored data abort model, when a Data Abort exception occurs during the execution of a memory access instruction, the base register is always restored by the processor hardware to the value the register contained before the instruction was executed. This removes the requirement for the Data Abort handler to unwind any base register update that might have been specified by the aborted instruction. The base restored data abort model significantly simplifies the software Data Abort handler. 2.2.2 ARM966E-S ARM966E-S macrocell abort sources Data Aborts can be generated from the following sources: · Data transactions to the AHB memory space that return an AHB ERROR response (except for buffered writes). · Data TCM reads for which the DTCMERROR input is asserted. · Instruction TCM data reads for which the ITCMERROR input is asserted. · Unaligned data accesses whenever data alignment checking is enabled. Prefetch aborts can be generated from the following sources (if the instruction fetched is executed): · Instruction fetches from the AHB memory space that return an AHB ERROR response. · Instruction fetches from the instruction TCM for which the ITCMERROR input is asserted. Executing a BKPT instruction causes the prefetch abort exception to be entered. Refer to the ARM Architecture Reference Manual for further information. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-3 Programmer's Model 2.3 ARM966E-S ARM966E-S CP15 registers CP15 allows configuration of the tightly-coupled memory and write buffer and other ARM966E-S ARM966E-S system options such as big-endian or little-endian operation. The ARM966E-S ARM966E-S coprocessor 15 registers are described in the following sections: · CP15 register map summary · Register 0, ID code on page 2-5 · Register 0, TCM size register on page 2-5 · Register 1, Control register on page 2-6 · Register 7, Core control on page 2-9 · Register 13, Trace process identifier on page 2-10 · Register 15, Test and configuration on page 2-10. 2.3.1 CP15 register map summary The ARM966E-S ARM966E-S macrocell incorporates CP15 for system control. The register map for CP15 is shown in Table 2-1. Table 2-1 CP15 register map Function Register Read 0 ID code Unpredictable 0 Tightly coupled memory size Unpredictable 1 Control Control 2-6 Unpredictable Unpredictable 7 Unpredictable Core control 8-12 Unpredictable Unpredictable 13 Trace process identifier Trace process identifier 14 Unpredictable Unpredictable 15 2-4 Write Test Test Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Programmer's Model Note Register 0 and register 15 provide access to more than one register. The register access depends on the value of the opcode_2 field. See the register descriptions in this section for more information. 2.3.2 Register 0, ID code This is a read-only register that returns a 32-bit device ID code. The ID code register is accessed by reading CP15 register 0 with the opcode_2 field set to any value other than 2. For example: MRC p15, 0, rd, c0, c0, {0, 1, 3-7}; returns ID register The contents of the ID code are shown in Table 2-2. Table 2-2 Register 0, ID code Register bits Value [31:24] Implementer 0x41 [23:20} Variant (specification) 0x2 [19:16] ARM architecture v5TE 0x05 [15:4] Part number 0x966 [3:0] 2.3.3 Function Silicon revision number Silicon revision specific Register 0, TCM size register This is a read-only register that returns the size of the tightly coupled instruction and data memories attached to the ARM966E-S ARM966E-S macrocell. Reading CP15 register 0 with the opcode_2 field set to 2 accesses the TCM size register. For example: MRC p15, 0, rd, c0, c0, 2; returns tightly coupled memory size register ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-5 Programmer's Model The contents of the TCM size register are shown in Table 2-3. Table 2-3 Register 0, TCM size register Register bits Function Value [31:23] Reserved b000000000 [22:18} Data TCM size Implementation specific [17:15] Reserved b000 14 Data TCM absent Implementation specific [13:11] Reserved b000 [10:6] Instruction TCM size Implementation specific [5:3] Reserved b000 2 Instruction TCM absent Implementation specific [1:0] Reserved b00 The memory size parameters take the values shown in TCM interface signals on page A-6. If TCM size is set to zero, the TCM absent bit is set to 1. 2.3.4 Register 1, Control register This register contains the global control bits of the ARM966E-S ARM966E-S macrocell (see Table 2-4). All reserved bits must either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. To read and write this register: MRC p15, 0, rd, c1, c0, 0; read Control register MCR p15, 0, rd, c1, c0, 0; write Control register Table 2-4 Register 1, Control register bit definitions Register bit Reset value [31:16] Reserved (should be zero) - 15 Configure disable loading TBIT Zero 14 Reserved (should be zero) - 13 2-6 Function Alternate vector select Value of VINITHI Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Programmer's Model Table 2-4 Register 1, Control register bit definitions (continued) Register bit Function Reset value 12 Instruction TCM enable Value of INITRAM [11:8] Reserved (should be one) - 7 Endianness Zero [6:4] Reserved (should be one) - 3 BIU write buffer enable Zero 2 Data TCM enable Value of INITRAM 1 Alignment fault check enable Zero 0 Reserved (should be zero) - Bit 15, Configure disable loading TBIT When HIGH, the ability to change from ARM to Thumb state by loading data to the PC is disabled. This bit is cleared LOW during reset to provide ARMv5TE compatibility. Bit 13, Alternate vector select This bit controls the base address used for the exception vectors. When LOW, the base address for the exception vectors is 0x0000 0000. When HIGH, the base address is 0xFFFF 0000. Note Bit 13 is initialized either HIGH or LOW during system reset, depending on the value of the input pin, VINITHI. This allows the exception vector location to be defined during reset to suit the boot mechanism of the application. You can then reprogram as required following system reset. Bit 12, Instruction TCM enable This bit controls the behavior of the tightly-coupled instruction TCM interface. When HIGH, all accesses to the fixed instruction memory space as shown in Figure 3-1 on page 3-2, access the instruction TCM interface. When LOW, all accesses to the instruction memory space access the AMBA AHB. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-7 Programmer's Model Note Bit 12 is initialized either HIGH or LOW during system reset depending on the value of the input pin INITRAM. Bit 7, Endianness Selects the endian configuration of the ARM966E-S ARM966E-S macrocell. When this bit is HIGH, big-endian configuration is selected. When LOW, little-endian configuration is selected. This bit is cleared LOW during reset. For further information on endianness refer to the ARM Architecture Reference Manual. Bit 3, Write buffer enable This bit controls the use of the write buffer. When HIGH, all stores to the fixed bufferable space of the AMBA AHB (as shown in Figure 3-2 on page 3-3) are treated as buffered writes. When LOW, all stores to the AMBA AHB are treated as nonbufferable. If the write buffer is disabled having previously been enabled, any writes already in the write buffer FIFO complete as buffered writes. This bit is cleared LOW during reset. Bit 2, Data TCM enable This bit controls the behavior of the tightly-coupled Data TCM interface. When HIGH, all data interface accesses to the fixed data memory space as shown in Figure 3-1 on page 3-2, access the Data TCM interface. When LOW, all accesses to the data memory space access the AMBA AHB. Note Bit 2 is initialized either HIGH or LOW during system reset depending on the value of the input pin INITRAM. Bit 1. Alignment checking enable This bit controls the generation of data aborts for unaligned data accesses. When HIGH, data accesses to addresses that are not aligned to the transfer size generate a data abort. When LOW, data aborts will not be generated for unaligned accesses. This bit is cleared LOW at reset. 2-8 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Programmer's Model 2.3.5 Register 7, Core control You can use a write to this register, to perform wait for interrupt and drain write buffer operations. Wait for interrupt This operation allows the ARM966E-S ARM966E-S macrocell to enter a low-power standby mode. When the operation is invoked, the clock enable to the processor core is negated until either an interrupt or a debug request occurs. This function is invoked by a write to Register 7. The following ARM instruction causes this to occur: MCR p15, 0, rd, c7, c0, 4; wait for interrupt This is the preferred encoding that must be used by new software. For compatibility with existing software, ARM966E-S ARM966E-S macrocell also supports the following ARM instruction that has the same affect: MCR p15, 0, rd, c15, c8, 2; wait for interrupt This stalls the processor from the time that the instruction is executed until nFIQ, nIRQ, or EDBGRQ are asserted. Also, if the debugger sets the debug request bit in the EmbeddedICE-RT control register then this causes the wait-for-interrupt condition to terminate. In the case of nFIQ and nIRQ, the processor core is woken up regardless of whether the interrupts are enabled or disabled (that is, independent of the I and F bits in the processor CPSR). The debug-related waking only occurs if DBGEN is HIGH, that is, only when debug is enabled. If interrupts are enabled, the ARM9E-S core is guaranteed to take the interrupt before executing the instruction after the wait for interrupt. If debug request is used to wake up the system, the processor enters debug-state before executing any more instructions. Wait for interrupt does not prevent the write buffer from emptying. Drain write buffers This CP15 operation causes instruction execution to be stalled until the AHB and TCM write buffers are emptied. This operation is useful in real-time applications where the processor has to be sure that a write to a peripheral has completed before program execution continues. An example is where a peripheral in a bufferable region is the source of an interrupt. When the interrupt has been serviced, the request must be removed before interrupts can be re-enabled. This can be ensured if a drain write buffer operation separates the store to the peripheral and the enable interrupt functions. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-9 Programmer's Model The drain write buffer operation is invoked by a write to Register 7 using the following ARM instruction: MCR p15, 0, rd, c7, c10, 4; drain write buffer Note This stalls the processor core until any outstanding accesses in the write buffers have been completed, that is, until all data has been written to memory. 2.3.6 Register 13, Trace process identifier This register provides a mechanism to enable the Real-time Trace tools to identify the currently executing process in multi-tasking environments. The contents of this register are replicated on the ETMPROCID pins of the ARM966E-S ARM966E-S macrocell. The ETMPROCIDWR signal is set HIGH for a single clock cycle whenever this register is written to. Table 2-5 shows the trace process identifier for read and write. Table 2-5 Register 13, Trace process identifier Register Write Trace process identifier 2.3.7 Read MRC p15,0,Rd,c13, {c0 - c15} MCR p15,0,Rd,c13, {c0 - c15} Register 15, Test and configuration This register provides access to: · the Instruction and Data TCM test features · the configuration control features. The register map for CP15 register 15 is shown in Table 2-6. Table 2-6 Register 15, Test register map Register Read Write Configuration control register MRC p15, 1, Rd, c15, c1, 0 MCR p15, 1, Rd, c15, c1, 0 BIST control register MRC p15, 1, Rd, c15, c1, 1 MCR p15, 1, Rd, c15, c1, 1 Instruction BIST address register MRC p15, 1, Rd, c15, c1, 2 MCR p15, 1, Rd, c15, c1, 2 2-10 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Programmer's Model Table 2-6 Register 15, Test register map (continued) Register Read Write Instruction BIST general register MRC p15, 1, Rd, c15, c1, 3 MCR p15, 1, Rd, c15, c1, 3 Data BIST address register MRC p15, 1, Rd, c15, c1, 6 MCR p15, 1, Rd, c15, c1, 6 Data BIST general register MRC p15, 1, Rd, c15, c1, 7 MCR p15, 1, Rd, c15, c1, 7 Note Opcode_1 is set HIGH when accessing Register 15. Opcode_2 is used to index registers within the Register 15 register map. 2.3.8 Configuration control register The configuration control register allows modification of the default behavior of the ARM966E-S ARM966E-S macrocell (Rev 2). This might be necessary in situations where the behavior of previous revisions of the ARM966E-S ARM966E-S macrocell is required, or where particular features are not compatible with a system design. Table 2-7 shows the bit values and meanings of the configuration control register. Table 2-7 Configuration control register Register bit [31:19] Reserved (should be zero) [15:3] Reserved (should be zero) 18 Instruction TCM order 17 Data TCM order 16 AHB instruction prefetch buffer disable 2 nFIQ mask during FIFOFULL 1 nIRQ mask during FIFOFULL 0 ARM DDI 0213C 0213C Content Reserved (should be zero) Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-11 Programmer's Model Bit 18 Instruction TCM order When HIGH, this bit ensures that read and write accesses over the Instruction TCM interface are performed in the order generated by the ARM9E-S core. This ensures that writes are committed to the memory before any subsequent read. The core is stalled for any TCM read access that occurs while the TCM write buffer is not empty. If this bit is asserted while data is still in the buffer, any subsequent access to the TCM is stalled until the buffer is empty.At reset this bit is cleared LOW. Bit 17 Data TCM order When HIGH, this bit ensures that read and write accesses over the Data TCM interface are performed in the order generated by the ARM9E-S core. This ensures that writes are committed to the memory before any subsequent read. The core is stalled for any TCM read access that occurs while the TCM write buffer is not empty. If this bit is asserted while data is still in the buffer, any subsequent access to the TCM is stalled until the buffer is empty. At reset this bit is cleared LOW. Bit 16, AHB instruction prefetch buffer disabled When HIGH, this bit disables the AHB instruction prefetch buffer. All instruction accesses to the AHB are performed as nonsequential transfers as required by the ARM9E-S core. This results in a number of idle cycles between each access. At reset this bit is cleared to enable instruction prefetching. See AHB instruction prefetch buffer on page 5-3 Bit 2, nFIQ mask during FIFOFULL When HIGH, this bit prevents the assertion of nFIQ from re-enabling the ARM966E-S ARM966E-S macrocell clocks for interrupt servicing if FIFOFULL is asserted. When LOW, the assertion of nFIQ re-enables the core clocks until the interrupt has been serviced.When the core exits FIQ mode, the clocks are disabled. At reset this bit is cleared to allow servicing of nFIQ while the ETM FIFO is full. 2-12 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Programmer's Model Bit 1, nIRQ mask during FIFOFULL When HIGH, this bit prevents the assertion of nIRQ from re-enabling the ARM966E-S ARM966E-S macrocell clocks for interrupt servicing if FIFOFULL is asserted. When LOW, the assertion of nIRQ re-enables the core clocks until the interrupt has been serviced When the core exits IRQ mode, the clocks are disabled. At reset this bit is cleared to allow servicing of nIRQ while the ETM FIFO is full. 2.3.9 BIST control register Table 2-8 shows the bit assignments within the BIST control register. Note If the ARM966E-S ARM966E-S BIST hardware is not present, the relevant BIST size field is always read back as all zeros. Table 2-8 BIST control register Register bit Meaning when written Meaning when read [31:21] Instruction TCM BIST size Instruction TCM BIST size 20 Reserved (should be zero) Instruction TCM BIST complete flag 19 Reserved (should be zero) Instruction TCM BIST fail flag 18 Instruction TCM BIST enable Instruction TCM BIST enable 17 Instruction TCM BIST pause Instruction TCM BIST pause 16 Instruction TCM BIST start strobe Instruction TCM BIST running flag [15:5] Data TCM BIST size Data TCM BIST size 4 Reserved (should be zero) Data TCM BIST complete flag 3 Reserved (should be zero) Data TCM BIST fail flag 2 Data TCM BIST enable Data TCM BIST enable 1 Data TCM BIST pause Data TCM BIST pause 0 Data TCM BIST start strobe Data TCM BIST running flag ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-13 Programmer's Model At reset, all bits are cleared LOW except for the BIST size fields. BIST must be enabled before a BIST operation is started. When BIST is enabled to test one or both tightly-coupled memories, the TCM being tested is automatically disabled by clearing its enable bit in CP15 Register 1. This is to prevent the programmer inadvertently using the TCM following a BIST operation, because the BIST algorithm corrupts the TCM contents. The BIST size field determines the size of the BIST operation. The value written to this field N, is decoded as follows: BIST size in bytes = 2N+2 Some examples are shown in Table 2-9. Table 2-9 BIST size encoding examples Instruction RAM BIST size [31:21] N Size of test b000000 00001 (minimum) 1 8 bytes b000000 00100 4 64 bytes b000000 00111 7 512 bytes b000000 01000 8 1KB b000000 01010 10 4KB b000000 01111 15 128KB 128KB b000000 11000 (maximum) 24 64MB Note BIST size bits [31:26] should be zero. Writing to the BIST control register with bit[0] set initiates a Data TCM BIST operation. Writing to the BIST control register with bit[16] set initiates an Instruction TCM BIST operation. 2-14 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Programmer's Model Running BIST operations You can run Instruction and Data BIST operations individually or concurrently. You must set up the Size, Pause and Enable bits within the BIST control register prior to initiating a BIST operation. Reading the BIST control register returns the status of the BIST operations. See BIST of tightly-coupled memory on page 9-5 for a detailed description of the BIST support and the additional register 15 BIST registers. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 2-15 Programmer's Model 2-16 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Chapter 3 Memory Map This chapter describes the ARM966E-S ARM966E-S macrocell fixed memory map implementation. It contains the following sections: · About the ARM966E-S ARM966E-S memory map on page 3-2 · Tightly-coupled memory address space on page 3-3 · Bufferable write address space on page 3-4. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 3-1 Memory Map 3.1 About the ARM966E-S ARM966E-S memory map The ARM966E-S ARM966E-S macrocell couples Instruction and Data TCM memories of configurable size to the ARM9E-S core. This enables high-speed operation without incurring the performance and power penalties of accessing the system bus. Write buffers are used to decouple the ARM9E-S core from wait states incurred when writing to the AHB bus, and from tightly-coupled memories. To provide simple control over the TCM and AHB write buffer, a fixed memory map is implemented within the ARM966E-S ARM966E-S macrocell. Figure 3-1 illustrates this map. 0xFFFF FFFF 256MB 256MB AHB unbuffered 256MB 256MB AHB buffered 256MB 256MB AHB unbuffered 128MB 128MB AHB buffered 64MB DTCM 64MB ITCM 0xF000 0000 0x2FFF FFFF AMBA AHB 0x2000 0000 0x1FFF FFFF 0x1000 0000 0x0FFF FFFF 0x0800 0x07FF 0x0400 0x03FF 0x0000 0000 FFFF 0000 FFFF 0000 Tightly-coupled memory Figure 3-1 ARM966E-S ARM966E-S memory map 3-2 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Memory Map 3.2 Tightly-coupled memory address space The Tightly-coupled Memory (TCM) is located at the bottom of the memory map. The Instruction TCM (ITCM) and Data TCM (DTCM) are each allocated 64MB address space, the bottom 64MB space mapping to ITCM and the next 64MB range mapping to DTCM. In practice, each TCM is likely to be much smaller than the 64MB allowable and the address decode is implemented so that each memory is aliased throughout its 64MB range. See Figure 3-2 for an example of a 16KB ITCM aliased through the 64MB address space. Figure 3-2 ITCM aliasing example All accesses to addresses above the 128MB 128MB combined TCM address space result in AMBA AHB transfers controlled by the Bus Interface Unit (BIU). An instruction fetch from the ARM9E-S core to the DTCM address space goes to the AHB, regardless of whether the DTCM is enabled. A data interface access from the ARM9E-S core can access both the DTCM and the ITCM. The ability to additionally access the ITCM is required to enable the fetching of inline literals within code, for programming of the instruction ITCM, and for debugging purposes. When a TCM is disabled, all accesses to its address space go to the AHB. When enabled, the TCM must be programmed before use. The tightly-coupled memories can be enabled or disabled during reset depending on the value of the input pin INITRAM. Several boot options are available using INITRAM and the exception vectors location pin VINITHI. These are discussed in Using INITRAM input pin on page 4-5. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 3-3 Memory Map 3.3 Bufferable write address space The use of the ARM966E-S ARM966E-S AHB write buffer is controlled by both the CP15 control register and the fixed address map. When the ARM966E-S ARM966E-S macrocell comes out of reset, the write buffer is disabled by default. All data writes to the AHB are performed as unbuffered. The ARM9E-S core is stalled until the BIU has performed the write on the AHB interface. When the AHB write buffer is enabled by writing to CP15 control register bit 3 (see ARM966E-S ARM966E-S CP15 registers on page 2-4), the data address (DA[31:0]) from the ARM9E-S core controls whether the AHB write buffer is used. If bit 28 of DA is set, the write is treated as un-buffered. If bit 28 is clear, the write is treated as a buffered write and the BIU write buffer FIFO is used. Buffered writes enable the core to continue program execution while the write is performed on the AHB. If the write buffer is full the core is stalled until space becomes available in the FIFO. See AHB write buffer on page 5-6 for details of the BIU and write buffer behavior. Note Writes to tightly-coupled memory address space memories do not get sent to the AHB if the TCM being accessed is enabled (the tightly-coupled memories do not write through to the system memory). If either TCM is disabled and a write is performed to its address space, the write is performed as a buffered AHB write if the write buffer is enabled. If not, the write is unbuffered. 3-4 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Chapter 4 Tightly-Coupled Memory Interface This chapter describes the ARM966E-S ARM966E-S Tightly-Coupled Memory (TCM) interface. It contains the following sections: · About ARM966E-S ARM966E-S macrocell tightly-coupled memory interface on page 4-2 · Enabling TCM on page 4-5 · TCM interface write buffers on page 4-8 · Tightly-coupled memory error detection signals on page 4-9 · Interface operation on page 4-10 · TCM implementation examples on page 4-14. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-1 Tightly-Coupled Memory Interface 4.1 About ARM966E-S ARM966E-S macrocell tightly-coupled memory interface The ARM966E-S ARM966E-S macrocell contains a Tightly-Coupled Memory (TCM) interface allowing separate instruction and data TCMs to be interfaced to the ARM966E-S ARM966E-S macrocell. TCMs are intended for storing real-time code and performance-critical code. The tightly-coupled instruction and data memories are instantiated externally to the ARM966E-S ARM966E-S macrocell providing for flexibility in the design of the memory subsystem. The system designer can select memory type and optimize the memory subsystem for power or speed. The interface supports wait states for multicycle access memory. As well as providing the ability to stall the ARM966E-S ARM966E-S macrocell using the wait signal, the interface indicates if an access is sequential, allowing efficient use of memories that have a different access penalty for sequential and nonsequential accesses.The TCMs are located in the TCM address space. See Chapter 3 Memory Map. There are two mechanisms for controlling the enable of the TCM: · the INITRAM input pin to enable booting from ITCM space. Both external instruction and data memory can be enabled or disabled during reset by the input pin INITRAM MCR software instructions to CP15 to individually enable or disable the instruction · and data TCMs. See Enabling TCM on page 4-5. The data side of the ARM9E-S core is able to access the ITCM. This is necessary to enable code to be loaded into the ITCM and to enable access to constants located in literal pools. Data read accesses to the ITCM are pipelined by a single cycle. The ARM966E-S ARM966E-S macrocell contains a TCM controller that: · schedules requests to the TCM interface · handshakes with the ARM966E-S ARM966E-S memory system controller to acknowledge when requests have been serviced · returns TCM read data back to the ARM9E-S core. The ARM966E-S ARM966E-S macrocell sends all valid TCM requests to the TCM interface. It expects the ITCM and DTCM to service all requests in a single cycle. If the TCMs cannot service a request in a single cycle, the relevant wait signal must be asserted. The TCM controllers use the wait signals to inform the system controller that the memory request has not taken place. The ARM966E-S ARM966E-S macrocell is stalled until the wait signal has been deasserted. Large SRAM arrays are susceptible to errors caused by alpha particle radiation. These errors can result in incorrect data being returned. Parity checking or some form of error detection may be used outside the ARM966E-S ARM966E-S macrocell to detect these errors. See Tightly-coupled memory error detection signals on page 4-9 4-2 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface 4.1.1 TCM size The TCM size can be determined by reading CP15 register 0 with opcode_2 field set to 2. See Register 0, TCM size register on page 2-5. The size values in this register are set by the ITCMSIZE[4:0] and DTCMSIZE[4:0] inputs. The supported sizes are 0 and 2n KB for n = 0 to 16. TCM sizes are configurable in the range 0 bytes to 64Mb as shown in Table 4-1. Table 4-1 TCM sizes Value TCM size b00000 0 bytes b00001 1KB b00010 2KB b00011 4KB b00100 8KB b00101 16KB . . b01011 1MB b01100 2MB b01101 4MB b01110 8MB b01111 16MB b10000 32MB b10001 64MB See TCM interface signals on page A-6. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-3 Tightly-Coupled Memory Interface 4.1.2 TCM interface write buffers To minimize the occurrence of stall cycles and to decouple the processor from memory wait states, there are write buffers in the DTCM and ITCM interfaces. See TCM interface write buffers on page 4-8. 4.1.3 TCM error detection signals There is an error signal on each of the DTCM and ITCM interfaces to support external error detection on the tightly-coupled memories. See Tightly-coupled memory error detection signals on page 4-9. 4-4 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface 4.2 Enabling TCM This section describes how to use the two mechanisms for controlling the enable of the TCM: · Using INITRAM input pin · Using CP15 control register on page 4-6. 4.2.1 Using INITRAM input pin The INITRAM pin is provided to enable the ARM966E-S ARM966E-S macrocell to boot with both external instruction and data memory blocks either enabled or disabled. Two resets are described in the following sections: · Reset with INITRAM LOW · Reset with INITRAM HIGH. Reset with INITRAM LOW If INITRAM is held LOW during reset, the ARM966E-S ARM966E-S macrocell comes out of reset with both external instruction and data memory disabled. All accesses to external instruction and data memory space go to the AHB. The TCMs can then be individually or jointly enabled by writing to the CP15 control register (register 1). Reset with INITRAM HIGH If INITRAM is held HIGH during reset, both external instruction and data memory are enabled when the ARM966E-S ARM966E-S macrocell comes out of reset. This is normally used for a warm reset where the TCM has already been programmed before the application of HRESETn to the ARM966E-S ARM966E-S macrocell. In this case, the TCM contents are preserved and the ARM966E-S ARM966E-S macrocell can run directly from the TCM following reset. Either one or both TCMs can be further disabled or enabled by writing to the CP15 control register. Note If INITRAM is held HIGH during a cold reset (the TCM has not previously been initialized), the VINITHI pin must be set HIGH to ensure that the ARM966E-S ARM966E-S macrocell boots from 0xFFFF 0000, that is in AHB address space and is substantially outside the TCM address space. This is necessary because if VINITHI is LOW, the ARM966E-S ARM966E-S macrocell attempts to boot from 0x0000 0000, and this selects the uninitialized ITCM. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-5 Tightly-Coupled Memory Interface 4.2.2 Using CP15 control register When out of reset, the behavior of the TCM is controlled by the state of CP15 control register. Enabling the ITCM You can enable the ITCM interface by setting bit 12 of the CP15 control register. This register must be accessed in a read-modify-write fashion, to preserve the contents of the bits not being modified. See ARM966E-S ARM966E-S CP15 registers on page 2-4 for details of how to read and write the CP15 control register. When the ITCM interface has been enabled, all future ARM9E-S core instruction fetches and data accesses to the ITCM address space cause the ITCM interface to be accessed as shown in Figure 3-1 on page 3-2. Enabling the ITCM interface greatly increases the performance of the ARM966E-S ARM966E-S macrocell as the majority of accesses to it can be performed with no stall cycles, whereas accessing the AHB might cause several stall cycles for each access.Care must be taken to ensure that the ITCM interface is appropriately initialized before it is enabled and used to supply instructions to the ARM9E-S core. If the core tries to execute instructions from uninitialized ITCM interface, the behavior is unpredictable. Disabling the ITCM You can disable the ITCM interface by clearing bit 12 of the CP15 control register. When the ITCM interface has been disabled, all further ARM9E-S core instruction fetches access the AHB. If the core performs a data access to the ITCM address space as shown in Figure 3-1 on page 3-2, an AHB access is performed. The contents of the memory are preserved when it is disabled. If it is re-enabled, accesses to previously initialized memory locations return the preserved data. Note The TCM write buffers must be drained before disabling the ITCM interface. Enabling the DTCM You can enable the DTCM interface by setting bit 2 of the CP15 control register. See ARM966E-S ARM966E-S CP15 registers on page 2-4 for details of how to read and write this register. When the DTCM interface has been enabled, all future read and write accesses to the DTCM address space, as shown in Figure 3-1 on page 3-2, cause the DTCM interface to be accessed. 4-6 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface Disabling the DTCM You can disable the DTCM by clearing bit 2 of the CP15 control register. When the DTCM is disabled, all further reads and writes to the DTCM address space, as shown in Figure 3-1 on page 3-2, access the AHB. Note The TCM write buffers must be drained before disabling the DTCM interface. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-7 Tightly-Coupled Memory Interface 4.3 TCM interface write buffers Each TCM write buffer is two entries deep. Each entry is an address and data pair. In normal operation, the data for a write access to the TCM address space is held in the write buffer until it is forced out by another write to the TCM address space or by natural drain when there are no read requests to the TCM address space. Write accesses from the core always go into the write buffer. Writes are always single-cycle operations if there is space in the write buffer (irrespective of external TCM wait states). If there is no space in the write buffer, any write access stalls the ARM9E-S core until a write buffer entry becomes free. 4.3.1 TCM order bit In normal operation, the write buffer drains naturally into the TCM whenever there are no read accesses to the TCM address space. One effect of this drain mechanism is that read and write accesses to the TCM can be in a different order to that issued by the ARM9ES core. If the write buffer contains the data required by a read access, data is returned from the buffer. Otherwise, reads can bypass writes that are pending in the write buffer. Read and write accesses to DTCM and ITCM can be maintained in the order that the ARM9E-S core generated them by using the TCM order bits in CP15 register 15. See Configuration control register on page 2-11.When the TCM order bit is set, the write buffer is still used but any subsequent read accesses to the TCM are stalled until the buffer is emptied. Performing a write drain operation immediately prior to setting the TCM order bit is recommended to ensure correct operation. A write buffer drain operation can be invoked by writing to CP15 register 7. See Drain write buffers on page 2-9. Note The ITCMSIZE[4:0] and DTCMSIZE[4:0] inputs are used to ensure that write accesses to aliased addresses return the correct data when read. xTCMSIZE values must match instantiated memory size for this to operate correctly. Refer to TCM interface signals on page A-6 for details of xTCMSIZE values. 4-8 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface 4.4 Tightly-coupled memory error detection signals Large SRAM arrays are susceptible to errors caused by alpha particle radiation. These errors can result in incorrect data being returned. You can use parity checking or some form of error detection outside the ARM966E-S ARM966E-S macrocell to detect these errors. To enable the ARM966E-S ARM966E-S macrocell to support external error detection on the tightly-coupled memories there is one error signal for each of the TCM interfaces: · DTCMERROR · ITCMERROR. DTCMERROR and ITCMERROR enable the ARM966E-S ARM966E-S macrocell to be informed of error conditions during TCM read accesses. DTCMERROR and ITCMERROR are ignored during write accesses. These signals are valid in the same clock cycle as the data returned from the TCM. Error detection is performed externally to the ARM966E-S ARM966E-S macrocell. If error support is not required DTCMERROR and ITCMERROR must be tied LOW. Parity information must be generated for each byte because the ARM966E-S ARM966E-S is capable of performing byte accesses. The parity bit must be generated at the same time as the data is written to memory. Data is always read from the TCMs in 32-bit words and a parity error in any one byte must be returned to the core as an error. For data reads from either ITCM or DTCM any error returned causes a Data Abort exception. The exception handler determines what corrective action (if any) to take. For instruction fetches from the ITCM any error returned causes a Prefetch Abort exception if the ARM966E-S ARM966E-S macrocell tries to execute the returned instruction. Note If all the data is returned from the TCM write buffer, xTCMERROR is ignored. If only part of the data is returned from the TCM write buffer, xTCMERROR is sampled. To prevent errors from uninitialized locations, memory must be initialized so that spurious read errors are not generated. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-9 Tightly-Coupled Memory Interface 4.5 Interface operation This section describes the operation of the TCM interfaces. 4.5.1 Single-cycle and multicycle accesses This section describes: · Single-cycle TCM interface · Multicycle TCM interface on page 4-11. Single-cycle TCM interface Figure 4-1 shows a mixture of read and write operations and that the TCM must be able to support for back to back operations. When DTCMWAIT is not asserted the TCM controller expects all read/write operations to be single-cycle. DTCMWAIT can be tied LOW if a memory always performs single-cycle accesses. The ITCM operation is identical. DTCMCANCEL is HIGH in the second cycle and so the data in A does not get used. Figure 4-1 Single-cycle TCM read/writes 4-10 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface Multicycle TCM interface If a TCM is not able to service a memory request in a single-cycle, it must assert its wait signal to stall the ARM966E-S ARM966E-S macrocell. For example, if a TCM is not able to return read data in the cycle following the request, its wait signal must be asserted in the request cycle before the next rising CLK edge. The wait signal must be deasserted in the cycle prior to the read data being returned. Figure 4-2 on page 4-12 shows TCM read/write operations to a DTCM that requires two cycles for all accesses. On each new memory request, the DTCM asserts DTCMWAIT to inform the ARM966E-S ARM966E-S macrocell that it is not able to service the memory request in that cycle. The ARM966E-S ARM966E-S macrocell stalls until DTCMWAIT is deasserted. To aid in efficient use of multicycle memories, if the current access is sequential to the previous access, the ARM966E-S ARM966E-S macrocell asserts DTCMSEQ. Note The ARM966E-S ARM966E-S macrocell can issue a new memory request in the waited cycle. It is the responsibility of the external DTCM control logic to register waited memory requests if necessary. The ARM966E-S ARM966E-S TCM controller samples the TCMWAIT input only during an active TCM access - it is effectively a 'don't care' input at other times. This means the state of the TCMWAIT input does not affect the decision by the TCM controller to start a TCM access if one is not already in progress. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-11 Tightly-Coupled Memory Interface wait state c1 c2 wait state c3 c4 wait state c5 c6 wait state c7 c8 wait state c9 c10 c11 c12 CLK DTCMCS DTCMnRW DTCMADDR[23:0] C B DTCMWD[31:0] DTCMRD[31:0] D(A) D W(C) A W(D) E D(B) D(E) DTCMWAIT DTCMWE[3:0] DTCMSEQ Figure 4-2 Two cycle TCM read/writes 4.5.2 Speculative TCM read access Some data reads from data memory and instruction reads from instruction memory are speculative. After a memory location is read it is likely that the next read comes from the same area of memory. This second read is speculative because it is likely that it is correct but it is not certain. Misreads from speculative accesses cannot be aborted within one clock cycle. DTCMCANCEL and ITCMCANCEL are asserted in the clock cycle following a memory misread. When asserted the data requested from the memory is not fed to the ARM9E-S core. DTCMCANCEL and ITCMCANCEL are also asserted when a memory access is canceled by the ARM9E-S core. 4-12 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface Canceled accesses Typical situations where the xTCMCANCEL signals occur are: · a change from one memory region to another, typically leaving TCM space · the ARM9E-S core aborts the first data access in a series of back to back data accesses · the ARM9E-S core cancels a speculative instruction fetch. Figure 4-3 shows examples of canceled accesses to the DTCM. In cycle c5 DTCMCANCEL goes HIGH when the memory access is canceled as a result of the error generated for the TCM access TCM1. TCM2 is canceled. In cycles c7 to c9 DTCMCANCEL goes HIGH because there has been a change of memory space and the next data address is an AHB address. DTCMCANCEL goes HIGH and the data is not used by the ARM9E-S core. c1 c2 c3 c4 c5 c6 c7 c8 c9 CLK DnMREQ DTCMCS DTCMERROR DA TCM1 TCM2 AHB DTCMRD[31:0] DTCMCANCEL DTCMADDR TCM1 TCM2 Figure 4-3 DTCM reads with cancels ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-13 Tightly-Coupled Memory Interface 4.6 TCM implementation examples This section contains the following examples: · Simplest zero-wait-state RAM example · Byte-banks of RAM example on page 4-15 · Multiple banks of RAM example on page 4-16 · Sequential RAM example on page 4-17 · Single or Multiple wait-state RAM example on page 4-18 · Dual port DMA-capable RAM example on page 4-21. Note The examples in this section are for the DTCM. These are also applicable to the ITCM. The additional logic required for implementing the examples in this section is the responsibility of the implementer. 4.6.1 Simplest zero-wait-state RAM example Figure 4-4 shows a single RAM device with a 32-bit data width connected directly to the TCM interface. The DTCMWAIT signal must be tied off to zero. Figure 4-4 Simplest zero wait state RAM example 4-14 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface Inverters must be used if there is any differences in the polarity of the RAM input signals compared to those of the TCM interface. When the RAM chip select is active-LOW, an inverter must be placed between DTCMCS and the RAM chip select. This integration places a limit on the size of the TCMs. Multiple banks of RAM can be used to overcome this limitation, see Multiple banks of RAM example on page 4-16. 4.6.2 Byte-banks of RAM example If byte-write RAM is not available, four banks of 8-bit wide RAM can be used with each of the four bits of DTCMWE routed to one of the four RAM write enable inputs, as shown in Figure 4-5. ARM966E-S ARM966E-S DTCMWE[3:0] DTCMWE[0] DTCMWE[1] WE A[14:0] DIN[7:0] CLK DTCMCANCEL DTCMWE[2] WE CS A[14:0] DIN[7:0] CLK 32K RAM DTCMWAIT DTCMRD[31:0] DTCMWD[23:16] DTCMWD[31:24] DTCMADDR[14:0] DTCMSEQ DTCMSIZE[4:0] DTCMCS DTCMWD[15:8] DTCMWD[7:0] DTCMWD[31:0] DTCMADDR[23:0] DOUT[7:0] DTCMWE[3] WE 32K RAM CS A[14:0] DIN[7:0] CLK DOUT[7:0] WE A[14:0] DIN[7:0] CLK 32K RAM CS DOUT[7:0] 32K RAM CS DOUT[7:0] b1000 DTCMRD[7:0] DTCMRD[15:8] DTCMRD[23:16] DTCMRD[31:24] Figure 4-5 Byte-banks of RAM example A small amount of power saving can be achieved if the chip select for each RAM device is ANDed with (DTCMWE OR NOT DTCMnRW), so that byte and halfword writes only cause requests to the required byte RAM as shown in Figure 4-6 on page 4-16. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-15 Tightly-Coupled Memory Interface ARM966E-S ARM966E-S DTCMWD[15:8] DTCMWD[7:0] DTCMWD[31:0] DTCMWD[23:16] DTCMWD[31:24] DTCMADDR[14:0] DTCMADDR[23:0] DTCMWE[0] DTCMWE[3:0] DTCMWE[1] WE A[14:0] DIN[7:0] CLK DTCMSEQ WE A[14:0] DIN[7:0] CLK 32K RAM DTCMCANCEL DTCMWE[2] DTCMWAIT WE A[14:0] DIN[7:0] CLK 32K RAM CS DOUT[7:0] CS[0] DTCMWE[3] A[14:0] DIN[7:0] CLK 32K RAM CS DOUT[7:0] CS[1] WE 32K RAM CS DOUT[7:0] CS[2] CS DOUT[7:0] CS[3] DTCMnRW CS[3:0] DTCMRCS DTCMRD[31:0] DTCMRD[7:0] DTCMRD[15:8] DTCMRD[23:16] DTCMRD[31:24] DTCMSIZE[4:0] b1000 Figure 4-6 Byte-banks of RAM alternative example 4.6.3 Multiple banks of RAM example If RAMs of sufficient size are not available, you can use multiple RAM devices. The read data can come from one of two or more devices that are selected using a multiplexor or multiplexors. To ensure that write data is not written to all devices, addition logic must be introduced, either on chip select or write enable. Figure 4-7 on page 4-17 shows an example of multiple banked RAM where the chip select signal DTCMCS is ANDed with the top bit address signal DTCMADDR[14]. Figure 4-6 gives an example of multiple banked RAM where the write enable signals DTCMWE[3:0] are ANDed with the top bit address signal DTCMADDR[14]. Note For the banked RAM example shown in Figure 4-7 on page 4-17 the reads and writes only occur on the RAM device required, giving a reduction in the power used and speed when compared to the example shown in Figure 4-6. 4-16 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface Figure 4-7 Multiple banks of RAM example 4.6.4 Sequential RAM example If the RAM devices require a single wait-state except for sequential reads, the device can be connected as shown in Figure 4-8 on page 4-18. The DTCMWAIT signal is derived by using an inverter. The behavior of the DTCMSEQ signal has been designed so that the correct wait signal behavior is produced. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-17 Tightly-Coupled Memory Interface ARM966E-S ARM966E-S CLK DTCMADDR[23:0] DTCMADDR[14:0] 128K RAM A[14:0] DIN[31:0] DTCMWD{31:0] WE[3:0] DTCMWE[3:0] CS DTCMCS DOUT[31:0] DTCMRD[31:0] SEQ DTCMSEQ DTCMCANCEL DTCMWAIT DTCMSIZE[4:0] b1000 Figure 4-8 Sequential RAM example 4.6.5 Single or Multiple wait-state RAM example If the RAM devices require more than one cycle for all accesses, logic is required to assert the wait signal for the required number of cycles. Figure 4-9 on page 4-19 shows a Wait State Controller asserting the wait signal as required. The power control block removes power to the TCM when it is not required. 4-18 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface ARM966E-S ARM966E-S CLK DTCMADDR[23:0] DTCMADDR[14:0] DTCMWD[31:0] A[14:0] DIN[31:0] DTCMWE[3:0] WE[3:0] DTCMCS CS DTCMRD[31:0] DOUT[31:0] VDD DTCMSEQ DTCMCANCEL DTCMWAIT Wait state control Power control Figure 4-9 Single or Multiple wait-state RAM example 4.6.6 Single port RAM example When using single port RAM, multiplexors are required to switch between DMA controller and ARM966E-S ARM966E-S memory interface signals. Figure 4-10 on page 4-20 shows a single port RAM example. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-19 Tightly-Coupled Memory Interface DMA controller DIN[31:0] MUXCONN A[14:0] DOUT[31:0] WE[3:0] CS WAIT ARM966E-S ARM966E-S DTCMWAIT DTCMADDR[23:0] DTCMADDR[14:0] RAM 128K 0 A[14:0] 1 0 DTCMWD[31:0] DIN[31:0] 1 0 DTCMWE[3:0] DTCMRD[31:0] WE[3:0] 1 DOUT[31:0] 0 DTCMCS CS 1 CLK DTCMSEQ CLK DTCMCANCEL DTCMCSIZE[3:0] b1000 Figure 4-10 Single port DMA-capable RAM example 4-20 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Tightly-Coupled Memory Interface 4.6.7 Dual port DMA-capable RAM example For dual port RAM, the TCM interface must be attached to one port and the DMA controller to the other port as shown in Figure 4-11. This requires minimal extra logic (more logic may be required to detect address conflicts, depending on the devices and the application). ARM966E-S ARM966E-S CLK RAM 128K CLK DTCMADDR[23:0] DTCMADDR[14:0] A[14:0] DIN[31:0] DTCMWD[31:0] WE[3:0] DTCMWE[3:0] CS DOUT[31:0] DTCMCS DTCMRD[31:0] DTCMSEQ DTCMCANCEL DTCMSIZE[4:0] CLK CLK A[14:0] DIN[31:0] WE[3:0] CS DOUT[31:0] DMA controller CLK A[14:0] DOUT[31:0] WE[3:0] CS DIN[31:0] b1000 DTCMWAIT Figure 4-11 Dual port RAM example ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 4-21 Tightly-Coupled Memory Interface 4-22 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Chapter 5 Bus Interface Unit This chapter describes the ARM966E-S ARM966E-S Bus Interface Unit (BIU) and write buffer. It contains the following sections: · About the BIU on page 5-2 · AHB instruction prefetch buffer on page 5-3 · AHB write buffer on page 5-6 · AHB bus master interface on page 5-9 · AHB transfer descriptions on page 5-10 · AHB clocking on page 5-15 · CLK to HCLK skew on page 5-17. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 5-1 Bus Interface Unit 5.1 About the BIU The ARM966E-S ARM966E-S macrocell supports an Advanced Microprocessor Bus Architecture (AMBA) Advanced High-performance Bus (AHB) interface. The AHB is a new generation of AMBA interface that addresses the requirements of high-performance synthesizable designs, including: · single clock edge operation (rising edge) · unidirectional (nontristate) buses · mapped burst transfers · split transactions · single-cycle bus master handover. See the AMBA Specification (Rev 2.0) for full details of this bus architecture. The ARM966E-S ARM966E-S BIU implements a fully-compliant AHB bus master interface and incorporates an instruction prefetch buffer and a write buffer to increase system performance. The BIU is the link between the ARM9E-S core with its tightly-coupled memory and the external AHB memory. The AHB memory must be accessed to initialize the tightly-coupled memory. The AHB memory must also be used to access code and data that are not assigned to the tightly-coupled memory address space (or if the TCM is disabled). 5-2 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Bus Interface Unit 5.2 AHB instruction prefetch buffer The BIU Instruction Prefetch Buffer (IPB) is four entries deep (one entry = 32 bits). All nonsequential instruction fetches to AHB space cause the IPB to be flushed and an initial burst of four words to be performed on the AHB. After this initial burst the buffer performs AHB accesses to keep the buffer full. If the ARM9E-S core takes an instruction out of the buffer on each clock cycle, the fetches on the AHB interface are performed as incrementing bursts of unspecified length (HBURST[2:0] = 001). Prefetching is only initiated from valid instruction requests. The prefetch buffer marks each entry with the error response returned from the AHB. The prefetch buffer also marks each entry with the external breakpoint request returned from the external memory system. Instruction prefetching does not cross 1KB boundaries. 5.2.1 Optimized Thumb instruction prefetch In Thumb mode, the prefetch buffer depth is reduced to two words (four Thumb instructions). The ARM966E-S ARM966E-S macrocell performs a two-word incrementing burst for nonsequential fetches. When space becomes available the IPB performs transfers to fill any vacant entries up to the buffer depth limit of two word entries available in Thumb mode. 5.2.2 IPB disable bit Bit 16, of the Configuration control register disables the IPB when asserted. Actual prefetch behavior does not change until the next nonsequential instruction fetch occurs. See Register 15, Test and configuration on page 2-10. At reset this bit is cleared (prefetching enabled). 5.2.3 AHB error response with prefetch buffer If an error response is returned from the AHB, it is stored in the IPB along with the instruction. If the instruction reaches the Execute stage of the ARM9E pipeline, a prefetch abort exception occurs. 5.2.4 Instruction prefetch buffer examples This section gives two instruction prefetch buffer examples: · Sequential instruction fetch · Instruction prefetching with data access. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 5-3 Bus Interface Unit Prefetching instructions from AHB Figure 5-1 shows AHB prefetching in operation. In this case the ARM9E-S core is executing code sequentially from the AHB. As soon as each instruction is returned from the AHB, it is returned to the ARM9E-S core. None of the returned data is placed into the prefetch buffer because the processor core is continuously requesting instructions from the AHB. The AHB runs ahead of the core to minimize the number of stall cycles. The ARM9E-S core generates a NONSEQUENTIAL instruction fetch. This can be as a result of a branch or an operation changing the value of the PC, for example. The BIU terminates the current burst and starts a new prefetch operation with a burst of length four to fill the prefetch buffer. The first instruction from the burst is returned to the ARM9E-S core. The BIU keeps the prefetch buffer full by performing an undefined length burst. This is because the ARM9E-S core is running sequentially and requesting instructions each cycle. This is a new burst so NSEQ is indicated on AHB. Figure 5-1 Effect of a nonsequential instruction fetch Note All timing examples in this chapter assume one-to-one clocking where the ARM966E-S ARM966E-S macrocell and AHB share the same clock. See AHB clocking on page 5-15 for details of AHB clocking modes. All timing examples assume that bus mastership has been granted. 5-4 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Bus Interface Unit Instruction prefetching with data access Figure 5-2 shows an AHB data access intermingled with instruction fetches. Data accesses take precedence over instruction fetches, and so the instruction fetch starts after the data access. After the first instruction address is issued on the AHB, sequential instruction prefetching starts. The core is not advanced until both of the simultaneous memory requests have been satisfied. As in the example shown in Figure 5-1 on page 5-4, the prefetch buffer is not used immediately as each instruction returned from the BIU is immediately used by the processor core. The second data memory request causes the processor core to stall until the data request has been completed. This causes the two outstanding instruction prefetches to be stored in the prefetch buffer. Prefetching stops as a result of data request. The instruction request issued with the data access can be acknowledged as soon as the associated transfer has successfully completed on the AHB. As soon as the core is re-enabled following the data access, the prefetching can continue, as the address is sequential to the previous instruction address. Figure 5-2 Nonsequential instruction fetch after a data access ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 5-5 Bus Interface Unit 5.3 AHB write buffer The ARM966E-S ARM966E-S macrocell implements a four-entry address, eight data word entry AHB write buffer. The write buffer decouples the core from the wait cycles incurred when accessing the AHB. If a write is sent to the write buffer, the core is able to continue program execution without having to wait for the write to complete on the AHB. More writes can be committed to the write buffer without stalling if spare entries are available. If the write buffer becomes full and the ARM9E-S core attempts a write to a buffered location, the ARM9E-S core must be stalled until there is space in the FIFO. If the ARM9E-S core performs a read from AHB address space or an unbuffered write to AHB address space, the core is stalled until all write buffer entries have been written. That is, the write buffer is drained to ensure data coherency. 5.3.1 Committing write data to the write buffer The write buffer is used when the following conditions are met: · the write buffer is enabled · the write address is in a bufferable region · the write address is in AHB, or the address selects a tightly-coupled memory that is disabled. For details on write buffer enable and the ARM966E-S ARM966E-S fixed address map, see · Register 1, Control register on page 2-6 · About the ARM966E-S ARM966E-S memory map on page 3-2. When a write is performed by the core and conforms to the above conditions, the address for the write is put into the first available address entry of the write buffer FIFO. The next available entry data is used for the write data. If the write is a store multiple (STM), subsequent data entries are used for each word of the STM. It is therefore possible for the FIFO to contain 8 words of an STM. Alternatively, if several shorter bufferable STM or single writes (STR) instructions are performed, one address entry is used for each write instruction. The worst case is that only four data words fill the FIFO caused by four STR writes. In this case the FIFO holds four address entries and four data entries. 5.3.2 Draining write data from the write buffer The write buffer can drain naturally where AHB writes occur whenever data is committed to the FIFO. The core is only stalled, if the write buffer overflows. However, there are times when a complete drain of the write buffer is enforced. 5-6 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Bus Interface Unit Natural write buffer drain When a write is being committed to the write buffer FIFO, a signal is sent to the BIU to initiate an AHB write. The BIU then pops the address for the write from the FIFO followed by the data and starts an AHB transfer (assuming the ARM966E-S ARM966E-S macrocell is the granted bus master). This process might take several cycles because the write access is to an AHB slave in a bufferable region that has a multi-cycle response. Additionally, the AHB can be run at a lower rate than the ARM966E-S ARM966E-S system introducing extra delay to the buffered write process. This can lead to the core trying to commit data at a higher rate than the FIFO can be drained, resulting in the FIFO becoming full. The ARM9E-S core is stalled until an entry becomes available. When an address is placed in the write buffer, a marker is also stored to indicate if the size of the write is, byte, halfword or word. If a STM is performed, a sequentiality marker is stored with the data, to indicate to the BIU that the address incrementer must be used to produce the AHB address for the second and following writes of the STM. This mechanism allows only one FIFO entry to be used for the address, leaving more room for data. Enforced write buffer drain There are two situations where the core is stalled and the write buffer is forced to drain completely before program execution can continue: · an instruction fetch, data load, or unbuffered write to the AHB is being requested · a drain write buffer instruction is being executed. AHB read access requested To ensure data coherency, the core must be prevented from reading data from a location that has recently been modified (by the core or an external coprocessor STC instruction) and is still in the write buffer awaiting AHB access. If the AHB read access is allowed to occur before the write buffer is drained, the old version of data at that location is fetched causing a data coherency failure. For this reason, whenever an AHB read is requested, as an ARM9E-S instruction fetch or a data load or load multiple, the core must be stalled until the write buffer is drained. No dedicated logic is used to force a write buffer drain as this process is occurring whenever data is present within the buffer. However, dedicated logic is used to stall the core until the last buffered write has completed on the AHB. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 5-7 Bus Interface Unit Drain write buffer instruction You can use an MCR instruction to CP15 register 7 to force the core to be stalled until the write buffer is empty and the final write is completed on the AHB. This instruction is described in Register 7, Core control on page 2-9. This instruction is useful when the software requires that a write is completed before program execution continues. 5.3.3 Enabling the write buffer The write buffer can be enabled by setting bit 3 of the CP15 control register. When this bit is set, all writes to bufferable address locations use the write buffer. If a slave peripheral in a bufferable region returns an AHB Data Abort, the abort is ignored when the write buffer is enabled. Note For debugging purposes, you can disable the write buffer to enable AHB Data Aborts to be returned from bufferable regions. 5.3.4 Disabling the write buffer When data is committed to the write buffer it is always written to the AHB. If the write buffer is disabled by clearing bit 3 of the CP15 control register, any existing write data in the write buffer is completed. Additionally, if the core is sent to sleep by the wait for interrupt command, any writes in the write buffer FIFO are also completed. If the programmer wants to ensure that no more buffered writes occur following write buffer disable or a wait for interrupt instruction, the write buffer must first be drained with a drain write buffer command. 5-8 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Bus Interface Unit 5.4 AHB bus master interface The ARM966E-S ARM966E-S macrocell implements a fully-compliant AHB bus master interface and is defined in the AMBA Specification (Rev 2.). Refer to this document for a detailed description of the AHB protocol. 5.4.1 Overview of AHB The AHB architecture is based on separate cycles for address and data (rather than the phase of the clock in the ASB architecture). The address and control values for an access are broadcast from the rising edge of HCLK in the cycle before the data is expected to be read or written. During this data cycle, the address and control values for the next cycle are driven out. This leads to a fully pipelined address architecture. When an access is in its data cycle, a slave can wait the access by driving the HREADY response LOW. This has the effect of stretching the current data cycle and therefore the pipelined address and control for the next access is also stretched. This creates a system where all AHB masters and slaves sample HREADY on the rising edge of the HCLK to determine whether an access has completed and a new address can be sampled or driven out. ARM DDI 0213C 0213C Copyright © 2000, 2002 ARM Limited. All rights reserved. 5-9 Bus Interface Unit 5.5 AHB transfer descriptions The ARM966E-S ARM966E-S BIU performs a subset of the possible AHB bus transfers available. This section describes the transfers that can be performed and some back-to-back transfer cases: · Back-to-back data transfers · Data burst crossing a 1KB boundary on page 5-12 · SWP instruction on page 5-13. 5.5.1 Back-to-back data transfers Figure 5-3 on page 5-11 shows ARM966E-S ARM966E-S bus activity when a sequence of STR instructions is executed where there are no AHB instruction fetches. The ARM9E-S core is executing instructions from the TCM space. In c2 the ARM9E-S core starts a nonsequential data write. A series of NONSEQ/IDLE transfers is indicated for each access. The ARM9E-S core is re-enabled in cycle c10. 5-10 Copyright © 2000, 2002 ARM Limited. All rights reserved. ARM DDI 0213C 0213C Bus Interface Unit c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 CLK CLKEN DA DA1 DA2 DnMREQ DSEQ DMORE DnRW HBUSREQ HTRANS HADDR IDLE NSEQ IDLE DA1 NSEQ IDLE DA2 HWRITE HRDATA R(DA2) HWDATA W(DA1) Figure 5-3 Back-to-back data transfer write followed by read Note An identical series of NONSEQ and IDLE transfers is seen if executing a sequence of back-to-back LDR instructions. STM followed by instruction fetch Figure 5-4 on page 5-12 shows an example of an STM transferring four words, immediately followed by an instruction fetch. The instruction read begins with a NONSEQ/SEQ sequence after the final sequential data access. In this example, subsequent instruction fetches are sequential. Instruction prefetching is enable