LH7A404 ARM922TTM ISO7816 11/SD ARM922T LH7A404-1 XTAL32IN XTAL32OUT A10/SA8 - Datasheet Archive

 

32-Bit System-on-Chip Preliminary Data Sheet FEATURES · PS/2 Keyboard/Mouse Interface (KMI) · ARM922TTM Core: ­

 

LH7A404 LH7A404 32-Bit System-on-Chip Preliminary Data Sheet FEATURES · PS/2 Keyboard/Mouse Interface (KMI) · ARM922TTM ARM922TTM Core: ­ 32-bit ARM9TDMITM RISC Core (200 MHz) ­ 16KB Cache: 8KB Instruction Cache and 8KB Data Cache ­ MMU (Windows CETM Enabled) · Three Programmable Timers · Smart Card Interface (ISO7816 ISO7816) · Four Pulse Width Modulators (PWMs) · 80KB On-Chip Memory · MultiMediaCard Interface with Secure Digital (MMC 2.11/SD 11/SD 1.0) · Vectored Interrupt Controller · External Bus Interface ­ 100 MHz ­ Asynchronous SRAM/ROM/Flash ­ Synchronous DRAM/Flash ­ PCMCIA ­ CompactFlash · AC97 Codec Interface · Smart Battery Monitor Interface · Real Time Clock (RTC) · Up to 64 General Purpose I/O Channels · Watchdog Timer · Clock and Power Management ­ 32.768 kHz and 14.7456 MHz Oscillators ­ Programmable PLL · JTAG Debug Interface and Boundary Scan · Operating Voltage ­ 1.8 V Core ­ 3.3 V Input/Output · Low Power Modes (Typical) ­ Run (147 mA), Halt (41 mA), Standby (42 µA) · Programmable LCD Controller ­ Up to 1,024 × 768 Resolution ­ Supports STN, Color STN, AD-TFT, HR-TFT, TFT ­ Up to 64 K-Colors and 15 Gray Shades · 10 Channel, 10-bit A/D Converter ­ Touch Screen Controller ­ Brownout Detector · 5 V Tolerant Inputs (except oscillator and VDDAD pins1) · Operating Temperature ­ 0°C to +70°C Commercial ­ -40°C to +85°C Industrial (With Clock Frequency Reduction1) · 324-Ball CABGA Package (324 PBGA Package for sample parts) · DMA (12 Channels) ­ External DMA Channels ­ AC97 ­ MMC ­ USB DESCRIPTION The advent of 3G technology opens the door for a wide range of multimedia applications in mobile information appliances. These appliances require high processing performance and low power consumption. The LH7A404 LH7A404 is designed from the ground up to provide high processing performance, low power consumption, and a high level of integration. · USB Host and Device Interface (USB 1.1) · Synchronous Serial Port (SSP) ­ Motorola SPITM ­ Texas Instruments SSI ­ National MICROWIRETM The LH7A404 LH7A404 contains a high performance 32-bit ARM922T ARM922T Core. Power consumption is reduced by the high level of integration, 80KB on-chip SRAM, fully static design, power management unit, low voltage operation (1.8 V Core, 1.8 V or 3.3 V I/O) and on-chip PLL. · On-board Boot ROM ­ Supports booting from NAND Flash, I2C, EEPROM, MMC/SD card, or XMODEM Motorola SPI is a trademark of Motorola, Inc. National Semiconductor MICROWIRE is a trademark of National Semiconductor Corporation. ARM922T ARM922T and ARM9TDMI are trademarks of Advanced RISC Machines Ltd. Windows CE is a trademark of Microsoft Corporation. Advance Data Sheet · Three UARTs ­ Classic IrDA (115 kbit/s) NOTES: 1. Oscillator pins AA16, AA21, Y16, and Y20 require 1.8 V ±10%; 12/17/03 VDDAD requires 3.3 V ±10% 1 LH7A404 LH7A404 32-Bit System-on-Chip 14.7456 MHz 32.768 kHz OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL VECTORED INTERRUPT CONTROLLER ASYNCHRONOUS MEMORY CONTROLLER PCMCIA/CF CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE SYNCHRONOUS MEMORY CONTROLLER LCD AHB BUS WATCHDOG TIMER TIMER (3) ARM 922T EXTERNAL BUS INTERFACE REAL TIME CLOCK GENERAL PURPOSE I/O (64) SYNCHRONOUS SERIAL PORT BATTERY MONITOR INTERFACE UART (3) IrDA INTERFACE 80KB SRAM USB DEVICE INTERFACE COLOR LCD CONTROLLER DMA CONTROLLER MULTIMEDIA CARD/ SECURE DIGITAL INTERFACE AC97 ADVANCED LCD INTERFACE (ALI) CODEC INTERFACE USB HOST INTERFACE SMART CARD INTERFACE (ISO7816 ISO7816) ADVANCED HIGH-PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB) PWM (2) A/D TOUCH SCREEN CONTROLLER PS2 KEYBOARD/MOUSE INTERFACE DC to DC INTERFACE (2) LH7A404-1 LH7A404-1 Figure 1. LH7A404 LH7A404 Block Diagram 2 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 1. LH7A404 LH7A404 Functional Pin List CABGA SIGNAL RESET STATE DESCRIPTION STANDBY STATE OUTPUT DRIVE I/O NOTES E10 E11 H10 H11 K5 K8 K13 K16 L5 VDD I/O Ring Power VSS I/O Ring Ground VDDC Core Power L8 L13 L16 N10 N11 T10 T11 U18 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 T18 E7 E9 E14 G5 G16 P5 P16 T7 T12 T14 Preliminary Data Sheet 12/17/03 3 LH7A404 LH7A404 32-Bit System-on-Chip Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA SIGNAL RESET STATE STANDBY STATE Input DESCRIPTION OUTPUT DRIVE Input I/O NOTES E6 E15 F5 F16 J16 VSSC Core Ground VDDA Analog Power for PLL1 and PLL2 VSSA Analog Ground for PLL1 and PLL2 W16 VDDAD Analog Power for A/D, Touch Screen Controller V13 VSSAD Analog Ground for A/D, Touch Screen Controller D2 nPOR Power on Reset E1 nURESET User Reset Input Input I 3 F3 WAKEUP Wake Up Input Input I 3 M5 R5 R16 T6 T15 Y17 W17 V16 U15 I 3 F4 nPWRFL Power Fail Signal Input Input I 3 C1 nEXTPWR External Power Input Input I 3 C5 nRESETOUT Reset Output to external devices Y18 XTALIN Y19 XTALOUT 14.7456 MHz Crystal Oscillator pins. To drive the device from an external clock source, XTALIN can be used while XTALOUT is left unconnected. T19 XTAL32IN XTAL32IN T20 XTAL32OUT XTAL32OUT 32.768 kHz Real Time Clock, Crystal Oscillator pins. To drive the device from an external clock source, XTAL32IN XTAL32IN can be used while XTAL32OUT XTAL32OUT is left unconnected. PGMCLK Programmable Clock (14.7456 MHz MAX.) LOW LOW 8 mA O CLKEN External Oscillator Enable Output LOW LOW 8 mA I/O 4 Y13 BOOTWIDTH0 Input Input I 3 W13 BOOTWIDTH1 Boot Width Pins. Used with the MEDCHG bit, and INTBOOT for internal Boot ROM. On power up, the values on these pins are latched to determine the width and type of Boot device. Boot width can be 8-, 16-, or 32-bit. 3 L2 T16 16 mA E4 Media Change bit; used with INTBOOT and BOOTWIDTHx pins to determine boot device at power on. Input No Change I Y20 4 MEDCHG INTBOOT When LOW, boot device is selected according to the MEDCHG bit. When HIGH, the lower 64KB addresses are mapped to the internal Boot ROM. Input No Change I 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA RESET STATE STANDBY STATE OUTPUT DRIVE Data Bus LOW LOW 16 mA I/O Asynchronous Address Bus HIGH LOW 16 mA O SIGNAL N19 DESCRIPTION I/O NOTES D0 P20 D1 N18 D2 N20 D3 M16 D4 M18 D5 L18 D6 L17 D7 L19 D8 J19 D9 K17 D10 J18 D11 H19 D12 G20 D13 G19 D14 H17 D15 F19 D16 E20 D17 E19 D18 D20 D19 E18 D20 C20 D21 D18 6 D22 B20 D23 C18 D24 A20 D25 B18 D26 C16 D27 B17 D28 A18 D29 A17 D30 B15 D31 P17 A0 N16 A1 Preliminary Data Sheet 12/17/03 5 LH7A404 LH7A404 32-Bit System-on-Chip Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA SIGNAL N17 OUTPUT DRIVE Asynchronous Address Bus and Synchronous Address Bus LOW LOW 16 mA O I/O NOTES A3/SA1 M20 STANDBY STATE A2/SA0 M19 RESET STATE DESCRIPTION A4/SA2 L20 A5/SA3 M17 A6/SA4 K18 A7/SA5 K20 A8/SA6 K19 A9/SA7 J20 A10/SA8 A10/SA8 H20 A11/SA9 A11/SA9 J17 A12/SA10 A12/SA10 H18 A13/SA11 A13/SA11 F20 A14/SA12 A14/SA12 G18 A15/SA13 A15/SA13 H16 A16/SB0 A16/SB0 · Asynchronous Address Bus · Synchronous Device Bank Address 0 LOW LOW 16 mA O F18 A17/SB1 A17/SB1 · Asynchronous Address Bus · Synchronous Device Bank Address 1 LOW LOW 16 mA O G17 A18 F17 A19 Asynchronous Address Bus LOW LOW 16 mA O LOW LOW 16 mA O LOW LOW 16 mA O D19 A20 E17 A21 C19 A22 D17 A23 B19 A24 A16 A25 Asynchronous Address Bus Asynchronous Address Bus D15 A26 B14 A27 V18 nCS0 Asynchronous Memory Chip Select 0 (ROM/Flash) HIGH HIGH 16 mA O R19 nCS1 Asynchronous Memory Chip Select 1 HIGH HIGH 16 mA 6 O R18 nCS2 Asynchronous Memory Chip Select 2 HIGH HIGH 16 mA O P19 nCS3/ nMMSPICS · Asynchronous Memory Chip Select 3 · Reserved nCS3: HIGH nCS3: HIGH 16 mA O R20 nCS6 Asynchronous Memory Chip Select 6 HIGH No Change 16 mA O R17 nCS7 Asynchronous Memory Chip Select 7 HIGH No Change 16 mA O C12 nOE Asynchronous Memory Output Enable HIGH HIGH 16 mA O 6 16 mA O 6 D12 nWE Asynchronous Memory Write Enable HIGH HIGH P18 nWAIT Asynchronous Memory Controller Wait Input No Change I C17 nSCS0 Synchronous Memory Chip Select 0 HIGH HIGH 16 mA I/O 4 A19 nSCS1 Synchronous Memory Chip Select 1 HIGH HIGH 16 mA I/O 4 D16 Synchronous Memory Chip Select 2 HIGH HIGH 16 mA I/O 4 nSCS3 Synchronous Memory Chip Select 3 HIGH HIGH 16 mA I/O 4 B16 nSWE Synchronous Memory Write Enable HIGH HIGH 16 mA O A14 SCKE0 Clock Enable 0 for Synchronous Memory HIGH No Change 16 mA O B13 6 nSCS2 E16 SCKE1_2 Clock Enable 1 OR 2 for Synchronous Memory HIGH No Change 16 mA O 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA SIGNAL RESET STATE DESCRIPTION STANDBY STATE OUTPUT DRIVE Depends on MEDCHG LOW 16 mA I/O 4 No Change 24 mA I/O 2, 4 4 I/O NOTES C14 SCKE3 Clock Enable 3 for Synchronous Memory D14 SCLK Synchronous Memory Clock LOW A13 nBLE0 Byte Lane Enable 0 HIGH HIGH 16 mA I/O U9 nBLE1 Byte Lane Enable 1 HIGH HIGH 16 mA O Y7 nBLE2 Byte Lane Enable 2 HIGH HIGH 16 mA O C13 nBLE3 Byte Lane Enable 3 HIGH HIGH 8 mA O C15 nCAS Synchronous Memory Column Address Strobe HIGH HIGH 16 mA I/O 4 A15 nRAS Synchronous Memory Row Address Strobe HIGH HIGH 16 mA I/O 4 D13 DQM0 E13 DQM1 B12 DQM2 Data Mask for synchronous memories HIGH No Change 16 mA O A12 DQM3 M2 PA0/ LCDVD16 LCDVD16 · GPIO Port A0 · LCD data pin 16 PA0: Input No Change 8 mA I/O L4 PA1/ LCDVD17 LCDVD17 · GPIO Port A1 · LCD data pin 17 PA1: Input No Change 8 mA I/O M3 PA2 M4 PA3 M1 PA4 GPIO Port A[6:2] PAx: Input No Change 8 mA I/O N3 PA5 N2 PA6 N1 PA7 GPIO Port A7 PA7: Input No Change 8 mA I/O N4 PB0/ UARTRX1 · GPIO Port B0 · UART1 Receive Data Input PB0: Input No Change 8 mA I/O P3 PB1/ UARTTX3 · GPIO Port B1 · UART3 Transmit Data Out PB1: Input No Change 8 mA I/O P2 PB2/ UARTRX3 · GPIO Port B2 · UART3 Receive Data In PB2: Input No Change 8 mA I/O P1 PB3/ UARTCTS3 · GPIO Port B3 · UART3 Clear to Send PB3: Input No Change 8 mA I/O R3 PB4/ UARTDCD3 · GPIO Port B4 · UART3 Data Carrier Detect PB4: Input No Change 8 mA I/O N5 PB5/ UARTDSR3 · GPIO Port B5 · UART3 Data Set Ready PB5: Input No Change 8 mA I/O R2 PB6/ SWID/ SMBD · GPIO Port B6 · Single Wire Data · Smart Battery Data PB6: Input No Change 8 mA I/O R1 PB7/ SMBCLK · GPIO Port B7 · Smart Battery Clock PB7: Input No Change 8 mA I/O P4 PC0/ UARTTX1 · GPIO Port C0 · UART1 Transmit Data Output PC0: LOW No Change 16 mA I/O T1 PC1 T2 PC2 GPIO Port C[5:1] PCx: LOW No Change 16 mA I/O T3 PC3 R4 6 PC4 U1 PC5 U2 PC6 GPIO Port C6 PC6: LOW No Change 16 mA I/O V1 PC7 GPIO Port C7 PC7: LOW No Change 16 mA I/O Preliminary Data Sheet 12/17/03 6 7 LH7A404 LH7A404 32-Bit System-on-Chip Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA RESET STATE STANDBY STATE OUTPUT DRIVE PDx: LOW LOW if 8-bit LCD enabled; else No Change 16 mA · GPIO Port E[3:0] · LCD Video Data Interface PEx: Input LOW if 8-bit LCD enabled; else No Change SIGNAL Y11 PD1/LCDVD9 W12 PD2/LCDVD10 PD2/LCDVD10 V11 PD3/LCDVD11 PD3/LCDVD11 W11 PD4/LCDVD12 PD4/LCDVD12 U11 PD5/LCDVD13 PD5/LCDVD13 V12 PD6/LCDVD14 PD6/LCDVD14 Y12 I/O NOTES PD0/LCDVD8 U10 DESCRIPTION PD7/LCDVD15 PD7/LCDVD15 · GPIO Port D[7:0] · LCD Video Data Interface I/O Y9 PE1/LCDVD5 V10 PE2/LCDVD6 T9 PE3/LCDVD7 D4 PE4/ SCCLKIN · GPIO Port E4 · Smart Card Push-Pull Mode Clock Input PE4: Input No Change 16 mA I/O C3 PE5/ SCCLKEN · GPIO Port E5 · Smart Card Push-Pull Mode External Clock Buffer Enable PE5: Input No Change 16 mA I/O B2 PE6/ SCIN · GPIO Port E6 · Smart Card Push-Pull Mode Data In PE6: Input No Change 16 mA I/O A1 PE7/ SCDATEN · GPIO Port E7 · Smart Card Push-Pull Mode Data Out External Buffer Enable PE7: Input No Change 16 mA I/O A9 PF0/ INT0 · GPIO Port F0 · Interrupt 0 PF0: Input No Change 8 mA I/O 3 D9 PF1/ INT1 · GPIO Port F1 · Interrupt 1 PF1: Input No Change 8 mA I/O 3 A8 PF2/ INT2 · GPIO Port F2 · Interrupt 2 PF2: Input No Change 8 mA I/O 3 C8 PF3/ INT3 · GPIO Port F3 · Interrupt 3 PF3: Input No Change 8 mA I/O 3 B8 PF4/ INT4 · GPIO Port F4 · Interrupt 4 PF4: Input No Change 8 mA I/O 3 D8 PF5/ INT5/ SCDETECT · GPIO Port F5 · Interrupt 5 · Smart Card Interface Card Detect Signal PF5: Input No Change 8 mA I/O 3 A7 PF6/ NT6/ PCRDY1 · GPIO Port F6 · Interrupt 6 · Ready for Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode PF6: Input No Change 8 mA I/O 3 E8 PF7/ INT7/ PCRDY2 · GPIO Port F7 · Interrupt 7 · Ready for Card 2 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode PF7: Input No Change 8 mA I/O 3 Y2 PG0/ nPCOE · GPIO Port G0 · Output Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode LOW No Change 8 mA I/O W4 PG1/ nPCWE · GPIO Port G1 · Write Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode LOW No Change 8 mA I/O Y3 8 PE0/LCDVD4 W10 PG2/ nPCIOR · GPIO Port G2 · I/O Read Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode LOW No Change 8 mA I/O 12/17/03 16 mA I/O Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA SIGNAL RESET STATE DESCRIPTION STANDBY STATE OUTPUT DRIVE I/O NOTES U5 PG3/ nPCIOW · GPIO Port G3 · I/O Write Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode LOW No Change 8 mA I/O T5 PG4/ nPCREG · GPIO Port G4 · Register Memory Access for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode LOW No Change 8 mA I/O PG5/ nPCCE1 · GPIO Port G5 · Card Enable 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal and nPCCE2 are used by the PC Card for decoding low and high byte accesses. LOW No Change 8 mA I/O Y4 PG6/ nPCCE2 · GPIO Port G6 · Card Enable 2 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal and nPCCE1 are used by the PC Card for decoding low and high byte accesses. LOW No Change 8 mA I/O W6 PG7/ PCDIR · GPIO Port G7 · Direction for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode LOW No Change 8 mA I/O V6 PH0/ PCRESET1 · GPIO Port H0 · Reset Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode PHx: Input No Change 8 mA I/O Y5 PH1/ CFA8/ PCRESET2 · GPIO Port H1 · Address Bit 8 for PC Card (CompactFlash) in Single Card mode · Reset Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode PHx: Input No Change 8 mA I/O PH2/ nPCSLOTE1 · GPIO Port H2 · Enable Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal is used for gating other control signals to the appropriate PC Card. PHx: Input No Change 8 mA I/O U6 PH3/CFA9/ PCMCIAA25/ PCMCIAA25/ nPCSLOTE2 · GPIO Port H3 · Address Bit 9 for PC Card (CompactFlash) in Single Card mode · Address Bit 25 for PC Card (PCMCIA) in Single Card mode · Enable Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode. Used for gating other control signals to the appropriate PC Card. PHx: Input No Change 8 mA I/O W8 PH4/ nPCWAIT1 · GPIO Port H4 · WAIT Signal for Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode PHx: Input No Change 8 mA I/O Y6 PH5/CFA10/ PH5/CFA10/ PCMCIAA24/ PCMCIAA24/ nPCWAIT2 · GPIO Port H5 · Address Bit 10 for PC Card (CompactFlash) in Single Card mode · Address Bit 24 for PC Card (PCMCIA) in Single Card mode · WAIT Signal for Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode PHx: Input No Change 8 mA I/O V7 PH6/ nAC97RESET · GPIO Port H6 · AC97 Reset PHx: Input No Change 8 mA I/O U7 PH7/ nPCSTATRE · GPIO Port H7 · Status Read Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode PHx: Input No Change 8 mA I/O T4 LCDFP/ LCDSPS · LCD Frame Pulse · ALI Reset Row Driver Counter LOW LOW if not in ALI mode 16 mA O W5 W7 Preliminary Data Sheet 12/17/03 9 LH7A404 LH7A404 32-Bit System-on-Chip Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA SIGNAL RESET STATE DESCRIPTION STANDBY STATE OUTPUT DRIVE I/O NOTES V2 LCDLP/ LCDHRLP · LCD Linepulse · ALI Latch Pulse LOW LOW if not in ALI mode 16 mA O U3 LCDCLS ALI Clock for Row Drivers Input No Change 16 mA O V3 LCDSPL ALI Start Pulse Left for reverse scanning LOW No Change 16 mA O U4 LCDUBL ALI Up, Down signal for reverse scanning Input No Change 16 mA O W1 LCDSPR ALI Start Pulse Right for normal scanning Input No Change 16 mA O V4 LCDLBR ALI Output for reverse scanning HIGH No Change 16 mA O W2 LCDMOD ALI MOD Signal used by the row driver LOW No Change 16 mA O V5 LCDPS ALI Power Save HIGH No Change 16 mA O Y1 LCDVDDEN ALI Power Sequence Control LOW No Change 16 mA O W3 LCDREV ALI Reverse HIGH No Change 16 mA O U8 LCDCLKIN External Clock Input for LCD controller Input No Change V8 LCDVD0 LCD Video Data Interface LOW LOW 16 mA O I T8 LCDVD1 W9 LCDVD2 Y8 LCDVD3 V9 LCDENAB/ LCDM · LCD TFT Data Enable · LCD STN AC Bias LOW LOW 16 mA O Y10 LCDDCLK LCD Pixel Clock LOW LOW 16 mA O U17 USBDCP USB Device Device Full Speed Pull-up Resistor Control Input Input 16 mA I U20 USBDP USB Device Data Positive (Differential Pair) Input Input 16 mA I/O U19 USBDN USB Device Data Negative (Differential Pair) Input Input 16 mA I/O W19 USBHDP0 USB Data Host Positive 0 (Differential Pair) Input HIGH 16 mA I/O W20 USBHDN0 USB Data Host Negative 0 (Differential Pair) Input LOW 16 mA I/O V19 USBHDP1 USB Data Host Positive 1 (Differential Pair) Input Input 16 mA I/O V20 USBHDN1 USB Data Host Negative 1 (Differential Pair) Input Input 16 mA I/O T17 USBHPWR USB Host Power LOW Input 16 mA O V17 USBHOVRCURR USB Host Overcurrent Input Input 16 mA I D11 nPWME0 DC-DC Converter PWM 0 Enable Input Input 8 mA I/O 5 A10 nPWME1 DC-DC Converter 1 PWM 1 Enable Input Input 8 mA I/O 5 C11 PWM0 DC-DC Converter 0 Output (Pulse Width Modulated) Input Input 8 mA I/O 4 4 C10 PWM1 DC-DC Converter 1 Output (Pulse Width Modulated) Input Input 8 mA I/O B9 PWM2 PWM Output 2 Input No Change 8 mA O D10 PWM3 PWM Output 3 Input No Change C9 PWMSYNC PWM Synchronizing Input for PWM2 Input No Change 8 mA I C7 ACBITCLK · Audio Codec (AC97) Clock · Audio Codec (ACI) Clock Input No Change 8 mA I/O B7 ACOUT · Audio Codec (AC97) Output · Audio Codec (ACI) Output LOW LOW 8 mA O A6 ACSYNC · Audio Codec (AC97) Synchronization · Audio Codec (ACI) Synchronization LOW LOW 8 mA O B6 ACIN · Audio Codec (AC97) Input · Audio Codec (ACI) Input Input No Change 8 mA I/O 5 A5 MMCCLK/ MMSPICLK · MultiMediaCard Clock (20 MHz MAX.) · SPI Mode Clock LOW LOW 8 mA I/O 4 D7 MMCCMD/ MMSPIDIN · MultiMediaCard Command · SPI Mode Data In Input Input 8 mA I/O 10 12/17/03 O Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA SIGNAL RESET STATE DESCRIPTION STANDBY STATE OUTPUT DRIVE I/O NOTES C6 MMCDATA0/ MMSPIDOUT · MultiMediaCard Data 0 · SPI Mode Data Out Input Input 8 mA I/O B5 MMCDATA1 MultiMediaCard Data 1 Input Input 8 mA I/O A4 MMCDATA2 MultiMediaCard Data 2 Input Input 8 mA I/O B4 MMCDATA3 MultiMediaCard Data 3 Input Input 8 mA I/O F2 UARTCTS2 UART2 Clear to Send Signal Input Input 8 mA I/O 5 F1 UARTDCD2 UART2 Data Carrier Detect Signal Input Input 8 mA I/O 5 G2 UARTDSR2 UART2 Data Set Ready Signal Input Input 8 mA I/O 5 G3 UARTIRTX1 IrDA Transmit LOW No Change 8 mA I/O 4 G1 UARTIRRX1 IrDA Receive Input Input 8 mA I/O 5 H2 UARTTX2 UART2 Transmit Data Output HIGH No Change 8 mA I/O 4 G4 UARTRX2 UART2 Receive Data Input Input Input 8 mA I/O 5 K3 SSPCLK Synchronous Serial Port Clock LOW LOW 8 mA O L1 SSPRX Synchronous Serial Port Receive Input Input 8 mA I/O L3 SSPTX Synchronous Serial Port Transmit Input INput 8 mA O K4 SSPFRM Synchronous Serial Port Frame Sync HIGH HIGH 8 mA O J2 COL0 H4 COL1 H5 COL2 J1 COL3 J3 COL4 Keyboard Interface HIGH HIGH 8 mA I/O 4 J4 COL5 J5 COL6 Input Input I 3 I 3 K2 COL7 E2 BATOK Battery OK 5 D1 nBATCHG Battery Change Input Input U12 BATCNTL Battery Control for A/D controller battery monitor. LOW No Change H1 KMIDAT Keyboard/Mouse data Input No Change 16 mA I/O H3 KMICLK Keyboard/Mouse clock Input No Change 16 mA I/O K1 TBUZ Timer Buzzer Output (254 kHz MAX.) LOW LOW 8 mA I/O Y16 AN0/UL/X+ · ADC channel 0 · Touch Screen Controller Upper Left · Touch Screen Controller X-plus Input Input I Y15 AN1/UR/X- · ADC channel 1 · Touch Screen Controller Upper Right · Touch Screen Controller X-minus Input Input I W14 AN2/LL/Y+ · ADC channel 2 · Touch Screen Controller Lower Left · Touch Screen Controller Y-plus Input Input I U13 AN3/LR/Y- · ADC channel 3 · Touch Screen Controller Lower Right · Touch Screen Controller Y-minus Input Input I V14 AN4/WIPER · ADC channel 4 · Wiper input from 5-wire Touch Screen Input Input I U14 AN5 ADC channel 5 Input Input I 16 mA O V15 AN6 ADC channel 6 Input Input I W15 AN7 ADC channel 7 Input Input I T13 AN8 ADC channel 8 Input Input 4 I Preliminary Data Sheet 12/17/03 11 LH7A404 LH7A404 32-Bit System-on-Chip Table 1. LH7A404 LH7A404 Functional Pin List (Cont'd) CABGA SIGNAL RESET STATE STANDBY STATE Input DESCRIPTION OUTPUT DRIVE Input I/O NOTES Y14 AN9 ADC channel 9 I E12 SCIO Smart Card Interface I/O LOW LOW 16 mA I/O A11 SCCLK Smart Card Interface Clock LOW LOW 16 mA I/O B11 nSCRESET Smart Card Interface Reset LOW LOW 16 mA O B10 SCVCCEN Smart Card Interface VCC Enable LOW No Change 16 mA O D6 CTCLKIN Counter Timer Clock Input Input No Change I A3 DREQ0 DMA Request 0 Input No Change I D5 DACK0 DMA Acknowledge 0 Input No Change 16 mA O C4 DEOT0 DMA End Of Transfer 0 Input No Change 16 mA I/O B3 DREQ1 DMA Request 1 Input No Change A2 DACK1 DMA Acknowledge 1 Input No Change 16 mA O E5 DEOT1 DMA End Of Transfer 1 Input No Change 16 mA I/O U16 nTEST0 Test Pin 0. Internally pulled up to VDD. Status latched at nPOR going HIGH. Pull LOW for JTAG mode. Pull HIGH (or leave open) for Normal mode. See Table 2. Input with pull-up Input with pull-up I W18 nTEST1 Test Pin 1. Internally pulled up to VDD. Status latched at nPOR going HIGH. Pull HIGH (or leave open) for both JTAG and Normal mode. See Table 2. Input with pull-up Input with pull-up I D3 TDI JTAG Data In. This signal should be pulled-up to VDD for normal operation Input No Change I C2 TCK JTAG Clock. This signal should be pulled-up to VDD Input No Change I 3 B1 TDO JTAG Data Out High Z No Change O 5 TMS JTAG Test Mode Select. This signal should be pulled-up to VDD Input No Change E3 I 4 mA I NOTES: 1. Signals beginning with `n' are Active LOW. 2. The SCLK pin can source up to 16 mA and sink up to 24 mA. See `DC Characteristics'. 3. Schmitt trigger input 4. Input only for JTAG boundary scan mode. 5. Output only for JTAG boundary scan mode. 6. These pins have alternate NAND Flash functions during boot-up when using the internal Boot ROM. Consult the Boot ROM Chapter of the User's Guide for more information. Table 2. nTEST Pin Function MODE nTEST1 nURESET JTAG 0 1 1 Normal 12 nTEST0 1 1 x 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 3. LCD Controller Pins STN CABGA PIN LCD SIGNAL K2 MONO 4-BIT LCDVD17 LCDVD17 SINGLE PANEL DUAL PANEL MONO 8-BIT SINGLE PANEL DUAL PANEL COLOR SINGLE PANEL TFT DUAL PANEL AD-TFT/ HR-TFT LOW K1 LCDVD16 LCDVD16 T13 LCDVD15 LCDVD15 MLSTN7 CLSTN7 Intensity Intensity LOW R12 LCDVD14 LCDVD14 MLSTN6 CLSTN6 BLUE4 BLUE4 R11 LCDVD13 LCDVD13 MLSTN5 CLSTN5 BLUE3 BLUE3 T12 LCDVD12 LCDVD12 MLSTN4 CLSTN4 BLUE2 BLUE2 T11 LCDVD11 LCDVD11 MLSTN3 CLSTN3 BLUE1 BLUE1 P10 LCDVD10 LCDVD10 MLSTN2 CLSTN2 BLUE0 BLUE0 K10 LCDVD9 MLSTN1 CLSTN1 GREEN4 GREEN4 M9 LCDVD8 CLSTN0 GREEN3 GREEN3 R10 LCDVD7 MLSTN3 MUSTN7 MUSTN7 MLSTN0 CUSTN7 CUSTN7 GREEN2 GREEN2 T10 LCDVD6 MLSTN2 MUSTN6 MUSTN6 CUSTN6 CUSTN6 GREEN1 GREEN1 K9 LCDVD5 MLSTN1 MUSTN5 MUSTN5 CUSTN5 CUSTN5 GREEN0 GREEN0 T9 LCDVD4 MLSTN0 MUSTN4 MUSTN4 CUSTN4 CUSTN4 RED4 RED4 T8 LCDVD3 MUSTN3 MUSTN3 MUSTN3 MUSTN3 CUSTN3 CUSTN3 RED3 RED3 R8 LCDVD2 MUSTN2 MUSTN2 MUSTN2 MUSTN2 CUSTN2 CUSTN2 RED2 RED2 P8 LCDVD1 MUSTN1 MUSTN1 MUSTN1 MUSTN1 CUSTN1 CUSTN1 RED1 RED1 M8 LCDVD0 MUSTN0 MUSTN0 MUSTN0 MUSTN0 CUSTN0 CUSTN0 RED0 RED0 · LCD TFT Data Enable · LCD STN AC Bias V9 LCDENAB/LCDM Y10 LCDDCLK T4 LCDFP/LCDSPS V2 LCDLP/LCDHRLP U3 LCDCLS ALI Clock for Row Drivers V3 LCDSPL ALI Start Pulse Left for reverse scanning U4 LCDUBL ALI Up, Down signal for reverse scanning W1 LCDSPR ALI Start Pulse Right for normal scanning LCD Pixel Clock · LCD Frame Pulse · ALI Reset Row Driver Counter · LCD Line Pulse · ALI Latch Pulse V4 LCDLBR ALI Output for reverse scanning W2 LCDMOD ALI MOD Signal used by the row driver V5 LCDPS Y1 LCDVDDEN W3 LCDREV U8 LCDCLKIN ALI Power Save ALI Power Sequence Control ALI Reverse External Clock Input for LCD controller NOTES: 1. The Intensity bit is identically generated for all three colors. 2. MU = Monochrome Upper Panel CU = Color Upper Panel CL = Color Lower Panel Preliminary Data Sheet 12/17/03 13 LH7A404 LH7A404 32-Bit System-on-Chip Table 6. UART Pins Table 4. MMC/SD Pins CABGA PIN SIGNAL FUNCTION CABGA PIN SIGNAL FUNCTION A5 MMCCLK/ MMSPICLK · MMC Clock · Reserved N4 PB0/ UARTRX1 · GPIO Port B0 · UART1 Receive Data Input D7 MMCCMD/ MMSPIDIN · MMC Command · Reserved P3 PB1/ UARTTX3 · GPIO Port B1 · UART3 Transmit Data Out C6 MMCDATA0/ MMSPIDOUT · MMC Data Channel 0 · Reserved P2 PB2/ UARTRX3 · GPIO Port B2 · UART3 Receive Data In B5 MMCDATA1 Data Channel 1 A4 MMCDATA2 Data Channel 2 P1 PB3/ UARTCTS3 · GPIO Port B3 · UART3 Clear to Send B4 MMCDATA3 Data Channel 3 R3 · GPIO Port B4 · UART3 Data Carrier Detect P19 nCS3/ nMMSPICS · Asynchronous Memory Chip Select 3 · Reserved PB4/ UARTDCD3 N5 PB5/ UARTDSR3 · GPIO Port B5 · UART3 Data Set Ready P4 PC0/ UARTTX1 · GPIO Port C0 · UART1 Transmit Data Output F2 UARTCTS2 UART2 Clear to Send Signal F1 UARTDCD2 UART2 Data Carrier Detect Signal G2 UARTDSR2 UART2 Data Set Ready Signal G3 UARTIRTX1 IrDA Transmit G1 UARTIRRX1 IrDA Receive. This pin is an output for JTAG boundary scan only. H2 UARTTX2 UART2 Transmit Data Output G4 UARTRX2 UART2 Receive Data Input. This pin is an output for JTAG boundary scan only. Table 5. Smart Card Pins CABGA PIN SIGNAL FUNCTION D4 PE4/ SCCLKIN · GPIO Port E4 · Smart Card Push-Pull Mode Clock Input C3 PE5/ SCCLKEN · GPIO Port E5 · Smart Card Push-Pull Mode External Clock Buffer Enable PE6/ SCIN · GPIO Port E6 · Smart Card Push-Pull Mode Data In B2 A1 PE7/ SCCLKIN · GPIO Port E7 · Smart Card Push-Pull Mode Data Out External Buffer Enable D8 PF5/ INT5/ SCDETECT · GPIO Port F5 · Interrupt 5 · Smart Card Interface Card Detect Signal E12 Smart Card Interface I/O SCCLK Smart Card Interface Clock B11 nSCRESET Smart Card Interface Reset B10 14 SCIO A11 SCVCCEN Smart Card Interface VCC Enable 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 7. PC Card/CompactFlash Pins CABGA PIN SIGNAL FUNCTION A7 PF6/ INT6/ PCRDY1 · GPIO Port F6 · Interrupt 6 · Card 1 ready for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode E8 PF7/ INT7/ PCRDY2 · GPIO Port F7 · Interrupt 7 · Card 2 ready for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode Y2 PG0/ nPCOE · GPIO Port G0 · Output Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode W4 PG1/ nPCWE · GPIO Port G1 · Write Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode Y3 PG2/ nPCIOR · GPIO Port G2 · I/O Read Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode U5 PG3/ nPCIOW · GPIO Port G3 · I/O Write Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode T5 PG4/ nPCREG · GPIO Port G4 · Register Memory Access for PC Card (PCMCIA or CompactFlash) in single or Dual Card mode W5 PG5/ nPCCE1 · GPIO Port G5 · Card Enable 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal and nPCCE2 are used by the PC Card for decoding low and high byte accesses. Y4 PG6/ nPCCE2 · GPIO Port G6 · Card Enable 2 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal and nPCCE1 are used by the PC Card for decoding low and high byte accesses. W6 PG7/ PCDIR · GPIO Port G7 · Direction for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode V6 PH0/ PCRESET1 · GPIO Port H0 · Reset Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode Y5 PH1/ CFA8/ PCRESET2 · GPIO Port H1 · Address Bit 8 for PC Card (CompactFlash) in Single Card mode · Reset Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode W7 PH2/ nPCSLOTE1 · GPIO Port H2 · Enable Card 1 for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode. This signal is used for gating other control signals to the appropriate PC Card. U6 · GPIO Port H3 PH3/ · Address Bit 9 for PC Card (CompactFlash) in Single Card mode CFA9/ · Address Bit 25 for PC Card (PCMCIA) in Single Card mode PCMCIAA25/ PCMCIAA25/ · Enable Card 2 for PC Card (PCMCIA or CompactFlash) in Dual Card mode. Used for gating other nPCSLOTE2 control signals to the appropriate PC Card. W8 PH4/ nPCWAIT1 · GPIO Port H4 · Card 1 WAIT signal for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode Y6 PH5/ CFA10/ CFA10/ PCMCIAA24/ PCMCIAA24/ nPCWAIT2 · · · · U7 PH7/ nPCSTATRE · GPIO Port H7 · Status Read Enable for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode Preliminary Data Sheet GPIO Port H5 Address Bit 10 for PC Card (CompactFlash) in Single Card mode Address Bit 24 for PC Card (PCMCIA) in Single Card mode Card 2 WAIT signal for PC Card (PCMCIA or CompactFlash) in Dual Card mode 12/17/03 15 LH7A404 LH7A404 32-Bit System-on-Chip Table 8. Synchronous Serial Port Pins Table 12. PWM/DC-DC Converter Pins CABGA PIN SIGNAL K3 SSPCLK Synchronous Serial Port Clock D11 nPWME0 DC-DC Converter PWM 0 Enable L1 SSPRX Synchronous Serial Port Receive A10 nPWME1 DC-DC Converter 1 PWM 1 Enable C11 PWM0 DC-DC Converter 0 Output (Pulse Width Modulated) C10 PWM1 DC-DC Converter 1 Output (Pulse Width Modulated) L3 SSPTX K4 SSPFRM FUNCTION CABGA PIN Synchronous Serial Port Transmit Synchronous Serial Port Frame Sync Table 9. Battery Monitor Interface Pins R1 FUNCTION SIGNAL FUNCTION PB6/SWID/SMBD PB7/SMBCLK B9 PWM2 PWM Output 2 D10 PWM3 PWM Output 3 C9 CABGA PIN R2 SIGNAL PWMSYNC PWM Synchronizing Input for PWM2 · GPIO Port B6 · Single Wire Data · Smart Battery Data · GPIO Port B7 · Smart Battery Clock Table 13. A/D Converter/Touch Screen Controller Pins CABGA PIN Table 10. USB Host and USB Device Pins SIGNAL FUNCTION Y16 CABGA PIN SIGNAL AN0/ UL/X+ · ADC channel 0 · Touch Screen Controller Upper Left · Touch Screen Controller X-plus Y15 AN1/ UR/X- · ADC channel 1 · Touch Screen Controller Upper Right · Touch Screen Controller X-minus W14 AN2/ LL/Y+ · ADC channel 2 · Touch Screen Controller Lower Left · Touch Screen Controller Y-plus FUNCTION U17 USBDCP USB Device Device Full Speed Pull-up Resistor Control U20 USBDP USB Device Data Positive (Differential Pair) U19 USBDN USB Device Data Negative (Differential Pair) W19 USBHDP0 USB Data Host Positive 0 (Differential Pair) U13 AN3/ LR/Y- · ADC channel 3 · Touch Screen Controller Lower Right · Touch Screen Controller Y-minus W20 USBHDN0 USB Data Host Negative 0 (Differential Pair) V14 AN4/ WIPER · ADC channel 4 · Wiper input from 5-wire Touch Screen V19 USBHDP1 USB Data Host Positive 1 (Differential Pair) U14 AN5 ADC channel 5 V15 AN6 ADC channel 6 USBHDN1 USB Data Host Negative 1 (Differential Pair) W15 AN7 ADC channel 7 T13 AN8 ADC channel 8 Y14 AN9 ADC channel 9 V20 T17 USBHPWR USB Host Power V17 USBHOVRCURR USB Host Overcurrent Table 14. KMI and Keyboard Interface Pins Table 11. ACI and AC97 Pins SIGNAL FUNCTION V7 PH6/ nAC97RESET ACBITCLK ACOUT G1 KMIDAT Keyboard / Mouse data H3 H3 KMICLK Keyboard / Mouse clock J2 H2 COL0 H4 H1 COL1 · Audio Codec (AC97) Output · Audio Codec (ACI) Output A6 B6 16 SIGNAL · Audio Codec (AC97) Clock · Audio Codec (ACI) Clock B7 PBGA PIN · GPIO Port H6 · AC97 Reset C7 CABGA PIN H1 CABGA PIN ACSYNC COL3 J2 COL4 J4 J1 COL5 J5 K4 COL6 K2 12/17/03 COL2 J3 J3 · Audio Codec (AC97) Input · Audio Codec (ACI) Input J4 J1 · Audio Codec (AC97) Synchronization · Audio Codec (ACI) Synchronization ACIN H5 K2 FUNCTION COL7 Keyboard Interface Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 15. CABGA Numerical Pin List CABGA SIGNAL Table 15. CABGA Numerical Pin List (Cont'd) SLEW RATE OUTPUT DRIVE CABGA 95 mA/ns 16 mA C6 ACBITCLK SIGNAL SLEW RATE OUTPUT DRIVE 110 mA/ns 8 mA A1 PE7 A2 DACK1 95 mA/ns 16 mA C7 PF3/INT3 110 mA/ns 8 mA A3 DREQ0 110 mA/ns 8 mA C8 PWMSYNC 110 mA/ns 8 mA A4 MMCDATA2 110 mA/ns 8 mA C9 PWM1 110 mA/ns A5 MMCCLK/MMSPICLK 110 mA/ns 8 mA C10 PWM0 110 mA/ns A6 ACSYNC 110 mA/ns 8 mA C11 nOE 110 mA/ns 8 mA A7 PF6/INT6/PCRDY1 110 mA/ns 8 mA C12 nBLE3 95 mA/ns 16 mA A8 PF2/INT2 110 mA/ns 8 mA C13 SCKE3 110 mA/ns 8 mA A9 PF0/INT0 110 mA/ns 8 mA C14 nCAS 95 mA/ns 16 mA A10 nPWME1 95 mA/ns 16 mA C15 D27 95 mA/ns 16 mA A11 SCCLK 95 mA/ns 16 mA C16 nSCS0 95 mA/ns 16 mA A12 DQM3 110 mA/ns 8 mA C17 D24 95 mA/ns 16 mA A13 nBLE0 95 mA/ns 16 mA C18 A22 95 mA/ns 16 mA A14 SCKE0 95 mA/ns 16 mA C19 D21 95 mA/ns 16 mA A15 nRAS 95 mA/ns 16 mA C20 nBATCHG 95 mA/ns 16 mA A16 A25 95 mA/ns 16 mA D1 nPOR A17 D30 95 mA/ns 16 mA D2 TDI A18 D29 95 mA/ns 16 mA D3 PE4 A19 D25 95 mA/ns 16 mA D4 D25 95 mA/ns 16 mA 95 mA/ns 16 mA A20 TDO 95 mA/ns 16 mA D5 DACK0 B1 PE6 100 mA/ns 4 mA D6 8 mA CTCLKIN B2 DREQ1 95 mA/ns 16 mA D7 MMCCMD/MMSPIDIN 110 mA/ns 8 mA B3 MMCDATA3 110 mA/ns 110 mA/ns D8 PF5/INT5/SCDETECT 110 mA/ns 8 mA B4 MMCDATA1 110 mA/ns 110 mA/ns D9 PF1/INT1 110 mA/ns 8 mA B5 ACIN 110 mA/ns 110 mA/ns D10 PWM3 110 mA/ns 8 mA B6 ACOUT 110 mA/ns 110 mA/ns D11 nPWME0 110 mA/ns 8 mA B7 PF4/INT4 110 mA/ns 110 mA/ns D12 nWE 95 mA/ns 16 mA B8 PWM2 110 mA/ns 110 mA/ns D13 DQM0 95 mA/ns 16 mA B9 SCVCCEN 110 mA/ns 110 mA/ns D14 SCLK 190 mA/ns 24 mA B10 nSCRESET 95 mA/ns 95 mA/ns D15 A26 95 mA/ns 16 mA B11 DQM2 95 mA/ns 95 mA/ns D16 nSCS2 95 mA/ns 16 mA B12 SCKE1_2 95 mA/ns 95 mA/ns D17 A23 95 mA/ns 16 mA B13 A27 95 mA/ns 95 mA/ns D18 D22 95 mA/ns 16 mA B14 D31 95 mA/ns 95 mA/ns D19 A20 95 mA/ns 16 mA B15 nSWE 95 mA/ns 95 mA/ns D20 D19 95 mA/ns 16 mA B16 D28 95 mA/ns 95 mA/ns E1 nURESET B17 D26 95 mA/ns 95 mA/ns E2 BATOK B18 A24 95 mA/ns 95 mA/ns E3 TMS B19 D23 95 mA/ns 95 mA/ns E4 MEDCHG B20 nEXTPWR 95 mA/ns 95 mA/ns E5 DEOT1 95 mA/ns 16 mA C1 TCK E6 VSSC 110 mA/ns 8 mA C2 PE5 C3 DEOT0 C4 nRESETOUT 95 mA/ns 16 mA E9 VDDC C5 MMCDATA/MMSPIDOUT 95 mA/ns 16 mA E10 VDD Preliminary Data Sheet E7 95 mA/ns 12/17/03 VDDC E8 16 mA PF7 17 LH7A404 LH7A404 32-Bit System-on-Chip Table 15. CABGA Numerical Pin List (Cont'd) CABGA SIGNAL SLEW RATE OUTPUT DRIVE Table 15. CABGA Numerical Pin List (Cont'd) SLEW RATE OUTPUT DRIVE COL5 100 mA/ns 8 mA 100 mA/ns 8 mA CABGA J4 SIGNAL E11 VDD E12 SCIO 95 mA/ns 16 mA J5 COL6 E13 DQM1 95 mA/ns 16 mA J9 VSS E14 VDDC J10 VSS E15 VSSC J11 VSS E16 nSCS3 95 mA/ns 16 mA J12 VSS E17 A21 95 mA/ns 16 mA J16 VSSC E18 D20 95 mA/ns 16 mA J17 A12/SA10 A12/SA10 95 mA/ns 16 mA E19 D18 95 mA/ns 16 mA J18 D11 95 mA/ns 16 mA E20 D17 95 mA/ns 16 mA J19 D9 95 mA/ns 16 mA F1 UARTDCD2 110 mA/ns 8 mA J20 A10/SA8 A10/SA8 95 mA/ns 16 mA F2 UARTCTS2 110 mA/ns 8 mA K1 TBUZ 110 mA/ns 8 mA F3 WAKEUP K2 COL7 100 mA/ns 8 mA F4 nPWRFL K3 SSPCLK 110 mA/ns 8 mA F5 VSSC K4 SSPFRM 110 mA/ns 8 mA K5 VDD K8 VDD F16 VSSC F17 A19 95 mA/ns 16 mA F18 A17/SBANK1 A17/SBANK1 95 mA/ns 16 mA K9 VSS F19 D16 95 mA/ns 16 mA K10 VSS F20 A14/SA12 A14/SA12 95 mA/ns 16 mA K11 VSS G1 UARTIRRX1 110 mA/ns 8 mA K12 VSS G2 UARTDSR2 110 mA/ns 8 mA K13 VDD G3 UARTIRTX1 110 mA/ns 8 mA K16 VDD G4 UARTRX2 110 mA/ns 8 mA K17 D10 95 mA/ns 16 mA G5 VDDC K18 A7/SA5 95 mA/ns 16 mA G16 VDDC K19 A9/SA7 95 mA/ns 16 mA G17 A18 95 mA/ns 16 mA K20 A8/SA6 95 mA/ns 16 mA G18 A15/SA13 A15/SA13 95 mA/ns 16 mA L1 SSPRX 110 mA/ns 8 mA G19 D14 95 mA/ns 16 mA L2 PGMCLK 110 mA/ns 8 mA G20 D13 95 mA/ns 16 mA L3 SSPTX 110 mA/ns 8 mA KMIDAT 95 mA/ns 16 mA L4 PA1/LCDVD17 PA1/LCDVD17 110 mA/ns 8 mA H2 UARTTX2 110 mA/ns 8 mA L5 VDD H3 KMICLK 95 mA/ns 16 mA L8 VDD H4 COL1 100 mA/ns 8 mA L9 VSS H5 COL2 100 mA/ns 8 mA L10 VSS H10 VDD L11 VSS H11 VDD L12 VSS H1 H16 A16/SBANK0 A16/SBANK0 95 mA/ns 16 mA L13 VDD H17 D15 95 mA/ns 16 mA L16 VDD H18 A13/SA11 A13/SA11 95 mA/ns 16 mA L17 D7 95 mA/ns 16 mA H19 D12 95 mA/ns 16 mA L18 D6 95 mA/ns 16 mA H20 95 mA/ns 16 mA L19 D8 95 mA/ns 16 mA COL3 100 mA/ns 8 mA L20 A5/SA3 95 mA/ns 16 mA J2 COL0 100 mA/ns 8 mA M1 PA4 110 mA/ns 8 mA J3 18 A11/SA9 A11/SA9 J1 COL4 100 mA/ns 8 mA M2 PA0/LCDVD16 PA0/LCDVD16 110 mA/ns 8 mA 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Table 15. CABGA Numerical Pin List (Cont'd) CABGA SIGNAL Table 15. CABGA Numerical Pin List (Cont'd) SLEW RATE OUTPUT DRIVE CABGA SIGNAL SLEW RATE OUTPUT DRIVE M3 PA2 110 mA/ns 8 mA T2 PC2 95 mA/ns 16 mA M4 PA3 110 mA/ns 8 mA T3 PC3 95 mA/ns 16 mA M5 VSSC T4 LCDFP/LCDSPS 95 mA/ns 16 mA 110 mA/ns 8 mA M9 VSS T5 PG4/nPCREG M10 VSS T6 VSSC M11 VSS T7 VDDC M12 VSS T8 LCDVD1 95 mA/ns 16 mA M16 D4 95 mA/ns 16 mA T9 PE3/LCDVD7 95 mA/ns 16 mA M17 A6/SA4 95 mA/ns 16 mA T10 VDD M18 D5 95 mA/ns 16 mA T11 VDD M19 A3/SA1 95 mA/ns 16 mA T12 VDDC M20 A4/SA2 95 mA/ns 16 mA T13 AN5 N1 PA7 110 mA/ns 8 mA T14 VDDC N2 PA6 110 mA/ns 8 mA T15 VSSC N3 PA5 110 mA/ns 8 mA T16 CLKEN 110 mA/ns 8 mA N4 PB0/UARTRX1 110 mA/ns 8 mA T17 USBHPWR 95 mA/ns 16 mA N5 PB5/UARTDSR3 110 mA/ns 8 mA T18 VSS N10 VDD T19 XTAL32IN XTAL32IN N11 VDD T20 XTAL32OUT XTAL32OUT N16 A1 95 mA/ns 16 mA U1 PC5 95 mA/ns 16 mA N17 A2/SA0 95 mA/ns 16 mA U2 PC6 95 mA/ns 16 mA N18 D2 95 mA/ns 16 mA U3 LCDCLS 95 mA/ns 16 mA N19 D0 95 mA/ns 16 mA U4 LCDUBL 95 mA/ns 16 mA U5 PG3/nPCIOW 110 mA/ns 8 mA 110 mA/ns 8 mA 110 mA/ns 8 mA 95 mA/ns 16 mA N20 D3 95 mA/ns 16 mA P1 PB3/UARTCTS3 110 mA/ns 8 mA P2 PB2/UARTRX3 110 mA/ns 8 mA P3 PB1/UARTTX3 110 mA/ns 8 mA P4 PC0/UARTTX1 95 mA/ns 16 mA P5 VDDC P16 VDDC P17 A0 95 mA/ns P18 nWAIT 95 mA/ns P19 nCS3/nMMCSPICS 95 mA/ns 16 mA P20 D1 95 mA/ns 16 mA U13 AN3/LR/Y- R1 PB7/SMBCLK 110 mA/ns 8 mA U14 AN5 R2 PB6/SWID/SMBD 110 mA/ns 8 mA U15 VSSA R3 PB4/UARTDCD3 110 mA/ns 8 mA U16 nTEST0 R4 PC4 95 mA/ns 16 mA U17 USBDCP R5 VSSC 110 mA/ns 8 mA U18 VDD PH3/CFA9/PCMCIAA25/ PH3/CFA9/PCMCIAA25/ U6 nPCSLOTE2 U7 PH7/nPCSTATRE U8 LCDCLKIN U9 nBLE1 U10 PD1/LCDVD9 U11 PD5/LCDVD13 PD5/LCDVD13 U12 16 mA BATCTL R16 VSSC U19 USBDN R17 nCS7 95 mA/ns 16 mA U20 USBDP R18 nCS2 95 mA/ns 16 mA V1 PC7 95 mA/ns 16 mA R19 nCS1 95 mA/ns 16 mA V2 LCDLP/LCDHRLP 95 mA/ns 16 mA R20 nCS6 95 mA/ns 16 mA V3 LCDSPL 95 mA/ns 16 mA T1 PC1 95 mA/ns 16 mA V4 LCDLBR 95 mA/ns 16 mA Preliminary Data Sheet 12/17/03 19 LH7A404 LH7A404 32-Bit System-on-Chip Table 15. CABGA Numerical Pin List (Cont'd) Table 15. CABGA Numerical Pin List (Cont'd) SLEW RATE OUTPUT DRIVE CABGA SLEW RATE OUTPUT DRIVE LCDPS 95 mA/ns 16 mA W13 V6 PH0/PCRESET1 110 mA/ns 8 mA W14 AN2/LL/Y+ V7 PH6/NAC97RESET PH6/NAC97RESET 110 mA/ns 8 mA W15 AN7 V8 LCDVD0 95 mA/ns 16 mA W16 VDDAD V9 LCDENAB/LCDM 95 mA/ns 16 mA W17 VDDA V10 PE2/LCDVD6 95 mA/ns 16 mA W18 nTEST1 V11 PD3/LCDVD11 PD3/LCDVD11 95 mA/ns 16 mA W19 USBHDP0 V12 PD6/LCDVD14 PD6/LCDVD14 95 mA/ns 16 mA W20 V13 VSSAD Y1 LCDVDDEN 95 mA/ns 16 mA V14 AN4/WIPER V15 AN6 Y2 PG0/nPCOE 110 mA/ns 8 mA Y3 PG2/nPCIOR 110 mA/ns 8 mA V16 V17 VSSA Y4 PG6/nPCCE2 110 mA/ns 8 mA USBHOVRCURR Y5 PH1/CFA8/PCRESET2 110 mA/ns 8 mA V18 nCS0 V19 USBHDP1 Y6 PH5/CFA10/PCMCIAA24/ PH5/CFA10/PCMCIAA24/ 110 mA/ns 8 mA Y7 nPCWAIT2 95 mA/ns 16 mA CABGA V5 SIGNAL V20 LCDSPR W2 W3 16 mA USBHDN1 W1 95 mA/ns SIGNAL BOOTWIDTH1 USBHDN0 Y8 nBLE2 95 mA/ns 16 mA 95 mA/ns 16 mA Y9 LCDVD3 95 mA/ns 16 mA LCDMOD 95 mA/ns 16 mA Y10 PE0/LCDVD4 95 mA/ns 16 mA LCDREV 95 mA/ns 16 mA Y11 LCDDCLK 95 mA/ns 16 mA W4 PG1/nPCWE 110 mA/ns 8 mA Y12 PD0/LCDVD8 95 mA/ns 16 mA W5 PG5/nPCCE1 110 mA/ns 8 mA Y13 PD7/LCDVD15 PD7/LCDVD15 W6 PG7/PCDIR 110 mA/ns 8 mA Y14 BOOTWIDTH0 W7 PH2/nPCSLOTE1 110 mA/ns 8 mA Y15 AN9 W8 PH4/nPCWAIT1 110 mA/ns 8 mA Y16 AN1/UR/X W9 LCDVD2 95 mA/ns 16 mA Y17 AN0/UL/X+ W10 PE1/LCDVD5 95 mA/ns 16 mA Y18 VDDA W11 PD4/LCDVD12 PD4/LCDVD12 95 mA/ns 16 mA Y19 XTALIN W12 PD2/LCDVD10 PD2/LCDVD10 95 mA/ns 16 mA Y20 XTALOUT 20 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 ROM FLASH 1 2 3 4 5 6 7 8 9 * 0 # SMART CARD SRAM STN/TFT/ AD-TFT GPIO SSP UART SCI TOUCH SCREEN CONTR. SDRAM LH7A404 LH7A404 MMC/SD MULTIMEDIA CARD DMA COMPACT FLASH CODEC AC97 PC CARD PCMCIA IR DEVICE HOST BMI DC to DC USB HOST BATTERY VOLTAGE GENERATION CIRCUITRY LH7A404-2 LH7A404-2 Figure 2. Application Diagram SYSTEM DESCRIPTIONS ARM922T ARM922T Processor The LH7A404 LH7A404 microcontroller features the ARM922T ARM922T cached core with an Advanced High-performance Bus (AHB) interface. The processor is a member of the ARM9T family of processors. For more information, see the ARM document, `ARM922T ARM922T Technical Reference Manual', available on ARM's website at www.arm.com. Clock and State Controller The clocking scheme in the LH7A404 LH7A404 is based around two primary oscillator inputs. These are the 14.7456 MHz input crystal and the 32.768 kHz real time clock oscillator; see Figure 3. The 14.7456 MHz oscillator supplies the main system clock domains for the LH7A404 LH7A404. The 32.768 kHz oscillator controls the power-down operations and real time clock peripheral. The clock and state controller provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and rest of the system. The amount of clock gating that actually takes place depends on the power saving mode selected. Preliminary Data Sheet The 32.768 kHz clock provides the source for the Real Time Clock tree and power-down logic. This clock is used for the power state control and is the only clock in the LH7A404 LH7A404 that runs continuously. The 32.768 kHz clock is divided down to 1 Hz for the Real Time Clock counter using a ripple divider to save power. The 14.7456 MHz source is used to generate the main system clocks for the LH7A404 LH7A404. It is the source for PLL1 and PLL2, the primary clock for the peripherals, and the source clock to the programmable clock (PGM) divider. PLL1 provides the main clock tree for the chip. It generates the following clocks: FCLK, HCLK, and PCLK. FCLK is the clock that drives the ARM922T ARM922T core. HCLK is the main bus (AHB) clock, as such it clocks all memory interfaces, bus arbitrators and the AHB peripherals. HCLK is generated by dividing FCLK by 1, 2, 3, or 4. HCLK can be gated by the system to enable low power operation. PCLK is the peripheral bus (APB) clock. It is generated by dividing HCLK by either 2, 4, or 8. PLL2 generates a fixed 48 MHz clock signal for the USB peripheral. 12/17/03 21 LH7A404 LH7A404 32-Bit System-on-Chip Power Modes Data Paths The LH7A404 LH7A404 has three operational states: Run, Halt, and Standby. During Run all clocks are hardware enabled and the processor is clocked. In the Halt mode the device is functioning, but the processor clock is halted while it waits for an event such as a key press. Standby equates to the computer being switched `off', i.e. no display (LCD disabled) and the main oscillator is shut down. Reset Modes Three external signals can generate resets to the LH7A404 LH7A404: nPOR (power on reset), nPWRFL (power failure) and nURESET (user reset). If any of these are active, a system reset is internally generated. An nPOR reset performs a full system reset. The nPWRFL and nURESET resets perform a full system reset except for the SDRAM refresh control, SDRAM Global Configuration, SDRAM Device Configuration, and the RTC peripheral registers. The SDRAM controller issues a self-refresh command to external SDRAM before the system enters an nPWRFL and nURESET reset. This allows the system to maintain its Real Time Clock and SDRAM contents. Upon release of Reset, the chip enters Standby mode. Once in the Run mode the PWRSR register can be interrogated to determine the nature of the reset and the trigger source, after which software can then take appropriate actions. PLL1 14.7456 MHz IN DIVIDE BY PREDIV+2 MUST BE BETWEEN 80 and 400 MHz VCO The data paths in the LH7A404 LH7A404 are: · The AMBA AHB bus · The AMBA APB bus · The External Bus Interface · The LCD AHB bus · The DMA busses. AMBA AHB BUS The Advanced Microprocessor Bus Architecture AHB (AMBA AHB) is a high speed 32-bit-wide data bus. The AMBA AHB is for high-performance, high-clock-frequency system modules. Peripherals with high bandwidth requirements are connected to the LH7A404 LH7A404 core processor using the AHB bus, Vectored Interrupt Controllers, and USB Device. These include the external and internal memory interfaces, the LCD registers, palette RAM and the bridge to the Advanced Peripheral Bus (APB) interface. The APB Bridge transparently converts the AHB access into the slower speed APB accesses. All control registers for the APB peripherals are programmed using the AHB-to-APB bridge interface. The main AHB data and address lines are configured using a multiplexed bus. This removes the need for tri-state buffers and bus holders and simplifies bus arbitration. GATE DIVIDE BY 2PS 200 MHz MAX. GCLK GATE HCLKDIV 500 kHz MIN. 32.768 kHz RTC OSC RTC HCLK_CPU HCLK PCLKDIV MAIN DIVIDER 1: MAIN DIVIDER 2: DIVIDE BY MAINDIV1+2 DIVIDE BY MAINDIV2+2 FCLK PCLK 32.768 kHz LH7A404-6 LH7A404-6 Figure 3. Clock and State Controller Block Diagram 22 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 AMBA APB BUS The AMBA APB bus is a low speed 32-bit-wide peripheral data bus. The speed of the APB bus is selected by dividing the clock speed of the AHB bus by two, four, or eight. EXTERNAL BUS INTERFACE (EBI) The External Bus Interface (EBI) provides a 32-bitwide, high speed gateway to external memory devices. The supported memory devices include: · Asynchronous RAM/ROM/Flash · Synchronous DRAM/Flash · PCMCIA interfaces · CompactFlash interfaces. The EBI can be controlled by either the Asynchronous Memory Controller or Synchronous Memory Controller. There is an arbiter on the EBI input, with priority given to the Synchronous Memory Controller interface. LCD BUS The LCD controller has its own local memory bus that connects it to the system's embedded memory and external SDRAM. The function of this local data bus is to allow the LCD controller to perform its video refresh function without congesting the main AHB bus. This leads to better system performance and lower power consumption. There is an arbiter on both the embedded memory and the synchronous memory controller. In both cases the LCD bus is given priority. Memory Map The LH7A404 LH7A404 system has a 32-bit-wide address bus, allowing addressing up to 4GB of memory. This memory space is subdivided into a number of memory banks, shown in Figure 4. Four of these banks (each 256MB 256MB) are allocated to the Synchronous Memory Controller. Eight banks (each 256MB 256MB) are allocated to the Asynchronous Memory Controller. Two of these eight banks are designed for PCMCIA systems. Part of the remaining memory space is allocated to the embedded SRAM, and to the control registers of the AHB and APB. The rest of the memory space is not used. The LH7A404 LH7A404 can boot from either synchronous or asynchronous ROM/Flash. The selection is determined by the value of the MEDCHG pin at power-on reset as shown in Table 16. When booting from synchronous memory, bank 4 (nSCS3) is mapped into memory location zero. When booting from asynchronous memory, memory bank 0 (nSCS0) is mapped into memory location zero. Figure 4 shows the memory map of the LH7A404 LH7A404 system for the two boot modes. Once the LH7A404 LH7A404 has booted, the boot code can configure the ARM922T ARM922T MMU to remap the low memory space to a location in RAM. This allows the user to set the interrupt vector table. Table 16. Boot Modes LATCHED BOOTWIDTH1 LATCHED BOOTWIDTH0 LATCHED MEDCHG 8-bit ROM 0 0 0 16-bit ROM 0 1 0 32-bit ROM 1 0 0 32-bit ROM 1 1 0 16-bit SFlash (Initializes Mode Register) 0 0 1 16-bit SROM (Initializes Mode Register) 0 1 1 32-bit SFlash (Initializes Mode Register) 1 0 1 32-bit SROM (Initializes Mode Register) 1 1 1 BOOT MODES DMA BUSES The LH7A404 LH7A404 has a DMA system which connects the higher speed/higher data volume APB peripherals (MMC, USB and AC97) to the AHB bus. This enables the efficient transfer of data between these peripherals and external memory without the intervention of the ARM922T ARM922T core. The DMA engine does not support memory-to-memory transfers. USB HOST CONTROLLER DMA BUS The USB Host Controller has its own DMA controller. It acts as another bus master on the AHB bus. It does not interact with the non-USB DMA controller except in bus arbritration. Preliminary Data Sheet 12/17/03 23 LH7A404 LH7A404 32-Bit System-on-Chip ASYNC. MEM (nCS0) F000.0000 E000.0000 D000.0000 C000.0000 B001.4000 B000.0000 8000.3800 8000.2000 8000.0000 7000.0000 6000.0000 5000.0000 4000.0000 3000.0000 2000.0000 1000.0000 SYNC. MEM (nSDCE3) 256MB 256MB SYNC. MEM (nSDCE2) SYNC. MEM (nSDCE2) 256MB 256MB SYNC. MEM (nSDCE1) SYNC. MEM (nSDCE1) 256MB 256MB SYNC. MEM (nSDCE0) SYNC. MEM (nSDCE0) 256 MB NOT USED NOT USED EMBEDDED SRAM EMBEDDED SRAM NOT USED NOT USED AHB INTERNAL REGISTERS AHB INTERNAL REGISTERS APB INTERNAL REGISTERS APB INTERNAL REGISTERS ASYNC. MEM (nCS7) ASYNC. MEM (nCS7) 256MB 256MB ASYNC. MEM (nCS6) ASYNC. MEM (nCS6) 256MB 256MB PCMCIA (SLOT1) PCMCIA (SLOT1) 256MB 256MB PCMCIA (SLOT0) PCMCIA (SLOT0) 256MB 256MB ASYNC. MEM (nCS3) ASYNC. MEM (nCS3) 256MB 256MB ASYNC. MEM (nCS2) ASYNC. MEM (nCS2) 256MB 256MB ASYNC. MEM (nCS1) ASYNC. MEM (nCS1) 256MB 256MB SYNC. ROM (nSDCE3) ASYNC. ROM (nCS0) 256MB 256MB 80KB 0000.0000 ASYNC. MEMORY BOOT SYNC. MEMORY BOOT LH7A404-7 LH7A404-7 Figure 4. Memory Mapping for Each Boot Mode Vectored Interrupt Controller (VIC) The LH7A404 LH7A404 has two VIC modules that work together to manage interrupt requests from on-chip peripherals and off-chip sources. Each VIC performs these primary functions: · Determine if an interrupt source is disabled or can generate an FIQ or IRQ to the ARM core · Prioritize up to 16 separate interrupt sources for simultaneous and nested processing · Obtain the address of the interrupt handler (vector) for up to 16 interrupt sources · Provide a default vector and a set of status registers for up to 16 non-vectored sources. Software determines the priority of these interrupts. Two VICs are daisy-chained together to support up to 64 different interrupts, 32 of which are vectored. The VIC supports both FIQ and IRQ interrupts. FIQ inter- 24 rupts have a higher priority than IRQ interrupts. If two interrupts with the same priority become active at the same time, the priority must be resolved in software. When an interrupt becomes active, the VIC generates an FIQ or IRQ if the corresponding mask bit is set. Interrupts are not latched in the VIC, but may latch on a particular peripheral when applicable. After a power-on reset, all mask register bits are cleared, masking all interrupts. They must be set by software after power-on reset to enable interrupts. A vectored interrupt has improved latency as it provides direct information about where its service routine is located and eliminates software arbitration needed with a simple interrupt controller. The VICs continue to operate in Halt and Standby modes, so external interrupts may bring the chip out of these low power modes. 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 External Bus Interface The ARM922T ARM922T, LCD controller, and DMA engine have access to an external memory system. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in Synchronous Memory for large displays. The processor and DMA engine share the main system bus, providing access to all external memory devices and the embedded SRAM frame buffer. An arbitration unit ensures that control over the External Bus Interface (EBI) is only granted when an existing access has been completed. See Figure 5. ASYNCHRONOUS MEMORY CONTROLLER ARBITER DMA CONTROLLER SRAM SDRAM ARM922T ARM922T SDRAM ROM DATA EXTERNAL BUS ADDRESS/ INTERFACE CONTROL (EBI) LCD CONTROLLER LCD MMU EMBEDDED SRAM 80KB USB HOST BUS ARBITER SYSTEM AHB BUS SYNCHRONOUS MEMORY CONTROLLER LCD AHB BUS LH7A404-8 LH7A404-8 Figure 5. External Bus Interface Block Diagram Preliminary Data Sheet 12/17/03 25 LH7A404 LH7A404 32-Bit System-on-Chip Embedded SRAM SDRAM (Synchronous) Memory Controller The LH7A404 LH7A404 incorporates 80KB of embedded SRAM. This embedded memory is used for storing code, data, or LCD frame data and is contiguous with external SDRAM. The 80KB is large enough to store a QVGA frame (320 × 240) at 8 bits per pixel, equivalent to 70KB of information. The SDRAM (Synchronous) Memory Controller provides a high speed memory interface to a wide variety of synchronous memory devices, including Synchronous DRAM, Synchronous Flash and Synchronous ROMs. Locating the frame buffer on chip reduces the overall power consumed by LH7A404 LH7A404 applications. Normally, the system performs external accesses to acquire this data. The LCD controller automatically uses an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any 4KB page boundary in SDRAM, allowing software to set the MMU (in the LCD controller) page tables so the two memory areas appear contiguous. Byte, half-word and word accesses are permissible. Static Memory Controller (SMC) The asynchronous Static Memory Controller (SMC) provides an interface between the AMBA AHB system bus and external (off-chip) memory devices. The SMC simultaneously supports up to eight independently configurable memory banks. Each memory bank can support: · SRAM · ROM · Flash EPROM Each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. The memory controller can be configured to support either littleendian or big-endian operation. The memory banks can be configured to support: · Non-burst read and write accesses only to highspeed CMOS static RAM · Non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. · · · · · · · LCD DMA port for high bandwidth · Up to four Synchronous Memory banks can be independently set up · Includes special configuration bits for Synchronous ROM operation · Includes ability to program Synchronous Flash devices using write and erase commands · On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset · Data is transferred between the controller and the Synchronous DRAM in four-word bursts. Longer transfers within the same page are concatenated, forming a seamless burst · Programmable for 16- or 32-bit data bus size · Two reset domains enable Synchronous DRAM contents to be preserved over a `soft' reset · Power saving Synchronous Memory SCKE and external clock modes provided. Secure Digital/MultiMediaCard (MMC) · Burst ROM memory. The SMC has six main functions: The key features of the controller are: The SD Memory Card is a flash-based memory card that meets the security, capacity, performance, and environment requirements inherent in electronic devices. The SD Memory Card host supports MultiMediaCard (MMC) operation as well and is compatible with MMC Cards. The SD/MMC controller can be used as an MMC card controller or as an SD Card controller, and supports the full SD/MMC bus protocol as defined in the MMC system specification 2.11 provided by the MMC Association and the SD Memory Card Spec v1.0 from the SD Association. Memory bank select Access sequencing Wait state generation Byte lane write control External bus interface CompactFlash or PCMCIA interfacing. 26 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 SD/MMC INTERFACE DESCRIPTION The SD/MMC controller uses the three-wire signal bus (clock, command, and data) to input and output data to and from the MMC, and to configure and acquire status information from the card. The SD controller differs in that it has four data lines instead of one. PROGRAMMABLE PARAMETERS · Smart Card clock frequency The SD/MMC bus lines can be divided into three groups: · Maximum time for first character of Answer to Reset (ATR) reception checking · Power supply: VSS1, VSS2, and VDD · Maximum ATR character stream duration checking · Data transfer group: MMCCMD, MMCDATA0, MMCDATA1, MMCDATA2, MMCDATA3 (for MMC, do not use MMCDATA1, MMCDATA2, MMCDATA3) · Maximum time of receipt of first character of data stream checking · Clock: MMCCLK · Character guard time MMC CONTROLLER The MMC controller implements MMC-specific functions, serves as the bus master for the MMC Bus and implements the standard interface to the MMC (card initialization, CRC generation and validation, command/response transactions, etc.). · Block guard time Smart Card Interface (SCI) The SCI (ISO7816 ISO7816) connects to an external Smart Card reader. The SCI can autonomously control data transfer to and from the Smart Card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. · Communication baud rate · Protocol convention · Card activation/deactivation time · Maximum time allowed between characters checking · Transmit/receive character retry. Direct Memory Access Controller (DMA) The DMA Controller can be used to interface streams from 20 internal peripherals to the system memory using 10 fully-independent programmable channels which consist of five M2P (transmit) channels and five P2M (receive) channels. The following peripherals may be allocated to the 10 channels: · USB Device · USB Host SCI FEATURES · Supports asynchronous T0 and T1 transmission protocols · Supports clock rate conversion factor F = 372, with bit rate adjustment factors of D = 1, 2, or 4 · SD/MMC · AC97 · UART1 · UART2 · Eight-character-deep buffered Tx and Rx paths · UART3 · Direct interrupts for Tx and Rx FIFO level monitoring Each of the above peripherals contain one Tx and one Rx channel, except the AC97, which contains three Tx and Rx channels. These peripherals also have their own bi-directional DMA bus, capable of simultaneously transferring data in both directions. All memory transfers take place via the main system AHB bus. · Interrupt status register · Hardware-initiated card deactivation sequence on detection of card removal · Software-initiated card deactivation sequence on transaction complete · Limited support for synchronous smart cards via registered input/output. Preliminary Data Sheet The DMA Controller can also be used to interface streams from memory-to-memory (M2M) or memoryto-external peripheral (M2P) using two dedicated M2M channels. External handshake signals are available to support memory-to-/from-external peripheral (M2P/P2M) transfers. A software trigger is available for M2M transfers only. 12/17/03 27 LH7A404 LH7A404 32-Bit System-on-Chip The DMA features: · Two dedicated channels for M2M and external M2P/P2M · Ten fully independent, programmable DMA controller internal M2P/P2M channels (5 Tx and 5 Rx) · Channels assignable to one of a number of different peripherals · Independent source and destination address registers. Source and destination can be programmed to auto-increment or not auto-increment for M2M channels · Two buffer descriptors per M2P and M2M channel to avoid potential data under/over-flow due to software introduced latency. A buffer refers to the area in system memory that is characterized by a buffer descriptor, ie., a start address and the length of the buffer in bytes · No AMBA wrapping bursts for DMA channels; only incrementing bursts are supported · Buffer size independent of the peripheral's packet size for the internal M2P channels. Transfers can automatically switch between buffers · Maskable interrupt generation · Internal arbitration between DMA channels, plus support for an AHB bus arbiter · DMA data transfer sizes, byte, word and quad-word data transfers are supported using a 16-byte data. Maximum data transfer size per M2M channel is programmable · Per-channel clock gating reducing power in channels that have not been enabled by software. See the `Clock and State Controller' section. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. System interrupts are generated when any/all of the DMA channels wish to inform the processor to update the buffer descriptor. The DMA controller can service 10 out of 20 possible peripherals using the ten DMA channels, each with its own peripheral DMA bus capable of simultaneously transferring data in both directions. The DMA controller includes an M2M transfer feature allowing block moves of data from one memory address space to another with minimum of program effort and time. An M2M software trigger capability is provided. The DMA controller can also fill a block of memory with data from a single location. The DMA controller's M2M channels can also be used in M2P/P2M mode. A set of external handshake signals, DREQ, DACK and TC/DEOT are provided for each of two M2M channels. DREQ (input) can be programmed edge or level active, and active HIGH or LOW. The peripheral may hold DREQ active for the duration of the block transfers or may assert/deassert on each transfer. DACK (output) can be programmed active HIGH or LOW. DACK will assert and return to de-asserted with each Read or Write, the timing coinciding with nOE or nWE from the EBI. TC/DEOT is a bidirectional signal with programmable direction and active polarity. When configured as an Output, the DMA will assert Terminal Count (TC) on the final transfer to coincide with the DACK, typically when the byte count has expired. When configured as an Input, the peripheral must assert DEOT concurrent with DREQ for the final transfer in the block. Transfer is terminated when DEOT is asserted by the external peripheral or when the byte count expires, whichever occurs first. Status bits indicate if the actual byte count is equal to the programmed limit, and if the count was terminated by peripheral asserting DEOT. Terminating the transfer causes a DMA interrupt on that channel and rollover to the `other' buffer if so configured. USB Device The features of the USB are: · Fully compliant to USB 1.1 specification · Provides a high-level interface that shields the firmware from USB protocol details · Compatible with both OpenHCI and Intel UHCI standards · Supports full-speed (12 Mbit/s) functions · Supports Suspend and Resume signalling. The SD/MMC, UART1/2/3, USB Device, and USB Host peripherals can each use two DMA channels, one for transmit and one for receive. The AC97 peripheral can use six DMA channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overheads. 28 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 USB Host Controller · Reception/transmission of control and status information via the AMBA APB interface The features of the USB Host Controller are: · Open Host Controller Interface Specification (OpenHCI) Rev. 1.0 Compliant · Universal Serial Bus Specification Rev. 1.1 compatible · Support for both Low Speed and High Speed USB devices · Root Hub has two Downstream Ports · DMA functionality. · Support for up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored independently in both transmit and receive modes. Three of the outgoing FIFOs can be written via either the APB interface or with DMA channels 1-3. Audio Codec Interface (ACI) The ACI provides: Color LCD Controller The LH7A404 LH7A404's LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A404 LH7A404's LCD Controller saves an external timnig ASIC by incorporating the timing conversion logic for thin LCD modules such as AD-TFT and HR-TFT. The Color LCD Controller features support for: · Up to 1,024 × 768 Resolution · 16-bit Video Bus · 16 bits-per-pixel (bpp) 5:5:5:1 or 5:6:5 direct color or on-chip color palette for 1, 2, 4, and 8 bpp resolution · STN, Color STN, AD-TFT, HR-TFT, TFT panels ­ Single and Dual Scan STN panels ­ Up to 15 Gray Shades (mono STN) ­ Up to 3375 colors (color STN) ­ Up to 64 k-Colors ­ An on-chip SRAM frame buffer conserves bus bandwidth and saves active power. · A digital serial interface to an off-chip 8-bit codec · All the necessary clocks and timing pulses to perform serialization or de-serialization of the data stream to or from the codec device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACBITCLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchronization output signal that is coincident with the bit clock. Pulse Width Modulator (PWM) The Pulse Width Modulator features: · Configurable dual output · Separate input clocks for each PWM output AC97 Codec Controller The AC97 Codec controller includes a 5-pin serial interface to an external audio codec. The AC97 link is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AC97 controller contains logic that controls the AC97 link to the audio codec and an interface to the AMBA APB. Its main features include: · Serial-to-parallel conversion for data received from the external codec · 16-bit resolution · Programmable synchronous mode support ­ Allows external input to start PWM · Programmable pulse width (duty cycle), interval (frequency), and polarity ­ Static programming: when the PWM is stopped ­ Dynamic programming: when the PWM is running ­ Updates duty cycle, frequency, and polarity at end of a PWM cycle The PWM is a configurable dual-output, dual-clockinput AMBA slave module, and connects to the APB. · Parallel-to-serial conversion for data transmitted to the external codec Preliminary Data Sheet 12/17/03 29 LH7A404 LH7A404 32-Bit System-on-Chip Synchronous Serial Port (SSP) The SSP is a master-only interface for synchronous serial communication with peripheral devices that have either Motorola SPI, National Semiconductor MICROWIRE, or Texas Instruments Synchronous Serial Interfaces. The SSP performs serial-to-parallel conversion on data received from a peripheral. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A404 LH7A404 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usually be determined by peripheral device's capability. UART/IrDA The LH7A404 LH7A404 contains three UARTs; UART1, UART2, and UART3. The UART performs: · Serial-to-Parallel conversion on data received from the peripheral device · Parallel-to-Serial conversion on data transmitted to the peripheral device. The transmit and receive paths can both be routed through the DMA separately or simultaneously, and are buffered with internal FIFO memories. This allows up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: · Four individually maskable interrupts from the receive, transmit, and modem status logic blocks Two identical timers, Timer 1 (TC1) and Timer 2 (TC2), use clock sources of either 508 kHz or 2 kHz. The clock source and mode are selectable by writing to the appropriate bits in the system control register. Each timer has a 16-bit read/write data register and a control register. The timer is loaded with the value written to the data register immediately. This value is then decremented on the next active clock edge to arrive after the write. When the timer underflows, it immediately asserts its appropriate interrupt. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. Once the timer has been enabled and written to, it decrements on the next rising edge of the 7.3728 MHz clock after the data register has been updated. FREE-RUNNING MODE In free-running mode, the timer wraps around to 0xFFFF when it underflows and continues counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a programmable frequency to drive the buzzer or generate a periodic interrupt. Real Time Clock (RTC) The RTC provides a basic alarm function or long time-base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in onesecond intervals is achieved by use of a 1 Hz clock input to the RTC. · A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. Keyboard and Mouse Interface (KMI) If a framing, parity or break error occurs during reception, the appropriate error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is prevented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). · IBM PS/2 or AT-compatible keyboard or mouse interface The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. · Polled or interrupt-driven mode Timers · Odd parity generation and checking The LH7A404 LH7A404 includes three programmable timers. Each of the timers can operate in two modes: free running and pre-scale. The timers are programmed using four registers; Load, Value, Control, and Clear. · Register bits for override of keyboard clock and data lines. 30 The Keyboard and Mouse Interface has the following features: · Half-duplex, bidirectional synchronous serial interface using open-drain outputs for clock and data. · Programmable 4-bit reference clock divider · Separately maskable transmit and receive interrupts · Single combined interrupt output Additional test registers and modes are implemented for functional verification and manufacturing test. 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 A/D Converter with Brownout Detector and Touch Screen Controller SINGLE WIRE INTERFACE The Single Wire Interface performs: The LH7A404 LH7A404 includes an A/D Converter (ADC) with integrated Touch Screen Controller (TSC) and brownout detector. The TSC is a complete interface to a Touch Screen for portable personal devices. It combines the front-end biasing and control circuitry with A/D conversion, reference generation, and digital interface functions to completely replace external ICs used to implement this interface. The ADC features: · Serial-to-parallel conversion on data received from the peripheral device · Parallel-to-serial conversion on data transmitted to the peripheral device · Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) · A 10-bit A/D converter with integrated sample-andhold, fully differential, high impedance signal and reference inputs The Single Wire interface uses a command-based protocol in which the host initiates a data transfer by sending a WriteData/Command word to the battery monitor. · Active matrix for bias and control circuits necessary for connection to external 4-, 5-, 7-, and 8-wire touch panels, including pen pressure implementation SMART BATTERY INTERFACE The Smart Battery Interface performs: · Battery voltage sense in addition to normal direct voltage inputs · Serial-to-parallel conversion on data received from the peripheral device · A 10-channel multiplexer for routing user-selected inputs to A/D · Parallel-to-serial conversion of data transmitted to the peripheral device. · A 16 × 16 FIFO for 10-bit digital output of A/D The Smart Battery Interface uses a two-wire multimaster bus (the SMBus), allowing multiple bus masters to be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data provided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism by relying on the wired-AND connection of all SMBus interfaces to the SMBus. · A pen down sensor to generate interrupts to the host · Low power circuitry and power control modes to minimize in-system power dissapation · Conversion automation for flexibility while minimizing CPU management and interrupt overhead · A brownout detector with separate interrupt Battery Monitor Interface (BMI) The BMI is a serial communication interface specified for two types of battery monitors/gas gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. DC-to-DC Converter The features of the DC-DC Converter interface are: · Dual-drive PWM outputs with independent closed loop feedback · Software programmable configuration of one of 8 output frequencies (each being a fixed division of the input clock). · Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. · Hardware-configured output polarity (for positive or negative voltage generation) during power-on reset via the polarity select inputs · Dynamically switched PWM outputs to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. Preliminary Data Sheet 12/17/03 31 LH7A404 LH7A404 32-Bit System-on-Chip Watchdog Timer (WDT) General Purpose I/O (GPIO) The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause an FIQ interrupt. Failure to service the FIQ interrupt generates a system reset. The GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI and PGHCON. Features of the WDT: · Timing derived from the system clock · 16 programmable time-out periods: 216 through 231 clock cycles · Generates a system reset (resets LH7A404 LH7A404) or a FIQ interrupt whenever a time-out period is reached · Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and the GPIOFEOI registers control edge-triggered Interrupts on Port F. The PINMUX register controls which signals are from Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and Port H. · Protection mechanism guards against interrupt-service-failure: ­ The first WDT time-out triggers FIQ and asserts nWDFIQ status flag ­ If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a system reset. 32 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER MINIMUM MAXIMUM DC Core Supply Voltage (VDDC) - 0.3 V 2.4 V DC I/O Supply Voltage (VDD) - 0.3 V 4.6 V DC Analog Supply Voltage (VDDA) - 0.3 V 2.4 V DC Analog Supply Voltage (VDDAD) - 0.3 V 4.6 V Storage Temperature -55°C 125°C NOTE: These stress ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended Operating Conditions PARAMETER MINIMUM TYPICAL MAXIMUM NOTES DC Core Supply Voltage (VDDC) 1.62 V 1.8 V 1.98 V 1 DC I/O Supply Voltage (VDD) 1.62 V 3.3 V 3.6 V 5 DC Analog Supply Voltage (VDDA) 1.62 V 1.8 V 1.98 V DC A/D and TSC Supply Voltage (VDDAD) 3.0 V 3.3 V 3.6 V Clock Frequency (Commercial) 10 MHz 200 MHz 3, 4, 5 Clock Frequency (Industrial) 10 MHz 195 MHz 3, 4, 5 Operating Temperature (Commercial) Operating Temperature (Industrial) 0°C 25°C 70°C -40°C 25°C +85°C NOTES: 1. Core Voltage should never exceed I/O Voltage. 2. Using 14.756 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal. 3. VDDC = 1.62 V to 1.98 V. 4. VDD = 3.0 V to 3.6 V. 5. Operating the LH7A404 LH7A404 below VDD = 3.0 V will affect the AC timing and the USB will not function. AC timing for VDD less than 3.0 V has not yet been characterized. Preliminary Data Sheet 12/17/03 33 LH7A404 LH7A404 32-Bit System-on-Chip DC/AC SPECIFICATIONS Unless otherwise noted, all data provided under commercial DC/AC specifications are based on -40°C to +85°C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6 V, VDDA = 1.62 V to 1.98 V; VDDAD = 3.0 to 3.6 V. DC Specifications SYMBOL PARAMETER MIN. VIH CMOS and Schmitt Trigger Input HIGH Voltage VIL CMOS and Schmitt Trigger Input LOW Voltage VHST MAX. 2.0 UNIT CONDITIONS V 0.8 V Schmitt Trigger Hysteresis 0.25 V VIL to VIH CMOS Output HIGH Voltage, Output Drive 1 2.6 V IOH = -2 mA Output Drive 2 2.6 V IOH = -4 mA Output Drive 3 2.6 V IOH = -8 mA Output Drive 4 and 5 VOH 2.6 V IOH = -16 mA CMOS Output LOW Voltage, Output Drive 1 0.4 V IOL = 2 mA Output Drive 2 0.4 V IOL = 4 mA Output Drive 3 0.4 V IOL = 8 mA Output Drive 4 0.4 V IOL = 16 mA Output Drive 5 VOL NOTES 0.4 V IOL = 24 mA 1 1 IIN Input Leakage Current -10 10 µA VIN = VDD or GND IOZ Output Tri-state Leakage Current -10 10 µA VOUT = VDD or GND IACTIVE Active Current (Operating Current) 200 mA IHALT Halt Current 41 mA 2 ISTANDBY Standby Current 35 µA 3 ISTARTUP Startup Current 50 µA 4 CIN Input Capacitance 4 pF COUT Output Capacitance 4 pF NOTES: 1. Output Drive 5 can sink 24 mA of current, but sources 16 mA of current. 2. Both oscillators running, LCD Active; all other peripherals stopped. 3. 32 kHz oscillator running; all other peripherals stopped. 4. Current consumption until oscillators are stabilized. 34 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 Analog-To-Digital Converter Electrical Characteristics Table 17 shows the derated specifications for extended temperature operation. See Figure 6 for the ADC transfer characteristics. Table 17. ADC Electrical Characteristics at Industrial Operating Range PARAMETER MIN. TYP. MAX. A/D Resolution 10 Throughput Conversion 17 CLK Cycles Acquisition Time 3 NOTES CLK Cycles Data Format 10 UNITS Bits binary 1 2 Clk Frequency 500 5,000 ns Differential Non-Linearity -0.99 2.0 LSB 3 Integral Non-Linearity -3.05 +3.0 LSB 4 -20 +20 mV 5 Offset Error Gain Error -4.0 4.0 LSB Reference Voltage Output 1.85 2.0 2.15 V VREF- VSSA VSSA VREF ±1.0 V V 6 VREF+ VREF ±1.0 V VREF VDDA V 6 Crosstalk between channels Analog Input Voltage Range -60 0 dB VDDA V Analog Input Current 5 µA Reference Input Current 5 µA Analog input capacitance Operating Supply Voltage 15 pF 3.6 3.0 7 V Operating Current, VDDA 590 1000 µA Standby Current 180 300 µA 1 10 µA 2.63 2.9 V Stop Current, VDDA Brown Out Trip Point (falling point) 2.36 Brown Out Hysterisis Operating Temperature 120 -40 8 mV 85 °C NOTES: 1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion, plus 1 × A2DCLK cycles to be made available in the PCLK domain. An additional 3 × PCLK cycles are required before being available on the APB. 2. Data out = 0000000000 when the analog input equals the negative reference. Data out = 1111111111 when the analog input equals the positive reference. 3. Guaranteed monotonic. 4. INL calculated as deviation from `best fit' line after subtracting offset/gain errors over the center 90% of full scale output range. 5. DC voltage error for the transition voltage from code 511 (0x1FF) to 512 (0x200) 6. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer, alternative low impedance (RS < 500) voltages can be selected as reference voltages. The range of voltages allowed are specified above. 7. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC. 8. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down. Preliminary Data Sheet 12/17/03 35 LH7A404 LH7A404 32-Bit System-on-Chip OFFSET GAIN ERROR ERROR 1024 1023 1022 1021 1020 1019 1018 IDEAL TRANSFER CURVE 9 8 CENTER OF A STEP OF THE ACTUAL TRANSFER CURVE 7 ACTUAL TRANSFER CURVE 6 5 INTEGRAL NON-LINEARITY 4 3 2 1 1 2 OFFSET ERROR 3 4 5 6 7 8 9 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 LSB DNL LH7A404-154 LH7A404-154 Figure 6. ADC Transfer Characteristics AC Test Conditions PARAMETER DC I/O Supply Voltage (VDD) DC Core Supply Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels 36 RATING UNIT 3.0 to 3.6 V 1.62 to 1.98 V VSS to 3 V 2 ns VDD/2 V 12/17/03 Preliminary Data Sheet 32-Bit System-on-Chip LH7A404 LH7A404 CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make these data more useable, the values presented in Table 18 were derived under the conditions described here. Maximum Specified Value PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 19 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the peripheral clock running at maximum frequency, typical conditions, and no I/O loads. This current is supplied by the 1.8 V power supply. The values specified in the MAXIMUM column were determined using these operating characteristics: · All IP blocks either operating or enabled at maximum frequency and size configuration Table 19. Peripheral Current Consumption · UART and AC97 peripherals operating; all other peripherals as needed by the OS · LCD enabled with 320 × 240 × 16-bit color, 60 Hz refresh rate, data in SDRAM · I/O loads at nominal mA 0.005 mA 0.1 mA 5.4 (1.0) mA MMC 0.6 mA SCI 23 mA PWM (each) · LINUX operating system running from SDRAM 1.0 LCD (+I/O) The values in the TYPICAL column were determined using a `typical' application under `typical' environmental conditions and the following operating characteristics: mA Timers (each) Typical 1.3 RTC · Maximum specified ambient temperature. UNITS UART (each) · All voltages at maximum specified values TYPICAL AC97 · Core operating at maximum power configuration PERIPHERAL