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ARM+7+series+controllers

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Abstract: DATA REG. PORT B DIR. REG. PORT B DATA REG. PAOE[7:0] PAOE[7:0] nPAOE[7:0] Active HIGH PORTA[7:0] PORTA[7:0] EPA[7:0] EPA[7:0] PBOE[7:0] XPA[7:0] PBOE[7:0] Active LOW PORTB[7:0] PORTB[7:0] EPB[7:0] XPB[7:0] EPB[7:0] Connection of GPIO lines to , . PSEL Port A Data direction Register PENABLE PWRITE PADDRH [7:6] AMBA APB Interface PADDRL [3:2] PWDATA [7:0] PRDATA [7:0] PCLK Port A Data register Port B Data direction ARM
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PL060 0142B
Abstract: . 3. Change the ARM920T/940T to BIGEND mode by setting bit 7 of coprocessor 15 register 1, see , coprocessor 15 register 1 ORR r0,r0,#0x80 ; set bit 7 MCR p15,0,r0,c1,0 ; write coprocessor 15 register , CPID20 CPID18 CPID16 1 3 5 7 9 11 13 15 17 19 POD2 2 4 6 8 10 12 14 16 18 20 , CPDOUT10 CPDOUT8 CPDOUT6 CPDOUT4 CPDOUT2 CPDOUT0 1 3 5 7 9 11 13 15 17 19 POD3 CPDIN14 CPDIN12 CPDIN10 CPDIN8 CPDIN6 CPDIN4 CPDIN2 CPDIN0 1 3 5 7 9 11 13 15 17 19 ARM
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ebe rotary switches ARM920T HBI-0011B 940T ARM 940T ARM920T guide KPI-0043A KPI-0034A
Abstract: . PORT B DIR. REG. PORT B DATA REG. SCANMODE PAOE[7:0] PAOE[7:0] nPAOE[7:0] Active HIGH PORTA[7:0] PORTA[7:0] EPA[7:0] EPA[7:0] PBOE[7:0] XPA[7:0] PBOE[7:0] Active LOW PORTB[7:0] PORTB[7:0] EPB[7:0] XPB[7:0] EPB[7:0] Connection of GPIO lines to , . PSEL Port A Data direction Register PENABLE PWRITE PADDRH [7:6] AMBA APB Interface PADDRL [3:2] PWDATA [7:0] PRDATA [7:0] Port A Data register Port B Data direction Register ARM
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DDI0142B AMBA APB bus ARM cpu
Abstract: 7 8 9 10 Introduction System Requirements Setting-up the Software and Hardware Building the , Further Information Warranty Information References 1 2 3 5 6 7 8 9 10 11 ARM Evaluation , , using the ARM Project Manager (APM). 1 2 3 4 5 6 7 8 Start APM. When APM is loaded , 4 Building the Sample Application on page 5. From APM: 1 2 3 4 5 6 7 8 Press the reset , 1331 14641 ARM Evaluation Board (AEB-1) Welcome Guide ARM DGI 0005D 7 7 Debugging an ARM
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LH77790A ARM 7 processor pin configuration ARM pin configuration ARM processor pin configuration power line Communication using ARM ARM250 ARM 7 pin configuration
Abstract: ] [31:24] DQM DQX 1 8 DQMOut[0] [23:16] [15:8] [7:0] 32 Byte 3 Byte 2 , (merging write buffer off). 1 2 A0 3 A1 4 5 6 7 8 9 10 HCLK HSELram , example (delayed ExtBusGnt signal). 1 2 A0 3 A1 4 5 6 7 8 9 10 11 , SDRAM Controller read example. 1 2 3 4 5 6 7 8 9 10 11 A2 12 13 , be set only when the dynamic CKE shutdown mode is active (E=1 and C=1 is not allowed). 15, 11, 7 ARM
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PL170 AMBA AHB memory controller ARM10 0159D
Abstract: 2 2-2 1 2 2-26 ARM7TDMI, 4T Cortex-M1, Cortex-M3, 7 , Security Extensions ARMv6 ARM1176JZF-S ARM1176JZ-S 7 Thumb-2 ARMv7 7 , Cortex-A9 7-R ARM Thumb-2 DSP 32 SIMD ARMv7 Cortex-R4 Cortex-R4F 7 , -cpu=7 ARMv7-A ARMv7-R ARMv7-M -cpu=7 ARMv7-A ARMv7-R ARMv7-M 2-36 ARM
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ARM SC300 ARMv7 neon 0348B SC300 ARM E328 CORTEX-A9 0348BJ
Abstract: Interface has 24 programmable Input/ Output (I/O) pins grouped into three, eigh8-bit ports: · PA[7:0] · PB[7:0] · PC[7:0] Each port has three modes, 0, 1, or 2. These modes determine which , external bus. nCS1 nCE1/nCAS1 nOE 64KB x 8 SRAM U4 nWE A[0 ­ 15] D[0 ­ 7] nOE nWE A[1 ­ 16] SHARP LH77790A CS2 D[0 ­ 7] microcontroller D[8 ­ 15] nBW A0 U1 nCS1 , tWTS tDH tXA Cycle 5 tAA Cycle 6 tWH LID VA tDS ALID V Cycle 7 tXBWH ARM
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16c40 LH77790 s9897 Pixel Magic 35 KPI-0041A
Abstract: exception-handling code running on: - A and R profiles of version 7 of the ARM architecture. - Versions of the ARM architecture earlier than version 7. Code that might be entered directly through an ARMV7M , , 2009 ARM Limited. All rights reserved. Page 1 of 7 SP must be 8-byte aligned on entry to , 6 7 7 ARM IHI 0046B Copyright © 2006, 2007, 2009 ARM Limited. All rights reserved. Page 2 of 7 SP must be 8-byte aligned on entry to AAPCS-conforming functions 1 ABOUT THIS DOCUMENT ARM
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ARM926EJ-S ARM946E-S ARM1136J-S ARM1156T2F-S ARMv7-M Architecture Reference Manual ARMv7 ARMv5TE ARMv5 ARMv7-M ARMv7 Architecture Reference Manual
Abstract: ) ARM version2.50 (ARM DUI 0041CJ-00) 5 6 C C+ ARM Thumb 7 ARM Thumb , 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Chapter 6 6.1 6.2 6.3 6.4 Chapter 7 , . 5-3 5.2.4 7 ARM FIQ - IRQ - (ARM 4 ) 9 , gcd less end 7 1 ARM DUI 0040DJ-00 Copyright © 1997 and 1998 ARM Limited. All , Thumb ARM Thumb 7 Thumb 16 14 ARM 16 16 Thumb 1 ARM 2 Thumb 2 ARM ARM DUI Matsushita Electronics
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ASM 1042 UUA 2224 Matsua LED Report 1998 embedded c programming examples E5940 ASM 1083 ARMDUI0040DJ011-00
Abstract: -2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure A-10 Figure A , :195] S1-7 USB 1 and 2 USB1_nOE, USB1_RCV, USB1_VP, USB1_VM, USB2_nRST, and USB2_RCV Z[230:212] S1-7 IDE IDE_RST and IDE_nOE[2:0] Y[36:0] ARM DUI 0188C Copyright © 2004-2007 , ] isolated by SW8 Y[68:61] - LED[7:0] - Y[76:69] - SW[7:0] - Y[79:77] T12-T10 , - Z[183:176] - CAM_D[7:0] - Z184 - CAM_SCL - Z185 - CAM_SDA - ARM
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Z147 Z188 PD1USBP11AD z137 Z226 Z224 VPB926EJ-S VPB/926EJ-S
Abstract: . See Peripheral Identification Registers on page 2-9 for the value of X, bits [7:4] of the register , :8] b0010 Major ETM architecture version number = 3. [7:4] b0010 Minor ETM , 13 12 8 7 4 3 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 Reserved ID , [15:13] 2 Number of counters [12:8] 0 Number of memory map decoders [7:4] 2 , bits[7:0] of each register are used. Table 2-5 shows the values of the fields when reading this set of ARM
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coresight ARM9 processor ETM9CS ARM922T ARM968E-S ATID 0315B
Abstract: A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 ARM DUI 0074A Header card connectors , -bit control bus FC[7:0] The expansion connector also supplies +3.3V power and ground. For details of the , buffered by U8 and light with a logic 0 on the control bus FC[7:0]. 2.7 BERROR If the processor , interface FPGA - Pin layout on page A-7. · Figure A-7 Clock generation - Schematic on page A-8. · , level schematic VDD J10 EXPANSION AND STATUS LEDS LK1 1 3 5 7 + + + + 2 +4 +6 +8 ARM
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XC4013XL XC4062XL XC4013XL-PQ240 ARm 7 fpga schematic W48C55 free arm processor FD31 KPI-0045A CON60AP
Abstract: .5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 Appendix B Specifications B.1 B.2 B.3 Appendix C , A-7 Keyboard and mouse interface . , . 4-37 Assignment of display memory to R[7:0], G[7:0], and B[7:0 , -4 Table A-5 Table A-6 Table A-7 Table A-8 Table A-9 Table A-10 Table A-11 Table B-1 Table B , D-5 Table D-6 Table D-7 Table D-8 Table D-9 Table D-10 Table D-11 Table D-12 Table D ARM
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MIVGSM0108 enfora enabler gsm0108 GSM0108-01 enfora MIVGSM0108 GSM0108 sandisk micro SD Card 2GB HBI-0118 0225B AB926EJ-S 16C550
Abstract: GPIOAFSEL PADDR[11:2] GPIODATA[7:0] GPINSync2[7:0] PRDATA[7:0] nGPAFEN[7:0] GPAFOUT[7:0] GPAFIN[7:0] nGPEN[7:0] nGPIODIR[7:0] Input/output control PWDATA[7:0] Hardware control interface Input/ output multiplexor GPOUT[7:0] XP[7:0] GPIN[7:0] ID PRESETn PCLK Interrupt detection logic Interrupt control GPIOMIS[7:0] GPIOINTR Figure 1-1 PrimeCell GPIO , PWRITE Register block Mode control multiplexor PADDR[11:2] PWDATA[7:0] Input/output control ARM
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PL061 ARM966E-S arm gpio PL011 0190B
Abstract: daughter board EB185-00-1 Technical datasheet Contents 1 2 3 4 5 6 7 8 About this document , .7 Re-flashing the ARM Board , information 2.1 Description This E-blocks board is a development tool for the powerful AT91 SAM 7 microcontroller from Atmel. The SAM 7 is a 32 bit RISC device running at an internal frequency of 36MHz, and , -1.cdr 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Screw terminals Power Matrix Multimedia
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EB185-30-1 EB031 computer mother board circuit diagram Projects of LED pattern with program led matrix projects EB031 driver ARM processor data sheet
Abstract: . B-7 Copyright © 2003 ARM Limited. All rights reserved. ARM DUI 0161A List of Tables , -3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Table A-9 Table B-1 Table B-2 Table B-3 Table B-4 Table B-5 Table B-6 Table B-7 Table B-8 Table B-9 viii Control Register, CM_CTRL , ) . A-7 HDRB signal description (AHB , . B-7 Copyright © 2003 ARM Limited. All rights reserved. ARM DUI 0161A Preface This ARM
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ARM10200E ARM1020E VFP10 338 u CLKREF24MHZ free circuit diagram of motherboard CM10220E HBI-0098
Abstract: 7 of coprocessor 15 register 1, see Example 3-1. Note Any byte accesses before this bit is set , BIGEND mode MRC p15,0,r0,c1,0 ; read coprocessor 15 register 1 ORR r0,r0,#0x80 ; set bit 7 MCR , of connectors POD1 to 6 is given in Figure 4-1. POD1 1 3 nOPC 5 nCPI 7 nUSER 9 CPnWAIT 11 13 , 1 3 5 7 9 11 13 15 17 19 POD3 CPDATA30 CPDATA28 CPDATA26 CPDATA24 CPDATA22 CPDATA20 CPDATA18 CPDATA16 1 3 5 7 9 11 13 15 17 19 SCREG0 SCREG2 TCK1 TAPSM0 TAPSM2 ARM
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ARM740T 60-way KPI-0038A
Abstract: -2 Peripheral connectors . B-7 ARM
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0159B PL041 MMC socket sandisk mmc 16MB IA23 Sharp PIC interface SD MMC HBI-0086
Abstract: Configuration 7 0 7 Configuration 4 3 24 23 31 Conceptual register bit assignment Revision Designer Designer Part 0 number 1 number 1 20 19 Revision number Part number 0 0 7 4 3 0 7 0 16 15 12 11 8 7 0 Designer Part number Figure 1-7 TZICPeriphlD0 , . Figure 1-8 shows the register bit assignments. 31 8 7 Undefined 0 Partnumber0 Figure 1-8 , TZICPeriphID0 Register bit assignments Bits Name Function [31:8] - Read undefined [7:0 ARM
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SP890 trustzone PL192 SIMPLE CODE LOCK 0013b 0x00000440 AMBA 3.0 technical summary 0013B
Abstract: ] HADDR[28:0] XDATAIN[15:8] XDATAOUT[15:8] HTRANS[1:0] nXDATAEN[1] HBURST[2:0] XDATAIN[7:0] XDATAOUT[7:0] HSIZE[2:0] HMASTER[3:0] HWRITE nXDATAEN[0] XADDR[25:0] HSELmem HSELreg nXOEN HREADYin HREADYout nXBLS[3:0] HRESP[1:0] nXWEN nXCS[3:0] XCS[7:4] ScanEnable , :8] nXDATAen[1] XDATAin[7:0] XDATAout[7:0] XDATA[7:0] nXDATAen[0] XADDRout[25:0] XADDR , ] nXCS[3:0] XCSout[7:4] XCS[7:4] SCANENABLE SCANIN SCANOUT BusReqSmc BIGENDIAN BusGntSmc ARM
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PL090 28F800F3 KM681002A ARM bus AMBA AHB to APB BUS Bridge verilog code amba ahb master slave sram controller 0160C
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