AND8346/D A519HRT A5191HRT 20C15 SPEC-54 TEST10 TEST11 TEST12 LSI20C15 AD589 - Datasheet Archive

 

A519HRT HART) Modem Prepared by: Paul Pulley ON Semiconductor http://onsemi.com APPLICATION NOTE Introduction Features of the

 

AND8346/D AND8346/D A519HRT A519HRT HART) Modem Prepared by: Paul Pulley ON Semiconductor http://onsemi.com APPLICATION NOTE Introduction Features of the A5191HRT A5191HRT This application note describes a demonstration circuit that permits a user to implement a HART slave or master interface between a microprocessor and a process loop using the ON Semiconductor A5191HRT A5191HRT HART modem integrated circuit. The information in this application note is correct to the best of our knowledge. Development of a circuit suitable to the user's particular system and application environment is the responsibility of the user. The HART (highway addressable remote transducer) communication protocol provides digital communication for microprocessor-based process control instruments. HART uses the Bell-202 forward channel signaling frequencies and bit rate (1200 bits/second) as making it a subset of the Bell-202 standard. HART-speaking devices can use virtually any Bell-202 standard modem. However, the ON Semiconductor A5191HRT A5191HRT single-chip modem has been designed to meet the low power requirements of 2-wire process instruments. Same modem design as LSI 20C15 20C15 Transmits a trapezoidal signal Internal oscillator cell Internal receive filter Carrier detect 28 pin PLCC package (green, RoHS compliant) 32 pin LQFP package (green, RoHS compliant) The ON Semiconductor A5191HRT A5191HRT modem is designed to allow the user to easily implement a HART compliant physical layer design (HART FSK Physical Layer Specification; HCF_SPEC-54 SPEC-54, Revision 8.1 November 24, 1999). The A5191HRT A5191HRT is intended to replace the LSI/NCR 20C15 20C15 for all existing and future HART applications. The A5191HRT A5191HRT is a near pin-for-pin replacement for the 20C15 20C15. The A5191HRT A5191HRT can be used in any circuit that uses the LSI 20C15 20C15 with no circuit topology changes. Only the values of four external resistors in the receive filter need to be changed. This application note explains how to interface the A5191HRT A5191HRT modem to the HART network, as well as other general advice on using the modem and on designing HART devices. A block diagram showing a typical application of the A5191HRT A5191HRT in a HART Slave is shown in Figure 1. · · · · · · · Figure 1. A5191HRT A5191HRT HART Slave Application Block Diagram © Semiconductor Components Industries, LLC, 2008 October, 2008 - Rev. 2 1 Publication Order Number: AND8346/D AND8346/D AND8346/D AND8346/D Overview of HART Communications Analog Signaling HART devices are connected in a current loop arrangement shown in Figure 2. The process transmitter (field instrument in HART specifications) signals by varying the amount of current flowing through itself. The controller (primary master) detects this current variation by measuring the DC voltage across the current sense resistor. The loop current varies from 4 to 20 mA at frequencies usually under 10 Hz. Figure 2. Conventional Current Loop with HART Signal Sources Digital Signaling HART Waveform The HART (digital) signal is superimposed on the 4-20 mA (analog) signal as shown in Figure 3. The master transmits HART signals by applying a voltage signal across the current sense resistor and it receives a voltage signal by detecting the HART current signal across the sense resistor. Conversely, the slave transmits by modulating the loop current with HART signals and receives HART signals by demodulating the loop current. HART signals using phase-continuous frequency-shift- keying (FSK) at 1200 bits/second. Phase-continuous FSK requires the phase angle of the mark (1200 Hz) and the space (2200 Hz) to remain continuous at the 1200 Hz bit boundaries. A field instrument transmits a HART signal by modulating a high-frequency carrier current of about 1 mAp-p onto its normal output current. This is illustrated in Figure 3 for a 6 mA analog signal. Figure 3. Field Instrument Current vs. Time http://onsemi.com 2 AND8346/D AND8346/D HART Slave Device Multiplexing a HART Master HART slaves transmit by modulating the process 4-20 mA DC loop current with a 1 mAp-p AC current signal as shown in Figure 3. Since the average value of the HART signal is zero, the DC value of the process loop remains unchanged. Receive circuits in a HART slave device amplify, filter and demodulate the current signal. To reduce the design complexity of a multiple loop HART master, the physical layer can be multiplexed to two or more process loops. This is usually done with analog switches that allow signals as high as 16 Vp-p to pass and exhibit an extremely low on resistance. The added impedance of the switch directly affects the output impedance of the master device. The multiplexer can switch only the HART signal or it can switch both the HART signal and the associated signal return. Switching the signal return insures the physical layer interface will be non-intrusive to the HART network if a failure were to occur. Typically, the analog switches connect to each process loop through a coupling capacitor (about 2.2 mF). The greatest disadvantage of multiplexing HART signals is the reduction in communication throughput to each slave device. HART Multi-dropped Slave Devices Some current loops (called networks in HART documents) use only digital signaling. The field instrument current is fixed at 4 mA or some other convenient value, and only digital communication occurs. Up to 15 such field instruments with unique addresses of 1 through 15 may be connected in parallel. A device that is not multi-dropped will usually have its address set to 0. HART Master Device HART masters transmit by driving the loop with a low impedance voltage source as shown in Figure 2. Regardless of whether a master or field device is transmitting, a signal voltage of about 500 mVp-p is developed across the conductors of the current loop (assuming a 500 W current sense resistor), and is seen by both devices. Receive circuits in each device filter and demodulate the signal voltage. HART Cabling Because of the relatively low HART frequencies there is little cable attenuation and delay distortion. This results in very few restrictions on constructing networks. The complete topology requirements and electrical requirements for HART devices are given in the HART physical layer specification (2). In most applications, HART communications can be performed up to a distance of 5000 feet (1500 meters) using existing field wiring for a 2-wire process instrument. HART Primary Master In general, a HART primary master is the device that provides the communications between the control system (DCS) and the remote process instruments with the intent to receive process information and perform maintenance operations. A HART network that has a HART master interface integrated into the DCS will usually be configured as a primary master. HART Data Link Layer Normally, one HART device talks while others listen. Talking means applying the modulated carrier to the network cable. A given device applies carrier in one unbroken segment called a frame. Between frames the network is silent. Field instrument frames are usually responses to commands by a master. Further information on network protocol is found in the HART data link layer specification (1). HART Secondary Master In general, a second HART interface connected to a network that contains a master will be a secondary master. An example of a secondary master is a hand-held communicator that would be connected directly across a HART. Such a network may have a primary master. A HART network can only have one primary and one secondary master connected at a time. http://onsemi.com 3 AND8346/D AND8346/D Signal Description Table 1. 28 Pin PLCC Pin Descriptions Pin No. Symbol Pin Name I/O 1 TEST1 Connect to VSS 2 TEST2 No connect 3 TEST3 No connect 4 TEST4 No connect 5 TEST5 Connect to VSS 6 INRESET 7 TEST7 Connect to VSS 8 TEST8 Connect to VSS 9 TEST9 Connect to VSS 10 OTXA Transmit analog output. OTXA is a trapezoidal signal controlled by ITXD. ITXD = logic low = 2200 Hz. ITXD = logic high = 1200 Hz. Active when INRTS is low, 0.5 VDC when INRTS is high. O 11 IAREF Analog reference input 1.2 to 2.6 VDC, typically 1.23 VDC I 12 ICDREF Carrier detect reference voltage input, typically 1.15 VDC (IAREF - 0.08 VDC) I 13 OCBIAS Bias current set. External resistor sets the bias current. IAREF/Rbias = 2.5 mA ±5% O 14 TEST10 TEST10 Connect to VSS 15 VDDA Analog VDD I 16 IRXA Receive analog input. Accepts 1200/2200 Hz signals from the external filter. I 17 ORXAF The square wave output of the high pass filter O 18 IRXAC The positive input of the carrier detect comparator and receiver filter comparator I 19 OXTL Oscillator output: 460.8 kHz O 20 IXTL Oscillator input: 460.8 kHz I 21 VSS Analog/digital ground I 22 VDD Digital VDD I 23 INRTS Request to send input. Selects operation of the modulator. When low asserts OTXA. When high sets OTXA = 0.5 V. Must be high during power-up. I 24 ITXD Transmit digital input. Logic high = mark (1200 Hz), logic low = space (2200 Hz) I 25 TEST11 TEST11 26 ORXD Receive digital output. Logic high = mark (1200 Hz), logic low = space (2200 Hz). ORXD is qualified with OCD. O 27 OCD Carrier detect output. It goes high if the received signal is larger than the ICDREF for 4 cycles of IRXA signal. O 28 TEST12 TEST12 Reset all digital logic when low, normal operation when high. This pin is intended to be used as a power-on-reset (POR). See the HART Slave section of this application note and section 3, Figure 3 of the data sheet for detailed information on the requirements for POR operation. No connect No connect http://onsemi.com 4 AND8346/D AND8346/D 32 Pin LQFP Table 2. 32 Pin LQFP Pin Descriptions Pin No. Symbol Pin Name 1 TEST5 2 INRESET 3 TEST7 Connect to VSS 4 TEST8 Connect to VSS 5 TEST9 Connect to VSS 6 VSS Digital ground* 7 OTXA Output transmit analog. FSK modulated HART transmit signal to 4 to 20 mA loop interface circuit. 8 IAREF Analog reference voltage 9 ICDREF Carrier detect reference voltage 10 OCBIAS Comparator bias current 11 TEST10 TEST10 Connect to VSS 12 VSSA Analog ground* 13 VDDA Analog supply voltage 14 IRXA FSK modulated HART receive signal from 4-20 mA loop interface circuit 15 ORXAF Analog receive filter output 16 IRXAC Analog receive comparator input 17 OXTL Crystal oscillator output 18 IXTL Crystal oscillator input 19 VSSA Analog ground* 20 VSS Digital ground* 21 VDD Digital supply voltage 22 INRTS 23 ITXD 24 TEST11 TEST11 25 ORXD 26 OCD 27 TEST12 TEST12 No connect 28 TEST1 Connect to VSS 29 TEST2 No connect Connect to VSS Reset all digital logic when low, normal operation when high. This pin is intended to be used as a power-on-reset (POR). See the HART Slave section of this application note and section 3, Figure 3 of the data sheet for detailed information on the requirements for POR operation. Request to send Input transmit data. Transmitted HART data stream from UART. No connect Received demodulated HART data to UART Carrier detect output 30 VDD 31 TEST3 Digital supply voltage No connect 32 TEST4 No connect *On the 32 LQFP the analog ground and digital ground pins must be connected together externally and connected to the system power ground. The separate 32 LQFP grounds help decrease the ground noise coupled into the chip. On the 28 PLCC version there are not separate analog and digital grounds. In the 28 PLCC these two grounds are connected inside the package to minimize pin count. http://onsemi.com 5 AND8346/D AND8346/D A5191HRT A5191HRT Functional Blocks Figure 4. A5191HRT A5191HRT Block Diagram HART Modem Demodulator The demodulator accepts an FSK signal at its IRXA input and reproduces the original modulating signal at its ORXD output shown in Figure 5. The modem uses shift frequencies of nominally 1200 Hz (logical one, mark) and 2200 Hz (logical zero, space). The bit rate is nominally 1200 bits/second. The output of the modulator ORXD is qualified with the carrier detect signal OCD. Therefore only IRXA signals large enough to be detected (100 mVp-p typical) by the carrier detect function will produce demodulated output at ORXD. Figure 5. Demodulator Signal Timing http://onsemi.com 6 AND8346/D AND8346/D Modulator The modulator accepts digital data in NRZ form at its ITXD input and generates the FSK modulated signal at its OTXA output. INRTS must be a logic low for the modulator to be active. Figure 6. Modulator Signal Timing Transmit Waveshaping The A5191HRT A5191HRT generates a HART compliant trapezoidal FSK modulated signal at its OTXA output. Shown below are actual transmit signals from a A5191HRT A5191HRT. Figure 7. OTXA Waveform The amplitude of OTXA is proportional to the analog reference voltage as follows: OTXAp-p = IAREF x 0.417 For IAREF = 1.235 VDC OTXAp-p = 1.235 x 0.417 = 0.515 Vp-p A voltage swing from 0.16 to 0.77 VDC When IRTS = logic high; OTXA = 0.5 VDC (When AREF = 1.235 VDC) which requires the receiver to activate CD between the incoming signal levels of 80 and 120 mVp-p. Carrier detect will be compliant when ICDREF - IAREF = 0.08 VDC. The circuit shown in the appendix is designed for a nominal CD level of 100 mVp-p. Internal to the A5191HRT A5191HRT, a comparator asserts a logic low if the IRXAC voltage is below ICDREF. The comparator output is fed into the carrier detect block, which asserts the output pin OCD to a logic high if INRTS is a logic high, and four consecutive pulses out of the comparator have arrived. The carrier detect output OCD stays at a logic high as long as INRTS is at a logic high and the next comparator Carrier Detect The A5191HRT A5191HRT implements a carrier detect (CD) that is compliant with the HART physical layer specification http://onsemi.com 7 AND8346/D AND8346/D pulse is received in less than 2.5 ms. Once OCD goes inactive to a logic low, it takes four consecutive pulses out of the comparator to set OCD to a logic high again. Four consecutive pulses amount to 3.33 ms when the received signal is 1200 Hz and to 1.82 ms when the received signal is 2200 Hz. quantities. Ceramic resonators that oscillate at 460 kHz are available from: MuRata Erie North America, Inc. 2200 Lake Park Drive Smyrna, GA 30080 Tel: 770-436-1300 Raltron Electronics Corp. 10651 Northwest 19th St. Miami, Florida 33172 Tel: 305-593-6033, Fax: 305-593-3973 Clock Oscillator The A5191HRT A5191HRT requires an external 460.8 kHz clock, ceramic resonator, or crystal, accurate to at least 1%. The oscillator requires two external capacitors and one external resistor, which varies depending on the type of the crystal/resonator. The specifications are listed in the two tables below. The A5191HRT A5191HRT has an internal oscillator cell, only requiring an external ceramic resonator and two capacitors. The oscillator cell is designed to use either a crystal, ceramic resonator or an external clock. When using a ceramic resonator or crystal, care should be taken to keep the circuit board traces between the A5191HRT A5191HRT and the external oscillator components as short as possible. External Clock It may be desirable to use an external clock (460.8 kHz) rather than the internal oscillator cell because of the cost and availability of ceramic resonators. In addition, the A5191HRT A5191HRT consumes less current when an external clock is used as shown below in Figure 8. An external clock associated with the microprocessor (running at a frequency that is a multiple of 460.8 kHz) can be used as an input to the oscillator cell. The interface between the microprocessor clock and the A5191HRT A5191HRT could be as simple as a direct connection or a single integrated circuit. Note: output OXTL is driven by an external source. Ceramic Resonator Sources Ceramic resonators are less expensive than crystals, but are not as accurate. Unfortunately, ceramic resonators at the needed frequency require special ordering in very large Figure 8. Oscillator Connection for Resonator, Crystal and External Clock Table 3. Resonator and Crystal Values Description Suggestion #1 Suggestion #2 Crystal Frequency 460.8 kHz 460.8 kHz C1 220 pF 47 pF C2 220 pF 22 pF R1