AND8260/D NCP1381 SOIC-14 SPP11N60C2 MMSD4148T1 BC807 MC33260 MUR480 TL431

NCP1381 Demonstration Board 120 W Notebook Adapter with Power Factor Correction http://onsemi.com Prepared by: Nicolas Cyr ON

AND8260/D AND8260/D NCP1381 NCP1381 Demonstration Board 120 W Notebook Adapter with Power Factor Correction http://onsemi.com Prepared by: Nicolas Cyr ON Semiconductor APPLICATION NOTE Overview NCP1381 NCP1381 is a quasiresonant controller developed to ease the design of 80 to 200 W switching power supplies requiring a Power Factor Correction (PFC) stage. One of its typical applications is notebook adapter power supply, in which high-efficiency, low standby power and low EMI are the key requirements. This demonstration board has been designed in order to demonstrate NCP1381 NCP1381 capabilities. It thus gives the choice to implement various options, while offering enough space to plug scope probes. Features To help designers quickly developing a notebook adapter, the NCP1381 NCP1381 has been introduced. This SOIC-14 SOIC-14 package hosts a high performance controller with all necessary features to build a rugged and reliable switching power supply: · Current-mode operation with Quasi-Resonant operation: implementing peak current mode control, the NCP1381 NCP1381 waits until the drain-source voltage crosses a minimum level. This is the quasi-resonance approach, minimizing both EMI radiations and capacitive losses. · Over Power Protection: using a voltage image of the bulk level, via the Brown-Out divider, the designer can select a resistor which, placed in series with the current sense information, provides an efficient line compensation method. · Frequency clamp: the controller monitors the sum of TON and TOFF, providing a real frequency clamp. Also the TON maximum duration is safely limited to 50ms in case the peak current information is lost. If the maximum TON limit is reached, then the controller stops all pulses and enters a safe auto-recovery burst mode. · Go-to-standby signal for PFC front stage: The NCP1381 NCP1381 includes an internal low impedance switch connected between pin 10 (VCC) and pin 11 (GTS). The signal delivered by pin 11 being of low impedance, it becomes possible to connect PFC's VCC directly to this pin and thus avoid any complicated interface circuitry © Semiconductor Components Industries, LLC, 2006 March, 2006 - Rev. 0 · · · 1 between the PWM controller and the PFC front-end section. In normal operation, pin 11 routes the PWM auxiliary VCC to the PFC circuit which is directly supplied by the auxiliary winding. When the SMPS enters skip-cycle at low output power levels, the controller detects and confirms the presence of the skip activity by monitoring the signal applied on its pin ADJ_GTS (typically FB signal) and opens pin 11, shutting down the front-end PFC stage. When this signal level increases, e.g. when the SMPS goes back to a normal output power, pin 11 immediately (without delay) goes back to a low impedance state. Finally, in short-circuit conditions, the PFC is disabled to lower the stress applied to the PWM main switch. Skip-cycle capability: a continuous flow of pulses is not compatible with no-load standby power requirements. Slicing the switching pattern in bunch of pulses drastically reduces overall losses but can, in certain cases, bring acoustic noise in the transformer. Thanks to a skip operation taking place at low peak currents only, no mechanical noise appears in the transformer. This is further strengthened by ON Semiconductor soft skip technique, which forces the peak current in skip to gradually increase. In case the default skip value would be too large, connecting a resistor to the pin 6 will reduce or increase the skip cycle level. Adjusting the skip level also adjusts the maximum switching frequency before skip occurs. Over Voltage Protection: by sensing the plateau level after the power switch has opened, the controller can detect an over voltage condition through the auxiliary reflection of the output voltage. If an OVP is sensed, the controller stops all pulses and permanently stays latched until the VCC is cycled down below 4 V. External latch input: by permanently monitoring pin 5, the controller detects when its level rises above 3.5 V, e.g. in presence of a fault condition like an OTP. This fault is permanently latched-off and needs the VCC to go down below 4 V to reset, for instance when the user un-plugs the SMPS. Publication Order Number: AND8260/D AND8260/D AND8260/D AND8260/D · Brown-out detection: by monitoring the level on pin 2 · short). Here, every time the internal 0.8 V maximum peak current limit is activated, an error flag is asserted and a time period starts, thanks to an external timing capacitor. If the voltage on the capacitor reaches 4 V (after 90 ms for a 220 nF capacitor) while the error flag is still present, the controller stops the pulses and goes into a latch-off phase, operating in a low-frequency burst-mode. As soon as the fault disappears, the SMPS resumes its operation. The latch-off phase can also be initiated, more classically, when VCC drops below VCCOFF (10 V typical). during normal operation, the controller protects the SMPS against low mains condition. When the pin 2 level falls below 240 mV, the controller stops pulsing until this level goes back to 500 mV to prevent any instability. During Brown-Out conditions, the PFC is not activated. Short-circuit protection: short-circuit and especially over-load protection is difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output Design description lower than 500 mW. In addition the board includes several protections like brown-out or overpower, and provides the possibility to build an overvoltage protection. To be close to a real notebook adapter, the board will deliver 120 W on a 19.5 V output while correcting the power factor, but its consumption in no-load conditions will be Schematic L2 B1 KBU8J 90 -265 VAC C1 1 m/X2 N R4 560 k D2 L T2A SPP11N60C2 SPP11N60C2 C5 1 m/X2 F1 L1 C2 6.1 mH MMSD4148T1 MMSD4148T1 2n2/Y1 C3 1 m/X2 R2 R1 C4 2n2/Y1 Q1 BC807 BC807 M1 1R R5 680 k Output +180 - 385 Vdc + E1 220 m/450 V Ground R6 680 k MC33260 MC33260 OSC VCTRL RTH1 R3 CS 20 k PE 1R Brown Out Detection D1 MUR480 MUR480 200 mH FB SYNC VCC GND DRV IC1 C6 470 p PE Figure 1. PFC Stage http://onsemi.com 2 Input +15 Vdc C7 C9 100 n 2n2 C8 220 n AND8260/D AND8260/D R27 19.5 V/6.2 A + R28 36 k E7 5k6 C23 470/25 V + R30 75 k 1n 2.2 mH L4 R29 56 k R33 1k C19 39 n NU R26 E6 IC4 TL431 TL431 2200 m/35 V R38 C20 NU 1k + E5 2200 m/35 V + R25 NU E4 2200 m/35 V C18 D12 MBR20300 MBR20300 NU C17 MRA4007 MRA4007 470 p D10 SPP11N60C2 SPP11N60C2 T1 R23 15 mH L3 D6 MURA120 MURA120 + 10 k C16 150 m/35 V (220 m/35) R22 22R D8 MMSD4148 MMSD4148 R17 R18 R19 270 k D7 MMSD4148 MMSD4148 R20 1k R21 47R 220 m/450 V MRA4007 MRA4007 0.15 R MUR1100E MUR1100E E1 D11 R24 M2 D9 10 n + E2 R31 4M7 IC3 PC817 PC817 270 k 270 k C15 R16 + E3 2k2 100 n 22 k IC2 NCP1381 NCP1381 R14 D4 NU NU 18 V C22 100 p C13 R37 R35 2k2 27 k R32 Q3 100 n D5 ADJ NC BO NC DMG REF TMR GTS OVP VCC FB DRV CS GND C14 NU R36 C25 R15 NU C24 R12 R13 100 k R11 22 k 33 p 330 n C10 R7B 560 k R7A R8 R9 BCP56T1 BCP56T1 PFC Output PFC VOC NU NU C11 15 V Q2 6k2 220 n C12 D3 5k6 R34 NU NU NU 910 k 910 k Brown Out Figure 2. Valley Switching Comverter http://onsemi.com 3 R10 10 k Ground C21 2.2 n/Y1 AND8260/D AND8260/D Design Steps PFC Stage protection, or after the PFC stage for a better overpower protection (see below). With the second solution, there is a minimum start-up voltage, but not any more minimum operating voltage, so it is not a true brown-out protection. The PFC controller used is the MC33260 MC33260, a controller for boost PFC stage featuring follower-boost capability. For the design of the PFC stage, please refer to the application notes AND8016 AND8016 and AND8123 AND8123. OPP Downstream Converter Please refer to the application note AND8240 AND8240 for the implementation of the NCP1381 NCP1381. Details of some design choices are described below. When OPP resistor is added, RSENSE must be adjusted. In order to set the overpower protection for an output power of 130 W, RSENSE is changed to 120 mW, and ROPP is set to 2.7 kW. Transformer PFC Control (GTS) The primary inductance has been chosen in order to ensure a switching frequency lower than 130 kHz at high line when the output load is equal to 50% of the maximum load. An additional constraint is the turn ratio between primary and secondary inductors that must ensure that the voltage appearing across the switching MOSFET during OFF time is lower than 600 V with some margin. Low line full load freq: 30 kHz High line full load freq: 70 kHz Valley jumping: < 50% load at high line The board provides two ways of connecting the PFC controller to the GTS signal: directly, or through a buffer (made with a bipolar transistor). The power levels at which PFC turn on and off are set by R35, R36, R37 and C25: these levels are currently 25 W (turn-off) and 40 W (turn-on), but can easily be adjusted depending on the needs. Auxiliary Winding In order to ensure a VCC higher than 10 V in no-load conditions, auxiliary voltage is 30 V, and VCC capacitor is split. A Zener diode is added to protect the controller. Splitting the tank capacitor allows to increase the stored energy (in capacitor E2), while keeping a small VCC capacitor (capacitor E1) that ensures a fast start-up time. LP = 240 mH IPmax at low line: 6 A Turn ratio primary / secondary is equal to 4.4 (2.75 for the auxiliary winding), ensuring a reflected voltage from secondary to primary VREFLECT < 100 V (exactly 90 V). (See "Transformer construction" paragraph at the end of this document) Clamp The MOSFET used cannot sustain voltages above 600 V, we thus need to add a clamping network to protect it. The RCD clamp made of D9, R23 and C16 give a sufficient protection without degrading too much the standby power. If a lower standby power is needed, R23 and C16 can be replaced by a 200 V TVS. RSENSE The sense resistor is designed to allow the maximum peak current of 6 A. Knowing that the current sense comparator threshold is 800 mV, RSENSE should then be smaller than 130 mW. Secondary Side For the simplicity of the demonstration board, a Schottky diode will be used as a rectifier, and not a synchronous rectifier as it would be in a real application. The regulation is made around a TL431 TL431. Brown-out The voltage sensing for brown-out protection can either be taken in front of the PFC stage, for a true brown-out MEASUREMENTS: Power Factor and Efficiency Current Harmonic THD Voltage Harmonic THD Power Factor IIN (Adc) UIN (Vdc) IOUT (Adc) UOUT (Vdc) PIN (W) POUT (W) Eff. (%) 6.959 20.134 0.995 1.65 89.03 6.307 19.56 146.68 123.4 83.65 8.267 0.142 0.992 1.27 114.25 6.307 19.56 145.52 123.4 84.07 9.851 0.072 0.985 0.99 149.38 6.307 19.56 147.67 123.4 82.28 10.631 0.060 0.976 0.84 179.48 6.307 19.56 150.67 123.4 79.92 11.983 0.056 0.960 0.72 209.52 6.307 19.56 151.77 123.4 78.06 13.377 0.053 0.937 0.646 239.54 6.307 19.56 154.80 123.4 74.70 15.065 0.051 0.912 0.600 264.52 6.307 19.56 158.59 123.4 70.98 http://onsemi.com 4 AND8260/D AND8260/D No-load Power: 140 mW at 90 Vac 450 mW at 230 Vac. Start-up VOUT VOUT Figure 4. Start-up at 110 VAC Figure 3. Start-up at 230 VAC Load Transient VOUT (Ac Variations) IOUT Figure 5. Load Dump from 100% to No-load http://onsemi.com 5 AND8260/D AND8260/D Short-circuit VOUT VOUT VDRAIN VDRAIN Figure 7. Detail of a Short-circuit Burst Figure 6. Short-circuit Burst Mode Skip Figure 8. Skip Mode Figure 9. Detail of a Skip Burst http://onsemi.com 6 AND8260/D AND8260/D PCB Layout Figure 10. Solder Side (bottom view) Figure 11. Top Side (top view) Figure 12. Top View of Component Side http://onsemi.com 7 AND8260/D AND8260/D Figure 13. Bottom View of Solder Side (SMD Components) Figure 14. Board Picture http://onsemi.com 8 AND8260/D AND8260/D Table 1. BILL OF MATERIALS Part B1 Value Package Part Value Package KBU810 KBU810 L1 6,3 mH C01 1 m/X2 L2 200 mH C02 1 m/X2 L3 15 mH C03 2n2/Y2/X1 L4 2,2 mH C04 2n2/Y2/X1 M1 SPP11N60C2 SPP11N60C2 C05 1 m/X2 M2 SPP11N60C2 SPP11N60C2 C06 470 p C1206 C1206 Q1 BC807 BC807 C07 100 n C1206 C1206 Q2 BCP56T1 BCP56T1 C08 220 n C1206 C1206 Q3 NU C09 2n2 C1206 C1206 R01 1R C10 1m C1206 C1206 R02 1R 2W C11 330 n C1206 C1206 R03 20 k R1206 R1206 C12 33 p C1206 C1206 R04 560 k R1206 R1206 C13 NU C1206 C1206 R05 680 k R1206 R1206 C14 100 n C1206 C1206 R06 680 k R1206 R1206 C15 100 n C1206 C1206 R07A NU 2W C16 10 n R07B 560 k R1206 R1206 C17 470 p R08 910 k R1206 R1206 R09 910 k R1206 R1206 R10 10 k R1207 R1207 C18 NU C19 39 n C20 NU R11 5k6 R1206 R1206 C21 2n2n/Y1/X1 R12 100 k R1206 R1206 C22 100 p R13 22 k R1207 R1207 C23 1n R14 NU C24 NU R15 NU C25 220 n R16 2k2 R1206 R1206 D01 MUR460 MUR460 R17 270 k R1206 R1206 D02 MMSD4148T1 MMSD4148T1 R18 270 k R1206 R1206 D03 15 V R19 270 k R1206 R1206 D04 NU R20 2k7 R1206 R1206 D05 18 V R21 47R R1206 R1206 D06 MURA120 MURA120 R22 22R R1206 R1206 D07 MMSD4148 MMSD4148 R23 10 k R1206 R1206 D08 MMSD4148 MMSD4148 R24 0,12R D09 MUR1100E MUR1100E R25 NU D10 MRA4007 MRA4007 R26 1k R1206 R1206 D11 MRA4007 MRA4007 R27 36 k R1206 R1206 D12 MBR20200 MBR20200 R28 5k6 R1206 R1206 E1 220 m/450 V R29 56 k R1206 R1206 E2 220 m/35 V R30 75 k R1206 R1206 E3 33 m/63 V R31 4M7 E4 2200 m/35 V R32 NU E5 2200 m/35 V R33 NU E6 2200 m/35 V R34 NU E7 220/63 V R35 2k2 R1206 R1206 F1 T2A R36 6k2 R1206 R1206 IC1 MC33260 MC33260 R37 27 k R1206 R1206 IC2 NCP1381 NCP1381 R38 1k R1206 R1206 IC3 PC817 PC817 RTH1 IC4 TLV431 TLV431 T1 C1206 C1206 http://onsemi.com 9 strapped Transformer AND8260/D AND8260/D Transformer Construction 1 12 N1 2 11 N1 10 3 N2 4 9 5 8 N3 6 N3 N1 N2 N1 7 Transformer Type: RM14 Material: N67 Marking: B65888-C1512-T1 B65888-C1512-T1 N1 - 11 turns of multiwire 20 x f0,2 mm 3 kV isolation N2 - 5 turns of 5 paralleled multiwires 25 x f0,2 mm 3 kV isolation N1 - 11 turns of multiwire 20 x f0,2 mm 1.5 kV isolation N3 - 8 turns of wire f0,2 mm ÄÄÄÄÄ ÄÄÄ ÄÄÄÄÄÄ ÄÄÄÄÄ Ä ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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