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AND8066/D Datasheet

Part Manufacturer Description PDF Type
AND8066D On Semiconductor Interfacing with ECLinPS Original

AND8066/D

Catalog Datasheet MFG & Type PDF Document Tags

E4-16

Abstract: LVEL16 AND8066/D Interfacing with ECLinPS Prepared by: Paul Shockman ON Semiconductor Logic , : AND8066/D AND8066/D VBB Reference Error For a standard differential receiver with two input pins ­ , http://onsemi.com 2 AND8066/D Dedicated Single­Ended Input Structure A device may have a , AND8066/D ECL 10 and 100 Performance Standards There currently exist two basic legacy standards for high , Vin vs. Vout Transfer Curves http://onsemi.com 4 AND8066/D ­0.8 ­1.0 ­1.0 Vout
ON Semiconductor
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E4-16 LVEL16 practical application of schmitt trigger AND8066/D

practical application of schmitt trigger

Abstract: AND8066/D Interfacing with ECLinPS Prepared by: Paul Shockman ON Semiconductor Logic Applications , , 2002 1 January, 2002 ­ Rev. 1 Publication Order Number: AND8066/D AND8066/D VBB Reference , Generator http://onsemi.com 2 AND8066/D Depending on system requirements, VBB may be generated by a , sensitivity). http://onsemi.com 3 AND8066/D · Wide signal interface windows. · High receiver , Figure 14. 100E Series Vin vs. Vout Transfer Curves http://onsemi.com 4 AND8066/D ­0.8 ­1.0 ­1.2
ON Semiconductor
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LVEL16

Abstract: NBSG16VS AND8066/D Interfacing with ECLinPS Prepared by: Paul Shockman ON Semiconductor Logic , Driver with Independent Standard Single­Ended Receivers 1 Publication Order Number: AND8066/D AND8066/D VBB Reference For a standard differential receiver with two input pins ­ D and D ­ only one , . VBB Voltage Reference Generator http://onsemi.com 2 AND8066/D Depending on system , sensitivity). http://onsemi.com 3 AND8066/D · Wide signal interface windows. · High receiver
ON Semiconductor
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NBSG16VS ECL schmitt trigger
Abstract: AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - , Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Figure 2. Dip Pin , Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2004 121 September, 2004 - Rev. 7 Publication Order Number: MC10H211/D MC10H211 , Brochure, BRD8011/D. *This device is manufactured with a Pb-Free external lead finish only. Resource ON Semiconductor
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10K-C CDIP-16 PDIP-16 PLCC-20 10H211 MC10H211P

KVT20

Abstract: AN1642 AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at , . The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAM 8 1 SO-8 D , Work Week *For additional marking information, refer to Application Note AND8002/D. ORDERING , Industries, LLC, 2004 266 September, 2004 - Rev. P1 Publication Order Number: MC100LVELT20/D MC100LVELT20 Table 1. PIN DESCRIPTION NC 1 8 VCC Q, Q Q 2 LVTTL D 7 D VCC GND NC Q 3 LVPECL 6 NC Pin Function
ON Semiconductor
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KVT20 AN1642 AND8002/D MC100LVELT20/D AND8020 MC100LVELT20D MC100LVELT20DR2

CML ECL termination

Abstract: MC100EP16 . AN1404/D ­ ECLinPSTM Circuit Performance at Non-Standard VIH Levels AN1568/D ­ Interfacing Between LVDS and ECL AND8020/D ­ Termination of ECL Logic Devices AND8066/D ­ Interfacing with ECLinPS , SGD508/D Jan-2002 Rev 0 1 to 12 GHz Differential Receiver/Drivers Bandwidth (GHz) Gain Input Termination (50) Open Input Default State (D, D) Input Level Output Level Output , using external components (See AND8020/D). 2. 50 termination fixed (See AND8020/D). 3. Reduced swing
ON Semiconductor
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MC10EP16T CML ECL termination MC100EP16 MC100EP16F MC100EP16VS MC100EP16VT MC100LVEP16 SGD508/D MC100EP16T MC10EP16VA MC100EP16VA MC100EP16VB

10H124

Abstract: plcc20 socket Brochure, BRD8011/D. *This device is manufactured with a Pb-Free external lead finish only. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - , /D. © Semiconductor Components Industries, LLC, 2004 42 September, 2004 - Rev. 8 Publication Order Number: MC10H124/D MC10H124 Table 1. DIP CONVERSION TABLE 16-Pin DIL to 20-Pin PLCC 16
ON Semiconductor
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10H124 plcc20 socket EIAJ-16 MC10H124P MC10H124L MC10H124PG MC10H124FN

KP140

Abstract: marking 1145 of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics , differential UP (U) and DOWN (D) outputs will provide pulse streams which, when subtracted and integrated , 5. Features · · · · · · · · · · · 8 8 1 A L Y W G SOIC-8 D SUFFIX CASE , *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See , Industries, LLC, 2006 MARKING DIAGRAMS* 1 Publication Order Number: MC100EP140/D MC100EP140
ON Semiconductor
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AND8040 KP140 marking 1145 100EP EP140 AND8090/D MC100EP140/D
Abstract: /D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution , MC100EL30 5V ECL Triple D Flip-Flop with Set and Reset The MC100EL30 is a triple master-slave D , Application Note AND8003/D · Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 · Transistor , marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering , : MC100EL30/D MC100EL30 VCC Q0 Q0 VCC Q1 Q1 VCC Q2 Q2 VEE Table 13. PIN DESCRIPTION Pin D0-D2 R0-R2 ON Semiconductor
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EIA/JESD78 AND8003/D SO-20 100EL30 AND8020/D MC100EL30DW

100LVEL92

Abstract: AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - , Level 1 For Additional Information, see Application Note AND8003/D · Flammability Rating: UL 94 V-0 @ , Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the , Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2004 261 October, 2004 - Rev. 9 Publication Order Number: MC100LVEL92/D MC100LVEL92 VCC 20 Q0 19 Q0 LVCC 18 17 Q1 16 Q1
ON Semiconductor
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100LVEL92 MC100LVEL92DW MC100LVEL92DWR2 MC100LVEL92DWR2G BRD8011/D AN1405/D AN1406/D

KLT24

Abstract: HLT24 AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - , V; VEE = -4.2 V to -5.5 V with GND = 0 V Pb-Free Packages are Available 8 1 SO-8 D SUFFIX CASE , additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed , : MC10ELT24/D MC10ELT24, MC100ELT24 Table 1. PIN DESCRIPTION VEE 1 8 VCC Pin Q, Q TTL D 2 ECL NC 3 6 Q 7 Q D VCC VEE GND NC Function ECL Differential Outputs* TTL Input Positive Supply Negative Supply
ON Semiconductor
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HLT24 KLT24 MC10ELT/100ELT24 ELT24 MC100 MC10ELT24/D

100EL91

Abstract: AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - , D input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the , Additional Information, see Application Note AND8003/D · Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen , AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package , , SOLDERRM/D. © Semiconductor Components Industries, LLC, 2004 115 October, 2004 - Rev. 4
ON Semiconductor
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100EL91 MC100EL91 MC100LVEL91 MC100EL91DW MC100EL91DWR2 MC100EL91DWR2G AN1503/D
Abstract: AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - , ground via 0.01 mF capacitors. Under open input conditions, the D input will be biased at VCC/2 and the D , information, refer to Application Note AND8002/D. VEE = -3.0 V to -5.5 V; GND = 0 V Q Output will Default , Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2004 256 June, 2004 - Rev. 7 Publication Order Number: MC100LVEL91/D MC100LVEL91 GND GND VCC VCC ON Semiconductor
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LVEL91 MC100LVEL91DW MC100LVEL91DWR2 MC100LVEL91DWR2G AN1504/D AN1568/D

KVL11

Abstract: AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - , DIAGRAMS* 8 8 1 SOIC-8 D SUFFIX CASE 751 1 8 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 A L Y W = Assembly Location , AND8002/D. Q0 2 7 D ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 160 of this data sheet. Q1 3 6 D Q1 4 5 , ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Pin Function Q0, Q0; Q1, Q1 D, D ECL Data
ON Semiconductor
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KVL11 MC100LVEL11 LVEL11 MC100LVEL11D MC100LVEL11DR2 MC100LVEL11DR2G

10H124G

Abstract: 10H124 Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC , information, refer to Application Note AND8002/D. Figure 2. Pin Assignment *For additional information on , Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 1 , the package dimensions section on page 3 of this data sheet. Publication Order Number: MC10H124/D , refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of
ON Semiconductor
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10H124G AN-1503 DIL socket 16pin MC10H124FNG MC10H124FNR2 MC10H124FNR2G 10KTM SOEIAJ-16 PLLC-20 MC10H124/D

kvt23

Abstract: AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - , ://onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC-8 D SUFFIX CASE 751 1 8 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 A L Y W = , AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package , August, 2004 - Rev. 11 Publication Order Number: MC100LVELT23/D MC100LVELT23 Table 7. PIN , JEDEC Spec EIA/JESD78 IC Latchup Test 13. Refer to Application Note AND8003/D for additional information
ON Semiconductor
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kvt23 LVELT23 KVT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DR2G MC100LVELT23DT
Abstract: Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066 , MC100LVEL30 3.3V ECL Triple D Flip-Flop with Set and Reset The MC100LVEL30 is a triple master-slave D flip-flop with differential outputs. Data enters the master latch when the clock input is LOW , Moisture Sensitivity Level 1 · · For Additional Information, see Application Note AND8003/D Flammability , additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ON Semiconductor
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100LVEL30 MC100LVEL30DW MC100LVEL30DWR2 SOIC-20 AN1642/D AND8001/D
Abstract: AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - , DIAGRAMS* 8 8 1 SOIC-8 D SUFFIX CASE 751 1 KVL32 ALYW · 2.6 GHz Typical Maximum Frequency · ESD , Level 1 · For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ , information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping , Industries, LLC, 2004 197 October, 2004 - Rev. 6 Publication Order Number: MC100LVEL32/D ON Semiconductor
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MC100LVEL32 LVEL32 MC100LVEL32D MC100LVEL32DR2 MC100LVEL32DR2G MC100LVEL32DT

kvt22

Abstract: transistor BD 540 /Size AN1406/D - 105.0 KB AN1672/D - 51.0 KB AND8066/D - 58.0 KB AND8001/D - 90.0 KB AND8090/D - 896.0 , signal. http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO-8 D SUFFIX CASE 751 1 8 8 1 TSSOP-8 DT SUFFIX CASE , Application Note AND8002/D. ORDERING INFORMATION Device MC100LVELT22D MC100LVELT22DR2 MC100LVELT22DT , -8 2500 Units/Reel *For additional tape and reel information, see Brochure BRD8011/D. © Semiconductor Components Industries, LLC, 2003 271 March, 2003 - Rev. 2 Publication Order Number: MC100LVELT22/D
ON Semiconductor
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kvt22 transistor BD 540 MC100LVELT22 LVELT22 KVT22 MC100LVELT22DTR2 MC100LVELT22/D AN1672/D

485G

Abstract: NB4L52MNG AND8002/D - Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - , NB4L52 2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination The NB4L52 is a differential Data and Clock D flip-flop with , Application Note AND8002/D. VTD D Data D Q VTD Q VTCLK CLK Clock CLK Reset , , please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
ON Semiconductor
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485G NB4L52MNG NB4L52MNR2G NB6L239 transistor tip 3055 QFN-16 NB4L52/D

MC100LVEL30

Abstract: MC100LVEL30DW AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D
ON Semiconductor
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MC100LVEL30/D

marking qna

Abstract: MC100LVEL13 Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC
ON Semiconductor
Original
MC100LVEL13 marking qna MC100LVEL13DW MC100LVEL13DWG 100LVEL13 MC100LVEL13/D
Abstract: AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ON Semiconductor
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MC100LVEL14 LVEL14 MC100LVEL14DW MC100LVEL14DWR2 MC100LVEL14DWG MC100LVEL14DWR2G

100lvel37

Abstract: MC100LVEL37 AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics of ECL Devices http
ON Semiconductor
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MC100LVEL37 100lvel37 MC100LVEL37DW MC100LVEL37DWG 100LVEL37 MC100LVEL37/D

MC100EL30DW

Abstract: MC100EL30 Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing
ON Semiconductor
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MC100EL30/D

780 AC

Abstract: pecl logic voltage levels Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing
ON Semiconductor
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780 AC pecl logic voltage levels MC100LVEL92/D

AND8020

Abstract: KVT20 of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics
ON Semiconductor
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