AN99068 UAA1570HL SAA1575HL SAA1575 UAA1570 RS232 WGS-84 NMEA0183 RTCM-SC104 - Datasheet Archive

 

AN99068 DESIGNERS GUIDE EXACT GPS Low Cost Reference Board (Version 1.0) Philips Semiconductors Philips Semiconductors DESIGNERS

 

APPLICATION NOTE AN99068 AN99068 DESIGNERS GUIDE EXACT GPS Low Cost Reference Board (Version 1.0) Philips Semiconductors Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Application Note (Version 1.0) AN99068 AN99068 Abstract EXACT is a Philips GPS (Global Positioning System) receiver circuit chip-set comprising an RF front-end, UAA1570HL UAA1570HL and a Baseband processor, SAA1575HL SAA1575HL. The firmware is supplied with the purchase of the chip-set providing the user with a complete navigation solution capable of accuracies to within 5 meters with the use of Differential GPS (DGPS). The EXACT low cost reference design has been developed to demonstrate a small, low cost, low power GPS receiver solution using the EXACT chip-set. This system is intended as a reference that can be used by the customer to greatly reduce the development time and cost for their own receiver design. The EXACT Designers Guide details every aspect of the reference system design through to PCB layout. Also provided in this document are the full schematics, parts lists and assembly drawings as well as detailed test instructions and a fault finding guide to aid production testing. Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conforms to the I2C specifications defined by Philips. © Philips Electronics NV 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation, is believed to be accurate and reliable, and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent - or other industrial or intellectual property rights. 2 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 APPLICATION NOTE AN99068 AN99068 DESIGNERS GUIDE EXACT GPS Low Cost Reference Board (Version 1.0) Author(s) M Thorne G Addey Philips Semiconductors Systems Laboratory Southampton, England Keywords: GPS EXACT PCB SAA1575 SAA1575 UAA1570 UAA1570 Date: 02 December, 1999 3 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 Summary EXACT is a Philips GPS receiver chip-set, including system firmware, providing the user with a complete navigation solution capable of accuracies to within 5 meters with the use of Differential GPS (DGPS). EXACT is a two chip solution comprising an RF front-end, UAA1570HL UAA1570HL and a Baseband processor, SAA1575HL SAA1575HL. The EXACT low cost reference design has been developed to demonstrate a small, low cost, low power GPS receiver solution using the EXACT chip-set.The EXACT Designers Guide details every aspect of the reference system design through to PCB layout. Also provided in this document are the full schematics, parts lists and assembly drawings as well as detailed test instructions and a fault finding guide to aid production testing. 4 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) Page Number Table of Contents 1 AN99068 AN99068 11 1.1 1.2 2 INTRODUCTION 11 13 Glossary Features 15 2.1 2.2 2.3 2.4 2.5 2.6 3 PRODUCT DESCRIPTION 15 16 17 18 18 19 TECHNICAL SPECIFICATION Performance Specification Antenna Specification Electrical Connections EXACT GPS Mother-Board GPS Engine PCB GPS ENGINE DESIGN GUIDE 21 3.1 3.1.1 3.1.2 3.1.3 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.2 3.5.3 3.6 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.9.1 3.9.2 3.10 3.10.1 3.10.2 3.10.3 3.11 3.11.1 3.11.2 21 21 22 22 22 23 24 26 26 28 29 30 31 32 33 34 34 36 37 38 38 42 44 44 45 49 51 54 55 56 57 57 57 58 58 60 61 61 62 63 63 64 64 GPS Antenna Selection Passive Antenna Solution Active Antenna Solutions Circuit Considerations for Disabling On-Chip LNA's Impedance Matching for RF Stages Microstrip Design Procedure determining track widths determining track lengths DC Bias Line Matching Circuit LNA2 Input Matching Circuit LNA2 Output Matching Circuit Mixer1 Input Matching Circuit LNA1 Input Matching Circuit LNA1 Output Matching Circuit Bandpass Filter Selection VCO and PLL Filter VCO Phase Locked Loop Filter First IF Filter Filter Specification IF1 Filter Design Procedure Verifying Maximum First Mixer Output Voltage Swing Second IF Filter Filter Specification IF2 Filter Design Procedure Verifying Maximum Second Mixer Output Voltage Swing SAW Filter Implementation for IF1 Reference Clock UAA1570 UAA1570 Considerations SAA1575 SAA1575 Considerations Digital Interface RF Serial Interface SCLK and SIGN Output Clock Circuits for SAA1575 SAA1575 30 MHz System Clock Real Time Clock Oscillator Power Up/Down Control for SAA1575 SAA1575 Power Up Sequence Power Down Sequence Split 5 V and 3 V Supply Considerations Battery Backup Circuit Single 3 V Application Split 3 V and 5 V Application 5 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) Table of Contents Cont'd AN99068 AN99068 Page Number 4 GPS ENGINE LAYOUT GUIDELINES 65 4.1 Summary of Critical Layout Areas65 4.2 Microstrip Line Layout 4.2.1 Avoid Close Proximity Stray Grounds Pertubations 4.2.2 Avoid Close Proximity Components 4.2.3 General Microstrip Layout Guidelines 4.3 VCO and PLL Filter 4.3.1 VCO 4.3.2 Phase Locked Loop Filter 4.4 First and Second IF Filters 4.5 Reference Clock 4.6 Digital Interface 4.6.1 RF Serial Interface 4.6.2 Sample Clock and SIGN Output 4.7 Clock Circuits for SAA1575 SAA1575 67 67 67 68 68 69 70 70 70 72 72 72 73 GPS MOTHER-BOARD DESCRIPTION 73 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 73 73 75 75 75 75 75 5 6 Power Supplies GPS System Supply Battery Backup Supply GPS Antenna Supply RS232 RS232 Interface Master Reset Switch LED Indicators 76 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 SCHEMATICS AND BUILD STANDARDS 76 79 80 82 84 85 86 GPS Engine Schematics GPS Engine Assembly Drawing GPS Engine Layout Plots Parts List For Gps Engine Board Mother-Board Schematic Mother-Board Assembly Drawing Parts List For Gps Mother-Board TEST INSTRUCTIONS 87 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.5 7.6 7.6.1 7.6.2 7.7 7.8 87 87 87 88 88 88 88 89 89 89 89 90 91 91 91 92 93 94 Test Equipment Required DC Voltage Checks System and Antenna Supplies Battery Backup Supply, VBATT PWR_DN and PWR_Fail VCO Tuning Voltage System Power Consumption Normal Operation Battery Backup mode VCO Phase Noise Inband Phase Noise up to 10 kHz Outband Phase Noise Up To 100 kHz Offset From Carrier SCLK Amplitude IF Filter Responses IF1 Filter Measurements IF2 Filter Measurements Gain Distribution Sensitivity and System Noise Figure 6 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) Table of Contents Cont'd 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.9.7 8 9 Page Number Functional Performance Position Accuracy Satellite Signal Level Acquisition Time (TTFF) Reacquisition Time Serial Communication Differential GPS 1PPS Output 94 95 95 96 96 97 97 98 TROUBLE SHOOTING GUIDE 8.1 8.2 8.3 8.4 8.5 8.6 8.7 AN99068 AN99068 99 VCO Not Running Poor VCO Phase Noise Response Poor Receiver Sensitivity No NMEA Message Output from SAA1575 SAA1575 Failure to Track Satellites Excessive Time To First Fix or No Valid Position Output Intermittent Power Failure 100 100 100 101 102 102 103 103 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.2.1 9.3 9.3.1 9.3.2 9.4 9.5 9.6 9.6.1 9.6.2 9.7 10 MANUFACTURER DETAILS AND USEFUL URL'S 103 103 104 104 105 105 105 105 105 106 106 107 107 108 108 108 Integrated Circuits EPROM SRAM Voltage Monitor ICs Reference Clock Squaring Circuit Discrete Components Varactors TCXO's and Crystals 14.40 MHz TCXO's 30 MHz Crystals (Processor Clock) Inductors Filters GPS Active and Passive Antenna Active GPS Antenna Passive Antenna Elements Eezmatch Software REFERENCES 109 APPENDICES A 110 B 111 7 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) Page Number List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 AN99068 AN99068 Technical Specification for the GPS Engine Technical Specification for the Mother-Board Performance Specifications Typical Active Antenna Characteristics EXACT Low Cost Reference Board Connector Pin Assignments Requirement Specification for Passive Antenna Requirement Specification for Active Antenna RF Matching Impedances (1.57542 GHz) Netlist Parameters Description Track Width Calculations for Impedance Controlled Lines Impedance and Velocity Factor for Microstrip Line Calculations Bandpass Filter Data for Mitsubishi and MuRata Components Constants Required for VCO Loop Filter Calculation Gain Stages Prior to Mixer1 input Constants for Verifying Mixer Output Voltage Swing Gain Stages Prior to Mixer2 Input Second Mixer Characteristics SAW Filter Characteristics Recommended Specification for Reference Oscillator Reference Clock and Sample Clock Limits for UAA1570 UAA1570 SAA1575 SAA1575 System Clock Oscillator Characteristics Specification for 30 MHz Crystal Watch Crystal Specification Power up Procedure for SAA1575 SAA1575 Power Down Procedure for the SAA1575 SAA1575 Overview of Most Critical Layout Aspects Of Gps Design Schematic and Build Standard Cross References Test Equipment Description Test Instruction - DC Supply Voltages Test Instructions - Battery Backup Supply Test Instructions - PWR_DN and PWR_FAIL Test Instructions - VCO Tuning Voltages Test Instructions - Typical System Power Consumption Test Instructions - Battery Backup Power Consumption Test Instructions - In-Band Phase Noise Measurement Set-up Test Instructions - Out-band Phase Noise Test Instructions - Out-band Phase Noise Measurement Set-up Test Instructions - Out-Band Phase Noise Test Instructions - SCLK Amplitude and DC Offset Test Instructions - IF1 Filter Measurement Set-Up Test Instructions - IF2 Filter Measurement Set-up Test Instructions - Receiver Sensitivity Test Instructions - -3dBSensitivity and Estimated Noise Figure Test Instructions - Standard Horizontal Position Accuracy (95%) Test Instructions - Satellite SNR Level Sensitivity Test Instructions - Acquisition Times (TTFF) 8 15 16 16 17 18 21 22 23 23 25 25 33 36 43 43 49 50 52 55 56 58 60 61 62 63 66 76 87 87 88 88 88 89 89 89 90 90 90 91 91 92 93 94 95 95 96 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) List of Tables cont'd 47 48 49 50 51 AN99068 AN99068 Page Number Test Instructions - Reacquisition Time Test Instructions - DGPS Position Accuracy (95%) Trouble Shooting Guide Key EPROM Requirements Key SRAM Requirements 9 97 98 99 103 104 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) Page Number List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 AN99068 AN99068 Simplified Block Diagram Picture of the EXACT Low Cost Reference Board (GPS Engine) Picture of the Complete EXACT Low Cost Reference System Overview of GPS Engine Board Layer Construction for GPS Engine Board Smith Chart Plot of Bias Line Matching Network Smith Chart Plot of LNA2IN Matching Network Smith Chart Plot of LNA2OUT Matching Network Smith Chart Plot of MIXER1 Input Matching Network Smith Chart Plot of LNA1IN Matching Network Smith Chart Plot of LNA1OUT Matching Network Typical VCO Circuit Configuration VCO Loop Filter Circuit Single-Ended 6th Order IF1 Filter Design (Based on 3rd Order Butterworth Lowpass) Double-Ended 6th Order IF1 Filter Design (Based on 3rd Order Butterworth Lowpass) Simulated Response of IF1 Filter at 41.82 MHz Single-Ended 6th Order IF2 Filter Design (Based on 3rd Order Butterworth Lowpass) Simulated Response of IF2 Filter at 3.48 MHz SAW Filter input Match to Mixer1 Output SAW Filter Output Match to Mixer2 input Circuit Implementation for 41.82 MHz SAW Filter SCLK Divider Circuit for UAA1570 UAA1570 Determining 30 MHz Oscillator Circuit Requirements PWR_FAIL Delay Circuit for Mixed Supply Applications Battery Backup Circuit for Single 3 V Supply Battery Backup Circuit for Mixed 3 V and 5 V Supplies Layout Principle for Reference Clock Routing Digital Interface Routing Between SAA1575 SAA1575 and UAA1570 UAA1570 System Supply Voltage Regulator Circuit GPS Schematic 1 RF Front-End GPS Schematic 2 Baseband Processor GPS Engine Component Ident (Top Layer) GPS Engine Component Ident (Bottom Layer) GPS Engine Layout (Top Layer) GPS Engine Layout (Inner Layer 1) GPS Engine Layout (Inner Layer 2) GPS Engine Layout (Bottom Layer) Schematic Diagram for GPS Mother-Board GPS Mother-Board Component Ident (Top Layer) GPS Mother-Board Component Ident (Bottom Layer) IF1 Filter Response IF2 Filter Response 10 14 19 19 20 24 27 28 29 30 31 32 34 36 40 40 41 41 47 48 53 53 54 56 59 63 64 65 71 72 74 77 78 79 79 80 80 81 81 84 85 85 92 93 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 1 Application Note (Version 1.0) AN99068 AN99068 INTRODUCTION EXACT is a Philips GPS (Global Positioning System) receiver circuit chip-set which will provide the user with a GPS receiver function, as well as an embedded controller to convert the raw satellite data to a navigation solution. The controller is capable of receiving Differential GPS (DGPS) data which will allow position accuracy to be within 5 meters. Philips technology will allow you to think of GPS as what it really is; a general purpose utility that provides position and time information. This board runs from a 3 V supply allowing very low power operation. It implements a cost optimised design both in terms of external components and board size. The design is typical of OEM modules currently available on the market and serves as an ideal reference layout for the chip-set. This document provides details of the hardware and layout to enable customers to design the chip-set in quickly, by greatly reducing development time. 1.1 Glossary 2D Two dimensional. 3D Three dimensional. Acquisition The process of finding and locking on to a satellite signal. A/D Analogue to Digital Converter. Almanac A set of data describing the position of all satellites in the GPS constellation. BIT Built In Test. BPF Bandpass Filter. Channel One of 8 physical hardware receivers available to demodulate a satellite signal. Channel algorithm Low level software to manage each channel of the EXACT baseband receiver. Constellation The arrangement of the satellites in the sky. Correlator A system for computing the correlation of a signal with another local reference. Datum A reference set of co-ordinates which defines the model of the surface of the earth used for position computations. The default is WGS-84 WGS-84. DGPS Differential GPS. DOP Dilution Of Precision, ie: reduction of precision in a computation due to bad satellite geometry. DRAM Dynamic RAM. ECEF Earth Centred Earth Fixed. EEPROM Electrically Erasable Programmable ROM. Elevation Angle above the horizon in degrees. Elevation Mask Elevation angle above which satellites will be used in navigation computation. 11 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 EPROM Electrically Programmable ROM. EXACT England XA Ashtech CPG Technology. GPS Global Positioning System. HDOP Horizontal Dilution of Precision. IC Integrated Circuit. Icc Current supplied to the positive terminal of a circuit. Image Rejection The attenuation of the image frequency in a mixing process. I/O Input/Output. J/S Jammer to Signal Ratio L1 The frequency band for civil GPS signals (centred on 1575.42 MHz). LNA Low Noise Amplifier. Mask A programmable threshold value above or below which data will not be used. Navigation solution High level software to compute the position from received satellite data. NMEA0183 NMEA0183 Standard for transmitting/receiving navigation information. Noise Figure The additional noise added by a circuit, over and above that due to the input noise. PPS Pulse per second. PRN Pseudo-Random Noise (ie: the unique spreading code used per satellite). RAM Random Access Memory. RF Radio Frequency. RF Sensitivity The minimum signal level required to achieve a given level of performance. ROM Read Only Memory. RTC Real Time Clock. RTCM-SC104 RTCM-SC104 Standard for differential correction data. UAA1570 UAA1570 The type number of the RF front-end IC of EXACT. SAA1575 SAA1575 The type number of the digital baseband IC of EXACT. Signal Strength The signal level of the satellite signal on a given channel, as computed by the correlator hardware in the channel. Spurious An unwanted signal. SV Space Vehicle, ie: a satellite. 12 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 TTFF Time To First Fix. UART Universal Asynchronous Receiver Transmitter. Update Rate The frequency at which navigation solutions are computed. UTC Universal Time Co-ordinated. VCC Positive supply voltage. VDOP Vertical Dilution of Precision. VSWR Voltage Standing Wave Ratio (a measure of quality of matching of impedance). WGS-84 WGS-84 A datum, World Geodetic System 1984. 1.2 Features · Eight parallel satellite channels tracking eight satellites at the same time. · Power Management functions. Power down mode. Reduced update rate option. · Supports true NMEA 0183 data protocol. · Direct differential RTCM SC-104 SC-104 capability. · Rapid Time-To-First-Fix (TTFF). · RF input designed for active or passive Antenna Systems. · Multiple Operating Modes. Automatic Mode. Fixed 3D mode. Fixed 2D mode. In all the above modes, UTC time is also available. · · User programmable DOP Masks.1 · User programmable Satellite signal level mask. 1 · 1. User programmable Elevation Mask.1 Standard serial I/O. The software provided defaults to selected values to optimize performance, but each parameter is user programmable. 13 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board UAA1570HL UAA1570HL LNA at Antenna (optional) UAA1570 UAA1570 Control IF Input Application Note AN99068 AN99068 (Version 1.0) SAA1575HL SAA1575HL NMEA O/P RTCM I/P 3 8 Channel GPS Correlator BP Filters SCLK Reference Clock Real-time Clock 1 PPS XA Processor IF Filter TCXO RAM Figure 1 ROM Simplified Block Diagram 14 Backup Switch 3 V Battery Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 2 Application Note (Version 1.0) AN99068 AN99068 PRODUCT DESCRIPTION The EXACT Low Cost Reference Board has been designed primarily to reduce system cost, and provide a reference layout for a typical OEM type module. It runs directly from a 3 V DC supply and provides a TTL interface for both UARTS. The battery backup supply must be provided externally as well as the antenna supply input. This enables the use of either 5 V or 3 V active antenna in the application. The system described is intended for use with an active GPS antenna with between 10 dB and 26 dB gain including cable losses. The description outlined in the following sections is specific to this particular application and does not form the total specification of the chip-set. For chip-set specifications please refer to the relevant data sheets, Reference [1] and [2]. 2.1 TECHNICAL SPECIFICATION Table 1 and 2 list the important technical specifications for the system. The total system comprises two PCB's the first being the GPS Engine and the other the GPS Mother-board. The GPS Engine provides the complete GPS solution and provides a 3 V CMOS interface for the serial ports. The GPS Mother-board primarily provides both the system and backup power for the GPS Engine as well as RS232 RS232 compliant outputs for interface to a standard PC serial port(s). Table 1 Technical Specification for the GPS Engine Item Specification General 8-Channel continuous tracking GPS Receiver Board GPS Parameters L1 Frequency, C/A code (SPS) Update Rate User Programmable Between 1 second and 999 seconds (Default = 1 second) Communication Interface Standard NMEA-0183 NMEA-0183 V2.1 Output Supports RTCM-SC104 RTCM-SC104 message types 1,3,6,9 and 16 for DGPS Input Serial Ports One TTL full duplex for standard I/O One TTL half duplex for RTCM Input Baud Rate User programmable between 300bps to 19200bps. Maximum recommended character rate is 400 characters per second Board Dimensions Bare Board: 2.29 x 1.72 x 0.06 Inches Populated: 2.29 x 1.72 x 0.79 Inches Board Connector 20 Way Header 0.1" Pitch (Dual 10 way) Input Voltage System Supply 3 V± 5% Input Power 3 V DC Backup Voltage 2.7 to 3.1 V (Typically 3 V Lithium cell) Backup Power 3 V DC < 40 µW typical (13 µA) Noise Figure 7 dB typical without antenna < 320 mW typical 15 (58.2 x 43.7 x 1.6 mm) (58.2 x 43.7 x 20 mm) Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Table 2 Application Note AN99068 AN99068 (Version 1.0) Technical Specification for the Mother-Board Item Specification General Indicators LED Indicators for 3 V, 5 V supplies and 1PPS Output Antenna Supply Switchable between 3 and 5 V Battery Backup 3 V Lithium Backup. Switchable to be on or off Serial Ports 2 Off 9-Way Male D-Types Master Reset Push button switch provided to force complete system reset Board Dimensions Bare Board: 4.06 x 3.58 x 0.06 Inches Populated: 4.06 x 3.58 x 0.98 Inches Input Voltage 2.2 Provides power regulators and RS232 RS232 interface for GPS Engine Supply input via molex type connector or standard DC adaptor Voltage Input Between 7 and 17 V DC (103 x 91 x 1.6 mm) (103 x 91 x 25 mm) Performance Specification Table 3 summarises the main performance specification for the GPS System. Table 3 Performance Specifications Item Specification Autonomous Position Accuracy Horizontal 95% Vertical 95% Speed 100 m 156 m 0.2 km/h DGPS Accuracy Horizontal 95% Vertical 50% Speed Typical Acquisition Time < 10 secs HOT (Valid ephemeris, almanac, last pos' and time) < 45 secs WARM (Valid almanac, last pos' and time) < 120 secs COLD (No valid data held) Typical Reacquisition Time 50% < 1 sec < 3 secs < 10 secs Update Rate User selectable from 1 second to 999 seconds in 1 second increments synchronised with GPS. 1PPS Output Calculates time and outputs a 1PPS pulse when it has a position and is tracking one or more satellites. 1PPS output is synchronised to GPS time ± 1 µS. 10 m 6.5 m 0.1 km/h (Typically 50 m) (Typically 5 m) (Complete satellite blockage < 10 seconds) (Complete satellite blockage < 60 seconds) (Complete satellite blockage < 600 seconds) 16 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 2.3 Application Note (Version 1.0) AN99068 AN99068 Antenna Specification For this board the VIC1 active antenna by Matsushita Electric Works, MEW, has been implemented. This is a fairly typical active antenna intended for in vehicle GPS applications. It is important that the antenna gets a clear view of the sky and is positioned on a surface level to the horizon for best results. The following specification is typical for use with the EXACT low cost reference design. Table 4 Typical Active Antenna Characteristics Characteristic Specification Polarisation Right-Hand Circular Polarised Receiving Frequency 1.57542 GHz ± 1.023 MHz Power Supply +3 to +5 V DC Current < 15 mA @ 3 V < 50 mA @ 5 V Total Gain +13 dBi to +26 dBi Output VSWR < 2.5 The Matsushita Electric Works, VIC1 antenna is a 5 V, 20 mA, active antenna with 26 dB gain. Part No: GPS-F-26-SMA-01-B GPS-F-26-SMA-01-B Manufacturing No: CCAD20KG01 CCAD20KG01 A good alternative to the Matsushita antenna is the 3900 range from SiGEM. These antenna can be operated over a wide voltage range, nominally 3 to 5 V, and exhibit very low current and Noise Figure. 1. SGM3900 SGM3900 I = 7 mA @ 3 V, G = 28 dB, NF = 0.8 dB 2. SGM3902 SGM3902 I < 5 mA @ 3 V, G = 13 dB, NF = 1.4 dB. 17 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 2.4 Application Note (Version 1.0) AN99068 AN99068 Electrical Connections A 20 way interface is provided on this board allowing general purpose lines to be used externally if required. In practice this could be reduced if required to minimise connector size. Table 5, lists the assigned signal connections for the board. Table 5 Pin # EXACT Low Cost Reference Board Connector Pin Assignments Signal Name Description 1 Antenna Supply (Switchable from mother-board between 3 and 5 V) 2 VRF 3 V RF Supply Input 3 VBATT Battery Backup Supply Input 4 RF GND GND For RF Supply 5 MRESET Master Reset Input (Active Low) 6 GPIO0 General Purpose I/O from SAA1575 SAA1575 (Port 0) 7 GPIO1 General Purpose I/O from SAA1575 SAA1575 (Port 1) 8 GPIO2 General Purpose I/O from SAA1575 SAA1575 (Port 2) 9 GPIO3 General Purpose I/O from SAA1575 SAA1575 (Port 3) 10 DIG GND GND for Digital Supply 11 TXD0 1st Transmit Output from SAA1575 SAA1575 12 RXD0 1st Receive Input to SAA1575 SAA1575 13 DIG GND GND for Digital Supply 14 TXD1 2nd Transmit Output from SAA1575 SAA1575 15 RXD1 2nd Receive Input to SAA1575 SAA1575 16 DIG GND GND for Digital Supply 17 NC This pin not used 18 DIG GND GND for Digital Supply 19 1PPS One Pulse Per Second output pin from SAA1575 SAA1575 20 2.5 VANT 3 V DIG Main 3 V Digital Supply Input EXACT GPS Mother-Board To enable the GPS Engine to be interfaced easily with a PC, and/or field tested, a mother-board has been developed which accommodates the GPS board. The mother-board provides 2 power connectors to allow drive from either a bench power supply or by mains power adaptor. It will accept a DC input between 7 and 17 V and regulate down to both 5 and 3 V. The 5 V regulator is used to provide an alternative power source for an active antenna. This board also converts the 3 V CMOS levels to true RS232 RS232 levels for interfacing with a PC and provides a lithium cell for battery backup operation. The power source for the antenna can be switched between 5 and 3 V and the battery backup facility can be enabled or disabled by a toggle switch. Two male 9 way D-Type connectors are provided allowing interface to a PC via a standard 9 way null modem cable assembly. Full details of the mother-board can be found in Section 5 on Page 73. 18 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 2.6 Application Note (Version 1.0) AN99068 AN99068 GPS Engine PCB This section provides a physical overview of the EXACT Low Cost Reference System. Figure 2 Figure 3 Picture of the EXACT Low Cost Reference Board (GPS Engine) Picture of the Complete EXACT Low Cost Reference System 19 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note RFIN (SMA) EPROM RF BPF PLCC44 PLCC44 Edge Connector (Version 1.0) AN99068 AN99068 43 mm (1.7") SRAM UAA1570 UAA1570 21 mm (0.83") 52 mm RTC XTAL (2.05") SAA1575 SAA1575 TCXO 14.4 MHz Edge Connector SRAM 30M XTAL Figure 4 Overview of GPS Engine Board The GPS Engine PCB is constructed from 4 layers using standard FR4 dielectric. For all microstrip line calculations a dielectric constant, Er, of 4.0 has been used which falls somewhere between a typical range of 3.8 to 4.2. The design of the microstrip matching lines and various calculations used can be found in Section 3.2 on Page 22. 20 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3 Application Note AN99068 AN99068 (Version 1.0) GPS ENGINE DESIGN GUIDE This section provides detailed design information related to the EXACT chip-set application. Each block of the EXACT GPS system is covered in turn, explaining the basic functionality and highlighting the critical areas of the design. 3.1 GPS Antenna Selection The reference system described in this manual has been designed for use with an active GPS antenna. The antenna used depends upon the implementation of the embedded LNA's on the UAA1570 UAA1570. This section describes the various possible combinations and associated antenna types that can be used, including passive antenna implementation. 3.1.1 Passive Antenna Solution When a passive antenna is to be used both on chip LNA's must be implemented to maximise the RF gain in the system. This application is generally the most difficult to achieve as in most cases the other goal in the system is small size. Typical passive patch antenna require a significant ground plane area to optimize gain and system Noise Figure. Table 6 gives an overview of the various constraints. Table 6 Requirement Specification for Passive Antenna LNA's Implemented Maximum External Gain Minimum External Gain Maximum Ext Noise Figure Minimum GND Plane Area LNA1 & LNA2 10 dB 2 dB 3.5 dB 50 mm X 50 mm The figures given in Table 6 are those recommended, including all cable and filter losses, and do not represent absolute system limits. For example if in this case an active antenna was used with greater than 10 dB of gain, the system would in many cases still function. The problem is that if great care is not taken to protect the RF stages from the antenna itself, feedback can occur resulting in instability in the system. Alternatively it may be possible to use a passive antenna with a typical gain at the zenith of 0 dB, but in this instance the layout and performance of the RF stages would be extremely critical. If the system gain and Noise Figure was not optimal throughout then problems may be encountered. We strongly advise that only high gain passive, ground-planed antenna are used in these applications with nominal gain at 1.57542 GHz of at least 4 dB to 5 dB at the zenith. Many typical passive elements on the market exhibit gains of around 4.5 dB, when implemented with an associated ground plane of 70 mm X 70 mm. This size of ground plane is invariably an obstacle in many applications where size is major factor of the design. It is recommended that at least 2 dB of gain is realised by the antenna element to ensure successful system performance. To achieve this the ground plane arrangement is absolutely critical. One of the fundamental problems with passive antenna is that the ground plane area and implementation affects the centre frequency resonance tuning. Therefore if the manufacturers ground plane specification is not followed the antenna element will be detuned and consequently the gain at the desired centre frequency is degraded. It is advisable to evaluate the chosen element with various ground plane configurations to establish suitable gain realisation prior to designing the PCB itself. If the element gain is not realised it is almost impossible to recover the consequences of it in the latter stages of the RF design. The mounting of the antenna is also a major consideration here. Ideally the antenna should be mounted offset to the PCB, that is to one side, with suitable ground plane arrangements. An alternative to this is to isolate the antenna with very short cable length. In both cases the RF sections of the PCB itself should be shielded to prevent any feedback resulting from the close proximity of the patch itself. 21 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.1.2 Application Note AN99068 AN99068 (Version 1.0) Active Antenna Solutions In applications intending to use active GPS antenna either one or both of the on-chip LNA's from the UAA1570 UAA1570 will be bypassed. More commonly a single LNA will be used together with a typical active antenna with gains in the region of 13 dB to 26 dB. In instances where active antenna gain is greater than 26 dB it is recommended to bypass both LNA's. Table 7 gives an overview of the constraints. Table 7 LNA's Implemented Maximum External Gain Minimum External Gain Maximum Ext Noise Figure 1 26 dB 8 dB 3.5 dB 1& 2 41 dB 23 dB 3.5 dB Single LNA Both LNA's Requirement Specification for Active Antenna 1) The maximum external NF listed is that which will produce approximately 1 dB degradation in system NF using the minimum recommended external gain. The maximum recommended external gain could result in approximately 1 dB compression in the second mixer input with an in-band continuous wave jammer present (J/S = 35 dB) for normal processed parts. 2) If a high gain external LNA is used both LNA1 and LNA2 should be removed from the signal path. However, the LNA2 supply must still be connected to Vcc to retain power to the first mixer. The figures given in Table 7 are those recommended, including all cable and filter losses, and do not represent absolute system limits. Whenever an active antenna is used it is suggested that its placement is reasonably clear of the RF stages of the PCB to prevent an chance of feedback and instability as a result. It is recommended that the RF stages are shielded to protect them from any external interference effects. 3.1.3 Circuit Considerations for Disabling On-Chip LNA's When at least one of the on-chip LNA's from the UAA1570 UAA1570 are to be bypassed it is important to ground the associated input pin and leave the output pins open circuit. In all cases VCCLNA2 must be connected to the main supply but VCCLNA1 can be left open circuit if LNA1 is bypassed. In typical 3 V applications disabling one or both on-chip LNA's will save around 6.5 mA of supply current. In a single LNA application it is recommended that LNA2 is implemented and LNA1 bypassed to save current. For manufacturer details of various passive and active antenna for GPS refer to Section 9.6 on Page 107. 3.2 Impedance Matching for RF Stages The RF inputs and outputs must be matched to a 50 Ohm environment using either microstrip line design or L and C matching circuits. Table 8 on Page 23 provides the matching impedances of all the RF input and output pins of the UAA1570 UAA1570 at the L1 frequency of 1.57542 GHz. In the reference design microstrip lines have been implemented to minimise external components, but if preferred the matching could also be done using L and C networks. 22 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Table 8 Function Application Note AN99068 AN99068 (Version 1.0) RF Matching Impedances (1.57542 GHz) UAA1570 UAA1570 Pin Number Real Part Imaginary Part LNA1 Input 45 31 - j32 LNA1 Output 48 77.5 + j6 LNA2 Input 3 24 - j25 LNA2 Output 6 74.5 - j0.5 Mixer1 Input 14 33.5 -j25.5 The EXACT Low Cost Reference Board Design utilises LNA2 only and the matching design for these pins are detailed in this section. The same design principle would apply if LNA1 was also to be implemented and for completeness the matching networks suggested for these pins are also included. In each case a netlist of the matching circuit as well as component and trace properties is included. Table 9, below helps to understand what the netlist represents in physical terms. Table 9 Netlist Parameters Description CAP TLIN CAP RES TLIN TLOC = Capacitor = Resistor = Microstrip Line = Open Stub Microstrip 2 0 Circuit Nodes (ie: between nodes 2 and 0) C = 0.25 E = 34.50 Capacitance in pF Resistance in Ohms Electrical Length in Degrees Electrical Length in Degrees The matching circuits were designed with the following goals: Magnitude of Reflection Coefficient -18 dB to -15 dB Voltage Standing Wave Ratio (VSWR) 3.2.1 1.28 to 1.43. Microstrip Design Procedure This section details the design approach used to produce the matching networks for the EXACT Low Cost reference Board. In order to minimise component count a microstrip approach was taken as opposed to using Inductor and Capacitor tuning networks. The latter makes on board tuning easier after manufacture provided track lengths are kept fairly short, but with care the microstrip approach provides a cheap and accurate solution. The design approach uses standard formulae and requires the use of a Smith Chart either in paper form or in this case a software program, EEZMatch. Details on how to obtain this software can be found in Section 9.7 on Page 108. 23 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.2.1.1 Application Note AN99068 AN99068 (Version 1.0) determining track widths The track width used to tune the network needs to be chosen such that it is wide enough to avoid any tolerance effects in production but at the same time able to be long enough to provide adequate interconnect between components. There are a number of detailed formulae available to determine impedance for given track widths and a simplified one is provided here as an example. In most cases the board manufacturer will be able to tune the line impedances to your requirements if you specify beforehand what tracks need to be impedance controlled. In this case a 4 layer board was used as detailed in Figure 5. The board uses FR4 dielectric with a Dielectric constant, Er, of around 4.0. Copper Thickness was specified at 0.035 mm. Characteristic Line Impedance chosen at around 100R. Characteristic Impedance of bias line chosen at nominally 78R. This was chosen as a compromise between minimum size and short circuit current handling. Given all these details it is now possible to determine the required track width to achieve the target line impedances used for the various Rf networks. . Top Layer 0.36 mm (14 mils) Inner Layer1 1.6 mm (63 mils) Inner Layer2 0.36 mm (14 mils) Bottom Layer Figure 5 Layer Construction for GPS Engine Board The following equations can be used; W = 1.25 × ( ( ( 5.98 × D ) / 10 ( ( Zo ) / ( 201 / ( Er + 1.41 ) ) ) ) ­ 2C ) Equation: Calculation of track width for given characteristic impedance, Zo. Zo = ( ( 201 / ( Er + 1.41 ) ) × log ( ( 5.98 × D ) / ( ( 0.8 × W ) + 2C ) ) ) Equation: Calculation of characteristic impedance for given track width, W. These equations generally give results more closely matched to those specified by our PCB manufacturer for track impedances of 50 Ohms or more. In general it is recommended that these formula are only used as a guide and ultimately the impedance objectives should be discussed with each specific manufacturer who will be able to tune their process to meet your objectives. 24 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note AN99068 AN99068 (Version 1.0) A description of the variables used and the final values these equations provide are shown in Table 10 and 11. Table 10 Track Width Calculations for Impedance Controlled Lines Description Label Value Dielectric Constant of PCB Er 4 Distance From Microstrip to Inner GND plane D 0.3556 mm (14 mils) Copper Thickness of Track C 0.035 mm (1.4 mils) Calculated Track Width for 100 Ohm W100 0.102 mm (4 mils) Calculated Track Width for 78 Ohm W78 0.229 mm (9 mils) Calculated Track Width for 50 Ohm W50 0.609 mm (24 mils) Calculated Track Width for 35 Ohm W35 1.270 mm (50 mils) Table 11 Impedance and Velocity Factor for Microstrip Line Calculations Microstrip Impedance (Zo) Velocity Factor (B) W = 4 mils 99.21 Ohms 3378 Deg/m W = 9 mils 79.74 Ohms 3485 Deg/m W = 24 mils 50.31 Ohms 3615 Deg/m aW 33.17 Ohms 3772 Deg/m = 50 mils a. Calculated by alternative method to that outlined in this Report When modelling the matching network with EEZMatch, it is necessary to enter the microstrip line lengths in angular distance. To do this we need to be able to calculate the velocity factor of the given line in degrees/metre. The following equations can be used to get an estimate of this ratio. These equations provide a typical expectation and do not take into account the effects imposed by shielding the board. However if the height of the shield is considerably greater than the distance between the associated layers of the PCB, ie: 5 to 10 times, then this effect is very small. Equation [1] Velocity Factor (Degrees/Metre) = (2 × ) / Equation [2] Wavelength Constant = c / ( Freq × re ) Where c = 299792458 m/s Speed of Light Frequency = 1.57542 GHzGPS Signal Frequency Er = 4 Typical Dielectric Constant for FR4 25 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Equation [3] Application Note (Version 1.0) AN99068 AN99068 Effective Dielectric Constant re = ( ( r + 1 ) / 2 ) + ( ( r ­ 1 ) / 2 ) × F ) Equation [4] Height and Width Scaling Factor (For w/h < 1) F = 1 / ( ( 1 + ( 1.2 × h / w ) ) + T ) Equation [5] Height and Width Scaling Factor (For w/h > 1) F = 1 / ( 1 + ( 1.2 × h / w ) ) Equation [6] Scaling Factor T (When track width < distance between layers) T = 0.04 × ( 1 ­ ( w / h ) ) 2 3.2.1.2 determining track lengths Taking a typical example the equations provided above should yield a velocity factor of 3378 Degrees/ metre for the following impedance controlled line. Track Impedance 100 Ohms Distance between layers (h) 14 mils (0.2556 mm) Track Width (w) 4 mils (0.1016 mm) Dielectric Constant (Er) 4.0. At this stage EEZMatch can be used to model the matching network entering impedance line lengths in angular degrees. Once the network is correct the angular length can be converted to metres using the velocity factor calculated earlier. Example: If line length was chosen at 45 degrees Track Width = 4 mils (100 Ohm) Velocity Factor 3378 Deg/m Therefore Track Length is 45/3378 = 0.0133m (13.3 mm). Note: In practice the matching networks for the reference design were derived using a number of alternative formulae, including those described here. An average between these results and those provided by the PCB manufacturer were used in the final design. Therefore the calculations provided, although closely matching the final design, are not always identical to those used in the final design. However these differences are reasonably small compared to the nominal 10% working practices of the PCB manufacturer and should not have a significant impact on the system performance. 3.2.2 DC Bias Line Matching Circuit The bias line is required only where an active antenna is to be used and provides a DC supply to power the antenna but represents an open circuit load condition at the frequency of operation, 1.57542 GHz. The 10 Ohm series resistor has been chosen arbitrarily to limit the current on the line to around 50 mA for a 5 V supply ± 10%. 26 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Figure 6 Application Note (Version 1.0) AN99068 AN99068 Smith Chart Plot of Bias Line Matching Network Netlisting for Bias Matching Circuit: RES CAP TLIN CAP TLIN 6 15 15 16 16 15 0 16 0 17 R=10.0 C=33000.0 Z=78.0 E=90.0 F=1.575 C=10.0 Z=78.0 E=97.0 F=1.575 R1 R = 10 Ohm C20 C = 33 NF (Length E = 91 degrees) C21 C = 10 pF (Length E = 98 degrees) In this network the line width is chosen at 9 mils to provide a characteristic impedance of 78 Ohms. In the network above the line lengths were chosen at 90 degrees and 97 degrees. Taking the velocity factor calculated above can determine the physical lengths of these lines as follows: Microstrip Lines (Z ~ 78R) Electrical lengths of 90 Degrees and 97 Degrees, Velocity Factor = 3485, L90 Deg = 90/3485 = 26 mm or 1017 mils (27 mm actually implemented) L97 Deg = 97/3485 = 28 mm or 1096 mils (29 mm actually implemented) For explanation of differences between the calculated results, and those implemented on the board, (see note Section 3.2.1.2 on Page 26). 27 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.2.3 Application Note (Version 1.0) AN99068 AN99068 LNA2 Input Matching Circuit Figure 7 Smith Chart Plot of LNA2IN Matching Network EEZ Match Network: CKT CAP 1 0 C=0.25 C1 C = 0.25 pF (Modelled pin stray capacitance) TLIN 1 2 Z=100.0 E=29.0 F=1.575 (Length E = 29 Degrees) CAP 2 0 C=2.3 C2 C = 2.3 pF In this network the line width is chosen at 4 mils to provide a characteristic impedance of 100 Ohms. In the network above the line length was chosen at 29 degrees. Taking the velocity factor calculated above can determine the physical lengths of these lines as follows: Microstrip Line (Z ~ 100R) Electrical lengths of 29 Degrees, Velocity Factor = 3378, L29 Deg = 29/3378 = 8.6 mm or 339 mils (8.9 mm actually implemented) For explanation of differences between the calculated results, and those implemented on the board, (see note Section 3.2.1.2 on Page 26). 28 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.2.4 Application Note (Version 1.0) AN99068 AN99068 LNA2 Output Matching Circuit Figure 8 Smith Chart Plot of LNA2OUT Matching Network EEZ Match Network: CKT CAP 6 0 C = 0.25 TLOC 15 0 Z = 35.0 C11 E = 10.18 F = 1.575 TLIN 6 10 Z = 100.0 E = 24.0 F = 1.575 C = 0.25 pF (Modelled pin stray capacitance) (Length E = 10.2 Degrees) (Length E = 24 Degrees) In this network the line width is chosen at 4 mils to provide a characteristic impedance of 100 Ohms. In the network above the line length was chosen at 24 degrees. Taking the velocity factor calculated above can determine the physical lengths of these lines as follows: Open Stub at LNA2OUT (Z ~ 35R) This was used to more accurately model the fractional capacitance required for successful matching of this port. Electrical lengths of 10 Degrees, Velocity Factor = 3772, L10 Deg = 10/3772 = 2.65 mm or 104 mils (3.1 mm actually implemented). 29 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 Microstrip Line (Z ~ 100R) Electrical lengths of 24 Degrees, Velocity Factor = 3378, L24 Deg = 24/3378 = 7.1 mm or 279 mils (7.1 mm actually implemented) For explanation of differences between the calculated results, and those implemented on the board, (see note Section 3.2.1.2 on Page 26). IMPORTANT If a physical shunt capacitor was used on the LNA2 output it would be significantly less than 1 pF. This very small capacitance is very difficult to realise with physical components so on the reference design an open stub microstrip line has been implemented. A via is placed directly at the LNA2OUT pin through to an open ended strip of copper on the other side of the board. This strip of copper is referred to as an open stub. The stub chosen on the reference board realised a 35 Ohm track impedance of length 121 mils. 3.2.5 Mixer1 Input Matching Circuit Figure 9 Smith Chart Plot of MIXER1 Input Matching Network 30 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 EEZ Match Network. CKT CAP 6 0 C = 0.25 ! C13 C = 0.25 pF (Modelled pin stray capacitance) TLIN 6 11 Z = 100.0 E = 31.0 F = 1.575 (Length E = 31 Degrees) CAP 11 0 C = 1.7 pF C = 1.7 ! C14 In this network the line width is chosen at 4 mils to provide a characteristic impedance of 100 Ohms. In the network above the line length was chosen at 31 degrees. Taking the velocity factor calculated above can determine the physical lengths of these lines as follows: Microstrip Line (Z ~ 100R) Electrical lengths of 31 Degrees, Velocity Factor = 3378, L31 Deg = 31/3378 = 9.2 mm or 362 mils (9.5 mm actually implemented) For explanation of differences between the calculated results, and those implemented on the board, (see note Section 3.2.1.2 on Page 26). 3.2.6 LNA1 Input Matching Circuit Figure 10 Smith Chart Plot of LNA1IN Matching Network 31 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 EEZ Match Network. CKT CAP 1 0 C = 0.25 ! C1 C = 0.25F (Modelled pin stray capacitance) TLIN 1 2 Z = 100.0 E = 33.5 F = 1.575 (Length E = 34 Degrees) CAP 2 0 C = 2.0 C = 2 pF ! C2 In this network the line width is chosen at 4 mils to provide a characteristic impedance of 100 Ohms. In the network above the line length was chosen at 34 degrees. Taking the velocity factor calculated above can determine the physical lengths of these lines as follows; Microstrip Line (Z ~ 100R) Electrical lengths of 34 Degrees, Velocity Factor = 3378, L34 Deg = 34/3378 = 10 mm or 394 mils. For explanation of differences between the calculated results, and those implemented on the board, (see note Section 3.2.1.2 on Page 26). 3.2.7 LNA1 Output Matching Circuit Figure 11 Smith Chart Plot of LNA1OUT Matching Network 32 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 EEZ Match Network. CKT CAP 1 0 C = 0.25 ! C3 CAP 15 0 C = 6.1886448e-1 C = 0.25 pF ! C10 (Modelled pin stray capacitance) C = 6.2 pF TLIN 4 5 Z = 100.0 E = 26.0 F = 1.575 (Length E = 26 Degrees). In this network the line width is chosen at 4 mils to provide a characteristic impedance of 100 Ohms. In the network above the line length was chosen at 26 degrees. Taking the velocity factor calculated above can determine the physical lengths of these lines as follows; Microstrip Line (Z ~ 100R) Electrical lengths of 26 Degrees, Velocity Factor = 3378, L26 Deg = 26/3378 = 7.7 mm or 303 mils. For explanation of differences between the calculated results, and those implemented on the board, (see note Section 3.2.1.2 on Page 26). 3.2.8 Bandpass Filter Selection There are a vast array of both ceramic bandpass filters and SAW filters specifically designed for the GPS frequency at 1.57542 GHz. On the reference design footprints for both types were implemented for demonstration purposes. On a final board design only one device type should be used and the grounding optimised for this device. Grounding is a particularly important issue with ceramics. If the casing is not adequately grounded then high insertion loss will result which will significantly degrade performance. To this end it is recommended that where possible vias are provided to the inner layer ground planes around the filters and each of the matching network shunt capacitors. This is preferred practice and greatly improves the ground return for this high frequency path. The Mitsubishi SAW filter was a small part but up to three times the cost of some ceramic parts. The key benefits are size, the improved out of band rejection characteristics and the slightly lower insertion loss. The Murata ceramic filter was very low cost and although not as good as the SAW filter in some respects produced very good results in the final design. The only issue here may be if good out of band rejection is required for frequencies close to the GPS carrier at 1.575 GHz. In this particular case a SAW filter may provide a better solution. Table 12, highlights the general specification for both parts. Table 12 Bandpass Filter Data for Mitsubishi and MuRata Components Mitsubishi MF1012S-1 MF1012S-1 Parameter MuRata DFC21R57P002HHC DFC21R57P002HHC Centre Frequency 1.57542 GHz 1.57542 GHz Bandwidth ± 1 MHz ± 1 MHz Insertion Loss at BW 2.7 dB 3.5 dB Ripple at BW 1.0 dB 0.5 dB VSWR at BW 2.0 dB 2.0 dB Stopband Attenuation 30 dB minimum @ 50 MHz 15 dB minimum @ 50 MHz 33 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.3 Application Note (Version 1.0) AN99068 AN99068 VCO and PLL Filter The VCO is tuned by a varactor and Inductor network to provide a local oscillator at around 1.5336 GHz. The varactor chosen on the reference design exhibits a typical total Ct at 1 V of 1.5 pF. Once the effects of the 15 pF series capacitor, SFR effects of the inductor and all stray effects are accounted for we have a nominal effect capacitance of 2.3 pF. This means an inductor in the order of 4.7 nH is required to provide the desired VCO frequency as shown: ­ 10 F = 1 / ( 2 LC ) = 1 / 6.52 ×10 = 1.5336GHz Where C = 2.3 pF and L = 4.68 nH The LC network tunes the VCO to the desired frequency whilst the loop filter components provide bandpass filtering to eliminate high frequency interference and optimize phase noise response. The use of 0805 air core inductors such as the coilcraft 0805CS 0805CS range will yield the highest effect Q and ultimately best wideband phase noise performance. In order to maintain optimal phase noise performance it is essential that VCO ground and supply inductances are minimal. This requires close proximity layout with ground returns directly to IC pins and also a liberal use of ground vias where practical. If stray inductance problems occur it will become obvious through the need to implement lower values of physical inductor for the VCO circuit. The reference design uses a 5.6 nH inductor. Values much less than this, ie: 3.9 nH suggest improvements in layout are required. 3.3.1 VCO This section details the function of the VCO circuit and the purpose of each section. . Risolate Rlowpass 2K7 2K7 4p7 Varactor Diode COMP (Pin 40) Clowpass GND 15p 5.6nH Cblock TANK (Pin 10) Ltune Rdcpath 10K GND Figure 12 Typical VCO Circuit Configuration 34 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 The comparator output pin of the UAA1570 UAA1570 provides the DC control to tune the varactor diode for the implemented inductor. The operating range of the COMP output is between 0 V and Vcc - 0.6 V. Therefore in a 3 V system we need to set the nominal tuning voltage midway between 0 and 2.4 V, ie: 1.2 V. By doing this we provide the maximum tuning range for the application to take into account component tolerances in production. 1) Rlowpass and Clowpass provide filtering to attenuate higher frequency harmonics of the reference oscillator. The -3 dB cut off of this filter is nominally set just below the reference clock frequency, and in this case 12.5 MHz. 2) Risolate provides isolation from the varactor circuit. This prevents Clowpass from greatly detuning the VCO. 3) The varactor chosen primarily for minimum capacitance at nominal tuning voltage of 1 V. The smaller the diode capacitance Ct, the higher the inductor value that can be used, which makes tolerance effects and layout less critical. Another factor is series resistance, where the higher the resistance the better the Q factor. 4) Rdcpath is used to provide a DC path for the tuning, as in this application a varactor pair has been used in series to minimise overall capacitance. 5) Cblock and Ltune complete the tuning circuit. Cblock provides the AC coupling and is chosen for low impedance at the VCO frequency. This ensures the tuning is controlled only by the varactor and inductor, Ltune.Cblock can also be used to pull the resonator circuit and required inductance to more practical values whilst optimising DC tuning centering. It is possible to use a single varactor in which case the anode would be tied to GND with the cathode tied to the junction of Risolate and Cblock. The main reason for not doing this was to ensure reasonably high inductor values could be realised.Another key reason for using double series varactor diodes was to maximise the VCO gain, Ko, by minimising series varactor capacitance at the negative input VCO TANK pin. Therefore using double series varactor diodes such as the SMV1233-004 SMV1233-004 maximises the realisable inductor values, VCO gain and resonator Q. Circuit parasitics inevitably mean that the overall Q of the resonant circuit is not very high. However an 0805 inductor will make a significant difference to out of band phase noise, compared to an 0603 part. To this end it is strongly recommended that 0805 inductors with high Q are used in the final solution, such as the Coilcraft 0805CS 0805CS range. 35 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.3.2 Application Note AN99068 AN99068 (Version 1.0) Phase Locked Loop Filter The purpose of the loop filter is to set the operating bandwidth of the VCO and optimize phase noise through outband attenuation. Cfilter 10nF Risolate Rfilter Rlowpass COMP (Pin 40) Cnoise 10K Clowpass 270pF GND GND Loop Filter Components Figure 13 VCO Loop Filter Circuit The loop filter bandwidth is set typically around 35 kHz or less. The following equations can be used to provide an estimate of component values for given loop bandwidths. Table 13 Label Constants Required for VCO Loop Filter Calculation Value Comments F(bw) 35 kHz Loop filter bandwidth being designed for (Nominally 35 kHz) k 2.2 Damping coefficient. (nominally 2 to 3 to minimise side lobe peaks either side of the VCO spectrum Kp 290 µA Maximum charge pump current (Icp maximum from data sheet). It is expected that this never goes above 290 µA Ko 75M Hz/V VCO gain typically between 60 MHz/V and 100 MHz/V so in this case chosen as nominally 75 MHz/V N 852 Divide ratio of VCO operating frequency and phase comparator frequency. The VCO runs at 1.5336 GHz and the phase comparator operates at 1.8 MHz, hence 852 Firstly Calculating Wo: Calculating for Cfilter: Cfilter = ( Kp × Ko ) / ( Wo 2 × N ) = 10.77nF 36 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 Wo = 2F ( bw ) / 1 + 2 ( k ) 2 + ( 1 + 2 ( k ) 2 ) 2 + 1 = 48675 Calculating for Rfilter: Rfilter = ( 2 × k ) / ( Wo × Cfilter ) = 8.39K Cnoise provides filtering of the high frequency harmonics of the reference and sample clocks. This is nominally chosen at around 30 or 40 times lower than Cfilter. In the reference design Cnoise was chosen at 270 pF, approximately 40 times lower than Cfilter. If this is made too high in relation to Cfilter it can start to affect the damping which could be identified by increase in the side lobe peaks of the VCO spectrum. Once the nominal values for the loop filter are calculated the resulting response can be measured at the bench and altered slightly to provide the desired characteristics. In the case of the reference design a 10 NF and 10 k combination was implemented. 3.4 First IF Filter The first IF filter performs four key functions: · Selectivity to protect second mixer from spurious RF signals passing through RF Filter(s). · Attenuates thermal noise and 2nd mixer image frequency. · Impedance transformation from RF mixer output to the IF2 mixer input. · If a double ended structure is implemented, it can enable better common mode rejection of spurious high level sources which have externally coupled into the filter path, such as the 3rd harmonic of the reference clock. For the Philips Reference Design a 6th order, coupled resonator filter based on a Butterworth response has been implemented. This section details the filter design used on the reference board, but section 3.6, describes how a dedicated SAW filter could be implemented into the design as a replacement. There were two critical aspects to the design to the design of the first IF filter, · Minimum bandwidth of 2 MHz + headroom to account for component tolerances. · Rejection of 2nd mixer image frequency at 34.86 MHz (At least 13 dB). The filter design was then determined using the capacitively coupled resonator approach based on 3 dB down k and q values from a 3rd order Butterworth lowpass response. This procedure is detailed in the Handbook of Filter Synthesis by Anatol I Zverev Reference [4]. This was originally chosen for its simplicity as well as selectivity advantage versus component count. 37 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.4.1 Application Note (Version 1.0) AN99068 AN99068 Filter Specification The first IF filter was chosen with the following characteristics: Centre Frequency 41.82 MHz 3 dB Bandwidth 5 MHz Outband Attenuation > 13 dB at 34.86 MHz. To achieve the required attenuation characteristics a 3rd order filter was opted for. Graphs are provided in Reference [4] which make the order of the filter easy to decide upon. 3.4.2 IF1 Filter Design Procedure First the inductive or capacitive element is chosen such that it will yield realisable values for the final filter design keeping in mind that the filter is being driven from a transconductance mixer output. That is the conversion gain of the mixer and delivered output power are maximised by maximising the real impedance level in an I2R relationship. Since the filter design impedance levels are proportional to the inductance as R = Q x Wo x L, we would like to maximise the reference inductance level. A balance has to drawn to ensure at the same time that the associated tank and coupling capacitances tolerances do not become impractically small. Generally, coupled resonator filters design input and output impedance are not realised exactly due to the availability of discrete component value. Care should be taken to calculate the realised impedance of the actual filter to detect and adjust significant divergence from the initial design impedance objective at both the input and output of the filter. To realise the tabular response and insertion loss, the filter must be driven from and terminated in the design impedance. Care must be taken to ensure that the Q effects of the input and output tank inductors are taken into account in determining this loading. That is the finite Q's of the tank inductors should be considered as providing an appropriate portion of these required source and load impedances. In this case the inductor was chosen at 165 nH. This should then provide capacitive values in the order of 90 pF for each resonator section, given the equation below: Fo = 1 / ( 2 LC ) Therefore with Fo at 41.82 MHz and L = 165 nH, C would be 88 pF. The 165 nH in would yield a typical Q factor in the order of 40 for most practical components. This now enables us to calculate the value of qo which will determine what k and q values to implement from the filter tables in Reference [4]. qo = BW 3 d B × Q / ( Fo ) = 5 × 40 / 41.82 = 4.78 Using qo = 5 we can now extract the following values from the design tables. Tables are provided in Reference [4], which allow the k and q values to be extracted based upon a typical loaded Q factor for the resonators. qo = 5, q1 = 0.8226, k 12 = 0.6567, k 23 = 0.7060 insertion Loss = 4.742 38 qn = 1.7115 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 Having now determined the table constants for a 3rd order Butterworth filter and also chosen resonator components L and C we can now calculate the full circuit values. Having chosen L at 165 nH and therefore C at 88 pF the following can be calculated, where the series C12 = ( k12 × BW3dB × C ) / ( Fo ) = 6.9pF capacitors, C12 and C23 provide the capacitive coupling between the tank nodes and the shunt capacitors, Ca, Cb and Cc are the physical nodal capacitances which provide the specified total capacitance of 88 pF in conjunction with the coupling capacitors. Ca = C ­ C12 = 81.1pF Continuing on we can now calculate all the remaining capacitive elements. C23 = ( k23 × BW3dB × C ) / ( Fo ) = 7.4pF Cb = C ­ C12 ­ C23 = 73.7pF Cc = C ­ C23 = 80.6pF We can now determine the load and source impedances that will ensure the desired response is obtained. Firstly we need to denormalise the tabular values for q1 and qn to determine the estimated Q factor of the filter source and load, as shown below: Q denormalise = ( Fo ) / ( BW3dB ) = 8.361 Qs = Q denormalise × q1 = 8.361 × 0.8226 = 6.88 The denormalised Q factor for the filter load can be determined in the same way, in this case yielding a value of 14.31, where qn = 1.7115.1 Rs = Qs × 2Fo × L Therefore when inserting values for QS and QL in the equation above, given L = 165 nH, the following source and load impedance for the filter can be determined. RS = 298 Ohms, and RL = 620 Ohms. 39 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board C12 6.9 pF RS 298R Figure 14 L 165 nH Application Note AN99068 AN99068 (Version 1.0) C23 7.4 pF Cb L 74 pF Ca L 81 pF Cc 81 pF RL 620R Single-Ended 6th Order IF1 Filter Design (Based on 3rd Order Butterworth Lowpass) At this stage we have a complete filter design that if simulated in SPICE or other simulation program would provide the required filter response. Inevitably the values that result are never practical and so it is necessary to select preferred component values by trial and error simulation and verification on the PCB itself. In our case we have chosen the first IF stage to be double ended to provide common mode rejection of the 14.4 MHz reference clock harmonics. In order to convert this structure into a double ended design we simply superimpose an identical network over the current one such that the shunt elements connect in series. In simple terms the shunt inductors and resistors are doubled and the capacitances halved. The series coupling capacitors remain unchanged. The single ended structure is shown in Figure 14 and the converted structure is shown in Figure 15. The SPICE netlist for this filter is provided in Appendix A. C12 6.9 pF C23 7.4 pF Figure 15 L 330 nH Ca L 40 pF Cb L 37 pF C12 6.9 pF RS 596R Cc 40 pF RL 1240R 1240R C23 7.4 pF Double-Ended 6th Order IF1 Filter Design (Based on 3rd Order Butterworth Lowpass) In practice we want to maximise the real inband loading of the transconductance mixer output. The tabular filter component values, RS and RL result in the prescribed filter response, but do not guarantee the inband impedances seen at the input or output of the filter. These must be determined by calculation over the frequency band with the actual component values used in the implemented design. Small changes in the selected values can result in significant inband impedance ripple and unexpected results. After calculating or simulating the realised filter input and output impedance against the associated filter response expectation, you may want to reverse the input and output ports, as we have done, to present the highest in band impedance to the first mixer output. This is to maximise gain and stability, while minimising post filtering stray spurious pick-up, by presenting the lowest port impedance of the filter to the input of the second mixer. 40 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Lin dB Application Note (Version 1.0) AN99068 AN99068 41.82 MHz +10 0 -10 Target > 13 dB -20 -30 -40 -50 Image @ 34.86MHz -60 10.0M Log Frequency Hz 80.0M Analysis: AC IF1 Filter Simulated Response Figure 16 Simulated Response of IF1 Filter at 41.82 MHz Note in both cases RS and RL are not physical components rather the required load to ensure the specified filter response is achieved and so the loads presented to the filter input and output must be determined. The load RL is calculated from the equivalent Q loss resistance of the inductor in parallel with a physical resistor. In order to maintain filter characteristics, as indicated in Figure 16, we need to tune this parallel combination to provide an effective load close to 1240R 1240R. Firstly calculate the series equivalent Q loss resistance of the inductor. After detailed simulation and calculation the final total inductance at the mixer1 output was made up of two separate components of 180 nH, providing a total effective shunt inductance of 360nH. The total inductance was split in order to allow both mixer outputs to be DC biased through the inductive elements of the filter. r = 2 × × Fo × L / Q = 2.365Ohms In this instance the unloaded Q factor of the inductors could be expected to be in the order of 40, with Fo at 41.82 MHz. Therefore in this case r = 2.365 Ohms. We can now determine the inductor equivalent load as follows: Req = r × Q 2 = 3783.8Ohms 41 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 We need to present a physical load resistor at the output of Mixer1 to reduce the effective load close to 1240 Ohms. Given Req = 3784 Ohms we can determine the approximate required R to complete the filter input load. Rload = Req × R / ( Req + R ) = ( 3784R 3784R ) / ( 3784 + R ) = 1240 R = 4692160 / 2544 = 1844Ohms Therefore in theory only a 1.8 k Ohm resistor should be required in parallel with the filter input to maintain the desired filter response. The final value chosen on the reference design was somewhat higher at 12 k, and was chosen based on detailed simulation and test results. In practice the filter impedance was lower than anticipated and so a compromise was made between maximising the conversion gain of the mixer whilst maintaining the desired filter response. The output of the filter is then completed in a similar way except in this instance the Mixer2 differential input resistance of 2.05 k Ohms must also be considered. Therefore if Req = 3784 Ohms and the Mixer2 input = 2.05 k Ohms the existing load is already at 1308 Ohms, (ie: 3.78 k // 2.05 k. In order to provide an equivalent load of 596 Ohms a load resistor of 1095 Ohms is required. Again after selecting preferred values of L and C a shunt resistor of 909 Ohms was eventually chosen to provide the desired filter response. The theory on the filter design given in this section details the approach and provides an approximation to the required solution. In practice the values inevitably need to be altered to find preferred equivalents and it is therefore partly an exercise of trial and error to achieve the realisable result. As stated earlier in this section once the filter is designed detailed calculations and/or simulations need to be carried out to carefully determine the realisable filter characteristics in a real application. From the schematics in Section 6.1 on Page 76 it can be seen that in practice the final filter design differs slightly from that produced in the initial design process. 3.4.3 Verifying Maximum First Mixer Output Voltage Swing The first mixer output voltage swing must be limited to 1 V peak differential in order to prevent clipping of the output ESD protection diodes. Under normal operating conditions the satellite signal level is so low that clipping at the mixer1 output is extremely unlikely. The main issue here is the maximum expected in-band jammer level and its effect on the mixer compression points. In theory a 1-Bit system such as EXACT with a good system Noise Figure cannot handle more than a 35 dB J/S ratio at the input of the 1-Bit quantizer, regardless of satellite level. It is important to verify at this stage that under worst case allowable jamming conditions that the mixer is not placed into compression and that clipping at the mixer output is also avoided. In order to verify performance under these conditions it is important to accurately determine the realised loads seen at both the mixer input and output. The actual loads presented at both the input and output of the first mixer are given in Table 15 on Page 49 and are based on detailed simulations. Given the information in Table 14 on Page 43, we can determine that the nominal expected mixer input level will be -78 dBm, under typical operating conditions. 42 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 . Table 14 Symbol Gain Stages Prior to Mixer1 input Gain Comments Sat Level -117 dBm The maximum likely GPS satellite signal level at antenna (-120 dBm maximum specified output + 3 dB to allow for sats running hot) Antenna 26 dB Maximum Active Antenna Gain including cable losses LNA2 13 dB Typical LNA2 gain including Bandpass Filter Loss Maximum J/S 35 dB Maximum Jammer to Signal Ratio Mixer1Input = ­ 117dBm + 26dB + 13 = ­ 78dBm This gives 53 dB headroom on the -1 dB compression point of the first mixer, typically -25 dBm, and more than accounts for the maximum allowable jammer to signal level of 35 dB. Symbol Value Description CP -43 dBm Nominal mixer input with 35 dB J/S ratio R 50 Ohms Matched Input Impedance of Mixer1 Zout 860 Ohms Effective load presented at Mixer1 output Zin 630 Ohms Effective load presented at Mixer2 input Y21 0.0531 A/V Typical Conversion Transconductance at 3 V IF1 Out 1 V peak Maximum differential Mixer1 output swing (ie: 2 V p - p) Having verfied this it is now important to confirm that under these worst case jamming conditions the output of the mixer is not clipped. Using the values provided in Table 15 on Page 49 we can determine the typical mixer output level and the maximum load that can be presented to avoid clipping at the output, under these conditions. With an in band jammer to signal level of 35 dB the maximum input to the first mixer would be -43 dBm. Mixer1Input = ­ 117dBm + 35dB + 26 dB + 13 = ­ 43dBm Converting -43 dBm to peak voltage; Vp = 0.001 × 10 CP / 10 × 2 × R = 5 × 10 ­ 6 = 2.24mVPeak Given the conversion transconductance of the mixer and the effective load at the output from Table 15 on Page 49 the differential output voltage, Vout, can be calculated as: Vout = 2.24mV × 0.0531 × 860 = 0.102VPeak 43 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 This is well within the recommended limit of 1 V peak differential. It can be further shown that if the mixer was driven to its -1 dB compression point of typically -25.4 dBm, or 17.8 mV Peak, that the corresponding output still remains less than the 1 V peak recommended limit. Vout = 17.8mV × 0.0531 × 860 = 0.813VPeak This means that even if the mixer was driven to compression at the input the corresponding output would still be low enough to avoid potential clipping of the ESD protection diodes. 3.5 Second IF Filter For the Philips Reference Design a 6th order, coupled resonator filter based on a Butterworth response has been implemented. There were three critical aspects to the design to the design of the first IF filter: · Bandwidth of nominally 2 MHz · Filter impedance levels required to maintain stability around the quantizer loop · Providing anti-alias selectivity for the sampling rate and sample mixed second IF of 1.32 MHz, (default application), actually used in the DSP baseband processing. The noise bandwidth of the GPS system is predominantly determined by the noise bandwidth of the second IF filter. A somewhat wider than necessary C/A code bandwidth was used here to accommodate component tolerances. Since the filter impedance was chosen low enough to ensure that signal coupling from the SIGN bit output back to the quantizer input, or IF2 filter output, a single ended design was implemented to save components. Also normal spurious products were not considered a significant problem in the second IF. Using a 6th order Butterworth bandpass design provides improved alias attenuation between the sampled passbands at the adjacent alias overlap point in the resulting spectrum. A somewhat wider than necessary C/A code bandwidth was used here also to accommodate component tolerances. The filter design was determined using the capacitively coupled resonator approach based on 3 dB down k and q values for a 3rd order Butterworth response. This procedure is detailed in the Handbook of Filter Synthesis by Anatol I Zverev Reference [4]. This was originally chosen for its simplicity as well as selectivity advantage versus component count. 3.5.1 Filter Specification The second IF filter was chosen with the following characteristics: Centre Frequency 3 MHz (Actually 3.48 MHz but chosen lower to compensate for geometric asymmetry given low frequency) 3 dB Bandwidth 1.75 MHz (In practice Q loss will result in higher bandwidth in practice, ie greater than 2 MHz) To maintain good outband attenuation characteristics a 3rd order filter was opted for. Graphs are provided in Reference [4] which make the order of the filter easy to decide upon. 44 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.5.2 Application Note (Version 1.0) AN99068 AN99068 IF2 Filter Design Procedure First the inductive or capacitive element is chosen such that it will yield realisable values for the final filter design keeping in mind that the filter is being driven from a transconductance mixer output. That is the conversion gain of the mixer and delivered output power are maximised by maximising the resistive port impedance level in an I2R relationship. Since the filter design impedance levels are proportional to the inductance as R = Q x Wo x L, we would like to maximise the reference inductance level. A balance has to be drawn to ensure at the same time that the associated tank and coupling capacitances tolerances do not become impractically small. Generally, coupled resonator filters design input and output impedance are not realised exactly due to the availability of discrete component values. Care should be taken to calculate the realised impedance of the actual filter to detect and adjust significant divergence from the initial design impedance objective at both the input and output of the filter. To realise the tabular response and insertion loss, the filter must be driven from and terminated in the design impedance. Care must be taken to ensure that the Q effects of the input and output tank inductors are taken into account in determining this loading. That is the finite Q's of the tank inductors should be considered as providing an appropriate portion of these required source and load impedances. First the inductive or capacitive element is chosen such that it will yield realisable values for the final filter design. In this case the inductor was chosen at 22 µH. This should then provide capacitive values in the order of 128 pF for each resonator section. Fo = 1 / ( 2 LC ) Therefore given the equation above with Fo at 3 MHz and L = 22 µH, C would be 128 pF. The 22 µH in many practical cases would yield a typical Q factor in the order of 40. This now enables us to calculate the value of qo which will determine what k and q values to implement from the filter tables in Reference [4]. qo = BW 3 d B × Q / ( Fo ) = 1.75 × 40 / 3 = 23.33 Using qo = 20, as the closest match, we can now extract the following values from the design tables. Tables are provided in Reference [4], which allow the k and q values to be extracted based upon a typical loaded Q factor for the resonators. qo = 20, q1 = 0.8041, qn = 1.4156 k 12 = 0.7687, k 23 = 0.6582 Insertion Loss = 0.958 Having now determined the table constants for a 3rd order Butterworth filter and also chosen resonator components L and C we can now calculate the full circuit values. 45 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 Having chosen L at 22 µH and therefore C at 128 pF the following can be calculated, where the series capacitors, C12 and C23 provide the capacitive coupling between the tank nodes and the shunt capacitors, Ca, Cb and Cc are the physical nodal capacitances which provide the specified total capacitance of 128 pF in conjunction with the coupling capacitors. C12 = ( k12 × BW3dB × C ) / ( Fo ) = 57.4pF . Ca = C ­ C12 = 70.6pF Continuing on we can now calculate all the remaining capacitive elements. C23 = ( k23 × BW3dB × C ) / ( Fo ) = 49.1pF Cb = C ­ C12 ­ C23 = 21.5pF Cc = C ­ C23 = 78.9pF We can now determine the load and source impedances that will ensure the desired response is obtained. Firstly we need to denormalise the tabular values for q1 and qn to determine the estimated Q factor of the filter source and load, as shown below: Q denormalise = Fo / BW3dB = 3 / 1.75 = 1.715 Qs = Q denormalise × q 1 = 1.38 The equation above calculates the denormalised Q factor for the filter source, but the denormalised Q factor fo the filter load can be determined in the same way, in this case yielding a value of 14.31, where qn = 1.7115.1. Rs = Qs × 2Fo × L Therefore when inserting values for QS and QL in the equation above, given L = 22 µH, the following source and load impedance for the filter can be determined. RS = 572 Ohms, and RL = 1008 Ohms. 46 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note C12 57pF RS 572R Figure 17 L 22 µH AN99068 AN99068 (Version 1.0) C23 49pF Ca L 71pF Cb L 22pF Cc 79pF RL 1008R 1008R Single-Ended 6th Order IF2 Filter Design (Based on 3rd Order Butterworth Lowpass) At this stage we have a complete filter design that if simulated in SPICE or other simulation program would provide the required filter response. Inevitably the values that result are never practical and so it is necessary to select preferred component values by trial and error simulation and verification on the PCB itself. In this design the second IF filter was kept single ended to minimise cost. In practice we want to maximise the real inband loading of the transconductance mixer output. The tabular filter component values, RS and RL result in the prescribed filter response, but do not guarantee the inband impedances seen at the input or output of the filter. These must be determined by calculation over the frequency band with the actual component values used in the implemented design. Small changes in the selected values can result in significant inband impedance ripple and unexpected results. The SPICE netlist for this filter is provided in Appendix B. After calculating or simulating the realised filter input and output impedance against the associated filter response expectation, you may want to reverse the input and output ports, as we have done, to present the highest in band impedance to the first mixer output. This is to maximise gain and stability, while minimising post filtering stray spurious pick-up, by presenting the lowest port impedance of the filter to the input of the Limiter. 47 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 3.48MHz Lin dB +10 0 -10 -20 -30 -40 -50 1.0M Log Frequency Hz 10.0M Analysis: AC IF2 Filter Simulated Response Figure 18 Simulated Response of IF2 Filter at 3.48 MHz Note in both cases RS and RL are not physical components rather the required load to ensure the specified filter response is achieved. The load presented to the filter input and output must be determined. The load RL is calculated from the equivalent Q loss resistance of the inductor in parallel with a physical resistor. In order to maintain filter characteristics, as indicated in Figure 18, we need to tune this parallel combination to provide an effective load close to 1008R 1008R. Firstly calculate the series equivalent Q loss resistance of the inductor; Note in this case that the final filter design used a 27 µH inductor as opposed to 22 µH used in the initial design process. Again this was a result of detailed simulations taking into account loss effects encountered in a real design. r = 2 × × Fo × L / Q = 14.76Ohms In this instance the Q of the inductors could be expected to be in the order of 40, with Fo at 3.48 MHz. Therefore in this case r = 14.76 Ohms. We can now determine the inductor equivalent load as follows: Req = r × Q 2 = 23.615KOhms 48 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 Therefore we need to present a physical load resistor at the output of Mixer2 to reduce the effective load close to 1008 Ohms. Given Req = 23.6 K Ohms we can determine the approximate required R to complete the filter input load. Rload = Req × R / ( Req + R ) = ( 23615R 23615R ) / ( 23615 + R ) = 1008 Therefore calculating for R we get: R = 23803920 / 22607 = 1053Ohms Therefore in theory only a 1 k resistor should be required in parallel with the filter input to maintain desired filter response. In the final application a 2 k resistor was implemented to overcome other losses and maximise the conversion gain of the second mixer. The output of the filter is then completed in a similar way. Because the inductor equivalent resistance is so high for the 27 µH in this design it is really a case of adding the calculated load directly to the output of the filter. In this case a 572 Ohm resistor was specified but in practice an 820 Ohm was selected. As discussed earlier in this section the final values chosen for the design are likely to differ slightly from the theoretical once all loss effects have been fully taken into account. 3.5.3 Verifying Maximum Second Mixer Output Voltage Swing As in the case of the first IF design, the main concern is the maximum expected in-band jammer level and its effect on the mixer compression points. In theory a 1-Bit system such as EXACT with a good system Noise Figure cannot handle more than a 35 dB J/S ratio at the input of the 1-Bit quantizer, regardless of satellite level. In the case of the reference design we can establish the likely maximum input to Mixer2 to determine what the maximum permissible load would be before clipping occurs at the output. In this case the design employs an active antenna with a single UAA1570 UAA1570 LNA application. The actual loads presented to the Mixer2 input and output were determined by detailed simulations and are provided in Table 16 on Page 50. Table 15 Symbol Gain Stages Prior to Mixer2 Input Gain Comments Sat Level -117 dBm The maximum likely GPS satellite signal level at antenna (-130 dBm minimum specified level + 13 dB) Antenna 26 dB Total Active Antenna Gain including cable losses LNA2 13 dB Typical LNA2 gain including bandpass filter loss Mixer1 18 dB Typical Power matched gain of first Mixer IF1 Loss -4 dB Nominal Insertion loss of first IF filter Maximum J/S 35 dB Maximum Jammer to Signal Ratio Given the figures in Table 15. we can estimate the mixer2 input level under normal operating conditions to be -64 dBm. 49 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note AN99068 AN99068 (Version 1.0) Mixer1Input = ­ 117dBm + 26dB + 13dB + 18dB ­ 4dB = ­ 64dBm This would result in a peak differential input voltage to the second mixer of 0.65mV Peak, where the load, Vp = 0.001 × 10 CP / 10 × 2 × R = 0.502 ×10 ­6 = 0.708mVPeak R, is approximated to 630 Ohm. (Effective loading at the Mixer2 input as defined during the design of the first IF filter in Section 3.4.3 on Page 42) Given typical -1 dB compression point for mixer2 o 67.2 mV Peak differential, it can be shown that under normal signal conditions the system would provide approximately 40 dB headroom on the typical compression point of the second mixer. Table 16 Symbol Second Mixer Characteristics Value Description -1 dB Point 67.2 mV Peak Typical -1 dB compression point of Mixer2 (Peak Differential) Rin 630 Ohms Effective load impedance seen at Mixer2 input Rout 825 Ohm Effective load impedance seen at Mixer2 output Y21 0.0294 A/V Typical Conversion Transconductance at 3 V IF2 Out 0.5 V peak Maximum single ended Mixer2 output swing Difference = 20 log ( 0.708 / 67.2 ) = ­ 39.5dB If an inband jammer is applied at a J/S ratio of 35 dB, the mixer 2 input level will rise to -29 dBm (Given by -64 dBm + 35 dB). An input of -29 dBm corresponds to a peak differential input voltage of approximately 40 mV, given the input impedance environment of 630 Ohms. Vp = 0.001 × 10 CP / 10 × 2 × R = 1.59 ×10 ­3 = 39.88mVPeak Given the output impedance and conversion transconductance in Table 16, the corresponding single ended output voltage at mixer2 can be calculated at 0.484V peak, which falls within the recommended limit of 0.5 V peak. Vout = 0.0399 × ( 0.0294 / 2 ) × 825 = 0.484VPeak Therefore under worst case allowable jamming conditions it can be verified that in a typical system the mixer2 input does not reach compression and potential clipping at the mixer output is also avoided. 50 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board 3.6 Application Note (Version 1.0) AN99068 AN99068 SAW Filter Implementation for IF1 The use of a SAW filter in the first IF is problematic and requires careful consideration of a number of special issues. 1) Insertion loss of IF SAW filters is typically quite high. Typical insertion losses range from 8 dB to 35 dB for IF frequencies in the range of 30 MHz to 300 MHz. Developing sufficient gain to overcome this loss can be difficult in light of specialized source and load impedance considerations below. 2) Many off-the shelf SAW devices are designed and specified against simple 50 Ohm source and loads. Others require elaborate matching networks. Unfortunately, these specialized termination requirements affect mixer output power, filter insertion loss, response, and group delay. 3) IF SAW filters with 50ns-pp group delay variation (ripple and warping) are suitable for GPS applications. Ripple is used here to describe the intrinsic chatter in an otherwise flat group delay response, while warping refers to larger scale deformations, such as "S" shaping across the entire pass band of the filter. Significant warping of SAW filter group delay response can result if matching is attempted on a filter designed to be unmatched and driven from 50 Ohm source. Likewise, group delay warping can result if a SAW filter, designed to be used with specific matching networks, is driven from arbitrary resistive source/load terminations. 4) Triple-Transit of signals through SAW devices can often result in destructive wave combinations. To avoid this many SAW designs actually expect and require large insertion losses, which are relied upon to attenuate these reflected waves. That is arbitrary power matching could result in unspecified filter response and or increased group delay variations. 5) The designer will generally find a frustrating physical package size trade-off associated with improvements in each performance category. The specific details and effects of these driving and loading specifications can be difficult to determine. SAW manufacturers must be pressed to provide the information specific to each design. Alternately, a detailed characterization must be undertaken. Consequently, it is very difficult to offer a straight forward standard solution to this problem. However, advice for two categories of SAW filter implementation can be offered. The first category is for simple 50 Ohm filter designs. The second is for higher impedance SAW designs that can be successfully matched to higher impedance first mixer collector loads, with minimal warping and insertion loss. Since the first mixer requires high impedance loading to develop maximum conversion gain, 50 Ohms SAWs can be matched passively through reactive matching networks or actively through an external impedance transforming stage, such as an emitter follower. The latter case provides additional external IF gain to overcome high insertion SAW losses while providing a low impedance sourcing drive to the filter. An emitter follower also buffers the mixer output with a very high gain impedance to maximize conversion gain. 51 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) AN99068 AN99068 Some manufactures will make recommendations on suggested active networks optimal for driving their designs. Basically, one can provide the required inductive pullup for the first mixer output/s, tuned to the mixers internal 2 pF differential capacitance, or 4 pf single-ended capacitance. The Q of the resulting LC band pass can be set as determined by the unloaded inductor Q or a fixed resistive termination across the inductor/s. The current in the emitter follower can be set based on drive requirements and the supply voltage roughly as ie: = (Vcc-Vbe)/RE by selecting the emitter resistance RE. The effective emitter follower source impedance to the filter or and additional stepup network on the input of the filter will be determined roughly as the equivalent LC Q loading resistance divided by beta, in series with the effective intrinsic emitter resistance re = Vt/Ie. An additional resistive buildout can be used to adjust/stabilize this sourcing impedance to the SAW filter. The impedance of the emitter follower can be set in this manner to values less than 50 Ohms if followed by a reactive stepup network, such as an inductor, into the SAW input. The emitter follower can dump additional power into such a low impedance load to overcome high SAW filter insertion loss. The following design procedure can be followed when implementing a passive reactive match to a SAW filter into the design. Table 17 Centre Frequency 41.82 MHz SAW Filter Characteristics Input Impedance Output Impedance 550R // 19 pF 370R // 21 pF In this example we are assuming our main objective is to power match the filter and to improve conversion gain by adding a series capacitor. It would be possible to match the filter with just a single inductor but this would result in low conversion gain and is more likely to impact on system Noise Figure. The following design steps are taken. 1) Model the high input impedance matching circuit (including the first mixer bias pull ups and internal capacitors) which transforms to the desired SAW input impedance goal. 2) Simultaneously and iteratively model the associated SAW filter output impedance and transform to an appropriate second mixer input impedance. Generally, optimum second mixer noise figure performance will be found driving from a 1.5 k Ohms source. However, other consideration, such as component count and stability, could result in other choices, which are made feasible by the optimal noise figure provided by the second mixer. 3) Calculate the voltage conversion gain of the first mixer from the real part of the modeled mixer loading impedance, Rlmix. Convert this to power conversion gain by subtracting 10log (Rlmix/50 Ohm). 4) Confirm through calculation that you have realized sufficient power gain, prior to the SAW filter, to ensure that the cumulative system noise figure is not significantly degraded due to the high insertion loss of the SAW filter. 5) Confirm through measurement that acceptable -3 dB sensitivity and system noise figure have been realized. In exactly the same way as the matching circuits were designed for the RF path in Section 3.2 on Page 22, the L and C matching can be derived using the EEZMatch software. Using the SAW filter described in Table 17 a matching network was derived within EEZMatch the results of which are shown in Figures 19 and 20. 52 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note (Version 1.0) · Mixer1 Output Match · · · · · · · · CKT CAP 22 0 C=19.0 ! C37 C=PF CAP 22 23 C=27.0 ! C38 C=PF IND 23 0 L=820.0 ! L13 L=NH CAP 23 0 C=5.5 ! C39 C=PF RES 23 0 R=4309.0 ! R10 R=OH R = Equiv parallel loss resistance of L R = 2 x PI x Freq x L x Q = 4309R 4309R (Q ~ 20) · From Chart Load = 18.25 * 50 = 913R Y21(mixer1) = 0.0593 A/V Conversion G = Y21/2 Y21/2 x Load Conversion G = 27.07 vdB Impedance Change 50R to 550R 10 log (550/50) = -10.4dB Total G = 27.07 - 10.4 = 16.67 vdB ­ ­ ­ ­ ­ ­ ­ Figure 19 SAW Filter input Match to Mixer1 Output · Mixer2 Input Match · · · · · · · · CKT CAP 22 0 C=21.0 ! C40 C=PF CAP 22 24 C=12 ! C41 C=PF IND 24 0 L=1000.00 ! L14 L=NH CAP 24 0 C=5.62 ! C42 C=PF RES 24 0 R=5225.0 ! R12 R=OH R = Equiv parallel loss resistance of L R = 2 x PI x Freq x L x Q = 5225R 5225R (Q ~ 20) · From Chart ­ ­ ­ Load = 39.2 * 50 = 1960R 1960R Mixer2 Input Z = 2K Hence matches Mixer2 Input Figure 20 SAW Filter Output Match to Mixer2 input 53 AN99068 AN99068 Philips Semiconductors DESIGNERS GUIDE EXACT GPS Low Cost Reference Board Application Note AN99068 AN99068 (Ve