AN9832 HC5514X HC55120 HC55121 HC55130 HC55140 HC55142 HC55150 775VRMS HC5514 - Datasheet Archive

 

Evaluation Board Application Note February 1999 AN9832 Author: Don LaFontaine Functional Description Power Requirements for the

 

Operation of the UniSLIC14 Family of SLICs Evaluation Board Application Note February 1999 AN9832 AN9832 Author: Don LaFontaine Functional Description Power Requirements for the HC5514X HC5514X Evaluation Board Power Supply Connections The HC5514X HC5514X evaluation board, because of the common pinout of the UniSLIC14 family, is capable of evaluating the performance for all the parts in the UniSLIC14 family (HC55120 HC55120, HC55121 HC55121, HC55130 HC55130, HC55140 HC55140, HC55142 HC55142 and HC55150 HC55150). The sample provided with this board (HC5514X HC5514X) will illustrate the electrical performance for all members of the family. The board is configured to match a 600 line impedance, have a minimum loop current of 20mA, a maximum loop current of 30mA, on-hook transmission of 0.775VRMS 775VRMS , off-hook voice transmission of 1.1VPEAK , simultaneous off-hook pulse metering transmission of 3.1VPEAK and a maximum loop resistance of 1820. For evaluation of the programmability of the HC5514 HC5514 family, reference the data sheet for calculation of external components. The HC5514X HC5514X requires three external power supplies. VBH = -48V (Typ), VBL = -24V (Typ) and VCC = +5V. The board is equipped with nine switches: 6 Single Pole Double Throw (SPST), 2 SPST and 1 DPDT switches. The switches control the logic state and performance of the HC5514 HC5514. The logic control (C3, C2, C1), SHD and GKD/LVM switches are center open toggle switches. If offboard mode control of the SLIC is desired, these switches can be set to center open position and driven by logic at the logic terminal port. The logic terminal port is located at the bottom right hand side of the board. The Double Pole Double Throw switch allows impedance matching of pulse metering signals into complex line impedances. Ground Connections The three external power supplies should each be grounded to the evaluation board. Getting Started Verify that the sample is oriented in its socket correctly. Correct orientation is with pin 1 pointing towards the top of the board (tip and ring pins to the left). (Reference the data sheet for device pinout). Verifying Basic SLIC Operation The operation of the sample part can be verified by performing the following tests: 1. Power Supply Current Verification · Forward active, reverse active and low power standby states. 2. Normal Loop Feed Verification · Forward active and reverse active states 3. Gain Verification · 4-wire to 2-wire and 4-wire to 4-wire 4. Polarity Reversal Time 5. Battery Switching/Thermal Management Features · Toggle Switch Programming for Logic States · Monitoring of Switch Hook Detect (SHD) and Ground Key/ Line Voltage Measurement (GKD_LVM) via On Board LEDs · Selectable Transmit Gain 0dB/-6dB · Selectable Thermal Management · Single/Dual Battery Operation · Logic Terminal Port for Easy Evaluation in Existing Systems · Includes Ring Relay for Evaluation of Ring Trip 6. Ring Trip Verification 7. Pulse Metering The evaluation of all 7 tests, requires the following equipment: a 600 load, a 1820 load, a sine wave generator, an AC/DC volt meter, three external supplies (VBH , VBL , VCC), a dual channel storage oscilloscope, a telephone, BNC to banana adaptor, a battery backed AC source and a dynamic signal analyzer. Application Tip: When terminating tip and ring, it is handy to assemble terminators using a Pomona MDP dual banana plug connector as the terminating resistor receptacle. Refer to Figure 1 for details. · Selectable/Programmable Polarity Reversal Time · Programmable 2-Wire Impedance · Programmable Loop Detect Threshold · Programmable On-hook and Off-hook Overheads · Provisions for Pulse Metering 1 www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Application Note 9832 GND TABLE 1. A HC5514X HC5514X B FIGURE 1. TERMINATION ADAPTER Using the termination shown in Figure 1 provides an unobtrusive technique for terminating tip and ring while still providing access to both signals using the banana jack feature of the MDP connector. Posts are also available that fit into holes A and B, providing a solderable connection for the terminating resistor. 0.0048 3.25 16.2 VBH = -48V 31.7 1520 1.5 36 5.0 25 On-hook VBH = -48V 0.91 43.6 VBL = -24V 0.0002 0.0048 VCC = +5V 3.34 16.7 VBH = -48V 31.4 1507 VBL = -24V 1.5 36.0 VCC = +5V 5.0 25 On-hook VBH = -48V 0.33 15.84 VBL = -24V 0.026 0.624 VCC = +5V 3.17 15.8 VBH = -48V 18.8 902 VBL = -24V 0.027 0.648 VCC = +5V Reverse Active 0.0002 VCC = +5V Forward Active 41.2 VBL = -24V Forward Active 0.85 VCC = +5V LOGIC STATE POWER DISSIPATION (mW) VBL = -24V 600 SUPPLY CURRENT TYP (mA) 3.78 18.9 RL () On-hook VBH = -48V 600 Test # 1 Power Supply Current Verification A quick check of the evaluation board and sample is to measure the supply currents. The readings should be similar to the values listed in Table 1. The measurements can be made using a series ammeter on each supply, or power supplies with current displays. Reverse Active Low Power Standby Setup: 600 1. Connect the power supplies to the Evaluation board. 2. Set VBH to -48V, VBL to -24V and VCC to +5V. 3. Verify the thermal management switch (located towards the middle of the board) is in the VBL = VBL position. 4. Verify that S4 is not in the EXTRSYNC position (center position). 5. Configure the SHD switch (S5) to be in the BANJK position. This will allow an accurate reading of the VCC current by removing the SHD LED current. 6. Configure the GKD_LVM switch (S6) to be in the BNC position. This will allow an accurate reading of the VCC current by removing the GKD_LVM LED current. 7. Configure the SLIC to be in the Forward Active State (C3=0, C2=1, C1=0). Measure the supply currents and compare to those in Table 1. 8. Terminate tip and ring with a 600 load. Measure the supply currents and compare to those in Table 1. 9. Repeat steps 7 and 8 for both the reverse active (C3=1, C2=1, C1=0) and low power standby (C3=1, C2=0, C1=1) states. Measure the supply currents and compare to those in Table 1. Low Power Standby SUPPLY VOLTAGE 600 Test # 2 Normal Loop Feed Verification This test verifies the correct tip and ring voltages in both on-hook and off-hook forward active and reverse active states. Loop current and ground key detect are also verified via the onboard SHD and GKD_LVM LEDs. Discussion The HC5514 HC5514 is designed to have its most positive 2-wire terminal (tip in the forward active state and ring in the reverse active state) fixed at a set voltage. This set voltage depends upon the required overheads for the application. The most negative 2-wire terminal's voltage is dependent upon the load across tip and ring and the programmable current limit. When power is applied to the SLIC a loop current will flow from tip to ring through the 600 load. Loop current detection occurs when this loop current triggers an internal detector that pulls the output of SHD low, illuminating the LED through the +5V supply. The Ground Key detector (GKD) operation is verified by configuring the HC5514X HC5514X in the tip open state and grounding the ring pin. Grounding the ring pin results in a current that triggers an internal detector that pulls the output of GKD_LVM low, illuminating the LED through the +5V supply. 2 Application Note 9832 Setup (tip and ring voltages) 1. Connect the power supplies to the Evaluation board. 2. Set VBH to -48V, VBL to -24V and VCC to +5V. 3. Configure the SLIC to be in the Forward Active State (C3=0, C2=1, C1=0). 4. Verify that S4 is not in the EXTRSYNC position (center position). 5. Configure S5 and S6 switches to be in the LED position. 6. Disconnect any loads from across tip and ring. 7. Measure tip and ring voltages with respect to ground and compare to those in Table 2 (on-hook). Equation 1. When an open circuit exists, a mismatch occurs and the tip to ring voltage doubles. An easy way to measure the 2-wire to 4-wire transmit gain, without using a floating signal generator, is to measure the 4-wire to 4-wire gain. This way the source can be applied on the ground referenced 4-wire side to the VRX pin. Given that the 4-wire to 2-wire gain is approximately one, it follows that the 2-wire to 4-wire transmission gain is also approximately equal to the 4-wire to 4-wire gain. The dB 4-wire to 4-wire gain is calculated in Equation 2. V TR dB 4W ­ 2W = 20 log -V RX (EQ. 1) V TX dB 4W ­ 4W = 20 log -V RX (EQ. 2) 8. Terminate tip and ring with a 600 load. 9. Measure tip and ring voltages with respect to ground and compare to those in Table 2 (600). 10. Configure the SLIC to be in the Reverse Active State (C3=1, C2=1, C1=0). Setup (4-Wire to 2-Wire Gain) 1. Connect the power supplies to the Evaluation board. 11. Repeat steps 6 through 9. TABLE 2. 2. Set VBH to -48V, VBL to -24V and VCC to +5V. HC5514X HC5514X 3. Configure the SLIC to be in the Forward Active State (C3=0, C2=1, C1=0). RL () TIP VOLTAGE REFERENCED TO GND RING VOLTAGE REFERENCED TO GND Forward Active VBH = -48V VBL = -24V VCC = +5V On-hook -2.08 -45.4 600 -7.78 -26.04 Reverse Active VBH = -48V VBL = -24V VCC = +5V On-hook -45.09 -2.14 600 -26.23 -8.04 LOGIC STATE 4. Terminate tip and ring with a 600 load. 5. Connect a sine wave generator, referenced to ground, to the VRX input. 6. Set the generator for 1VRMS at 1kHz. 7. Connect an AC voltmeter across tip and ring Verification 1. Tip to ring AC voltage of 1VRMS when terminated. The dB gain is approximately 0dB. 2. Tip to ring AC voltage of 2VRMS when not terminated. The dB gain is approximately 6dB. Verification of SHD: 1. With the SLIC in the forward active state, the SHD LED is on when tip and ring are terminated with 600 and off when tip and ring are an open circuit. Verification of GKD: 1. Configure the SLIC to be in the Tip Open State (C3=1, C2=0, C1=0). 2. The GKD_LVM LED is on when ring is shorted to ground and off when ring is an open circuit. Notice that the SHD light is also on during this time. Test #3 Gain Verification This test will verify the SLIC is operating properly and that the 4-wire to 2-wire gain is 1.0 or 0.0dB. The programmable 2-wire to 4-wire transmission gain will also be verified by measuring the SLIC's 4-wire to 4-wire gain with the PTG pin floating (gain is -1.0 or 0.0dB) and grounded (gain is -0.5 or -6.0dB). Setup (2-Wire to 4-Wire Gain) 1. Connect the power supplies to the Evaluation board. 2. Set VBH to -48V, VBL to -24V and VCC to +5V. 3. Configure the SLIC to be in the Forward Active State (C3=0, C2=1, C1=0). 4. Terminate tip and ring with a 600 load. 5. Verify the PTG toggle switch (middle switch at bottom of board) is in the 0dB position. This condition floats the PTG pin. 6. Connect a sine wave generator, referenced to ground, to the VRX input. 7. Set the generator for 1VRMS at 1kHz. 8. Connect an AC voltmeter, referenced to ground, to the VTX output. Verification Discussion When tip and ring are terminated with 600 load, the SLIC will exhibit unity gain from the 4-wire VRX input pin to the 2-wire tip and ring (VTR). The dB gain is calculated in 3 1. VTX voltage of 1.15VRMS 15VRMS when PTG toggle switch is in the 0dB position. Application Note 9832 2. VTX voltage of 0.57VRMS 57VRMS when PTG toggle switch is in the -6dB position. This condition grounds the PTG pin. Test # 4 Polarity Reversal Time Discussion The HC5514X HC5514X has a programmable polarity reversal time. The evaluation board is equipped with a toggle switch for evaluation of 10ms and 40ms reversal times. Equation 3 gives the formula for programming a desired reversal time. 3.47k RSYNC ­ REV = -ms (EQ. 3) Capacitor C8 performs three different functions: Ring trip filtering, polarity reversal time and line voltage measurement. C8 and R5/R6 set the timing for the polarity reversal time. It is recommended that programming of the reversal time be accomplished by changing the value of R5/R6 (see Figure 2). Setup: 1. Connect the power supplies to the Evaluation board. For extremely short lines, the SLIC is operating from the VBL (low voltage negative supply). For line lengths in between, the SLIC is operating from both VBH and VBL. This test will illustrate the automatic switching of the supplies by monitoring the VBH and VBL supply currents during on-hook and off-hook with a 600 load across tip and ring. Setup: 1. Reference Test #1 "Power Supply Current Verification" and the results in Table 1. Verification 1. Notice for the on-hook condition (extremely long line) that all the current is provided by VBH . This feature enables on-hook transmission on the longest loop for a given battery voltage. 2. Notice for a 600 load, the current is shared by both VBH and VBL. If tip and ring are shorted, then all the loop current will come from VBL. 3. Notice the same is true for both the reverse active and standby states. 2. Set VBH to -48V, VBL to -24V and VCC to +5V. Discussion (Thermal Management) 3. Configure the SLIC to be in the Forward Active State (C3=0, C2=1, C1=0). If two negative battery supplies are not present in the design, a power sharing technique can be used to divert power off-chip for short loop high battery applications. Diverting power off-chip will preclude the SLIC from going into thermal shutdown during extreme application conditions. The total system power is not reduced, as in the battery switching case, just the power in the SLIC. 4. Terminate tip and ring with a 600 load. 5. Select either 10ms or 40ms polarity reversal time via the POL/REV switch at the bottom right hand side of the board. 6. Monitor the tip and ring voltage levels with a dual channel storage scope. Trigger the scope so when the polarity of tip and ring reverses, the time of reversal can be recorded. 7. Configure the SLIC to be in the Reverse Active State (C3=1, C2=1, C1=0). 8. Measure the time of reversal. Compare results to that listed in Table 3. 9. Switch the POL/REV switch to the other reversal time and repeat steps 6 through 8. TABLE 3. Mathematical Verification POLARITY REVERSAL TIME FORWARD ACTIVE TO REVERSE POLARITY REVERSAL TIME REVERSE ACTIVE TO FORWARD 10ms 10ms 10ms 40ms 40ms 40ms POLARITY REVERSAL SWITCH SETTING Test # 5 Battery Switching/Thermal Management Discussion (Battery Switching) The HC5514X HC5514X family of SLICs achieve their ultra low power operation via an automatic single and dual battery operation. The simultaneous operation from either a single battery or two batteries is dependent upon the loop length. For extremely long lines, the SLIC is operating from VBH (most negative supply). 4 The power dissipation in the SLIC is the sum of the smaller quiescent supply power and the much larger power that results from the loop current. The power that results from the loop current is equal to the loop current times the voltage across the SLIC. The thermal management resistor (R21) reduces the voltage across the SLIC, and thereby the on-chip power dissipation. The voltage across the SLIC is reduced by the voltage drop across R21. This occurs because R21 is in series with the loop current and the negative supply. Given: VBH = VBL = -48V, Loop current = 30mA, RL (load across tip and ring) = 600, Quiescent battery power = (-48V)(0.8mA) = 38.4mW, Quiescent VCC power = (5V)(2.7mA) = 13.5mW, Thermal Management resistor = 600. 1. Without thermal management the on-chip power dissipation would be would be 952mW (Equation 5). 2. With thermal management the on-chip power dissipation is 412mW (Equation 7). A power savings of 540mW On-chip power dissipation without thermal management resistor. Pd = ( V BH ) ( 30mA ) + 38.4mW + 13.5mW ­ ( RL ) ( 30mA ) 2 (EQ. 4) Application Note 9832 Pd = 952mW (EQ. 5) On-chip power dissipation with 600 thermal management resistor. Pd = ( V BH ) ( 30mA ) + 38.4mW + 13.5mW 2 ­ ( RL ) ( 30mA ) ­ ( R ThermalManagement ) ( 30mA ) 2 Pd = 412mW (EQ. 6) (EQ. 7) The design trade-off in using the thermal management resistor is loop length vs. on-chip power dissipation. Test #6 Ring Trip Verification This test will verify the ringing function of the HC5514 HC5514. A telephone, a battery referenced AC signal source, and a BNC to banana adaptor are the only additional hardware required to complete the test. Discussion The 600 termination is not necessary for this test since the phone provides this nominal impedance when off-hook. If the RSYNC_REV pin is grounded, the ring relay driver pin (RRLY) pin goes low after the SLIC is placed in the ringing state. This energizes the ring relay. The ring relay disconnects tip and ring lines from the phone and connects the path for the ringing signal. The DT and DR comparator inputs will sense the flow of DC loop current, enabling the ring trip comparator to sense when the phone is either onhook or off-hook. When an off-hook condition is detected, the HC5514X HC5514X will automatically disconnect the ringing signal to the phone at zero current crossing. This reduces impulse noise to the system. Refer to the HC5514 HC5514 Subscriber Line Interface Circuit electrical data sheet for more information about the functionality of the ring trip detector. Setup: 1. Connect the power supplies to the Evaluation board. 2. Set VBH to -48V, VBL to -24V and VCC to +5V. 3. Configure the SLIC to be in the Ringing State (C3=0, C2=0, C1=1). condition is detected, the HC5514X HC5514X will automatically disable the RRLY pin (pin goes high) at zero current crossing. This will disable the ring relay and reconnect the tip and ring lines to the phone. 4. When the phone is returned to the On-hook condition, the ring relay will remain disabled and the phone will not ring. Also, during this time the SHD LED will remain on. This feature precludes any false detects during the transition to On-Hook Active. To ring the phone again, toggle the C1 pin. Test #7 Pulse Metering This test will verify that an off-hook 3.1VPEAK pulse metering signal and a 1.1VPEAK voice signal can be transmitted simultaneously across a loop resistance of 1820. Reference Function Description of evaluation board on page 1 of this document for the details of the board design vs. performance. A signal generator, an 1820 load and a dynamic signal analyzer are required to complete this test. Discussion This test will verify the overhead voltage range of the design to accommodate an input signal of 4.2VPEAK (3.1VPEAK pulse metering amplitude and 1.1VPEAK voice amplitude) with less than 1% Total Harmonic Distortion (THD). Setup: 1. Connect the power supplies to the Evaluation board. 2. Set VBH to -48V, VBL to -24V and VCC to +5V. 3. Configure the SLIC to be in the Forward Active state (C3=0, C2=1, C1=0). 4. Connect a load resistor of 1820 across tip and ring. 5. Put a 4.2VPEAK 1kHz signal into the VRX input. 6. Measure the THD across the 1820 load. Verification: 1. The THD is less than 1% with a 4.2VPEAK signal applied. Functional Circuit COMPONENT Descriptions A brief description of each component is provided below. The components will be grouped by function to provide further insight into the operation of the HC5514X HC5514X board. 4. Connect the telephone across tip and ring. TABLE 4. TWO WIRE SIDE, TIP AND RING 5. Connect the BNC to banana adaptor to the RSYNC pin and connect this pin to ground. RF1, RF2 6. Connect battery backed AC (20Hz, 90VRMS 90VRMS +VBH) source to RING GEN INPUT located just below the tip and ring terminals on the board. U2 Verification: Protection resistors used for limiting the current into the transient voltage suppressor in the event of a surge. Secondary surge protection. TABLE 5. THERMAL MANAGEMENT 1. Toggle the C1 logic pin (S1) to ring the phone. 2. While ringing and On-hook, SHD LED is not illuminated. 3. While ringing, going off-hook will illuminate the SHD LED and the phone will stop ringing. When an off-hook 5 R21, S9 R21 is used to provide off-chip power dissipation to prevent the SLIC from going into thermal shutdown in short loop high power applications. Application Note 9832 TABLE 6. PROGRAMMABLE FEATURES OF THE HC5514X HC5514X TABLE 6. PROGRAMMABLE FEATURES OF THE HC5514X HC5514X (Continued) R19, R20, C10 R20 is used to set the overhead voltage. R19 is optional. C10 is used for filtering. R22, R23, C11 ZT resistor. Used in the impedances matching of the 2-wire side. C7 CDC Provides filtering of the DC loop. R1 RD resistor. Used to set the off-hook detect threshold. R24, R25, S5, S6 Current limiting resistors for SHD and GKD_LVM LEDs. S8 ROH resistor. Used to set the minimum loop current with maximum overhead voltage. Switch 8 is used to program the 2-Wire to 4-Wire transmission gain. C8 RSYNC_REV resistor. Used to set the polarity reversal time with C8 and provide an input for ring Synchronization. CRT_REV_LVM capacitor. Filters ring trip and is used in setting both the polarity reversal time and line voltage measurement. C9 CH capacitor. Provides AC and DC separation on the 2-wire side. S1, S2, S3 Toggle switches to set the logic state of the SLIC. R2 R3, R5, R6, S4 R4 RILIM resistor. Used to set the current limit. R7, R8, C14 Used to set the impedance matching for pulse metering signal. TABLE 7. SUPPLY DECOUPLING CAPACITORS R9, R10, Used for transhybrid balance of the voice signal. R11, R12, R13, R14, C12, C13, S7 R15, R16, R17, R18 C1-C6 Supply decoupling capacitors. Used in the detection of ring trip. Demo Board Schematic 20 C2 RELAY 2 3 C9 RF2 5 U2 6 J4 RRLY PTG CH RF1 7 8 -48V VRX RING C3 C4 R21 VBL=VBH SPDT -24V J3 R20 R19 S9 R17 C6 10 C7 ZT TIP RSYNC_REV VBL RDC_RSG 11 R15 J12 C8 DR GKD_LVM C1 R2 R5 21 R1 C3 R23 C11 40ms R3 J9 10ms J11 19 J10 17 S5 15 R24 H L CENTER OFF S3 S2 SHD S6 LED GKD_LVM LED LED ON DET LOW DET LOW S1 FIGURE 2. UniSLIC14 DEMO BOARD SCHEMATIC R25 LED ON LOGIC TERMINAL PORT 6 J5, J6 12/16kHz PULSE METERING INPUT SIGNAL S4 SPDT +5V R9 18 RING GENERATOR VBAT R22 R6 C2 +5V R11 S7 R4 16 CRT_REV_LVM R10 24 22 SHD 13 DPDT R13 R12 C14 23 RD C12 R7 4 ILIM CDC 14 R14 R8 25 ROH DT R16 S8 26 J13 12 C10 VBL=VBL C5 9 R18 C13 0dB GND VBH OPEN -6dB 1 C3 J2 SPST SPM ZSPM TIP J8, J7 28 C1 RING VTX SHD C1 +12V U1 C2 J15 VCC GKD LVM +5V J1 RJ-11 RJ-11 Application Note 9832 TABLE 8. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT VALUE U2 - Dual Asymmetrical Transient Voltage Suppressor TOLERANCE RATING UniSLIC14 Family U1 - SLIC N/A N/A TISP1082F3P TISP1082F3P N/A N/A 30 Matched 1% 2.0W RF1, RF2 (Line Feed Resistors) R1 (RD Resistor) R = 500/ISH 500/ISH, ISH = 9.78mA 51.1k 1% 1/4W R2 (ROH Resistor) R = 500/Iloop(min)-ISH- , (Iloop(Min) = 20mA, ISH- 6.54mA) 34.8k 1% 1/4W R3, R6 (RSYNC_REV Resistors) R = 3.47k/ms (10ms) 34.8k 1% 1/4W R4 (RILIM Resistor) R = 1000/ILIM 1000/ILIM (ILIM = 30mA) 33.2k 1% 1/4W R5 (RSYNC_REV Resistor) R = 3.47k/ms (40ms) 140k 1% 1/4W R7, R8 (ZSPM) 10.7k 1% 1/4W R9, R12 (Voice Transhybrid Resistors) 10k 1% 1/4W R10, R11, R13, R14, C12, C13 (Option for "Complex Impedance" Transhybrid, where ZO does not equal ZB) OPEN - - R15, R17 (Input Current Limiting Resistors for DT and DR) 2M 1% 1/4W R16 (Sense Resistor for DC current during ringing) 400 1% 2W R18 (Series Resistor to simulate loop length during ringing) 600 1% 2W R20 (RDC/RSG) R = 50*RFEED, RFEED = 381 19.1k 1% 1/4W R19 R = 0 - - R21 (Thermal Management Resistor) OPEN - - R22 (2-Wire Impedance Matching Resistor) R = 200(ZO-2RF) Z0 = 600, RF = 30 107 1% 1/4W R = 0 C = OPEN - - R23, C11 (For matching a complex 2-Wire impedance) R24, R25 (Current Limiting Resistors for LEDs) - - - 1.0µF C1, C3, C6 20% 100V C2, C4, C5 0.1µF 20% 100V C7 2.2µF 20% 100V C8, C9, C10 0.47µF 20% 16V C14 680pF 10% 50V RED - - D1, D2 (SHD and GKD_LVM LEDs) Design Parameters: Switch Hook Threshold = 9.8mA, Loop Current Limit = 29.6mA, Synthesize Device Impedance = 600-60 = 540, with 30 protection resistors, impedance across Tip and Ring terminals = 600. Where applicable, these component values apply to the Basic Application Circuits for the HC55120 HC55120, HC55121 HC55121, HC55130 HC55130, HC55140 HC55140, HC55142 HC55142 and HC55150 HC55150. Pins not shown in the Basic Application Circuit are no connect (NC) pins. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 7 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029