AN7862 SPT7862 EB7862 TK11227 TK11227B SB101B SP7862 J20/J22 J28/J29 J34/35 - Datasheet Archive

 

EVALUATION BOARD APPLICATION NOTE FEATURES APPLICATIONS · · · · · · 10-Bit Resolution

 

AN7862 AN7862 EVALUATION BOARD APPLICATION NOTE FEATURES APPLICATIONS · · · · · · 10-Bit Resolution Up to 40 MSPS Conversion Rate Single +5 V Supply Required for SPT7862 SPT7862 On-Board Dual Clock Driver On-Board Adjustable References On-Board Input Buffers, with Adjustable DC Offset Levels · Digital Output Buffer · 5 V Logic Output · · · · · · GENERAL DESCRIPTION The EB7862 EB7862 evaluation board is intended to be used as a tool for device characterization and to demonstrate the performance of the SPT7862 SPT7862 ADC. The SPT7862 SPT7862 10-bit dual ADC (analog-to-digital converter), is a fast analog input device, providing outstanding dynamic performance with very low power dissipation while operating with a +5 V supply. It is provided in a 64-lead Thin Quad Flat Pack (TQFP) package. Low-Power, High-Speed Design Applications Evaluation of the SPT7862 SPT7862 Engineering System Prototype Aid Major Block for Prototype System Guide to System Layout AC Dynamic Analysis of the SPT7862 SPT7862 (with customer-provided data capture and FFT system) The SPT7862 SPT7862 is a monolithic dual 10-bit ADC that can sample input at a rate of up to 40 MSPS. Its logic inputs and outputs are compatible with 3 V logic. BLOCK DIAGRAM CMP +2 +2 Vref hift Buffer DAVA el S Lev OE2 RefH RefL Vin +1 10 10 DO B Buffer hift DAVB el S Lev OE1 /OEA SPT7862 SPT7862 VinB 10 10 DO A P2 +1 P1 VinA RefH RefL Vin Vref CLKB +2 w/VOS Adj CMP +2 w/VOS Adj CLKA 2.7V REF OE2 OE1 /OEB Ferrite Bead +AV -AV 10 10 + AGND -AV + +5 +D5 10 DGND +AV -D5 10 AGND + +A5 AGND 10 + -D5 + DGND +D5 EB7862 EB7862 Signal Processing Technologies, Inc. 4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com The analog inputs of the SPT7862 SPT7862 permit 4 VP-P (typical). Input voltages come on board via two SMA connectors labeled VINA and VINB. The common-mode voltage, nominally +2 V, is generated by R45 and U8. The common-mode voltage and the input signals are summed together and then buffered before reaching the SPT7862 SPT7862. Power supply connection points are labeled for operator convenience. Before connecting any power supply to the evaluation board, set the supply to the correct value and power off. Ensure that all power supplies are connected and preset before full power is applied. Figure 1 shows the proper connection of the power supplies. After powerup verify that the supply voltages are within specification before proceeding (refer to Table I). Make any necessary adjustments, referencing your measuring instrument to the appropriate return node. The 20 digital output bits, plus data valid are buffered out for downstream digital processing. The EB7862 EB7862 also features on-board voltage references that allow the user to adjust both the top and bottom of each reference ladder. Figure 1 - Power Supply Connections 7V ­ + 3V ­ + A clock comparator/buffer allows a sinewave input to generate the TTL sample clock. In addition, this allows for a modest variation of the sample clock duty cycle. There are five separate voltage inputs which power the various circuits on the evaluation board: ±5 V digital, +7 V and ­3 V analog, +5 V analog for the reference driver circuits. ­AV AGND +AV AGND +A5 5V + +D5 5V + ­ DGND ­ ­D5 EB7862 EB7862 This application note describes the function of the EB7862 EB7862 in seven separate sections. They include the following: Power Supplies and Grounding Layout Reference Circuits Analog Inputs Clock Circuit Digital Output Control Options and Test Points Table I - EB 7862 Power Supply Requirements Vmin Vtyp Vmax Ityp ­AV ­3.1 V ­3 V ­2.9 V ­66 mA +AV +6.9 V +7 V +7.1 V +45 mA +A5 +4.9 V +5 V +5.1 V +140 mA ­D5 ­5.1 V ­5 V ­4.9 V ­10 mA +D5 Figures 7 and 8 show a detailed schematic of the evaluation board. Table IV is a list of materials/parts for the EB7862 EB7862. Layout of the board layers are included (Figures 9, 10, 11, 12). +4.9 V +5 V +5.1 V +95 mA Note: If the +AV and ­AV supplies are set to voltages other than the recommended values, damage to the SPT7862 SPT7862 may occur. To reduce the risk of damage in this situation, install diodes D3, D4, D5, and D6. POWER SUPPLIES AND GROUNDING The SPT7862 SPT7862 is designed to use a separate analog and digital ground plane. The EB7862 EB7862 application board separates the analog and digital grounds at the digital output section of the SPT7862 SPT7862. It is at this split that SPT recommends connecting analog and digital grounds together using a ferrite bead. The EB7862 EB7862 requires analog +7 V and ­3 V (designated +AV and ­AV on the board), and +5 V analog supply (designated +A5 on the board), digital ±5 V (designated +D5 and ­D5 on the board). The +AV and ­AV supplies provide power to the input buffer operational amplifiers and the low force reference circuits. As mentioned above, the nominal voltages are +7 V and ­3 V. Alternate op-amps may be used but may require different supply voltages. When this is the case, remove jumper J9 and provide ­3 V to the ­A3 test point referenced to analog ground. LAYOUT This evaluation board is designed and manufactured with four layers: two signals (top and bottom layers), one ground plane layer with both analog and digital and one power layer that accommodates all power distribution, including all postpower supply filtered power. The ordering of the layers are: Top ­ Signal (used for critical signals requiring controlled impedance), Second ­ Ground, Third ­ Power and Bottom ­ Signal. The signal layers are designed with a controlled characteristic impedance of 50 ohms. Figures 9, 10, 11, and 12 show the actual layout for the EB7862 EB7862. The +A5 supply powers the reference buffers, the TK11227 TK11227 voltage regulator, and the SPT7862 SPT7862. The ±D5 supply powers the dual clock buffer chip and the digital outputs for the SPT7862 SPT7862. SPT 5V ­ + AN7862 AN7862 2 5/15/00 FORCE HIGH WITH OFFSET ADJUST - FORCE LOW WITH OFFSET ADJUST Some applications may require matching the offset and gain of the two ADCs inside the SPT7862 SPT7862. The EB7862 EB7862 accommodates this by including offset adjustments to ADC B's reference driver circuits. This configuration requires jumpers J28 and J29 to be installed and jumpers J26 and J27 to be connected to the outputs of U11. Figure 4 shows the evaluation board configuration for this application. REFERENCE CIRCUITS The EB7862 EB7862 has an on-board reference voltage which is established from a TK11227B TK11227B (+2.7 V reference, low dropout). This reference voltage is used to set the SPT7862 SPT7862's reference ladder voltages. The reference voltages can be applied in any one of three configurations. FORCE HIGH - LOW AT AGND This is the most basic configuration for driving the references. The A and B reference highs are derived from the same source, and the two reference lows are at AGND. In this configuration, jumpers J28 and J29 are removed. Jumpers J26 and J27 are in the ground position. The reference high A and B voltages are adjusted using R33; its range will be approximately +2.7 V to +4.8 V at the output of the buffers. Figure 2 shows a block diagram of this configuration. Figure 4 - Force High with Offset Adjust - Force Low with Offset Adjust G = +2 R33 ADC A R35 ADC B Figure 2 - Force High - Low at AGND R34 G = +2 SPT7862 SPT7862 R36 R33 G = +2 R39 ADC A ADC B ANALOG INPUTS SPT7862 SPT7862 The two analog input signals required for the SPT7862 SPT7862 are applied to the EB7862 EB7862 via the VINA and VINB SMA connectors. If needed, termination resistors are present at the inputs, providing proper termination for generators and other signal sources. The EB7862 EB7862 has resistor values installed which produce a 50 ohm thevenin equivalent when the onboard VOS circuit is used. If the offset voltage is not present on the input signal, a voltage may be summed in either externally or from an on-board circuit. Figure 5 shows the input circuitry which drives the SPT7862 SPT7862. FORCE HIGH - FORCE LOW When it is necessary to drive the high and low reference voltages to a specific (but common to A and B) level, move jumpers J26 and J27 to connect to the outputs of U11. Jumpers J28 and J29 are removed. R33 adjusts the reference high voltage; its range will be approximately +2.7 V to +4.8 V at the output of the buffers. R34 adjusts the reference low voltage; its range will be approximately ­0.7 V to +1 V. Figure 3 shows a block diagram of this configuration. Figure 5 - Analog Input Circuitry Figure 3 - Force High - Force Low VRHFA R33 G = +2 ADC A R45 R58 ­ + J31 VINA VOS ADC B ­ + To SPT7862 SPT7862 VINA G = +2 VINB R34 G = +2 SPT7862 SPT7862 + VRLFA ­ R57 SPT To SPT7862 SPT7862 VINB AN7862 AN7862 3 5/15/00 INPUT OFFSET VOLTAGE - ON BOARD The common-mode voltage (labeled VOS) is generated using a resistor network with one end tied to VRHFA and the other end tied to VRLFA. The center tap of R45, which adjusts the voltage, is buffered and provides the voltage to the VIN input amplifiers. Jumper J31 must be installed to use this circuit. slew rate will cause this with any comparator). The clock circuits for the A and B ADCs are independent as long as jumpers J3 and J4 are in the A position and jumper J1 is removed. Figure 6 - On-Board Clock Driver Circuits INPUT OFFSET VOLTAGE - EXTERNAL Removing J31 allows the user to apply an external voltage to the input amplifiers which can be connected at the VOS test point. B R3 +D5 J4 ­D5 J7 The input amplifier/summer has a gain of +2. The feedback resistors are socketed, allowing the user to change the gain of the amplifiers. This is especially useful when using amplifiers different from the ones provided with the board. R13 B To P2 ­ + A CLKA J4 To SPT7862 SPT7862 CLKA R9 U2 OUTPUT CLAMPING The output of the amplifiers directly feed the input of its respective side. In addition, clamping diodes (D3­6, SB101B SB101B) are designed in to ensure that the input levels at powerup, and during any other anomalistic occurrence, do not exceed the limit specification for the input to this device. A monitoring test point is designed into the PCB for direct observation of the signals into the SPT7862 SPT7862. CLKB R12 R8 J1 To SPT7862 SPT7862 CLKB + ­ A J2 J3 B +D5 To P1 ­D5 R2 B A C SINGLE SOURCE When it is necessary to drive the two analog inputs of the SPT7862 SPT7862 with the same signal, install jumper J35 and move jumper J34 to the B position. Both inputs will be driven from the VINA signal. J3 SINGLE CLOCK When only one ADC is being used it is important to commit the clock for the unused ADC to either high or low. This can be accomplished on the board by ensuring that the input termination resistor is installed and then moving the J7 or J2 jumper, whichever is the unused clock circuit, to the B position. If the jumper on the unused channel is left in the A position, the comparator's inputs will be at zero volts and an oscillation will result. FILTERING SPT recommends appropriate bandpass filters on the input when performing AC characterization of this part. CLOCK CIRCUIT Figure 6 shows the on-board clock driver circuits. The two clock signals, nominally 40 MHz, are applied to the EB7862 EB7862 via two SMA connectors labeled CLKA and CLKB. SPT recommends a 50% clock duty cycle ±3%. The inputs are set up to accept a generator which can drive 50 ohms to ground. When this is not required, R8 and R9 may be removed. IN-PHASE COMMON CLOCK It may be desirable to drive both ADCs with the same clock source. The EB7862 EB7862 makes this possible through either the CLKA or CLKB signal paths. This is done by having only jumper J3 or J4 installed and installing J1 to tie the two clocks together. For example, if the CLKA signal was used to drive both ADC clocks, place jumper J4 in the A position and install jumper J1. Jumper J3 may be placed in the C position to send the common clock to downstream circuitry, exiting the EB7862 EB7862 at connector P1. The on-board clock drive is performed by a TTL comparator. The comparator's reference may be set to ground, or it may be set by a variable DC voltage. Switching between the two options involves changing jumpers J7 (for A) or J2 (for B). Adjust the reference voltages using R3 (for A) and R2 (for B). The adjustment range is from ­1 V to +1 V. The drive signal is assumed to be a sinusoid signal with a maximum amplitude of ±2.5 V. However, any square wave signal with correct clock pulse width high and low would be acceptable. When using a sinusoid input be sure not to allow the compare level to reach the crest of the signal as this may cause serious jitter problems at the output of the comparator (slow SPT C A OUT-OF-PHASE COMMON CLOCKING In some applications the user may want to sample the same input signal with 180 degrees of phase between the two sampling ADCs. The EB7862 EB7862 provides this capability by using the differential outputs of the clock comparator U2. For example, if the CLKA signal was used as the reference clock, install jumper J4 in the A position and jumper J3 in the B position. Jumper J1 is not installed. AN7862 AN7862 4 5/15/00 buffers direct the data directly to the connectors P1 and P2. Refer to Figure 8 for the pinout of the P1 and P2 connectors. DIGITAL OUTPUT The SPT7862 SPT7862 output is capable of driving either +5 V or +3.3 V logic levels. However, the EB7862 EB7862 is set up to drive only +5 V logic levels. Note that series damping resistors (value of 51 ohms) are in series with the outputs of the SP7862 SP7862, and with the P1 and P2 outputs, to reduce oscillation when there would be a mismatch of impedance or long signal or cable lengths from the output of the EB7862 EB7862 to the user's receiver circuit. These may be modified or replaced with zero ohm resistors as the user's application may require. Data buffers (U3, U4, and U5) are furnished with the EB7862 EB7862, while the user will need to furnish required latch and/or data storage circuitry external to the EB7862 EB7862. The CONTROL OPTIONS AND TEST POINTS Table II outlines the name, use and intent of the jumpers, test points and control potentiometers. Table II - Controls and Options NAME DESCRIPTION INTENDED USE R2 POTENTIOMETER Adjust the CLKB comparator reference value (range between ­1.0 and +1.0) R3 POTENTIOMETER Adjust the CLKA comparator reference value (range between ­1.0 and +1.0) R33 POTENTIOMETER Adjust the VRHF voltage R34 POTENTIOMETER Adjust the VRLF voltage R35 POTENTIOMETER Adjust the VRHFB voltage R36 POTENTIOMETER Adjust the VRLFB voltage R39 POTENTIOMETER Adjust the reference range for the B side R45 POTENTIOMETER Adjust the VOS voltage for VIN J1 JUMPER Jumpers the A clock to the B clock for common in-phase clock applied to both ADCs J2/J7 JUMPERS Selects between a fixed or adjustable reference voltage to the comparator J3/J4 JUMPERS Selects individual and/or out-of-phase clock J5/J6 JUMPERS Selects between VINR being tied to ground or to VINLS J20/J22 J20/J22 JUMPERS If installed, connects ODVDD to +D5 J28/J29 J28/J29 JUMPERS If installed, allows individual adjustment of B channel references J31 JUMPERS If installed, allows use of on-board VOS circuit J34/35 J34/35 JUMPERS Allows for common input drive or individual input drive PTP1 TESTPOINT VINB scope probe point with ground PTP2 TESTPOINT VINA scope probe point with ground +VOS TESTPOINT Measure input VOS or add external voltage here +2.7/+VR TESTPOINT Measure output of voltage regulator HF/2 TESTPOINT Measure input of reference high force amplifiers LF/2 TESTPOINT Measure input of reference low force amplifiers ­VR TESTPOINT Measure low side of reference driver resistor network RHFA TESTPOINT Measure ADC A reference high force RHFB TESTPOINT Measure ADC B reference high force RLFA TESTPOINT Measure ADC A reference low force RLFB TESTPOINT Measure ADC B reference low force CLKA TESTPOINT Clock A scope probe point with ground CLKB TESTPOINT Clock B scope probe point with ground SPT AN7862 AN7862 5 5/15/00 1. Power Supplies Ensure that the power supplies are disconnected from the EB7862 EB7862. Set power supplies as suggested in Table I. Turn off supplies and connect power supplies to the evaluation board. Turn on all power supplies simultaneously. SETUP AND CALIBRATION The setup and calibration operation involves setting power supplies, connecting and powerup, establishing the desired reference voltage(s), setting input offset if necessary, setting up and verifying sample clock operation, and verifying functional operation of the output of the EB7862 EB7862. 2. Reference Adjust R33 while monitoring RHFA testpoint and set it to +4 V ±0.005 V. The board will be configured to use the A clock channel to drive both ADC clock pins. Only the VINA is expected to have an input signal. It will be distributed to both ADC inputs. The reference-high pins will be driven from the same voltage source and the low references will be tied to ground. For other configurations of this board see the board descriptions in the text portion of the application note. 3. Sample Clock Set user-provided sinewave clock. Ensure that the clock frequency is within part specification. Connect clock to the CLKA SMA connector on the evaluation board. 4. Analog Input Set up a 2 VP-P, symmetrical around ground, 1 MHz sinewave signal. Connect this signal to the VINA SMA connector. If necessary, adjust R45 to center the sine ­wave within the range of the ADC. Table III - Jumper Setup Two-Pin Jumpers Three-Pin Jumpers J1 Installed J2 B position J9 Installed J3 Removed J20 Installed J4 A position J22 Installed J5 Ground position J28 Removed J6 Ground Position J29 Removed J7 A position J31 Installed J27 Ground position J35 Installed J26 Ground position 5. Digital Output If user does not have a digital capture system for processing and observing data, an oscilloscope or logic analyzer may be used to observe the digital encoded data of the analog input signal. Another option is to purchase the EB9713 EB9713 board, which is a 100 MWPS TTL DAC, that mates up easily with the EB7862 EB7862. This board may be used for reconstruction of the encoded data for spectral analysis. J34 B position SPT AN7862 AN7862 6 5/15/00 Figure 7 - EB7862 EB7862 Detailed Schematic Rev A Board, Sheet 1 of 2 SPT AN7862 AN7862 7 5/15/00 Figure 8 - EB7862 EB7862 Detailed Schematic Rev A Board, Sheet 2 of 2 SPT AN7862 AN7862 8 5/15/00 Table IV - EB7862 EB7862 Bill of Materials # Reference Manufacturer Part Number Description 1 C1,2,6,7 ECU-S2A150JCA ECU-S2A150JCA 15 pF Radial Cap (100 Mil) [socketed] 2 C3-5,10-15,18,19,22,23, 27,29,30,36-38,40-42,44, 48,50,52,53,60,62,64, 67-71,76,78,79 ECU-V1H103KBM ECU-V1H103KBM .01 µF Chip Cap 3 C8,9 ECQ-V1H103JL ECQ-V1H103JL .01 µF Radial Cap (200 Mil) [socketed] 4 C16,17 ECU-S1H101JCA ECU-S1H101JCA 100 pF Radial Cap (100 Mil) [socketed] 5 C20,24,26,28,31,35,39,43, ECS-T1CY475R ECS-T1CY475R 45-47,49,51,54,55,58,59, 61,63,65,66,72-75,77 4.7 µF Tantalum Chip Cap 6 C21,25,32-34 ECS-T1CX106R ECS-T1CX106R 10 µF Tantalum Chip Cap 5 Panasonic/Any 7 D1,2 1N4148DICT 1N4148DICT Axial Diode 2 LiteOn 8 D3-6 SD101B SD101B Schottky Diode 4 LiteOn 9 FB1-4 EXC-ELSA35V EXC-ELSA35V Ferrite Bead 4 Panasonic 10 J1,3,4,34,35 Pin Receptacles Jumpers [socketed] 11 J2,5-7,9,20-24,26-29,31 PZC36SAAN PZC36SAAN Jumper Pins [trim from 36-Pin] 1 Sullins 12 J8,16,32,33 901-144-8-RFX 901-144-8-RFX SMA Coax Connector 4 Amphenol 13 J9,20-24,28,29,31 PZC36SAAN PZC36SAAN Jumper, 2-Pin [trim from 36-Pin] 1 Sullins 14 J11-13 J11-13,39-43 108-0740-001 Banana Jack 8 Johnson 15 P1,2 PZC36DBAN PZC36DBAN 40-Pin Rt Ang Male Conn [trim from 72-Pin] 2 Sullins 16 R1,10,11,59-62 ERJ-8ENF5111 ERJ-8ENF5111 5.1 k Ohm Chip Resistor 7 Panasonic/Any 17 R2,3,35,36,39,45 3266W-1-102 1 k Ohm Potentiometer 6 Bourns 18 R4-7 ERJ-8ENF2001 ERJ-8ENF2001 2 k Ohm Chip Resistor 4 Panasonic/Any 19 R8,9,14,15 51 MF 51 Ohm 1/4W 1% [socketed] 4 Yageo/Any 20 R12,13,47,48 100 MF 100 Ohm 1/4W 1% [socketed] 4 Yageo/Any 21 R16,17,24,25,46 ERJ-8ENF22R1 ERJ-8ENF22R1 22.1 Ohm Chip Resistor 5 Panasonic/Any 22 R18-21 R18-21,26-29,43,44 ERJ-8ENF1002 ERJ-8ENF1002 10 k Ohm Chip Resistor 10 Panasonic/Any 23 R23,63-65 ERJ-8ENF51R1 ERJ-8ENF51R1 51.1 Ohm Chip Resistor 4 Panasonic/Any 24 R30,32 ERJ-8ENF5112 ERJ-8ENF5112 51.1k Ohm Chip Resistor 2 Panasonic/Any 25 R31 82 MF 82 Ohm 1/4W 1% [socketed] 1 Yageo/Any 26 R33 3266W-1-502 5 k Ohm Potentiometer 1 Bourns 27 R34 3266W-1-103 10 k Ohm Potentiometer 1 Bourns 28 R37 ERJ-8ENF1001 ERJ-8ENF1001 1 k Ohm Chip Resistor 1 Panasonic/Any 29 R38 ERJ-8ENF2002 ERJ-8ENF2002 20 k Ohm Chip Resistor 1 Panasonic/Any 30 R40 470 MF 470 Ohm 1/4W 1% [socketed] 1 Yageo/Any 31 R49-52 R49-52 430 MF 430 Ohm 1/4W 1% [socketed] 4 Yageo/Any 32 R53-56 R53-56 130 MF 130 Ohm 1/4W 1% [socketed] 4 Yageo/Any 33 R57,58 62 MF 62 Ohm 1/4W 1% [socketed] 2 Yageo/Any 34 RP1-4 760-3-R51 760-3-R51 51 Ohm 7-Res DIP Array 4 CTS 35 RP5,6 766-163-R51 766-163-R51 51 Ohm 8-Res SMD Array 2 CTS 36 TP1-28 TP1-28 40F6045 40F6045 Solder Terminal 37 U1 SPT7862 SPT7862 Dual 10-Bit 40 MSPS A/D Converter SPT Qty Suggested Manufacturer 4 Panasonic/Any 40 Panasonic/Any 2 Panasonic/Any 2 Panasonic/Any 26 Panasonic/Any 15 28 1 Item #45 NEWARK SPT AN7862 AN7862 9 5/15/00 Table IV - EB7862 EB7862 Bill of Materials (Cont'd) Reference Manufacturer Part Number Description 38 U2 MAX9698BCPE MAX9698BCPE TTL Latch-Output Comparator 1 Maxim 39 U3,4 74ACTQ827SP 74ACTQ827SP 10-Bit Tri-State Buffer 2 National 40 U5 74ACT86D 74ACT86D Quad 2-Input X-OR Gate 1 Texas Inst. 41 U6,7 OPA642P OPA642P Op Amp 2 Burr-Brown 42 U8 TLV2461CP TLV2461CP R-R Op Amp 2 Texas Inst. 43 U9,11 TLV2462CP TLV2462CP Dual R-R Op Amp 2 Texas Inst. 44 U10 TK11227B TK11227B_MCL Volt Reg with On/Off 1 Toko 45 N/A ED5044-ND ED5044-ND Pin Receptacles [for "socketed" parts] 71 DIGI-KEY 46 N/A 929955-06 Shunt for Jumper 14 DIGI-KEY (3M) 47 N/A 1902EK-ND 1902EK-ND 1" Nylon Spacer [Note #1] 4 DIGI-KEY 48 N/A H143-ND H143-ND 4-40 Pan-head Screw [Note #1] 4 DIGI-KEY 49 EB7862 EB7862 Rev A Evaluation Board 1 SAS Circuits # Qty Suggested Manufacturer NOTE #1 Mount in four corners as bottom side legs. SPT AN7862 AN7862 10 5/15/00 Figure 9 - Top Layer ­ Signal SPT AN7862 AN7862 11 5/15/00 Figure 10 - Layer 2, Ground SPT AN7862 AN7862 12 5/15/00 Figure 11 - Layer 3, Power SPT AN7862 AN7862 13 5/15/00 Figure 12 - Bottom Layer ­ Signal SPT AN7862 AN7862 14 5/15/00