AN7851 SPT7851 EB7851 TK11247B OP291 OPA642 OP191 SB101B 74LVX00 SP7851 EB9713

EVALUATION BOARD APPLICATION NOTE FEATURES APPLICATIONS · · · · · · · ·

AN7851 AN7851 EVALUATION BOARD APPLICATION NOTE FEATURES APPLICATIONS · · · · · · · · · · · · 10-Bit Resolution Up to 20 MSPS Conversion Rate Single +3.3 V Supply Required for SPT7851 SPT7851 On-Board Clock Driver On-Board Adjustable References and Common Mode On-Board Single-Ended to Differential Input Buffers with Adjustable Level · On-Board Single-Ended to Differential Transformer (1:1) · Digital Output Buffer · +3.3/5 V Logic Output For Low Power, High-Speed Design Applications Evaluation of the SPT7851 SPT7851 Engineering System Prototype Aid Major Block for Prototype System Guide to System Layout AC Dynamic Analysis of the SPT7851 SPT7851 (With Customer-Provided Data Capture and FFT System) GENERAL DESCRIPTION The SPT7851 SPT7851 is a 10-bit, 20 MSPS ADC (analog-to-digital converter). It is a fast differential analog input device that provides outstanding dynamic performance with very low power dissipation and operates with a +3.3 V supply. It is provided in a 44-lead Thin Quad Flat Pack (TQFP) package. The EB7851 EB7851 evaluation board is intended to be used as a tool for device characterization and to demonstrate the performance of the SPT7851 SPT7851 ADC. BLOCK DIAGRAM The AN7851 AN7851, application note for the EB7851 EB7851, has ten separate sections: Power Supplies and Grounding, Layout, Reference Circuits, Bias Circuits, Analog Inputs, Common Mode Voltage, Clock Circuit, Digital Output, Control Options and Test Points, and Setup and Calibration. Figure 6 is a detailed schematic of the evaluation board. Table III lists the materials and parts for the EB7851 EB7851. Layouts of the board layers are included (figures 7, 8, 9 and 10). References Circuit 4.7 V Regulator VINN VCM SPT7851 SPT7851 CLK-In +A5 A5 +D3/5 10 (3 V Logic) 10 (3V/5 V Logic) Digital Output VINP Input Select RF-In RefP RefN Buffers Bias1 Bias2 40-Pin Ribbon Connector Bias Currents Circuit Video-In Single to Differential + +A5 AGND A5 +A3 CLK In Voltage Comparator DGND +D3/5 Signal Processing Technologies, Inc. 4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com The SPT7851 SPT7851, monolithic 10-bit ADC, can sample the input at a rate up to 20 MSPS. Its logic inputs and outputs are compatible with +3.3 V logic. The analog input of the SPT7851 SPT7851 permits ±1 V differential (typical) with +1.5 V of common mode voltage, internally provided. The board supports straight AC transformer coupling of the input signal or op-amp buffering as a single-to-differential converter. Both signals are exclusively input. The 10 digital output bits and the sample clock are buffered out for downstream digital processing. The EB7851 EB7851 features on-board voltage references that allow the user to adjust the top and bottom of the reference ladder as well as the bias current. Figure 1 - Power Supply Connections User Power Supplies + 3.3 V + 3.3 or 5 V + +A5 5V +A3 DGND +D3/5 5V + A5 AGND EB7851 EB7851 Table I Power Supply Specifications VMIN VMAX ITYP A5 4.9 V 5 V 6 V 54 mA +A5 +4.9 V +5 V +6 V +60 mA +A3 +2.7 V +3.3 V +3.6 V +22 mA +D3/5 The clock comparator/buffer allows sine wave input to generate the TTL sample clock. This also allows for a modest variation of the sample clock duty cycle. VTYP +2.7 V +5 V +5.5 V +26 mA Four separate voltage inputs power the various circuits on the evaluation board. They are: +5 V analog, 5 V analog, +3.3 V analog for the SPT7851 SPT7851 (which also powers the +3.3 V for SPT7851 SPT7851 digital outputs via a ferrite bead) and an adjustable +3/5 V digital output for the output buffers. The board has room on either side for breadboarding of additional circuits as required by the user. SPT suggests you use the left side prototype area for analog and the right side for digital circuits. The SPT7851 SPT7851 design uses a common analog and digital ground plane. The EB7851 EB7851 application board separates the analog and digital grounds at the final digital buffer drivers U9U10. SPT recommends connecting analog and digital grounds together with a ferrite bead at this split. POWER SUPPLIES AND GROUNDING LAYOUT The EB7851 EB7851 requires analog +5 V and 5 V (designated +A5 and A5 on the board), digital +3.3 or +5 V for output (designated +D3/5 on the board), and a +3.3 V analog supply for SPT7851 SPT7851 operation (designated +A3 on the board). This evaluation board has four layers: two signal layers (top and bottom layers), one ground plane layer (both analog and digital) and one power layer that accommodates all power distribution including all post-power supply filtered power. The ordering of the layers is as follows: the top is the signal layer (used for critical signals requiring controlled impedance), the second is ground, third is power and bottom is signal. The signal layers are designed with a controlled characteristic impedance of 50 ohms. Figures 7, 8, 9 and 10 show the actual layout for the EB7851 EB7851. The +A5 and A5 supply the input buffer operational amplifiers, reference circuits, clock generator comparator and reference generation device (+4.7 V reference). The +D3/5 digital supply provides for two logic levels on the digital output. The +A3 supplies the internal circuit operation of the SPT7851 SPT7851. Power supply connection points are labeled for operator convenience. Before connecting any power supply to the evaluation board, set the supply to the correct value and power off. Ensure that all power supplies are connected and preset before full power is applied. Figure 1 shows the proper connection of the power supplies. After powerup, verify that the supply voltages are within specification before proceeding. (Refer to table I.) Make any necessary adjustments, referencing your measuring instrument to the appropriate return node. SPT REFERENCE CIRCUITS The common on-board reference voltage is established from a TK11247B TK11247B (+4.7 V reference, low drop out). This reference voltage is used to set the SPT7851 SPT7851's reference ladder voltages via U3 with the adjustments of potentiometers R1 and R2. Nominal voltage for the reference is +1 V (low reference, VREF) and +2 V (high reference, VREF+). Adjust R1 and monitor the VRN test point to set the VREF. Adjust R2 and monitor the VRP test point to set the VREF+. This evaluation board is designed to limit the reference voltages so as not to exceed specifications during normal operation. AN7851 AN7851 2 11/30/99 The range for VREF+ is from +1.5 to +2.5 V, and the range for VREF is from +0.5 to +1.5 V on this evaluation board. The recommended minimum delta between VREF+ and VREF is 0.6 V, with the maximum delta of 1.6 V. Adjust the current for Bias 1 by measuring the voltage drop across R17 using test points B1P and B1N. Calculate the current, using the measured voltage and the specified resistance. Adjust as necessary. The analog input full scale voltage range (FSR) is a function of the delta voltage between the VREF+ and VREF. Adjust the current for Bias 2 by measuring the voltage drop across R16 using test points B2P and B2N. Calculate the current, using the measured voltage and the specified resistance. Adjust as necessary. Note that U3, an OP291 OP291, is supplied only from a +5 V supply. This technique is used to ensure that the reference ladder never goes negative at power up and that the reference voltage potentials are always positive. Figure 3 Bias 1 Voltage vs Bias 1 Current 3.4 BIAS CIRCUITS 3.2 The best AC performance is achieved when the bias currents are optimized for the selected sample rate. Figure 2 shows the settings for Bias 1 and Bias 2 at selected frequencies. VBias1 (V) 3.0 Figure 2 Suggested Bias Currents vs Sample Rate 90 2.8 Bias 1 30 60 90 120 150 2.6 2.4 80 Bias 1 (µA) 2.2 VBias 1 2.19 2.53 2.79 3 3.22 Bias Current (µA) 70 2.0 60 S 1 MHz 5 MHz 10 MHz 20 MHz 50 40 30 Bias 1 30 µA 50 µA 70 µA 90 µA 0 Bias 2 3.0 µA 6.0 µA 7.5 µA 9.5 µA 30 60 90 120 150 180 IBias1 (µA) Figure 4 Bias 2 Voltage vs Bias 2 Current 20 0.90 Bias 2 (µA) 10 0.85 0 5 10 15 20 VBias 2 (V) 0 Sample Rate (MHz) It is critical to measure the bias voltage across the specified resistor and not at the bias pin on the device since the bias voltage changes as the bias current changes. Figures 3 and 4 show the relationship between the bias current and the bias voltage. 0.80 IBias 2 3 6 9 12 15 0.75 0.70 VBias 2 0.6975 0.7535 0.796 0.8295 0.8595 0.65 0.60 0 3 6 9 12 15 18 IBias 2 (µA) SPT AN7851 AN7851 3 11/30/99 ANALOG INPUTS Analog input signals required for the SPT7851 SPT7851 are differential video input signals presented to the VIN+ and VIN pins. The differential video input signals may be applied from either one of two input circuits. The first is a single-ended to differential RF transformer, and the second is through an op-amp circuit that takes a single-ended input and creates a differential analog input signal for the SPT7851 SPT7851. The transformer circuit consists of a mini-circuit T1-6T RF transformer (1:1, with center tap), center-tapped secondary with a 1 dB passband from approximately 50 kHz to 300 MHz. In this design, the differential output is loaded to a 50 ohm load, reflecting this back to the primary for impedance matching and maximum power transfer. In addition, there is a 180-degree phase inversion from the input at the RF-In to the differential input to the SPT7851 SPT7851. Ensure that J1 and J2 are jumpered appropriately when using the transformer input as the signal source. The center tap of the RF transformer is driven by the VCM output pin of the SPT7851 SPT7851. VCM is typically one-half of VDD, which translates to 1.5 V nominal on the EB7851 EB7851. The maximum input signal allowed at RF-In is 2 V peakto-peak. The Video-In signal source is processed by two op-amps (OPA642 OPA642, U6 and U7) to create the differential input signal. The offset voltage required for the common mode is generated by U5 (OP191 OP191). The operation of the two operational amplifiers is as follows. Selection criteria of buffer op-amps are as follows: - Dynamic Range (open loop gain of >75 dB) - Gain Bandwidth >50 MHz - THD 75 dB The VIN+ buffer operates as follows. The Video-In signal is applied through a BNC connector terminated to 50 ohms Thevenin equivalent. The common mode voltage biases the level of the inverting input to maintain CM. The input is resistor divided by two and applied to the noninverting input. The amplifier is designed to produce a gain of two. The result of this inputs a signal that is of the same amplitude and in phase with the single-ended input signal. The VIN buffer operates as follows. The Video-In signal is applied through an BNC connector terminated to 50 ohms Thevenin equivalent. The common mode voltage is summed into the inverting input of U7, while the SPT noninverting input is referenced to analog ground, with the input and feedback resistors the same. The result of the output is the algebraic sum of the input voltages (VIN and Common Mode). The common mode voltage sets the mid-scale value. The results of this amplifier signal are of the same amplitude and out-of-phase with the single-ended input signal. The output of the amplifiers directly feeds the input of its respective side. In addition, clamping diodes (D14, SB101B SB101B) are designed in to ensure that the input levels at powerup and during any other anomalistic occurrence do not exceed the limit specification for the input to this device. A monitoring test point is designed into the PCB for direct observation of the signals into the SPT7851 SPT7851. SPT recommends appropriate bandpass filters on the input when performing AC characterization of this part. COMMON MODE VOLTAGE CIRCUIT The SPT7851 SPT7851 has an on-board common mode voltage reference. It is typically one-half of VDD and is capable of driving up to 20 µA. It is used for either one of two purposes on the EB7851 EB7851. One use is to drive the center tap of the RF transformer at the RF-In connection. The second use is to provide level shifting for the single-to-differential converter present at the Video-In connection. CLOCK CIRCUIT SPT recommends a 50% clock duty cycle, ±3%. Onboard clock drive is performed by a TTL comparator. The comparator's reference is set by a variable DC voltage input to the inverting input. The drive signal is assumed to be a sinusoid signal; however, any modified signal with correct clock pulse width high and low is allowed. The compare level is between ±1 V. When using a sinusoid input, be sure not to allow the compare level to reach the crest of the signal as this may cause serious jitter problems at the output of the comparator. (A slow slew rate will cause this with any comparator.) However, the drive signal is capable of exceeding these comparator levels, up to a maximum value of ±2.5 V. The output of the TTL comparator goes to a 74LVX00 74LVX00 NAND gate. This device acts as a level translator accepting the TTL (0 to 5 V) levels from the output of the comparator and producing the 0 to +3.3 V drive levels for the SPT7851 SPT7851. Ensure the clock source signal is capable of driving a 50 ohm load. If not, remove or modify the input termination resistor (R36) to accommodate the user's drive circuit. AN7851 AN7851 4 11/30/99 DIGITAL OUTPUT Figure 5 Clock to Output Delay vs VDD The SPT7851 SPT7851 output is a 3.3 V logic level. Voltage translator ICs were used to accept this logic level and support either +3.3 or +5 V logic levels on the output. To accommodate either output, adjust the +3.3/5 V power supply. Digital buffers U9 and U10 on the EB7851 EB7851 can operate at either voltage. Refer to figure 6 for the J1 connector pinout. Clock to Output Delay (ns) 10.0 Data buffers are furnished with the EB7851 EB7851. The user will furnish required latch and/or data storage circuitry external to the EB7851 EB7851. Note that series damping resistors (value of 51 ohms) are in series with the output of the SP7851 SP7851 and J1 outputs to reduce oscillation when there would be a mismatch of impedance, long signal or cable lengths from the output of the EB7851 EB7851 to the user's receiver circuit. These may be modified or replaced with zero ohm resistors as the user's application requires. 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 2.5 2.8 3.1 3.4 3.7 VDD The clock to output delay is typically 9 ns. This parameter will change as a function of VDD. Figure 5 shows this relationship. SPT AN7851 AN7851 5 11/30/99 CONTROL OPTIONS AND TEST POINTS Table II outlines the names, use and intent of the jumpers, test points and control potentiometers. Table II Jumper Descriptions Name Description Intended Use R1 Potentiometer Adjust the VREF value. (Range between +0.5 and +1.5.) R2 Potentiometer Adjust the VREF+ value. (Range between +1.5 and +2.5.) R3 Potentiometer Adjust the threshold for the clock comparator. (Range from + to 1 V.) R4 Potentiometer Adjust the Bias 1 input current (typical value of 90 µA, for 20 MSPS). Measured voltage across R17 (4.75 k) will determine the current. R5 Potentiometer Adjust the Bias 2 input current (typical value of 9.5 µA, for 20 MSPS). Measured voltage across R16 (100 k) will determine the current. +R4.7 Test Point Measure the regulated +4.7 V reference device. Vrp Test Point Measure the voltage high reference input to the DUT. Vrn Test Point Measure the voltage low reference input to the DUT. B1P/B1N Test Points Used together to measure the voltage across the resistor feeding the Bias 1 current input. Used to determine the input current. B2P/B2N Test Points Used together to measure the voltage across the resistor feeding the Bias 2 current input. Used to determine the input current. +CM Test Point Used to measure the common mode voltage that is sourced from the common mode output of the DUT. CM Test Point Used to measure the offset voltage (common mode) that will be applied to the dual op-amp buffers to create the differential input to the DUT. VP (PTP2) Test Point Oscilloscope probe test point with short ground connection to accurately measure the positive input signal. VN (PTP3) Test Point Oscilloscope probe test point with short ground connection to accurately measure the negative input signal. J1 Jumper Pins Allows selection of the transformer (inverted input) or buffered analog input signal to VIN+. J2 Jumper Pins Allows selection of the transformer (inverted input) or buffered analog input signal to VIN+. SETUP AND CALIBRATION The setup and calibration operation involves setting power supplies, connecting and powering up, establishing the desired reference voltages, setting Bias 1 and Bias 2, setting up and verifying sample clock operation and verifying functional operation of the output of the EB7851 EB7851. The following setup assumes video input is used for test. 1) Power supplies: Disconnect the power supplies from the EB7851 EB7851. Set power supplies per table I. Turn off the supplies and connect the power supplies to the evaluation board. Turn on all power supplies simultaneously. 2) Reference: Adjust R1 while monitoring the VRP test point and set it to +2 ±0.005 V. Adjust R2 while monitoring the VRN test point and set it to +1 ±0.005 V. Adjust Bias 1 (potentiometer R4) to produce a voltage reading across B1P and B1N to 0.427 ±0.001 V. Adjust Bias 2 (potentiometer R5) to produce a voltage reading across B2P and B2N to 0.95 ±0.001 V. SPT 3) Sample Clock: Set the user-provided TTL or sine wave clock. Ensure that the clock frequency and duty cycle are within the part's specification. Connect the clock to the CLK IN, BNC connector on the evaluation board. 4) Analog Input: Set up a 1 VP-P, symmetrical around ground, 1 MHz sine wave signal. Connect this signal to Video-In. Jumper J1 and J2 to section B. 5) Digital Output: If you don't have a digital capture system for processing and observing data, use an oscilloscope or logic analyzer to observe the digital encoded data of the analog input signal. Another option is to purchase the EB9713 EB9713 board (the board features the SPT9713 SPT9713, a 100 MWPS TTL DAC) that mates up easily with the EB7851 EB7851. This board may be used for reconstruction of the encoded data for spectral analysis. AN7851 AN7851 6 11/30/99 Figure 6 Detailed Schematic, EB7851 EB7851 Rev B SPT AN7851 AN7851 7 11/30/99 Table III Bill of Materials No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Reference C1,4,13,24,26,27, 29,32,45,50 53-> C2,3,5,9-11,14,15 20-23,25,28,30,31 34-40,43,44,46,51,52 C16-18 C16-18 C19 C33,54-57 C41,42,47,48 C58,59 D1-4 FB1,3,4 J3-5 J1,7,8 J9-12 J9-12,14,15 P1 R1-3 R4,5 R6-8,10,16 R9 R11 R12,13,22 R14 R17 R18,36 R19,20 R21 R23,25,29-31 R24,26 R27 R28,33 R32 R34,35 RP3-4 T1 TP1,3-12,14,16-19 U1 U2 U3 U4 U5 U6,7 U8 U9,10 N/A N/A N/A N/A EB7851 EB7851 Part Number ECS-T1CY475R ECS-T1CY475R Description 4.7 µF Tantalum Chip Cap Qty 11 Manufacturer Panasonic/Any per assy dwg ECU-V1H103KBM ECU-V1H103KBM .01 µF Chip Cap 28 Panasonic/Any ECU-S2A150JCA ECU-S2A150JCA ECU-S2A680JCA ECU-S2A680JCA ECU-V1H102KBM ECU-V1H102KBM ECS-T1CX106R ECS-T1CX106R ECS-T1CX106R ECS-T1CX106R SD101B SD101B EXC-ELSA35 EXC-ELSA35 PZC36SAAN PZC36SAAN (Note 2) 31-5329 108-0740-001 PZC36DBAN PZC36DBAN 3266W-1-102 3266W-1-504 ERJ-8ENF1003 ERJ-8ENF1003 ERJ-8ENF5110 ERJ-8ENF5110 ERJ-8ENF2211 ERJ-8ENF2211 ERJ-8ENF22R1 ERJ-8ENF22R1 ERJ-8ENF33R2 ERJ-8ENF33R2 ERJ-8ENF4751 ERJ-8ENF4751 51 MF 1.0M MF ERJ-8ENF4753 ERJ-8ENF4753 ERJ-8ENF4750 ERJ-8ENF4750 ERJ-8ENF1000 ERJ-8ENF1000 75 MF ERJ08ENF49R9 ERJ08ENF49R9 ERJ-8ENF2000 ERJ-8ENF2000 ERJ-8ENF2001 ERJ-8ENF2001 760-3-R51 760-3-R51 T1-6T (KK81) 40F6045 40F6045 SPT7851 SPT7851 TK11247B TK11247B OP291GP OP291GP TC74LVX00FN TC74LVX00FN OP191GP OP191GP OPA642P OPA642P MAX9686CPA MAX9686CPA 74LVXC3245DW 74LVXC3245DW 1902EK-ND 1902EK-ND (Note 1) H143-ND H143-ND (Note 1) ED5044-ND ED5044-ND 929955-06 Rev B 15 pF Radial Cap (Socketed) 3 68 pF Radial Cap (Socketed) 1 1000 pF Chip Cap 5 10 µF Tantalum Chip Cap 4 10 µF Tantalum Chip Cap (per assy dwg) 2 Schottky Diode 4 Ferrite Bead 3 Jumper, 2 Pin (Trim from 36-pin) 3 Board Mount BNC 3 Banana Jack 6 72 Pin Horiz Male Conn (Trim to 40-Pin) 1 1 k Variable Resistor (Pot) 3 500 k Variable Resistor (Pot) 2 100 k 1/8 W 1% Chip Resistor 5 511 Ohm 1/8 W 1% Chip Resistor 1 2.21 k 1/8 W 1% Chip Resistor 1 22.1 Ohm 1/8 W 1% Chip Resistor 3 33.2 Ohm 1/8 W 1% Chip Resistor 1 4.75 k 1/8 W 1% Chip Resistor 1 51 Ohm 1/4 W 1% Axial (Socketed) 2 1.0M 1/4 W 1% Axial (Socketed) 2 475 k 1/8 W 1% Chip Resistor 1 475 Ohm 1/8 W 1% Chip Resistor 5 100 Ohm 1/8 W 1% Chip Resistor 2 75 Ohm 1/4 W 1% Axial (Socketed) 1 49.9 Ohm 1/8 W 1% Chip Resistor 2 200 Ohm 1/8 W 1% Chip Resistor 1 2.0 k 1/8 W 1% Chip Resistor 2 51 Ohm 7-Res DIP Array 2 RF Transformer 1 Solder Terminal 16 10-Bit 20 MSPS ADC 1 Volt Regulator With On/Off 1 Dual R-R Op Amp 1 Low Volt Quad NAND Gate 1 R-R Op Amp 1 Low Distortion Op Amp 2 Fast TTL Output Comparator 1 Octal Bus Transceiver 2 1" Nylon Spacer 4 4-40 Pan-Head Screw 4 Pin Receptacle (for socketed parts) 18 Shunt for Jumper 3 Evaluation Board 1 Panasonic/Any Panasonic/Any Panasonic/Any Panasonic/Any Panasonic/Any Liteon/Any Panasonic Sullins Amphenol Johnson Sullins Bourns Bourns Panasonic/Any Panasonic/Any Panasonic/Any Panasonic/Any Panasonic/Any Panasonic/Any Yageo/Any Yageo/Any Panasonic/Any Panasonic/Any Panasonic/Any Yageo/Any Panasonic/Any Panasonic/Any Panasonic/Any CTS/Any Mini-Circuits Newark SPT Toko Analog Devices Toshiba Analog Devices Burr-Brown Maxim Texas Instruments Digi-Key Digi-Key Digi-Key 3M (Digi-Key) SAS Circuits Note 1: Mount in four corners as bottom side legs. Note 2: Mount J5 on bottom side of board. DIGI-KEY is a recommended vendor, as they would have most of these parts. Contact ritchie@spt.com for a listing (give fax #). SPT AN7851 AN7851 8 11/30/99 Figure 7 Component Side EB7851 EB7851 SPT AN7851 AN7851 9 11/30/99 Figure 8 Ground Layer SPT AN7851 AN7851 10 11/30/99 Figure 9 Power Layer SPT AN7851 AN7851 11 11/30/99 Figure 10 Solder Side SPT AN7851 AN7851 12 11/30/99