AN7830 SPT7830 EB7830 74VHC595 VHC04 74LVXC4245 74VHC161 74VHC74 OP191 VHC74

SPT AN7830 AN7830 EVALUATION BOARD SIGNAL PROCESSING TECHNOLOGIES FEATURES APPLICATIONS · · · · · · · · · · 10-Bit Resolution 1 kSPS to 2.5 MSPS Conversion Rate On-Board Reference Driver Clock Driver Serial-to-Parallel Conversion On-Board 3.3 or 5.0 V Logic Family Operation Evaluation of SPT7830 SPT7830 Engineering System Guide Guide for Design of SPT7830 SPT7830 Interface Circuitry Guide for Design of SPT7830 SPT7830 PCB Layout GENERAL DESCRIPTION The EB7830 EB7830 is designed to cover a wide variety of applications but can also be greatly simplified to suit a specific application. Contact the SPT Applications Engineering department if assistance is required. The EB7830 EB7830 is intended to be used as a tool for evaluation and characterization of the SPT7830 SPT7830 (10-bit, 2.5 MSPS serial output ADC). This application note describes the function and operation of the EB7830 EB7830 evaluation board and is a supplement to the SPT7830 SPT7830 data sheet. BLOCK DIAGRAM Serial/Parallel VIN Level Shift/ Buffer CS 10 11 (2X 74VHC595 74VHC595) 11 /Q VHC04 VHC04 D D-F/F - CLK Comp 11 TC Connector (3.3 V/5 V Dig. Out) A=+2 VIN 10 Connector (5 V Logic Dig. Output) SO 3.3 V or 5 V to 5 V Translator (2X 74LVXC4245 74LVXC4245) SPT7830 SPT7830 Latches VREF Buffer 2X8-Bit Shift Resistor Reference Circuit ANALOG /PE 4-Bit Counter (74VHC161 74VHC161) (74VHC74 74VHC74) + Data 4 3.3 V or 5 V Logics +5 V ±5 RTN 5 V Logic (0001) -D5 -5 V +3.3 V DGND FB -A5 FB DGND FB AGND FB +D5 FB FB +A5 FB 5 V Logic +3.3/5 V ±3.3/5 RTN Signal Processing Technologies, Inc. 4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 VOLTAGE REFERENCES ON-BOARD TIMING SIGNAL GENERATION The EB7830 EB7830 includes an on-board voltage reference for driving the top of the reference ladder of the SPT7830 SPT7830 (pin 1). A 1.2 V on-board reference is developed by using diode CR1. (Refer to the detailed schematic in figure 3.) U2 (OP191 OP191) is a rail-to-rail op amp and is configured with a gain of 4. The reference output from U2 can be adjusted using R2. The range of adjustment is 0 to 4.8 V. The maximum input rating for Ref+ on the SPT7830 SPT7830 is 2/3 * VDD. Care should be taken not to exceed the maximum value of Ref+ which is +3.3 V when VDD = +5 V and +2.2 V when VDD = +3.3 V. U6, U7 and U8 generate the required timing signals including generation of the SPT7830 SPT7830 Start Convert signal and serial clock; and the clock for the serial-to-parallel converters U9 and U10. U6 (VHC04 VHC04) in hex inverter, U7 (VHC74 VHC74) is a dual D flip-flop and U8 (VHC161 VHC161) is a synchronous binary counter. The jumpers D0 - D3 are for loading the binary starting count value into U8. The EB7830 EB7830 ships with a jumper on D1 to D3 and none on D0. This setup allows the ADC to convert every 15 clock cycles. U9 and U10 (VHC595 VHC595) are 8-bit shift registers with output latch. They provide serial-to-parallel conversion of the SPT7830 SPT7830 serial output data. All of the National VHC family can operate from 2 V to 5.5 V power supplies. For a detailed timing diagram of the EB7830 EB7830, refer to figure 1. (Refer to the SPT7830 SPT7830 data sheet for detailed timing and modes of operation for the SPT7830 SPT7830.) The EB7830 EB7830 is shipped configured for +5 V operation such that VRef+ = +3.3 V. When a VDD of +3.3 V is used, the VRef+ must be readjusted down to a maximum of +2.2 V. To avoid exceeding the absolute maximum rating of the SPT7830 SPT7830, the jumper JP1 should be removed before powering up with VDD = +3.3 V. With JP1 removed, readjust R2 for the proper value of VRef+ as seen on the R7 side at JP1. Once the proper value of VRef+ has been established, reinstall JP1. (Refer to the Set-Up and Calibration section for proper procedures.) The bottom of the SPT7830 SPT7830 reference ladder (pin Ref-) is normally tied to AGND using jumper JP3. PARALLEL OUTPUTS The parallel data and clock output from U9 and U10 are brought out through P1. The SPT7830 SPT7830 can operate at either +3.3 V or +5 V supply levels. The P1 connector provides for parallel output of the data at either +3.3 V or +5 V logic depending on the supply voltage level used for the +3.3/5 V power supply input pin. The parallel output data from U9 and U10 is then translated into a +5 V logic family operation through U11 and U12 (LVXC4245 LVXC4245 8-bit, dual supply, configurable voltage, interface transceivers.) The P2 connector provides for parallel output of the data at the +5 V logic level regardless of which supply level is used for the +3.3/5 V power supply input pin. External references for the top and bottom of the SPT7830 SPT7830 reference ladder may be applied through test points REF and NREF. An external VRef+ can be applied through the REF test point by removing jumper JP1 and installing JP2. An external VRef- can be applied through the NREF test point by installing jumper JP2. The Ref+ pin is decoupled using capacitors C8 and C9 and the Ref- pin is decoupled using C45. ANALOG INPUTS U3 provides the required common mode offset. VOS should be adjusted to (VRef+ - VRef-)/2 using R3. This will give U4 an offset to level shift the analog input to accommodate the SPT7830 SPT7830 required common mode input. The analog input at VIN should be symmetric about zero. D1 and R50 provide for negative voltage limiting of the input. Test point VIN is provided at the output of U4. OPTIONAL RECONSTRUCTION DAC CLOCK DRIVER CIRCUIT REQUIRED POWER SUPPLIES U5 (MAX9686 MAX9686 comparator) is the clock input driver for the board. The clock input should be a sinewave between ±1 V and ±2 V and should not exceed ±2.5 V. The clock duty cycle can be adjusted by R1. The SPT7830 SPT7830 and U6 - U10 are capable of +3.3 V or +5.0 V operation. For correct clock input level, R23 (100 ) should be installed when operating in +3.3 V mode and removed when operating in +5.0 V mode. Note: R23 is not shipped with the EB7830 EB7830 board. The EB7830 EB7830 requires three power supplies: 1) An analog +5 V supply that is applied to the reference circuit and input buffer (U2, U3 and U4), 2) A digital +5 V supply that is applied to the clock buffer (U5) and P2 parallel output logic (U11 and U12), and 3) Either a +3.3 V or +5 V supply (depending on the desired SPT7830 SPT7830 logic family operation), that is applied to the SPT7830 SPT7830 (U1), timing generation circuitry and serialto-parallel converters (U6 - U10). Figure 2 shows the external power supply connections to the EB7830 EB7830. SPT When a reconstructed analog signal is desired, an optional reconstruction DAC board is available from SPT. The EB9713 EB9713 is an evaluation board for the SPT9713 SPT9713 12-bit, 100 MHz TTL DAC. It has appropriate buffers, a SPT9713 SPT9713 DAC and analog output BNC connector on board.The EB9713 EB9713 can be connected directly into the EB7830 EB7830 via P2 connector. 2 AN7830 AN7830 5/1/96 +3.3 V DATA OUTPUT LOGICAL OPERATION Before applying power, remove jumper JP1. SET-UP AND CALIBRATION All voltage measurements are referenced to analog ground AGND. First select the desired logic operation voltage level of either +3.3 V or +5 V. 1) Top reference ladder voltage adjustment: With JP1 REMOVED, power up the board and adjust R2 for +2.2 V at JP1 (R7 side). Install jumper JP1. Verify that jumper JP3 is installed. +5 V DATA OUTPUT LOGICAL OPERATION 1) Top reference ladder voltage adjustment: With JP1 installed, power up the board and adjust R2 for +3.3 V at test point REF. Verify that jumper JP3 is installed. 2) Input level shift adjustment: Adjust R3 for a voltage of +2.2/2 = +1.1 V at test point VOS. Install R23 (100 ) (not shipped with EB7830 EB7830 board.) 2) Input level shift adjustment: Adjust R3 for a voltage of +3.3/2 = +1.65 V at test point VOS. Verify that R23 (100 ) is NOT installed. 3) Clock duty cycle adjustment: Adjust R1 for 0 V at U5, pin 3. This will give a 50% duty cycle for an external sinewave clock input of ±1 to ±2 V. 3) Clock duty cycle adjustment: Adjust R1 for 0 V at U5, pin 3. This will give a 50% duty cycle for an external sinewave clock input of ±1 to ±2 V. Figure 1 - Timing Diagram 10 ns CNTR CLK 14 CLK/SCK (40 MHz) 14 1 X 2 3 1 2 4 3 5 4 6 5 7 8 6 7 C8 C7 9 8 10 9 11 10 12 11 13 12 14 13 L 14 TRI-STATE SO CNTR OUTPUT L B0 14 C9 Binary 15 Binary 1 Binary 2 Binary 3 Binary 4 Binary 5 Binary 6 Binary 7 C6 Binary 8 Binary 9 C5 Binary 10 C4 Binary 11 C3 Binary 12 C2 Binary 13 C1 X 1 TRI-STATE C0 Binary 14 1 Binary 15 Binary 1 Binary 2 TC /PE P. Load RCK /CS VHC595 VHC595 Parallel output A B C Figure 2 - Power Supplies Power Supplies +5 V +5 V + + +5 ±5 RTN VIN VIN Source SPT -5 +3.3/ +5 V + +3.3/5 RTN +3.3/5 V CLK Sinewave Generator ±1 V to ±2 V 3 AN7830 AN7830 5/1/96 +A5 -A5 VOS + 51 3 2 750 2 k R1 51 R21 -D5 + - JP2 6 C2 D1 C45 6 68 X9 MA 4 1 6 AG2 +D5 -D5 C30 7 8 U1 C10 10 k R6 C9 + 10 k R2 VCC 8 R23 8 7 100 FB6 5 14 /PR2 GND Q2 VHC74 VHC74 2 3 2 1 D2 CK2 4 C33 5 C32 U6 10 8 7 15 6 9 R55 RCK C15 16 CP 1 C18 2 /MR R16 +3.3/5 V 13 4 11 R54 VCC 12 3 12 /CLR2 11 CK1 /PR1 U7 10 4 CLK 1 13 C34 SCK +3.3/5 V R24 C14 +3.3/5 V R51 FB7 VZ /CLR1 9 CR1 ICL8069 ICL8069 Q1 /Q1 6 2 k (1.2 V) TC VCC S1 RESET 100 R52 47 /CS /SC 5 GND SPT7830 SPT7830 Ref- R31 4 CLK 6 2 V IN 3 SO 7 Ref+ 1 2 C1 10 9 R26 6 TC 47 3 13 VCC Qa SER /G RCK SCK 10 +3.3/5V +3.3/5 V 5 6 U9 8 7 NPE Qb Qc Qd Qe Qf Qg Qh GND Qb Qc Qd Qe Qf Qg Qh GND 3 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 2 +3.3/5 V U10 VHC595 VHC595 /SCLR Q'h VCC Qa SER /G RCK SCK 7 VHC595 VHC595 /SCLR Q'h 4 C35 16 15 14 13 12 11 10 9 16 X C36 15 14 13 12 11 1 k 1 k 1 k 1 k 4 9 10 5 11 12 U8 8 9 R32 C16 +3.3/5 V 14 P0 +3.3/5 V 1K 47 R53 REF 30 k R7 1 U2 4 OP 19 7 NREF JP3 U5 5 C13 51 R50 C31 3 2 AG1 R15 X C41 C12 C11 6 JP1 22 R10 2 k R3 D1 P1 R19 R18 R17 1) X = 0.01 µF chip cap to DGND 2) R24-27 R24-27, C14-16 C14-16,C18 were not installed 3) S1 was not installed +D5 4 7 750 7 22 1 LT U4 C6 R9 R13 20 k -A5 +A5 + - R12 C5 22 6 R14 R22 R11 C4 7 R8 20 k R5 Q0 NOTES: CLOCK VIN C3 4 U3 2 - 820 C8 3 820 X + C7 X X +3.3/5 V +A5 P2 D1 P1 Q2 X +3.3/5 V P3 CEP D2 X +3.3/5 V Q3 GND D0 X 4 100 CET D3 + Vcc R60 +5 V + +A5 DG1 RP1 R61 C20 1 FB1 VIN GND Q1 + +D5 C21 RP2 R63 R62 DG2 10 9 8 7 6 5 4 3 2 1 FB2 VHC04 VHC04 +3.3/5 V DG3 ±5 RTN AGND +3.3/5 V X C38 U11 GND A7 17 B4 18 B3 2 3 4 C22 + VCCA T/NR A0 A1 A2 A3 A4 A5 A6 A7 GND -A5 U12 24 VCCB 23 NC 22 /OE 21 B0 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 -5 V 10 RP3 + C23 -D5 X C39 1 2 3 4 5 6 7 8 9 R66 X C40 11 R64 R65 5 MSB 6 7 8 9 VCCA 1 T/NR A0 A1 A2 11 10 LVXC4245 LVXC4245 12 13 GND GND VCCB 23 NC 22 /OE 21 B0 20 B1 A3 A5 A4 16 B5 19 B2 A6 15 B6 14 B7 LVXC4245 LVXC4245 12 13 GND GND X 24 C37 FB8 -07 SER FB3 R27 /PE FB4 - + SPT OP +D5V +3.3/5 V C24 + +3.3/5 V +D5 +D5 -A5 +A5 FB5 3 +A5 P2 40 38 39 34 35 31 30 32 33 36 37 27 26 28 29 22 23 21 20 24 25 18 12 10 8 6 4 13 11 9 7 5 3 +3.3/5 RTN DGND 2 14 15 1 16 17 19 Figure 3 - EB7830 EB7830 Detailed Schematic, Rev A +D5 V VHC161 VHC161 R20 R25 /Q2 AN7830 AN7830 5/1/96