AN7275 CDP1879 CDP1879C1 CDP6805 Z-80TM 8085/NSC800 CDP1802 CDP1872 CDP1802A - Datasheet Archive

 

No. AN7275.1 Harris Digital March 1997 User's Guide to the CDP1879 and CDP1879C1 CMOS Real-Time Clocks Author: D. Derkach

 

Harris Semiconductor No. AN7275 AN7275.1 Harris Digital March 1997 User's Guide to the CDP1879 CDP1879 and CDP1879C1 CDP1879C1 CMOS Real-Time Clocks Author: D. Derkach Introduction The CDP1879 CDP1879 and CDP1879C1 CDP1879C1 Real-Time Clocks [1] are 24 pin devices, each consisting essentially of a long string of counters that supply standard clock time and date information in BCD format, Figure 1. In addition, the CDP1879 CDP1879 features an alarm circuit that activates the interrupt output pin and a separate clock output pin that provides a programmable square-wave output signal. Both the internal-alarm and clock-out signals can trigger the interrupt output pin, so that a status register is available to indicate the interrupt source. Users can supply a signal to the power-down pin that allows the interrupt-output pin level to control external power-down and wake-up circuits. Software generally required by other real-time clocks to prevent clock rollover is eliminated by a transparent "freeze" circuit that assures data integrity when accessing the clock. The clock's counters, plus a control register that regulates operation, are individually selectable using three address lines. Internal control signals governing read and write operations are selected through the IO/MEM pin, which places the device in a memory-mapped or I/O-mapped mode of operation. The real time clocks were designed using Harris PaCMOS standard-cell approach and are manufactured under a silicon-gate CMOS process. Both the CDP1879 CDP1879 and CDP1879C1 CDP1879C1 have guaranteed dc and dynamic parameters that allow operation at temperatures of -40oC to +85oC in a plastic package. In addition, both versions can operate in a ceramic package from -55oC to 125oC (see data sheet [1] for complete static and dynamic values). labels on the clocks, Figure 2, match the pin names of these processors. Figure 3 indicates clock I/O control and direction pins; the functions of these pins are explained immediately below. Figure 4 is an I/O control and device-enabled schematic. Table 1 shows I/O pin connections. TPA (Timing Pulse A) - TPA refers to a timing signal from the CDP1800-series processors that occurs early in the machine cycle, and that is used to latch the processor's multiplexed high-order address. In the real-time clock, this pin carries a strobe input used to latch the value of the CS pin. In memory-mapped operation, the pin may be tied high, requiring that CS be held for the duration of each read or write cycle. When the I/O-mapping mode is selected, this pin must be pulsed when the CS input is high. CS (Chip Select) - The chip-select pin is an active high input that is used to enable the clock. IO/MEM (I/O or Memory-Mode Select) - This pin is tied low to place the clock in the memory-mapped mode, and high when I/O operation is desired. Most processors will use the memory-mapped mode of operation. RD (Read) - When the clock is in the memory-mapped mode, RD is an active low signal that enables data from the counters or status register to be placed on the data bus for the processor to read. When the clock is in the I/O mode, the read operation occurs when RD is high; a write operation occurs when RD is low and TPB/WR is high. The CDP1879 CDP1879 operates from a supply of 4V to 10.5V. It accepts a parallel resonant crystal or will keep time with an external clock source. Crystal frequencies are 1.048576MHz, 2.097152MHz, and 4.194304MHz. The CDP1879C1 CDP1879C1 is the lower voltage version with an operating voltage range of 4V to 6.5V. Like the CDP1879 CDP1879, it also operates with either an external clock source or at the same crystal frequencies. It can also run with a 32,768Hz crystal. TPB/WR (Timing Pulse B/Write) - TPB refers to a timing signal from the CDP1800-series processors that appears late in each machine cycle and that is used to write data into accessed peripherals. When the clock is in the memorymapped mode, TPB/WR is an active low signal used to write data into the clock's counters or control register. During I/Omapping, a high level on this pin allows data latched on the trailing edge of the signal to be written into the counters or register. Interfacing - Hardware Considerations CD1800-Series Interface I/O-Control and Device-Enable Pins The clocks interface to CDP1800-series processors that use memory-mapping and I/O-mapping techniques to communicate with peripherals and memory. Memory-mapping implies address-line decoding to select memory locations and chip selects. With this technique, the real-time The real-time clocks, shown in block diagram form in Figure 1, are designed to interface directly to Harris CDP1800series processors (described briefly below). Therefore, pin Copyright © Harris Corporation 1997 7-70 Application Note 7275 clock's counters and registers are treated as memory locations. Read and write signals are active low. The CDP1800-series processors include three separate N-lines that are active during the 14 I/O instructions. These instructions are memory referenced so that data traveling in either direction is transferred between the peripherals and memory. When I/O instructions are executed, the memory location is the reference for data transfer. Therefore, when an output instruction is performed (write cycle) the processor's RD line is activated and puts the data in memory onto the data bus. Late in the same cycle, the TPB from the processor is used to write data into the peripheral. An input instruction (read cycle) allows external data to be placed in memory. The processor's WR line is activated, and the data is written in. AM - PM AND HOUR LOGIC FREEZE CIRCUIT CALENDAR LOGIC XTAL OSCILLATOR XTAL PRESCALE PRESCALE SELECT CLOCK OUT INT RESET VDD CLOCK AND INT LOGIC SECOND MINUTE HOUR CLOCK SELECT CONTROL REGISTER 8-BIT DATA BUS COMPARATOR VSS SECOND LATCH MINUTE LATCH HOUR LATCH INT. STATUS REGISTER DB0-DB7 I/O INTERFACE A0 A1 A2 TPA IO/MEM TPB/WR ADDRESS DECODE AND CONTROL LOGIC RD CS POWER DOWN FIGURE 1. BLOCK DIAGRAM OF REAL-TIME CLOCK XTAL CONNECTIONS DATA DIRECTIONAL SIGNALS SELECTS DEVICE SELECTS OPERATIONAL MODE XTAL CLK OUT XTAL A0 TPB/WR A1 RD A2 TPA CS IO/MEM POWER DOWN SELECT PWR DOWN INITIALIZES DEVICE RESET SQUARE-WAVE OUTPUT ADDRESS INPUTS CHIP-SELECT GATE AND LATCH INT INTERRUPT OUTPUT DB0 TO DB7 BIDIRECTIONAL DATA BUS FIGURE 2. REAL-TIME-CLOCK PIN FUNCTIONS 7-71 DAY MONTH Application Note 7275 TPA CS DB0DB7 DATA BUS RD TPB/WR IO/MEM VDD FIGURE 3. I/O CONTROL AND DIRECTION PINS RD ENABLE OUTPUTS READ REGS LATCH REGS (TRAILING EDGE) IO/MEM TPB/WR DFF A0 C TPA R A1 Q A2 RESET VALID ADDRESS (SEE NOTE) Q CS NOTE: AN ADDRESS OF ZERO WILL DISABLE THE READ AND WRITE FUNCTIONS. FIGURE 4. I/O CONTROL AND DEVICE ENABLE SCHEMATIC TABLE 1. I/O PIN CONNECTIONS CDP1879 CDP1879 PIN PROCESSOR TPA CS RD TPB/WR IO/MEM Harris CDP1800-Series (Memory-Mapped) TPA (Note 1) Hi or Decoded Address MRD MWR VSS MA0, MA1, MA2 Harris CDP1800-Series (I/O mapped) TPA N or Decoded N Lines MRD TPB VDD N0, N1, N2 CDP6805 CDP6805 AS Hi or Decoded Address R/W DS VDD B0 (Note 2), B1, B2 Zilog Corp. Z-80TM Z-80TM VDD Hi or Decoded Address RD WR VSS A0, A1, A2 ALE (Note 1) Hi or Decoded Address RD WR VSS AD0 (Note 2), AD1, AD2 8085/NSC800 8085/NSC800 NOTES: 1. May be connected to VDD when CS is externally latched. 2. Latch externally. Z-80TM Z-80TM is a Trademark of Zilog Corporation. 7-72 A0-A2 Application Note 7275 Figure 5 shows a typical memory-mapped interface utilizing the CDP1802 CDP1802. This interface places the clock and countertimer in selectable 4k memory blocks. Figure 6 shows the CDP1872 CDP1872 ADDRESS LATCH CDP1802A CDP1802A TPA MA0-MA7 CDP1878 CDP1878 CD74HC154 CD74HC154 40F16 40F16 DECODER CS CLOCK MA8MA15 MA8MA15 interface of the clock to an 8085 processor, Figure 7 the interface to a CDP6805 CDP6805, and Figure 8 the interface to a Zilog Corporation Z-80. MA12MA15 MA12MA15 CD74HC240 CD74HC240 IO/MEM CS DB0-DB7 CS MA0-2 MICROPROCESSOR CS'S DUAL COUNTER-TIMER DATA BUS CDP1879 CDP1879 MA8-MA11 MA8-MA11 CS'S IO/MEM CS MA0-MA7 MEMORY MATRIX DB0-DB7 MA0-2 CD40117B CD40117B DUAL 4-BIT TERMINATOR REAL-TIME CLOCK BIDIRECTIONAL DATA BUS FIGURE 5. REAL-TIME CLOCK AND COUNTER-TIMER IN MEMORY-MAPPED INTERFACE CDP1879 CDP1879 IO/MEM A/D BUS WR TPB/WR RD RD A8 CS A0 8085 A1 TPA A2 ALE A/D BUS 8085 RD WR A8 I-O/M VDD TPA CDP1875 CDP1875 LATCH MA0 MA1 MA2 CLOCK CDP1879 CDP1879 IO/MEM RD TPB/WR A0 A1 CS A2 ALE CDP1875 CDP1875 LATCH MA0 MA1 MA2 CLOCK FIGURE 6A. MEMORY-MAPPED INTERFACE 7-73 Application Note 7275 A/D BUS VDD TPA CDP1879 CDP1879 IO/MEM WR RD RD IO/M CS ALE TPB/WR CDP1875 CDP1875 LATCH MA0 MA1 MA2 CLOCK A0 8085 A1 A2 ALE LOW ADDR. A/D BUS DATA RD/WR FIGURE 6B. I/O-MAPPED INTERFACE FIGURE 6C. TIMING CYCLES FIGURE 6. 8085 INTERFACE AND TIMING CDP1879 CDP1879 IO/MEM A/D BUS DS TPB/WR R/W A8 CS TPA LOW ADDR. A/D BUS RD 6805 AS AS VDD CDP1875 CDP1875 LATCH MA0 MA1 MA2 CLOCK A0 A1 A2 DATA R/W DS FIGURE 7A. CDP6805 CDP6805 I/O-MAPPED INTERFACE FIGURE 7B. TIMING DIAGRAM Z-80 INT CDP1879 CDP1879 INT WR TPB/WR RD RD A15 CS A0 A1 A1 A2 A2 IO/MEM A0 D0-D7 TPA VDD DB0-DB7 DATA BUS FIGURE 8. ZILOG CORPORATION Z-80 INTERFACE TO THE CDP1879 CDP1879 7-74 Application Note 7275 Timing Considerations Figures 9 and 10 show read and write-cycle timing wave forms, respectively. The read and write limits shown must be observed to successfully access the clock. Three of the characteristics, hold after read and write, and read access time, may represent critical limit values when the clock is interfaced to processors operating at their maximum frequency limit. TABLE 2. READ-CYCLE TIMING CHARACTERISTICS LIMITS (ns) READ CYCLE TIMES (NOTE 1) MINIMUM (NOTE 2) MAXIMUM 400 Data Access from Address tDA - Read Pulse Width tRD 270 - Data Access from Read tDR - 375 Address Hold After Read tRH 0 - Output Hold After Read tDH 50 230 Chip Select Setup to TPA tCS 50 - NOTES: 1. Characteristics at TA = -40oC to +85oC; VDD = 5V ±5%; Input tR, tF = 10ns; CL = 50pF and 1 TTL load. 2. Time required by a limit device to allow for the indicated function. tRH TPA tCS DATA ADDRESS/CHIP SELECT tRD READ DATA TO CPU tDR tDH tDA FIGURE 9. READ-CYCLE TIMING WAVEFORMS TABLE 3. WRITE-CYCLE TIMING CHARACTERISTICS LIMITS (ns) MINIMUM (NOTE 2) MAXIMUM Address Setup to Write WRITE CYCLE TIMES (NOTE 1) tAS 225 - Write Pulse Width tWR 150 - Data Setup to Write tDS 65 - Address Hold After Write tAH 0 - Data Hold After Write tWH 150 - Chip Select Setup to TPA tCS 50 - NOTES: 1. Characteristics at TA = -40oC to +85oC; VDD = 5V ±5%; Input tR, tF = 10ns; CL = 50pF and 1 TTL load. 2. Time required by a limit device to allow for the indicated function. tAH TPA tCS ADDRESS/CHIP SELECT tAS tWR WRITE DATA TO REAL TIME CLOCK tDS FIGURE 10. WRITE-CYCLE TIMING WAVEFORMS 7-75 tWH Application Note 7275 Output Hold After Read (tDH) When multiplexed bus processors, in which address and data share the same pins, are interfaced to the clock, the output-hold-after-read parameter (230ns) may cause bus contention. As an example, at 5MHz, the CDP6805 CDP6805 requires data to be off the bus within 160ns after data strobe. The 8085A operating with a 6MHz crystal requires 150ns after read. Since the clock may hold data for 230ns, bus contention may occur if these processors are interfaced to the clock at their maximum operating frequencies. Data Hold After Write (tWH) Writing to and reading from the clock is as straightforward as accessing memory. Software considerations regarding clock rollover (when the one-second clock may pulse the counters during read or write cycles) are eliminated by utilizing the freeze circuit (described below), which requires only one additional instruction. Use of the freeze circuit eliminates the software burden of looking for a signal or register bit that guarantees valid data. A write cycle with address 1 and don't -care data before any series of counter accesses (read or write cycles) assures that the one-second clock has been held and will not interfere with accesses for 250ms. The real-time clocks require that data be held after the trailing edge of the write pulse for 150ns. Neither the 8085/NSC800 8085/NSC800, Z-80, nor CDP6805 CDP6805 meet this requirement at their maximum operating frequencies. SECONDS-TO MONTHS COUNTERS PWR DWN Data Access From Read (tDR) INTERRUPT VDD The clock will supply data a maximum of 375ns from the leading edge of the read pulse. The data setup requirements for processors operating at their maximum frequencies may require faster access. ALARM LATCHES CLOCK OUT Hold and Access-Time Solutions All of the above parameters are frequency dependent. Often, simply lowering the frequency when accessing the clock will solve any timing problems. Access times can be extended by inserting wait states. Write and read-hold-time problems are more difficult to correct; glue parts, such as latches and buffers, are required to meet the requirements of these timing parameters. CLOCK OUT CONTROL REGISTER STATUS REGISTER BIDIRECTIONAL DATA BUS FIGURE 11. FUNCTIONS THAT MUST BE ACCESSED TO WRITE IN AND READ OUT TIME AND DATE INFORMATION Interfacing - Software Considerations Programming Model Freeze Circuit Figure 11 illustrates the counters, alarm latches, and registers that must be accessed to write in and read out time and date information. The functions are selected through internal decoding of three address lines. Table 4 contains the register access codes for different combinations of address inputs. Figure 12, a programming model of the same registers, shows their read and/or write availability. These address lines and data lines, in conjunction with the I/O control pins, constitute the interface to the clock. The freeze circuit is designed to allow the user easy access to the real-time clock without the fear that clock rollover will cause erroneous time data. Clock rollover problems occur during counter reads while the asynchronous one-second clock input to the counter-divider chain is rippling through the counters. When the clock is configured for memory-mapped operation, it can be considered as six memory locations that reside in an area of memory determined by the definitive decoding of the upper address bits. The clock's I/O-mapped mode utilizes the N-lines (I/O lines) and I/O instructions of the CDP1800-series processor. The processor's N-lines are decoded for use as a chip select, and in a two-level scheme, are also used as the address input signals. As an example in Figure 13A, the one-second clock is about to set the time to 0 seconds, 0 minutes and 3 hours. A read is performed, and the hours counter indicates 2 hours. But before the second and minute counters are read, the onesecond clock ripples through them, with the result that the counters hold the time shown in Figure 13B. When the seconds and minutes counters are read (Figure 13B), their values are correct, but the hours time, read before the ripple, is 1 hour off. It is apparent that this type of error can be a substantial problem, particularly if the date and month counters are involved. When other processors are interfaced to the clock, the clock will generally be placed in its memory-mapped mode. An exception is interface with the CDP6805 CDP6805, where the clock is usually wired for I/O operation. 7-76 Application Note 7275 WRITE AND READ REGISTERS SECONDS COUNTER CONTROL REGISTER MINUTES COUNTER SECONDS ALARM LATCH HOURS COUNTER MINUTES ALARM LATCH DAY OF MONTH COUNTER Operation WRITE ONLY REGISTERS HOURS ALARM LATCH The counter-series string is clocked by the negative transition of the one-second clock. This clock transition must pass through the freeze circuit before toggling the counterseries string, as shown in Figure 14. The freeze circuit creates a "window" 250ms wide shown as time (A) in Figure 15. If the counter reads or writes (for addresses other than address 7) are performed during this window, the clock transition is held and is not allowed through the freeze circuit until time (C) Figure 15, when the transition is inserted into the counter series string. If counter accesses are initiated just before the one-second-clock transition, the clock would toggle the counters 250ms later. Therefore, a requirement when using the real-time clocks is to finish operations within 250ms of the initial access. READ ONLY REGISTERS MONTH COUNTER If the clock is accessed during time (A), Figure 15, and then accessed again at time (C), when the counter is allowed to toggle, ripple problems would occur. To preclude this problem, a second window is created by the freeze circuit during time (B). This window will allow a write to address 1 to immediately reset the freeze circuit and clock the counters. Subsequent accesses to the real-time clock will occur well after the clock has rippled through the counters. INTERRUPT STATUS REGISTER FIGURE 12. PROGRAMMER'S MODEL OF THE REGISTERS OF FIGURE 11 If read or write operations are performed during time periods other than (A) or (B), the freeze circuit is not functional. Figure 16 shows a simplified freeze circuit (a), and the sequence of freeze-circuit operation (b). TABLE 4. REGISTER TRUTH TABLE ADDRESS ACTIVE SIGNAL A2 A1 A0 TPB/WR 0 1 0 X 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 0 0 1 1 RD BIT 3 CONTROL REGISTER REGISTER OPERATION 0 Write Seconds Counter 0 Read Seconds Counter 0 Write Minutes Counter 0 Read Minutes Counter 0 Write Hours Counter 0 Read Hours Counter 0 Write Date Counter 0 Read Date Counter 0 Write Month Counter 0 Read Month Counter X 1 Write Seconds Alarm Latch 1 X 1 Write Minutes Alarm Latch 0 0 X 1 Write Hours Alarm Latch 1 1 1 X 1 1 1 X X X X X X X X X Write Control Register X 7-77 Read Int. Status Register Application Note 7275 59 02 00 00 03 SEC. MIN. HR. SEC. MIN. HR. READ 1 SECOND CLOCK 59 READ READ (A) (B) FIGURE 13. FREEZE-CIRCUIT READ EXAMPLE XTAL OR CLOCK IN OSC. PRESCALER FREEZE CKT. SEC. MIN. HR. DATE MONTH FIGURE 14. COUNTER SERIES STRING 250ms (1) 500ms 1 SECOND (2) (A) (C) (B) FIGURE 15. FREEZE-CIRCUIT TIMING WAVEFORMS READ (1) WRITE NOT ACCESSING CONTROL REGISTER 500ms 500ms 1 SECOND (2) 1Hz FROM PRESCALER 1 SECOND WRITE ADDRESS 1 1 SECOND CLOCK (3) 1 SECOND 500ms FIGURE 16. (A) SIMPLIFIED FREEZE CIRCUIT, AND (B) FREEZE-CIRCUIT OPERATION NOTES: 1. Set freeze during time period A, (one second clock is held high) 2. Reset freeze at time period C, 3. or during time period B if address 1 is present during a write cycle. Restrictions on Accuracy The data sheet for the real-time clock states that when the seconds counter is written to, the last 7 stages of the prescaler are reset, resulting in a 10ms accuracy. Normally, the seconds counter will be clocked 1 second from the time of the write to the seconds counter. However, if the freeze circuit has been activated, this sequence may not occur, there- fore, to assure the 10ms accuracy, the following procedure should be used: 1. Write to seconds counter - don't care data - address 2 2. Dummy write - don't care data - address 1 3. Write to seconds counter - valid data - address 2 7-78 Application Note 7275 The mild restrictions on accesses to the real-time clock require no additional software or hardware considerations to assure data integrity. In all other known clocks, software solutions to clock rollover problems range from reading and comparing the time data twice to sampling register values. Hardware solutions vary between stopping any internal clock updates to monitoring output-pin transitions. The addition of an address 1 write operation preceding accesses to the CDP1879 CDP1879 real-time clock in conjunction with the requirements to finish accesses in 250ms will guarantee stable and accurate time data. Register Descriptions The real-time clock contains a control register to configure its operation, and a status register to identify interrupts, five registers or counters to hold the time from seconds to months, and three additional registers that are referred to as alarm latches, which hold the alarm time. Control Register The control register is a write-only register that shares the same address as the status register, address 7. A brief explanation of the functions of the eight bits in the control register are shown in Figure 17; more detail is given in the paragraphs that follow. Bits 0 and 1 - Frequency Select - The logic levels in bits 0 and 1 are decoded and used to select the appropriate input to the last 14 stages of the prescaler chain, Figure 18. Their selection must match the crystal or external clock source used to drive the oscillator selection of the real-time clock. Bit 2 - Start/Stop - As shown in Figure 18, a 1 in bit 2 enables the input to last through 14 stages of the prescaler chain. A zero in this position inhibits counting. D7 BIT D0 7 6 5 4 3 2 1 0 SELECTS DIVIDER IN PRESCALER CHAIN ENABLES COUNTING SELECTS ONE OF 15 CLOCK OUT SIGNALS DETERMINES DATA TRANSFER TO/FROM TIME OR ALARM REG. ALSO ENABLES ALARM. FIGURE 17. CONTROL REGISTER XTAL XTAL OSCILLATOR ÷2 ÷ 16 ÷2 ÷2 ÷2 ÷ 16 ONE SECOND OUT TO SECONDS COUNTER 16kHz 32kHz BIT 0 BIT 1 DECODE 1MHz BIT 2 START/STOP 2MHz 4MHz BIT 0 0 1 0 1 BIT 1 0 0 1 1 BIT 2 32,768Hz 1.048576MHz 2.097152MHz 4.194304MHz 0 Stop Counter 1 Start Counter FIGURE 18. FREQUENCY-SELECT OPERATION Bit 3 - Counter/Latch Control - Figure 19 is a simplified diagram of the counter/alarm latch access. Bit 3 has two functions. First, if set to zero, it directs written data to the time counters. If set to 1, data is written into the alarm latches. This bit function is necessary because the time counters and their comparable alarm latches have the same addresses. The second function of bit 3 is to enable the alarm-out signal. An alarm signal (interrupt output low and bit 7 set in the status register) will only appear if this bit (bit 3) is a logic 1. Bits 4, 5, 6 and 7 - Clock Select - Figure 20 is a block diagram of the clock-out select function; Figure 21 is a table of clock-out selections. Bits 4, 5, 6, and 7 are decoded, and enable the required prescaler or time counter output to toggle the clock-out pin. Status Register The status register, Figure 22, is used to indicate the interrupt source. Bits 0 through 5 are held low. Bit 6 high indicates that a programmed negative clock-out transition has occurred, and bit 7 high identifies the alarm circuit as the interrupt source. These bits are reset by an external reset or by writing to the control register. Note, in Figure 23, the delay of approximately 30ms before the alarm signal sets bit 7. 7-79 Application Note 7275 SECONDS MINUTES HOURS DATE MONTH ADDRESS BUS IN BIT 3 IN CONTROL REGISTER SECOND ALARM LATCH MINUTE ALARM LATCH HOUR ALARM LATCH RESET SET 30H IN ALARM LATCH 3 3 COMPARATOR Q D 1Hz 16kHz DEBOUNCE LOGIC ALARM SIGNAL TO INTERRUPT OUTPUT PIN AND MSB STATUS REGISTER C FIGURE 19. SIMPLIFIED DIAGRAM OF COUNTER/ALARM LATCH ACCESS ONE SECOND TICK XTAL XTAL OSCILLATOR 22 STAGES ÷ 2 2048kHz TIME COUNTERS 488 µSEC BIT 4 5 6 7 TO CLOCK OUT AND INTERRUPT OUT PIN DECODE ONE OF 15 ENABLING SIGNALS FIGURE 20. BLOCK DIAGRAM, CLOCK-OUT SELECT 7-80 Application Note 7275 COUNTER/LATCH CONTROL CLOCK SELECT START/STOP CONTROL FREQUENCY SELECT 7 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 6 BIT 6 5 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 5 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4 3 FREQUENCY Deselect 488.2µs 976.5µs 1953.1µs 3906.2µs 7812.5µs 15.625ms 31.25ms 62.5ms 125.0ms 250.0ms 500.0ms Second Minute Hour Day 2 1 0 CLOCK-OUT WAVEFORM (1 OF 15) HIGH 12 HRS 12 HRS FIGURE 21. CLOCK-OUT SELECTIONS DATA B0 VDD D CLOCK OUT SIGNAL Q DATA B1 C READ STATUS REGISTER R 1Hz DATA B6 FF1 DATA B2 16kHz WRITE CONTROL REGISTER RESET DEBOUNCE LOGIC DATA B3 R ALARM SIGNAL ALARM SIGNAL C DATA B7 Q FF2 DATA B4 D READ STATUS REGISTER R DATA B5 INT OUT RESET OR WRITE TO CONTROL REGISTER FIGURE 22. STATUS REGISTER 16kHz 1Hz ALARM STROBE ALARM SIGNAL INT OUT RESET FIGURE 23. DEBOUNCE WAVEFORMS 7-81 READ STATUS Application Note 7275 Operating Sequence Although accessing of the clock is similar to accessing of memory, certain procedures should be followed when writing the data to assure correct operation. The control register is accessed first to set the operating characteristics and to direct subsequent accesses to the counters or alarm latches. The upper nibble of the controlregister byte selects one of 15 square-wave output signals that appear at the clock-out pin. If a clock-out is selected before the time counters are accessed and loaded, an inadvertent interrupt may be generated. To preclude this occurrence when the interrupt signal is utilized, the upper nibble of the control register byte is set to zero during the initial control-register write cycle. The time counters and/or alarm latches are then loaded. The control register is then written to again, and the value in the upper nibble selects the required clock. seconds counter would be represented as 00010010. The hours counter, however, utilizes its upper bits for AM/PM designation and 12/24-hour selection. Moreover, bit 7 in the months counter is set by the user to indicate leap year. All of these bits must be set as required in addition to the BCD hour and month information. For example, if 4 PM is written to the hours counter, a BCD code of 00000100 for the hours plus a 1 in bits 6 and 7 to enable PM and 12-hour operation would require a data byte of 11000100 (Hex C4). Procedure to Set the Time 1. Chip selected and address 7 present on the address lines to access the control register. 2. Write to control register with the required data byte. Bit 3 must be set to zero. 1. Seconds and Minutes counters and alarm latches 00 to 59 3. Use addresses 2 to 6 to access seconds-to-months counters, in any order, and load appropriate data byte. (BCD data plus bits 6 and 7 in hours counter and bit 7 in month counter.) 2. Hours counter: 01 to 12 for AM/PM 00 to 23 for 24-hour time 4. Writing to the seconds counter resets the last 7 stages of the prescaler, thereby setting an accuracy of 10ms. Data Format Required (BCD) Bit 7: 0 = AM, 1 = PM Setting the Alarm Bit 6: 0 = 24 hour, 1 = 12 hour Setting the Time Figure 24 shows the alarm logic. As previously described, bit 3 in the control register must be a 1 to direct subsequent data to the alarm latches. A comparator circuit compares the time and alarm latch seconds, minutes, and hour outputs. When this comparison is true and bit 3 in the control register is set to 1, an alarm is generated that activates the interruptout pin and sets bit 7 in the status register to a high logic level. The two most significant bits in the hours time counter are used for an AM/PM indication (User set for AM or PM with subsequent toggling every 12 hours) and to set 12/24hour operation. The time counters, from seconds to months, are accessed and written into using the procedure described below. Data entered is in BCD format. For example, 12 seconds in the If bit 6, the 12/24-hour control bit, is set to zero (24-hours), a match of bit 7 (AM/PM) between the hours time counter and alarm latch is not required to generate a true comparison. Hour alarm latch: 01 to 12 for AM/PM, 00 to 23 for 24 hour. 12 hour (AM/PM): Bit 7: 0 = AM, 1 = PM If the time counter is set for 24-hour time, bit 7 is don't care. 3. Day-of-month counter: 01 to 28, 29, 30 or 31. 4. Month counter: Jan. = 1, Dec. = 12 Bit 7: 0 = No leap year, 1 = leap year HOUR COUNTER BIT 0 1 2 3 4 5 6 7 BIT 3 CONTROL REGISTER COUNTER/LATCH CONTROL 16kHz DEBOUNCE LOGIC SECONDS, MINUTES TRUE COMPARISON BIT 0 1 ALARM TO INTERRUPT OUT AND BIT 7 IN STATUS REGISTER 2 3 4 5 X 7 HOUR ALARM LATCH FIGURE 24. ALARM LOGIC 7-82 Application Note 7275 When an alarm occurs, there is a delay of 30µs before the alarm bit is set in the status register. The interrupt-out pin signal is also delayed for this period. Additionally, if a clock out was selected that also activates the interrupt-out in coincidence with the alarm-out signal (for example, clock-out set for one second and any alarm-time set), the status register will indicate a clockout transition (bit 6 = 1) 30µs before bit 7 is set to 1 in the status register. The clock continues to keep time and there is no appreciable change in operating power. The interrupt output will go low if an alarm or clock transition (internal clock transition) occurs after power down has been initiated. An application using the power-down feature to control a microprocessor's clock signal is illustrated in Figure 26. This application is especially appealing in a CMOS circuit design where only quiescent current will be drawn when the processor's clock input is disabled. Resetting the Interrupt-Out Signal and Status Register There are two methods of resetting the interrupt-out signal and status register once an alarm or clock-out transition has occurred. POWER DOWN PIN 3 Reset Pin (Schmitt Input) CDP1879 CDP1879 D Q A low on the reset pin will accomplish the following: TO POWER DOWN CONTROL C 1. Set the interrupt-out pin high. 2. Clear the status register. READ ENABLE 3. Place 30 Hex in the hour alarm latch. This entry will prevent an inadvertent interrupt when programming the time. Control Register Write Writing to the control register sets the interrupt-out high and clears the status register. Power-Down Operation Figure 25 shows power-down input-control logic. A low on the power-down pin (Schmitt input) activates the real-timeclock's power-down function. This function is enabled at the trailing edge of a read or write signal and, therefore, power down will not occur until the read or write cycle is concluded. When power down is activated, the following events occur: 1. Read and write control signals are disabled. 2. The data bus is placed in an input condition and logic transitions are ignored. (Therefore, the bus must be terminated.) 3. The clock-out signal is set low. WRITE ENABLE FIGURE 25. POWER-DOWN INPUT-CONTROL LOGIC In an operational sequence utilizing the circuitry of Figure 26, the serial Q output of the CPU is activated after the clock is configured with an alarm time. The oscillator then stops and the device enters the power-down mode. When the alarm activates and the INT output is set low, the CPU resets and polls the EF1 flag to determine whether a cold or warm start routine is in order. The control register is then written to, an event that resets the interrupt requests. Any general-purpose microprocessor can utilize the low operating power of the real-time clock. Typical operating current with a crystal-controlled oscillator at 32kHz and 5V is 100µA, and at 4MHz, 600µA. The trade-off between high frequency and accuracy and low-frequency operation with lower power consumption must be resolved by the user. The ease of programming and the features offered by the realtime clock aid the designer and lower the level of programmed support required. 4. The interrupt-out pin is three-stated. 7-83 Application Note 7275 Power Considerations XTAL A0 A1 A2 N0 N1 N2 XTAL VDD The CDP1879 CDP1879 power requirements are shown in Table 5. The values listed are maximum limits with a VDD of ±5% and a temperature range of -40oC to 85oC. XTAL Table 6 shows output drive capabilities under the same conditions. All inputs must meet CMOS requirements with a minimum high of 3.5V and a maximum low of 1.5V at a VDD of 5V. IO/MEM CLOCK Standby Operation (Low Voltage) 1/2 CD40107 CD40107 CDP1800 CDP1800 SERIES Q When utilizing an external crystal with its on-board oscillator as the frequency source, the CDP1879 CDP1879 and CDP1879C1 CDP1879C1 can operate at a supply voltage no lower than 4 volts. However, if a 32kHz external frequency source is provided at the XTAL input pin, the clock can operate in a standby mode down to 2.5V at 0 to 70oC, and 3V at -40oC to +85oC. Figure 27 shows the typical minimum standby voltage. Figure 28 shows that the real-time clock must be disabled by CS (chipselect signal) a minimum of 2µs before reaching the standby voltage level, and enabled again after the same period of time when the voltage is raised again. CDP1879 CDP1879 RTC VDD PD VDD 1/2 CD40107 CD40107 CLEAR VDD EF1 INT BIDIRECTIONAL DATA BUS TO MEMORY FIGURE 26. APPLICATION OF REAL-TIME CLOCK THAT USES POWER-DOWN FEATURE TO CONTROL A MICROPROCESSOR'S CLOCK SIGNAL When the clock is in the standby mode, it functions only as a timekeeping device; all read/write data accesses are disallowed. TABLE 5. POWER REQUIREMENTS OF THE REAL-TIME CLOCK POWER-SUPPLY VOLTAGE MODE 10V UNITS (NOTE 1) 32kHz 0.25 - mA 0.5 3.0 mA 2MHz 0.6 3.5 mA 4MHz 0.8 5.0 mA 32kHz 0.15 0.25 mA 1MHz 1.0 2.0 mA 2MHz 1.5 3.0 mA 4MHz Operating Current with External Clock Source 5V 1MHz Operating Current with Crystal Oscillator INPUT FREQUENCY 2.0 4.5 mA NOTE: 1. CDP1879C1 CDP1879C1 Only TABLE 6. OUTPUT DRIVE CAPABILITIES POWER-SUPPLY VOLTAGE 5V 10V UNITS 1.8 3.6 mA -1.10 -2.6 mA Clock Out (Sink) 0.6 1.2 mA Clock Out (Source) -1.1 -2.6 mA Data-Bus and Interrupt-Out Drive (Sink) Data-Bus and Interrupt-Out Drive (Source) 7-84 Application Note 7275 Oscillator Operation 5 4 TYPICAL MINIMUM TIMEKEEPING (STBY) VOLTAGE 32.768kHz EXTERNAL CLOCK The CDP1879 CDP1879 operates with a crystal connected to its XTAL and XTAL inputs, or accepts an external clock source at its XTAL input that has a rise and fall time of less that 10µs. Typical oscillator parameters are listed in Table 8; suggested circuits are described in Figures 29 through 32. VDD (V) 3 2 GUARANTEED TIMEKEEPING VOLTAGE -40oC T 85oC VDD = 3V 0oC T 70oC VDD = 2.5V 1 -40 -20 0 20 40 60 80 100 TEMPERATURE (oC) FIGURE 27. TYPICAL MINIMUM STANDBY VOLTAGE TABLE 7. STANDBY-VOLTAGE CHARACTERISTICS CDP1879 CDP1879 CDP1879C1 CDP1879C1 VDD MIN MAX UNITS 2.5, 3 2 - 2 - µs 2.5, 3 1 - - - µs 5 2.5, 3 2 - 2 - µs 10 Recovery to Normal Operation Time, tRC MAX 10 Chip Deselect to Stby Voltage Time, tC(STBY) MIN 5 PARAMETER V (STBY) 2.5, 3 1 - - - µs tRC NOTE: tR, tF > 1µs STBY VOLTAGE MODE 0.95 VDD 0.95 VDD VDD tR VSTBY tF (NOTE) (NOTE) tCSTBY CS VIH VIL VIL VIH FIGURE 28. WAVEFORMS AND TIMING DIAGRAM CDP1879 CDP1879 CDP1879CI CDP1879CI PIN 23 EXTERNAL FREQUENCY SOURCE XTAL PIN 23 RF PIN 22 FIGURE 29. CONNECTIONS FOR CDP1879 CDP1879 WHEN AN EXTERNAL FREQUENCY SIGNAL IS SUPPLIED XTAL RS CL 32kHz CRYSTAL CO CI FIGURE 30. SUGGESTED OSCILLATOR CIRCUIT FOR 32kHz CRYSTAL OPERATION 7-85 Application Note 7275 22 MEG CDP1879 CDP1879 XTAL PIN 23 XTAL 14 PARALLEL RESONANT CRYSTAL 39pF RF RL 23 2 200K 3 4 22 CO PIN 22 24 32kHz CI 5pF RF +3V 1 1/3 CD54/74HC04 CD54/74HC04 FIGURE 31. SUGGESTED OSCILLATOR CIRCUIT FOR 1, 2, OR 4MHz OPERATION CDP1879 CDP1879 FIGURE 32. TYPICAL EXTERNAL-CLOCK-SOURCE DIAGRAM Design Considerations for a Stable Crystal Oscillator 1. Stray capacitance should be minimized for best oscillator performance. Circuit-board traces connected to the oscillator pins should be kept to a maximum of 1 inch, and there should be no parallel traces. 2. A signal or power-source line must not cross or approach the oscillator-circuit line. 3. It is advisable to put a nonelectrolytic 0.1µF capacitor between VDD and VSS of the CDP1879 CDP1879. Real-Time-Clock System quent output and input instructions will then address the clock, if it is selected, to read or write to its registers. When the LCD driver is selected, the processor's OUT 2 instructions load the driver with the display information. The backplane signal from the LCD driver is input to one of the processor's flag lines, and is sampled to flash the colon by placing the colon input, via the processor's Q line, in or out of phase with the backplane signal. The CDP1879 CDP1879's clock-out signal is set for one second, and drives the processor's interrupt to turn the display colon off. A routine in the main program turns the colon on when the interrupt is not present. Figure 33 illustrates a working system in which the CDP1879 CDP1879 is configured for I/O operation to display time in minutes and hours. Figure 34 shows the real-time-clock flowchart. A CDP1802 CDP1802 processor outputs instructions and data in a twolevel device-selection scheme. An output instruction of OUT 1 (Hex 61) activates the processors N lines, and is decoded by the CDP1873C CDP1873C to provide a chip-select signal to the CDP1875C CDP1875C output port. The data present on the data bus during the output instruction is latched in the CDP1875C CDP1875C and provides the chip-select signal for the clock or the CD22105A CD22105A LCD driver. A sample program that illustrates the CDP1879 CDP1879's clock-out signal and alarm capability is listed in Figure 35. The alarm routine is written to flash eights when the alarm activates. The clock will continue to keep time and will display it along with the alarm display. If no other OUT 1 instruction with different bus data is issued by the processor, the device will remain selected. Subse- [1] CDP1879 CDP1879, CDP1879C-1 CDP1879C-1 Data sheet, Harris Semiconductor, AnswerFAX Doc No. 1360 Reference For Harris documents available on the web, see http://www.semi.harris.com/ Harris AnswerFAX (407) 724-7800 TABLE 8. TYPICAL OSCILLATOR-CIRCUIT PARAMETERS FOR SUGGESTED OSCILLATOR CIRCUITS OSCILLATOR FREQUENCY 4.197MHz 2.097MHz 1.049MHz (NOTE 1) 32768Hz UNITS RF 22 22 22 22 M CO 39 39 39 39 pF CI 5 5 5 5 pF RS - - - 200 k PARAMETER CL Crystal Impedance - - - 91 pF 73 200 200 50K (max) NOTE: 1. CDP1879C1 CDP1879C1 Only 7-86 Application Note 7275 COLON MEMORY WR OE Q MRW CDP1873C CDP1873C DIGIT DATA BACKPLANE EF2 N0 N1 N2 A0 A1 A2 CS OUT 1 OUT 2 CS CS D7 CS D4 CDP1875C CDP1875C TPB TPB/WR A0 A1 CS A2 RD CDP1879 CDP1879 CLOCK OUT IO/MEM MRD INT VDD DATA BUS FIGURE 33. REAL-TIME CLOCK SYSTEM 7-87 CD22105A CD22105A 5 SELECTION CDP1879 CDP1879 61 10 CD22105A CD22105A 61 80 Application Note 7275 START DISABLE INTERRUPTS LOAD TIME AND ALARM INTERRUPT ROUTINE RETURN INPUT TIME ENTER DISPLAY TIME EF2 LOW? ENABLE INTERRUPT COLON OFF RESET Q DISABLE INTERRUPT READ STATUS REGISTER SET PROGRAM COUNTER YES DISPLAY 8's ALARM NO COLON ON EF2 LOW? YES SET Q NO RESET Q FIGURE 34. REAL-TIME-CLOCK FLOWCHART 7-88 SET Q Application Note 7275 INPUT HR OUT CHK ON ALARM BACK ENTER OFF SET HOURS MIN . PROGRAM DISPLAYS 8:30 A.M. AND FLASHES . 8'S AND TIME WHEN ALARM ACTIVATES . AT 8:31:10. . INTERRUPT ON PROCESSOR CONNECTS TO 1 SEC. . CLOCK OUT ON CDP1879 CDP1879. EF2 CONNECTS TO . BACKPLANE SIGNAL ON LCD DRIVER. . INTERRUPT ROUTINE IS USED TO TURN COLON OFF . BY SAMPLING EF2 AND TOGGLING Q. . TWO LEVEL I/O IS USED FOR SELECTION . CLOCK IS SELECTED WITH 61 10. . LCD DRIVER IS SELECTED WITH 61 80. . AND 62 INSTRUCTIONS LOAD DRIVER AFTER SELECTION. DIS; DC00H DC00H LDI A.1 (ENTER); PHI R1 . SET INTERRUPT POINTER LDI A.0 (ENTER); PLO R1 OUT 1; DC 010H . SELECT CLOCK OUT 7; DC 003H . LOAD C.R. OUT 2; DC 000H . ZERO SECONDS OUT 3; DC 030H . 30 MINUTES OUT 4; DC 048H . 8 A.M. OUT 7; DC 00BH . SELECT ALARM LATCH OUT 2; DC 010H . 10 SEC. ALARM OUT 3; DC 031H . 31 MIN. ALARM OUT 4; DC 048H . 8 A.M. ALARM OUT 7; DC 0CFH . ONE SEC. CLOCK . ALARM ACTIVATES 1 MIN. . 10 SEC. AFTER START SEX 0; OUT1; DC 010H . SELECT CLOCK LDI A.1 (MIN); PHI R8 LDI A.0 (MIN); PLO R8 SEX 8 INP 3; PLO R7 . INP MINUTES ANI 0FH . MASK UPPER STXD; GLO R7 . STR LOW MIN. ANI 0F0H . MASK LOWER SHR; SHR; SHR; SHR ADI 010H; STXD . ADD CHAR. POS. INP 4; PLO R7 . INPUT HOURS ANI 0FH . MASK UPPER ADI 020H; STXD . ADD CHAR. POS GLO R7; ANI 030H . MASK 6 BITS BNZ HR . CHECK FOR 0 HRS LDI 03FH; STR R8 . STR BLANK HRS BR OUT SHR; SHR; SHR; SHR ADI 030H STR R8 SEX 0 OUT 1; DC 080H SEX 8 OUT 2; OUT 2; OUT 2; OUT 2 SEX 0 RET; DC 00H DIS; DC 00H OUT 1; DC 010H SEX 8 INP 7; XRI 0C0H BX ALARM B2 ON REQ; BR INPUT SEQ BR INPUT LDI A.1 (MIN); PHI R8 LDI A.0 (MIN); PLO R8 LDI 008H; STXD LDI 018H; STXD LDI 028H; STXD LDI 038H; STR R8 SEX 0; OUT 1; DE 080H; SEX 8 OUT 2; OUT 2; OUT 2; OUT 2 BR CHK SEP R0 B2 OFF SEQ BR SET REQ LDI A.1 (INPUT); PHI R0 LDI A.0 (INPUT); PLO R0 BR BACK DS 3 DS 1 . ADD CHAR. POS. . SELECT LCD DRIVER . LOAD DRIVER . ENABLE INT TO SAMPLE CLOCK OUT . DISABLE INT . READ STATUS REG . FOR ALARM . COLON ON . REPEAT . LEAD 8'S INTO . LCD DRIVER . . . . RETURN MAIN ENTER POINT FOR INTERRUPT ROUTINE COLON OFF . RESET P.C. FIGURE 35. REAL-TIME-CLOCK PROGRAM 7-89