AN5295NK SDIP030-P-0400 - Datasheet Archive

 

AN5295NK 3-ch. sound signal processing single chip IC for TV (with I2C bus) s Overview 0.5±0.1 Unit: mm 30 1.778

 

ICs for TV AN5295NK AN5295NK 3-ch. sound signal processing single chip IC for TV (with I2C bus) s Overview 0.5±0.1 Unit: mm 30 1.778 26.7±0.3 0.9±0.25 1 The AN5295NK AN5295NK is a television-use 3-ch. sound signal processing IC which incorporates volume, tone control (L/R/C 3-ch.), and surround sound, sound AGC, lower sound enforce (L/R 2-ch.) functions. All of the functions (including changeover switch) including external I/ O port can be controlled by I2C bus. s Features · 3-ch. of volumes can be controlled independently (max. attenuation is 75 dB or more) · Center output can be switched, ether center input or inside L+R signal (for HDTV) · Lower sound enforce effect (frequency and gain) can be adjusted with external parts · With L+R output 15 16 8.6±0.3 1.0±0.25 3.3±0.25 4.7±0.25 +0.1 0.35­0.05 10.16±0.25 3° to 15° SDIP030-P-0400 SDIP030-P-0400 s Applications · Television L-In 30 Buffer C-sel On LT 22 LB 23 STT 25 16 SLV 13 SRV SCV Add Vol.+mute 19 L-Out Tone Vol. Buffer PS LPF 1st amp.1 stage Off VCA Add R-S L-R Buffer L+R B-Out/ 28 C-In 12 L+S On L+R 1 STB Off VCA Tone Vol. 11 R-Out Buffer Loop Level sense Control Bass add Tone On Off Vol. C-Out 20 CT 21 CB 10 RT 9 RB B-Gain 24 26 B-In 27 ADD 5 LS2 4 3 AGC Adj. 18 Buffer 0 dB adj. LS1 R-In 8 VREF 17 Extension I/O (H/L) DAC1 7 PS I2C I2C Buffer 6 14 SCL SDA 15 GND 2 29 VCC s Block Diagram 1 AN5295NK AN5295NK ICs for TV s Pin Descriptions Pin No. Description Pin No. Description 1 R-ch. input pin 16 C-ch. volume DAC output pin 2 Ground pin 17 Extension DAC pin 1 3 AGC 0 dB adjustment pin 18 C-ch. output pin 4 AGC level sensor-1 pin 19 L-ch. output pin 5 AGC level sensor-2 pin 20 C-ch. treble fC setting pin 6 1/2 VCC pin 21 C-ch. bass fC setting pin 7 Phase shift pin 22 L-ch. treble fC setting pin 8 L/R/C-ch. bass DAC output pin 23 L-ch. bass fC setting pin 9 R-ch. bass fC setting pin 24 Bass mix. gain adjustment pin 10 R-ch. treble fC setting pin 25 L/R/C-ch. treble DAC output pin 11 R-ch. output pin 26 Bass detection LPF ope.-amp. input pin 12 R-ch. volume DAC output pin 27 L+R add after AGC output pin 13 L-ch. volume DAC output pin 28 C-ch. input pin 14 I2C communication clock pin 29 Power supply pin (12 V) 15 I2C communication data pin 30 L-ch. input pin s Absolute Maximum Ratings Parameter Symbol Power dissipation Operating ambient temperature Storage temperature *1 *1 V 80 mA PD *2 13.5 ICC Supply current Unit VCC Supply voltage Rating 1 143 mW Topr -20 to +75 °C Tstg -55 to +150 °C Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: Ta = 70 °C. s Recommended Operating Range Parameter Supply voltage 2 Symbol Range Unit VCC 10.8 to 13.2 V ICs for TV AN5295NK AN5295NK s Electrical Characteristics at Ta = 25°C Parameter Symbol Conditions Min Typ Max Unit VVO (max) VIN = 1 V[rms], f = 1 kHz -2.3 - 0.3 1.7 dB VVO (typ) VIN = 1 V[rms], f = 1 kHz -16.2 -13.2 -10.2 Tone control Volume max. level * Volume typ. level * Volume min. level VVO (min) VIN = 1 V[rms], f = 1 kHz * dB -75 dB Bass: boost level VBB VIN = 400 mV[rms], f = 50 Hz 9.2 11.2 13.2 dB Bass: cut level VBC VIN = 400 mV[rms], f = 50 Hz -11.7 -9.7 -7.7 dB Treble: boost level VTB VIN = 400 mV[rms], f = 20 kHz 9.7 11.7 13.7 dB Treble: cut level VTC VIN = 400 mV[rms], f = 20 kHz -12.1 -10.1 -8.1 dB mV[rms] AGC Input/output level 1 * VAGC1 VIN = 1 mV[rms], f = 1 kHz 0.7 1.7 2.7 Input/output level 2 * VAGC2 VIN = 50 mV[rms], f = 1 kHz 70 110 150 mV[rms] Input/output level 3 * VAGC3 VIN = 1 V[rms], f = 1 kHz 275 345 415 mV[rms] VIN = 0 mV 25 45 65 mA VIN = 1 V[rms], f = 1 kHz 0.1 0.5 % 2.8 V[rms] -80 dB Circuit current * ICC Total harmonics distortion Max. input voltage Mute level * THD VIN (max) THD = 1% * * VMUTE VIN = 1 V[rms], f = 1 kHz Noise level at volume max. * VNO (max) VIN = 0 mV, Rg = 0 115 200 µV[rms] Noise level at volume min. * VNO (min) VIN = 0 mV, Rg = 0 45 100 µV[rms] VSU (max) VIN = 100 mV[rms], f = 1 kHz 12.4 14.4 16.4 dB VSU (min) VIN = 100 mV[rms], f = 1 kHz 2.9 4.9 6.9 dB VLPSUL VIN = 100 mV[rms], f = 1 kHz 4.9 6.9 8.9 dB VBAONL VIN = 400 mV[rms], f = 50 Hz 3.95 5.95 7.95 dB Surround level (max.) * Surround level (min.) * Surround level at loop on Level at bass add on * * CT VIN = 1 V[rms], f = 1 kHz -70 -68.5 dB CB VIN = 1 V[rms], f = 1 kHz -1.5 0 1.5 dB VTR VIN = 1 V[rms], f = 1 kHz -2.0 0 2.0 dB Sink current at ACK IACK Maximum value of pin 15 sink current at ACK 2.0 10 mA SCL, SDA signal high-level input VIHI 3.5 5.0 V SCL, SDA signal low-level input VILO 0 0.9 V Max. allowable input frequency fImax 100 kbit/s Cross talk * Channel balance * L-R volume tracking (1/4) I2C * interface Note) * : Uses DIN audio filter. 3 AN5295NK AN5295NK ICs for TV s Electrical Characteristics at Ta = 25°C (continued) · Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Min Typ Max Unit tBUS 4.0 µs Start condition setup time tSU. STA 4.0 µs Start condition hold time tHD. STA 4.0 µs Low period SCL, SDA tLO 4.0 µs High period SCL tHI 4.0 µs Rise time SCL, SDA tr 1.0 µs Fall time SCL, SDA tf 0.35 µs Data setup time (write) tSU. DAT 0.25 µs Data hold time (write) tHD. DAT 0 µs Acknowledge setup time tSU. ACK 3.5 µs Acknowledge hold time tHD. ACK 0 µs Stop condition setup time tSU. STO 4.0 µs 0.1 1.0 1.9 LSB/step I2C Symbol Conditions interface Bus free before start DAC 6-bit DAC DNLE Start condition SDA tBUF Slave address tSU. DAT SCL tSU. STA 1 LSB = (data (max.) - data (00)/63 L6 tr ACK Sub address ACK tHD. DAT tf Stop ACK condition Data byte tSU. STO tHI tLO tLO tHDSTA s Terminal Equivalent Circuits Pin No. Equivalent circuit 1 Description Voltage (V) R-In: R-ch. Input pin 1 6 GND: GND pin 0 200 50 k 1/2 VCC 2 4 ICs for TV AN5295NK AN5295NK s Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage (V) AGC Adj.: AGC on/off changeover AGC off at 1.2 V or less. 96 k 20 k 20 k 7 3 40 k 4 18 k 900 250 1/2 VCC 4 5 LS2: AGC level sensor 1, 2 CTL Level 2 Level 1 430 LS1: AGC level sensor 1 3 0.5 to 1.5 20 k 5 6 VREF : Reference voltage to be stabilized 6 PS: Phase shift pin 6 50 k 6 50 k 7 7 200 18 k 18 k 8 STB: L/R/C-ch. bass DAC output pin 500 8 500 20.5 k 5.8 k 3±1 20.5 k 3V 5 AN5295NK AN5295NK ICs for TV s Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 9 Voltage (V) RB: R-ch. bass fC setting pin RT: R-ch. treble fC setting pin 6 9 10 4 k 6 R-Out: R-ch. output pin 4 k 6 10 11 11 12 SRV: R-ch. volume DAC output pin SLV: L-ch. volume DAC output pin VCC 5.8 k 20.5 k 500 3±1 SCL: I2C bus clock input pin 500 12 3±1 20.5 k 3V 13 500 13 5.8 k 20.5 k 500 20.5 k 3V 14 100 k 14 1 k 500 6 2.5 V ICs for TV AN5295NK AN5295NK s Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 15 Voltage (V) SDA: I2C bus data input pin VCC SCV: C-ch. volume DAC output pin 3±1 100 k 1 k 15 500 2.5 V 16 500 16 500 5.8 k 20.5 k 20.5 k 3V 17 100 k 50 k DAC1: Extension DAC output pin 850 0 or 5 17 50 k 5.7 V 18 C-Out: C-ch. output pin 6 L-Out: L-ch. output pin 6 CT: C-ch. treble fC setting pin 6 18 19 19 20 4 k 20 7 AN5295NK AN5295NK ICs for TV s Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 21 Voltage (V) CB: C-ch. bass fC setting pin LT: L-ch. treble fC setting pin B-Gain: Bass mix. gain adjustment pin 6 22 23 4 k 6 21 22 4 k 6 LB: L-ch. bass fC setting pin 4 k 6 23 24 4.7 k 24 25 STT: L/R/C-ch. treble DAC output pin 500 25 500 20.5 k 5.8 k 3±1 20.5 k 3V 26 B-In: Bass detection LPF ope.-amp. input pin 26 8 6 ICs for TV AN5295NK AN5295NK s Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 27 Voltage (V) ADD: L+R (after AGC) output pin 6 C-In: C-ch. input pin 6 VCC : Power supply pin 12 L-In: L-ch. input pin 6 27 28 28 200 50 k 1/2 VCC 29 30 30 200 50 k 1/2 VCC s Technical Information · I2C bus 1. DAC 1) Built-in 5 DAC controls and 8 switches 2) Incorporating auto-increment functions (1) Sub address 0* : Auto-increment mode (Data are inputted by the change of sub-address according to the transfer when data are sequentially transferred.) (2) Sub address 8* : Data renewal mode (Data are inputted with the same sub-address when data are sequentially transferred.) 3) I2C bus protocol (1) Slave address: 10000000 (80H) (2) Format (normal) S Slave address A Sub address Start condition A Data byte A P Acknowledge bit Stop condition (3) Auto-increment mode/data renewal mode S Slave address A Sub address A Data 1 A Data 2 A Data n A P 4) Typical data should be inputted at power on because initial state of DAC is not guaranteed. 9 AN5295NK AN5295NK ICs for TV s Technical Information (continued) · I2C bus (continued) 2. I2C bus transfer sequence SDA SCL Slave address Acknowledge Sub address Acknowledge bit bit Start condition 1 0 0 0 0 0 0 0 8 0 0 0 0 0 0 1 0 0 0 Data Acknowledge Stop bit condition 0 0 0 1 0 0 1 0 2 1 2 Transfer message example Two type of transfer messages of SCL and SDA are sent by synchronous serial transfer. SCL is a clock of constant frequency and SDA indicates address data to control receiving side and is sent in parallel by synchronizing with SCL. Data are transferred in principle with 8-bit 3 octet (byte) and acknowledge bit exists every one octet. Frame organization are described as follows: 1) Start condition When SDA becomes low from high at SCA = high, receiver is on a data receiving mode. 2) Stop condition When SDA becomes high from low at SCA = high, receiver stops receiving data. 3) Slave address 4) Sub address Address determined by device. Receiving is stopped when address of another device is sent. Address determined by function 5) Data 6) Acknowledge bit Data to control To let the master acknowledge that data has been received for each octet in such manner that the master sends a high signal and the receiver sends back a low signal as shown by above transfer sequence. SDA is not changed when SCL is high except start and stop conditions. 3. Sub address byte and data byte format Upper MSB Sub address D7 Data byte D6 D5 D4 D3 D2 D1 D0 AGC on/off 00 L-ch. vol. Mute on/off 01 R-ch. vol. C-ch. mute Surround on/off on/off 02 C-ch. vol. Bass mix. on/off 03 04 05 10 L/R/C treble 0 0 0 Surround effect C-In select L/R/C bass 0 0 0 0 0 Surround loop on/off 0 0 DAC1 L/H ICs for TV AN5295NK AN5295NK s Technical Information (continued) · I2C bus (continued) 3. Sub address byte and data byte format (continued) 1) L-ch. Vol., R-ch. Vol., C-ch. Vol. Min. at data = 00 Max. at data = 3F 2) L/R/C treble, L/R/C bass Min. at data = 0 Max. at data = F 3) Surround effect Min. at data = 0 Max. at data = F 4) Switches (except C-ch. mute SW) Off at data = 0 On at data = 1 5) DAC1 Low (0 V) at data = 0 High (5 V) at data = 1 6) C-In select L+R in at data = 0 C-In at data = 1 7) C-ch. mute Off at data = 0 On at data = 1 L-In 30 VCA VCA C-sel On LT LB Add 22 Vol.+mute 19 L-Out Tone Vol. 10 µF Buffer PS LPF 1st amp.1 stage Off L+R Add R-S L-R Buffer 10 µF 0.01 µF 25 0.22 µF 4.7 µF 16 L+S On L+R 1 23 4.7 µF Off 10 µF R-In STT SCV 4.7 µF 13 SLV SRV 8 12 STB 4.7 µF 4.7 µF PS VREF 17 Extension I/O (H/L) DAC1 0.1 µF 7 6 I2C I2C Buffer 100 µF SCL SDA 14 2 29 100 µF 15 VCC 12 V GND s Application Circuit Example Tone Vol. Bass add Tone On Off 10 µF Vol. 10 µF 20 CT 0.01µF 21 0.22µF CB 10 0.01µF RT 9 0.22 µF RB B-Gain 4.7 k 24 B-In 26 C 100 k 10 µF 220 k To sound discrimination LS2 LS1 C-In: At HV Without no AGC. Possible also for 3D at 2-ch. ADD: Add signal after AGC 0.015 µF 5 4.7 µF ADD 27 4 10 µF 3 10 k 12 V 24 k 18 C-Out Buffer 0 dB adj. AGC Adj. 10 µF Buffer Loop Level sense Control B-Out/ C-In 28 Buffer 11 R-Out Tone : LB : L-ch. bass fC LT : L-ch. treble fC RB: R-ch. bass fC RT : R-ch. treble fC CB: C-ch. bass fC CT : C-ch. treble fC 11 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. 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