MCF5211/12/13 MCF5214/16 M5282EVB M52233DEMO AN3749 MCF5282UM MCF5282 M5282LITE - Datasheet Archive

 

Application Note Using ADC and QADC Modules with ColdFire Microcontrollers The MCF5211/12/13 and MCF522xx ADC Module The

 

Freescale Semiconductor Application Note Using ADC and QADC Modules with ColdFire Microcontrollers The MCF5211/12/13 MCF5211/12/13 and MCF522xx ADC Module The MCF5214/16 MCF5214/16 and MCF528x QADC Module by: David Tosenovjan Technical Information Center, Roznov 1 Introduction This application note helps understand how to use the ColdFire MCF528x, MCF5214/16 MCF5214/16 microcontrollers queued analog-to-digital converter and the ColdFire MCF5211/12/13 MCF5211/12/13, MCF522xx microcontrollers analog-to-digital converter. It provides basic examples for different ADC and QADC configurations. QADC examples were created for evaluation board M5282EVB M5282EVB and ADC examples for evaluation board M52233DEMO M52233DEMO. The M5282EVB M5282EVB does not include any devices connected to the QADC inputs. It needs to have a signal generator or voltage source (preferably both). The M52233DEMO M52233DEMO includes a potentiometer and accelerometer connected to a few analog pins. No external equipment is needed. © Freescale Semiconductor, Inc., 2008. All rights reserved. Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Queued Analog-to-Digital Converter . . . . . . . . . . . . . . . . 2 2.1 Brief Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Conversion Command Word (CCW) Table . . . . . . . 2 2.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.5 QADC Programming Examples. . . . . . . . . . . . . . . . 5 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Brief Description . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 ADC Programming Examples . . . . . . . . . . . . . . . . 16 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB Document Number: AN3749 AN3749 Rev.0, 10/2008 Queued Analog-to-Digital Converter Queued Analog-to-Digital Converter 2.1 Brief Description · · · · · · · · · 2.2 10-bit, unipolar, and successive approximation converter Up to eight analog input channels if internal multiplexing is used Up to 18 analog input channels if external multiplexing is used Possibility of using as a GPIO Conversion command word table with 64 command words 64 right-justified unsigned result registers 64 left-justified signed result registers 64 left-justified unsigned result registers Two independent various length queues (can be cut to various numbers of subqueues except software triggered and externally gated modes) Terms Queue 1 (Q1) - Sequence of commands that begin with the first entry of CCW and ends with one of the following options: · An entry that contains the first EOQ code. Using the EOQ code is strongly recommended. · One entry before the entry determined by BQ2. Queue 2 (Q2) - Sequence of commands that begins with the entry the BQ2 points to and ends with second EOQ code or ends at the end of the CCW table if the second EOQ is not used. Subqueue (SQxx) - Sequence of commands between the beginning and the CCW entry with pause bit set, two entries with pause bit set, or entry with pause bit set, and the end of queue. Pause - If pause bit in the CCW entry is set the conversion is paused after this command execution and waits for another trigger event. The queue is in a pause state except both externally gated modes and both software-triggered modes where pause state is ignored. End of queue (EOQ) - If the command has set channel number 63, the whole command is interpreted as end of queue notification. The rest of this entry is not important. Beginning of queue 2 (BQ2) - An entry of the CCW table pointed to by QACR2[BQ2]. The entry prior can contain the EOQ code. 2.3 Conversion Command Word (CCW) Table The conversion command word table defines Q1 and Q2. Every row (command, CCW entry) contains an input channel number and input sample time (usually zero) that can be set to a pause state after conversion and to a sample amplifier bypass (not usually used). Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB 2 Queued Analog-to-Digital Converter Command (entry) Input channel number Pause Sample amplifier bypass Input sample time 00 0 No No 0 01 1 No No 0 02 2 No No 0 03 3 Yes No 0 04 0 No No 0 05 1 No No 0 06 2 No No 0 07 3 No No 0 08 63 (EOQ) x x x 09 52 No No 0 10 53 Yes No 0 11 52 No No 0 12 53 Yes No 0 13 55 No No 0 14 56 No No 0 15 63 (EOQ) x x x QUEUE SUBQUEUE SQ11 Q1 SQ12 SQ21 SQ22 2.4 2.4.1 Q2 SQ23 Modes of Operation Software Triggered Single-Scan Mode The Q1/Q2 scan is initiated by asserting the QACR1[SSE1]/QACR2[SSE2] bit. The CCW entry with the pause bit set does not cause the pause state although the PFn flag is set and the interrupt is invoked if allowed. After the appropriate queue scan completion the SSE1/SSE2 bit is negated. Another scan may be initiated by another SSE1/SSE2 bit assertion. 2.4.2 Externally Triggered Single-Scan Mode Triggering can be set for rising or falling edge for the ETRIGn signal. The SSE bit has to be asserted to allow queue triggering. After the appropriate queue scan completion, the SSE1/SSE2 bit is negated. Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 Freescale Semiconductor 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB Table 1. Example of CCW Configuration with Market Queues and Subqueues Queued Analog-to-Digital Converter Interval Timer Single-Scan Mode The timer interval between two triggering events can be set from 27 to 217 QCLK cycles in binary multiples. The Q1/Q2 scan is initiated by asserting the SSE1/SSE2 bit. After the appropriate queue scan completion the SSE1/SSE2 bit is negated. The conversion can continue after the SSE1/SSE2 bit is set again by the software. For example, it is useful if the interrupt service routine takes more time than the time between a scan completion and another triggering event. This approach ensures coherent results. For more information go to MCF5282UM MCF5282UM - MCF5282 MCF5282 ColdFire Microcontroller User's Manual. 2.4.4 Externally Gated Single-Scan Mode This mode can only be used with Q1. High level on the ETRIG1 (or ETRIG2 if QACR0[TRG] bit is set) input allows scan initialization by asserting bit SSE1 and vice versa. In this mode the pause bit set in CCW entry is ignored during the queue scan. The queue pause flag is redefined and set if the gate closes during the scan. After the scan is complete, the SSE1 bit is negated. 2.4.5 Software Triggered Continuous-Scan Mode Queue execution begins immediately after the QACRn[MQn] settings for this mode. The CCW entry with pause bit set does not cause pause state. The PFn flag is set (and interrupt is invoked if allowed). This mode is usually used only for Q2. If used in Q1, Q2 never executes. In this mode, interrupts are not usually used. After the scan completion the queue execution continues immediately from the beginning. 2.4.6 Externally Triggered Continuous-Scan Mode Triggering can be set for rising or falling edge of the ETRIGn signal. After the scan completion another trigger event on the ETRIGn is needed for scan continuance. No software involvement is required. 2.4.7 Periodic Timer Continuous-Scan Mode The timer interval between two triggering events can be set from 27 to 217 QCLK cycles in binary multiples. In comparison to the interval timer single-scan mode the SSE1/SSE2 bit does not have any influence on queue scan behavior. After scan completion, the queue execution immediately continues from the beginning. 2.4.8 Externally Gated Continuous-Scan Mode This mode can only be used with Q1. High level on ETRIG1 (or ETRIG2 if QACR0[TRG] bit is set) input causes cyclic execution of the queue. The pause bit set in the CCW entry is ignored during the queue scan in this mode. The queue pause flag is redefined and is set if the gate closes during the queue scan. Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB 2.4.3 Queued Analog-to-Digital Converter QADC Programming Examples 2.5.1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB 2.5 Evaluation Tools Needed Unfortunately the evaluation boards (M5282EVB M5282EVB and M5282LITE M5282LITE) used in this application note do not have a device connected to the QADC inputs. A voltage source/function waveform generator is needed. An oscilloscope is a great benefit. Connecting the UART0 to the terminal window with these settings is needed: · 115200 baud · 8-bits · No parity · 1 stop bit · No flow control Table 2. Signal Inputs can be Connected to these Pins Signal name AN0 AN1 AN2 AN3 AN52 AN53 AN55 AN56 VSSA ANW ANX ANY ANZ MA0 MA1 ETRIG1 ETRIG2 ­ PQB0 PQB1 PQB2 PQB3 PQA0 PQA1 PQA3 PQA4 ­ EVB pin no. 5 16 17 19 3 14 11 13 1 LITE pin no.2 14 13 12 11 10 9 8 7 50 Alternate GPIO 1 1 2 J5 header of MCF5282EVB MCF5282EVB MCU_PORT header of MCF5282LITE MCF5282LITE When using an evaluation board a few jumpers influence the QADC behavior. Table 3. Analogue Power Selector JP24 Selected VDDA and VDDH reference 1­2* 3.3 V 3­4 5V 5­6 On pin J5­18 Table 4. Analogue Ground Selector JP23 Selected VSSA reference 1­2* GND 2­3 Pin J5­1 Table 5. Voltage Reference High Selector JP19 Selected VRH reference 1­2* VDDA 2­3 Pin J5­20 Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 Freescale Semiconductor 5 Queued Analog-to-Digital Converter Table 6. Voltage Reference Low Selector Selected VRL reference 1­2* VSSA 2­3 Pin J5­2 *Default settings NOTE The MCF5282 MCF5282 is a 5 V tolerant device and has up to a 5 V digital output driven by a VDDH input. In case of using a LITE board, fixed analog references are used: · VDDA = VRH = +3.3 V · VSSA = VRL = 0 V 2.5.2 General Programing Scheme All examples are based on the CodeWarrior 6.4 stationery and are built as separate targets of this project. Intended to prepare the code example for easy configuration with minimum possible system mistakes. Headers with operating modes and a template for the CCW easy editing are prepared. The BQ2 parameter can be automatically extracted from the CCW table. Interrupt service routines know what results are needed to read. 2.5.2.1 Files Modified or Added in Comparison with the Standard CodeWarrior 6.4 Stationery Files modified: · vectors.s Files added: · QADC_CCW_table.h · QADC_opmodes.h Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB JP18 Modified and differs for a particular example: · main_x.c · int_handlers_x.c Added and differs for a particular example: · QADC_CCW_table_x.c 2.5.2.2 2.5.2.2.1 File Description vectors.s Added vectors for the following interrupt service routines: · EPORT_IRQ7_button_pressing · QADC_Q1_conversion_pause · QADC_Q2_conversion_pause · QADC_Q1_conversion_complete · QADC_Q2_conversion_complete 2.5.2.2.2 int_handlers_x.c Added interrupt service routines for the sources mentioned above. 2.5.2.2.3 main_x.c This file includes a description of the example by displaying a notice on the terminal window, initialization part of EPORT module, interrupt controller module, and the QADC module. Functions: · void QADC_init(void) - Initializes the QADC module and its CCW table. This function calls functions set_CCW and get_BQ2. · void cpu_pause(int usecs) - For the required time in s, this function can be used for a wait in the loop. It uses the DMA timer 3. 2.5.2.2.4 QADC_opmodes.h The file includes headers with the list of Q1 and Q2 operating modes for easy configuration of QACR1[MQ1] field and QACR2[MQ2]. 2.5.2.2.5 QADC_CCW_table_x.c This file includes two functions and a template for creating the CCW table. The table is prepared as a one-dimensional unknown size data field. Every item (row) is composed of macros and is an entry to the CCWtable. Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 Freescale Semiconductor 7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB Queued Analog-to-Digital Converter Functions: · void set_CCW (void) - Copies the CCW table from the data field CCWtable[] located in the file QADC_CCW_table.c to the appropriate registers. · int32 get_BQ2 (void) - Identifies and returns the beginning of Queue 2. The return value is the index of the first EOQ entry increased by one. The CCW table can contain two entries with the EOQ code. If the CCW table includes only one EOQ code all entries below are considered as Queue 2 and the end of the CCW table is considered as end of Queue 2. If the CCW table does not include any EOQ code default value, 127 is returned. It is the same as the default QACR[BQ2] value and it means that the trigger event for Q2 does not cause any conversion. 2.5.2.2.6 QADC_CCW_table.h Headers for configuring the CCW table. 2.5.2.3 How Initialization is Performed The initialization has to be executed after beginning the main routine in these configuration phases: 1. Edge port module, this is because of the used IRQ7 button. 2. Interrupt controller that allows interrupts from the QADC and EPORT - The interrupt sources for the INTC0 are set in such a way that the IRQ7 button has higher priority therefore the conversion pause interrupts: Table 7. Interrupt Levels and Priorities of Added Interrupt Sources Interrupt source Priority Level EPORT_IRQ7_button_pressing Mid (between 3 and 4) 7 (fixed) QADC_Q1_conversion_pause 3 4 QADC_Q2_conversion_pause 2 4 QADC_Q1_conversion_complete 1 4 QADC_Q2_conversion_complete 0 4 3. QADC Conversion Command Table - The following function is used for copying the CCWtable[] data field to the CCW registers: void set_CCW (void) { int32 i; int32 CCWtable_length = sizeof(CCWtable)/2; // length of CCW is 16 bit words /* initialize Conversion Command Word Table */ for (i = 0; i < CCWtable_length; i+) { MCF5282 MCF5282_QADC_CCW(i) = CCWtable[i]; } // copy CCW table to CCW registers } Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB Queued Analog-to-Digital Converter 4. The rest of the QADC - Settings vary according to the given example. All examples use a function for getting the BQ2 parameter from the CCW table. Call of this function is placed to the MCF5282 MCF5282_QADC_QACRx_BQ macro instead of a direct number parameter: int32 get_BQ2 (void) { int32 i; int32 CCWtable_length = sizeof(CCWtable)/2; // length of CCW /* identify beginning of Queue 2 */ for (i = 0; i < CCWtable_length; i+) { if (MCF5282 MCF5282_QADC_CCW(i) & EOQ) = EOQ) { return (i+1); } } return (127); // identify end of Q1 // return line after first EOQ code // no EOQ code (whole CCW is assigned for Q1) } 2.5.2.4 How Event Servicing is Performed The software waits in the infinite loop after initialization. All examples use only interrupt service routines for the QADC event servicing. 2.5.2.5 Determining what Results are Read The QADC does not contain any sample ready status registers. For determining results that are supposed to be read only command word pointers QASR1[CWPQ1], QASR1[CWPQ2], and the CCW table can be used. All QADC interrupt handlers use global static variables previous_CWPQ1 and previous_CWPQ2. These are used for remembering the last read result (by the previous QADC interrupt service routine). The current CWPQn are found during the interrupt service routine and all samples between these two pointers must be read. Information about channel to result register assignments can be found in the appropriate entry of the CCW table. The EOQ must be excluded. for (i = 1 + previous_CWPQ1; i i) & 0x0001) { printf("%d",i); printf(":"); printf("%6d",(int16) MCF_ADC_ADRSLT(i); printf(" "); } } Interrupt service routines are written for universal service of all modes. ADCA_conversion_complete routine has two main branches. First, the sequential or parallel simultaneous mode and the second for the parallel independent mode. In case parallel independent sampling, read half of the result registers in the interrupt service routine initiated by the ADCA. Read the other half in ISR initiated by ADCB. Sequential mode is possible to determine by CTRL1[SMODE0]: !(MCF_ADC_CTRL1 & 0x0001) Parallel simultaneous mode can be determined by CTRL2[SIMULT]: (MCF_ADC_CTRL1 & 0x0001) && (MCF_ADC_CTRL2 & MCF_ADC_CTRL2_SIMULT) Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB Interrupt sources for INTC0 are set in such a way that higher priority has buttons and conversion complete interrupts. See Table 8: Analog-to-Digital Converter Similar testing is used in routines EPORT_SWx_button_pressing and used for the following condition: This determines whether ADC uses the mode once or not. If yes, pressing the button starts the conversion. If no, it means loop or triggered mode is used and pressing the button alternately starts/stops conversion. 3.3.3 Example 1 ­ Mode Once, One Channel Scan, (Single Ended Input) This example uses a parallel independent scan. It does not matter what mode is chosen in this case because behavior is the same. Pressing the SW1 button starts scanning channel AN0 where the demo board has the potentiometer connected. Jumper POT_EN has to be on. 3.3.3.1 ADC Power-Up Sequence These examples use a normal power mode. First power-up the voltage reference circuit and both converters wait for POWER[PUDELAY] ADC clock cycles until PSTS0, PSTS1, and PSTS2 are cleared: MCF_ADC_POWER &= ~(MCF_ADC_POWER_PD0 | MCF_ADC_POWER_PD1 | MCF_ADC_POWER_PD2); // power-up converter A, converter B and voltage reference circuit while (MCF_ADC_POWER & (MCF_ADC_POWER_PSTS0 | MCF_ADC_POWER_PSTS1 | MCF_ADC_POWER_PSTS2) {}; // stay here as long as converter A, B and voltage reference circuit are power-down 3.3.3.2 Clock Divisor Select The clock divisor is set for maximum conversion clock but not to exceed 5 MHz. It is closely involved with the value of the peripheral system clock that equals ½ of the core clock according to the reference manual by the following equation: DIV = round up (peripheral clock / 2 x 5MHz) ­ 1) if (CORE_CLOCK % 20000) MCF_ADC_CTRL2 = MCF_ADC_CTRL2_DIV(CORE_CLOCK/20000 CLOCK/20000) | // MCF_ADC_CTRL2_STOP1; // else MCF_ADC_CTRL2 = MCF_ADC_CTRL2_DIV(CORE_CLOCK/20000 CLOCK/20000)-1) | // MCF_ADC_CTRL2_STOP1; // 3.3.3.3 Eqn. 1 divison remainder!=0 stop ADCB divison reminder=0 stop ADCB Offset Settings Offset registers (ADOFSn) are used for determining whether the result is signed or unsigned. 0 means positive unsigned results, 2047 means signed results, and 4095 means negative unsigned results: MCF_ADC_ADOFS0 = MCF_ADC_ADOFS_OFFSET(2047); Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 Freescale Semiconductor 19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB !(MCF_ADC_CTRL1 & 0x0006) Analog-to-Digital Converter Disabling Unused Sample Slots Setting the ADSDIS[DS1] causes disabling sample slot 1 and all higher sample slots, this means from slot one to slot seven in case of sequential sampling and from slot one to slot three in case of parallel sampling. Similarly ADSDIS[DS4] disables sample slots from four to seven (entire ADCB converter) in case of parallel sampling. In case of a sequential sampling no action is taken. MCF_ADC_ADSDIS = MCF_ADC_ADSDIS_DS1 | // disable SAMPLE1 slot and higher MCF_ADC_ADSDIS_DS4; // disable SAMPLE4 slot and higher 3.3.3.5 Used Configuration MCF_ADC_CTRL1 = MCF_ADC_CTRL1_EOSIE0 | // ADCA end of scan interrupt enable MCF_ADC_CTRL1_CHNCFG(0) | // all inputs single ended MCF_ADC_CTRL1_SMODE(1) | // once parallel mode MCF_ADC_CTRL1_STOP0; // stop until button is pressed 3.3.4 Example 2 ­ One Channel Loop (Differential Input) This example uses a parallel independent scan. It does not matter what mode is chosen in this case because behavior is the same. Pressing the SW1 button causes start/stop of the scan of the differential input. This consists of channel AN0 where the potentiometer is connected to the demo board and AN1 where you can connect the DC voltage source. Do not exceed 3.6 V. This example uses zero crossing (both edges) and limits interrupts (low limit approximately 0.5 V, high limit 2.8 V). After each scan the converted value is displayed on the terminal window. The signed results are used. Limits or zero crossing events also cause notices on the terminal window and has a higher priority then the results displayed. The ADC power-up sequence, clock divisor select, offset settings, and disabling unused sample slots are essentially the same parts as Section 3.3.3, "Example 1 ­ Mode Once, One Channel Scan, (Single Ended Input)". 3.3.4.1 Used Configuration MCF_ADC_CTRL1 = MCF_ADC_CTRL1_EOSIE0 MCF_ADC_CTRL1_HLMTIE MCF_ADC_CTRL1_LLMTIE MCF_ADC_CTRL1_ZCIE MCF_ADC_CTRL1_CHNCFG(1) MCF_ADC_CTRL1_SMODE(3) MCF_ADC_CTRL1_STOP0; 3.3.5 | | | | | | // // // // // // // ADCA end of scan interrupt enable high limit interrupt enable low limit interrupt enable zero crossing interrupt enable (AN0 +, AN1 -), the rest single-ended loop parallel mode stop until button is pressed Example 3 ­ Loop Sequential Scan of Multiple Channels (Single Ended Inputs) Pressing the SW1 button causes the scan to start/stop channel AN0 (connected to the potentiometer) and AN4­6 (connected to the accelerometer). Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB 3.3.3.4 After each scan the converted value is displayed on the terminal window. The signed results are used. First column shows potentiometer value, second, third, and fourth shows X, Y, and Z axis of accelerometer outputs. The ADC power-up sequence, clock divisor select, offset settings, and disabling unused sample slots are essentially the same parts as Section 3.3.3, "Example 1 ­ Mode Once, One Channel Scan, (Single Ended Input)". 3.3.5.1 Channels to Sample Slots Linking This example does not use default assignments between channels and sample slots. Because of using sequential scan mode any channel to any sample slot can be assigned: MCF_ADC_ADLST1 = MCF_ADC_ADLST1_SAMPLE0(0) MCF_ADC_ADLST1_SAMPLE1(4) MCF_ADC_ADLST1_SAMPLE2(5) MCF_ADC_ADLST1_SAMPLE3(6) 3.3.5.2 | | | ; // // // // sample sample sample sample slot slot slot slot 0 1 2 3 for for for for channel channel channel channel 0 4 5 6 Used Configuration MCF_ADC_CTRL1 = MCF_ADC_CTRL1_EOSIE0 | // ADCA end of scan interrupt enable MCF_ADC_CTRL1_CHNCFG(0) | // all inputs as single ended MCF_ADC_CTRL1_SMODE(2) | // loop sequential mode MCF_ADC_CTRL1_STOP0; // stop until button is pressed 3.3.6 Example 4 ­ Triggered Parallel Independent Scan of Multiple Channels (Single Ended Inputs) Pressing SW1/SW2 carries out one conversion and starts/stops the ADCA/ADCB converter to accept rising edge triggering signal on the input SYNCA/SYNCB. After each scan the converted value is displayed on the terminal window. The ADCA conversion scan complete shows potentiometer value and the ADCB conversion scan complete shows the X, Y, and Z axis of the accelerometer outputs. The signed results are used. The ADC power-up sequence, clock divisor select, offset settings, and disabling unused sample slots are essentially the same parts as Section 3.3.3, "Example 1 ­ Mode Once, One Channel Scan, (Single Ended Input)". 3.3.6.1 Used Configuration MCF_ADC_CTRL1 = MCF_ADC_CTRL1_EOSIE0 MCF_ADC_CTRL1_SYNC0 MCF_ADC_CTRL1_CHNCFG(0) MCF_ADC_CTRL1_SMODE(5) MCF_ADC_CTRL2|= MCF_ADC_CTRL2_EOSIE1 MCF_ADC_CTRL2_SYNC1 | | | ; | ; // // // // // // ADCA end of scan interrupt enable rising edge of SYNCA can initiate scan all inputs as single ended triggered parallel ADCB end of scan interrupt enable rising edge of SYNCB can initiate scan Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 Freescale Semiconductor 21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB Analog-to-Digital Converter References References MCF52235 MCF52235 ColdFire® Integrated Microcontroller Reference Manual, MCF52235RM MCF52235RM MCF52235 MCF52235 ColdFire Microcontroller Data Sheet, MCF52235DS MCF52235DS MCF52235 MCF52235 Device Errata, MCF52235DE MCF52235DE MCF5282 MCF5282 ColdFire® Microcontroller User's Manual, MCF5282UM MCF5282UM MCF5282 MCF5282 Device Errata, MCF5282DE MCF5282DE Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB 4 Using ADC and QADC Modules with ColdFire Microcontrollers, Rev.0 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB M5282EVB THIS PAGE IS INTENTIONALLY BLANK 23 Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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